Attachment 129549 Details for Bug 99788 – dmesg during run

dmesg during run

dmesg-during.log (text/plain), 6.69 MB, created by Jani Saarinen on 2017-02-13 08:40:47 UTC

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Creator: Jani Saarinen

Created: 2017-02-13 08:40:47 UTC

Size: 6.69 MB

patch

obsolete

>[   26.003119] Console: switching to colour dummy device 80x25
>[   26.003470] [IGT] core_auth: executing
>[   26.028665] [IGT] core_auth: starting subtest basic-auth
>[   26.029820] [IGT] core_auth: exiting, ret=0
>[   26.057300] Console: switching to colour frame buffer device 240x75
>[   26.207703] Console: switching to colour dummy device 80x25
>[   26.208172] [IGT] core_prop_blob: executing
>[   26.237738] [IGT] core_prop_blob: starting subtest basic
>[   26.238091] [IGT] core_prop_blob: exiting, ret=0
>[   26.283166] Console: switching to colour frame buffer device 240x75
>[   26.401541] Console: switching to colour dummy device 80x25
>[   26.401647] [IGT] drv_getparams_basic: executing
>[   26.413476] [IGT] drv_getparams_basic: starting subtest basic-eu-total
>[   26.413544] [IGT] drv_getparams_basic: exiting, ret=0
>[   26.466503] Console: switching to colour frame buffer device 240x75
>[   26.605372] Console: switching to colour dummy device 80x25
>[   26.605677] [IGT] drv_getparams_basic: executing
>[   26.632457] [IGT] drv_getparams_basic: starting subtest basic-subslice-total
>[   26.632614] [IGT] drv_getparams_basic: exiting, ret=0
>[   26.674473] Console: switching to colour frame buffer device 240x75
>[   26.824102] Console: switching to colour dummy device 80x25
>[   26.824404] [IGT] drv_hangman: executing
>[   26.853696] [IGT] drv_hangman: starting subtest error-state-basic
>[   26.862331] [drm] GPU HANG: ecode 9:-1:0x00000000, reason: Manually setting wedged to 1, action: reset
>[   26.862344] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
>[   26.862346] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
>[   26.862348] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
>[   26.862349] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
>[   26.862351] [drm] GPU crash dump saved to /sys/class/drm/card0/error
>[   26.864171] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   26.864508] drm/i915: Resetting chip after gpu hang
>[   26.867069] [drm] RC6 on
>[   26.880112] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   26.880322] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   26.880493] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   26.880659] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   26.880824] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   26.880999] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[   26.881032] [drm] GuC firmware load skipped
>[   26.903822] [IGT] drv_hangman: exiting, ret=0
>[   26.933225] Console: switching to colour frame buffer device 240x75
>[   27.075769] Console: switching to colour dummy device 80x25
>[   27.076158] [IGT] gem_basic: executing
>[   27.105568] [IGT] gem_basic: starting subtest bad-close
>[   27.105736] [IGT] gem_basic: exiting, ret=0
>[   27.141425] Console: switching to colour frame buffer device 240x75
>[   27.281257] Console: switching to colour dummy device 80x25
>[   27.281475] [IGT] gem_basic: executing
>[   27.309457] [IGT] gem_basic: starting subtest create-close
>[   27.309689] [IGT] gem_basic: exiting, ret=0
>[   27.350032] Console: switching to colour frame buffer device 240x75
>[   27.450438] Console: switching to colour dummy device 80x25
>[   27.450577] [IGT] gem_basic: executing
>[   27.473441] [IGT] gem_basic: starting subtest create-fd-close
>[   27.474213] [IGT] gem_basic: exiting, ret=0
>[   27.525199] Console: switching to colour frame buffer device 240x75
>[   27.663626] Console: switching to colour dummy device 80x25
>[   27.663837] [IGT] gem_busy: executing
>[   27.680380] [IGT] gem_busy: starting subtest basic-busy-default
>[   27.706040] [IGT] gem_busy: exiting, ret=0
>[   27.758670] Console: switching to colour frame buffer device 240x75
>[   27.864788] Console: switching to colour dummy device 80x25
>[   27.865029] [IGT] gem_busy: executing
>[   27.889065] [IGT] gem_busy: starting subtest basic-hang-default
>[   37.745327] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   37.745436] drm/i915: Resetting chip after gpu hang
>[   37.745587] [drm:i915_gem_reset [i915]] context gem_busy[6169]/0 marked guilty (score 10) banned? no
>[   37.745621] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x38e
>[   37.745708] [drm] RC6 on
>[   37.759344] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   37.759362] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x38e, 0x0]
>[   37.759465] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   37.759514] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   37.759562] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   37.759608] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   37.759642] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[   37.759647] [drm] GuC firmware load skipped
>[   37.760108] [IGT] gem_busy: exiting, ret=0
>[   37.816854] Console: switching to colour frame buffer device 240x75
>[   38.150647] Console: switching to colour dummy device 80x25
>[   38.150759] [IGT] gem_close_race: executing
>[   38.165607] [IGT] gem_close_race: starting subtest basic-process
>[   38.174506] [IGT] gem_close_race: exiting, ret=0
>[   38.217204] Console: switching to colour frame buffer device 240x75
>[   38.348718] Console: switching to colour dummy device 80x25
>[   38.348838] [IGT] gem_close_race: executing
>[   38.375014] [IGT] gem_close_race: starting subtest basic-threads
>[   39.450132] [IGT] gem_close_race: exiting, ret=0
>[   39.501450] Console: switching to colour frame buffer device 240x75
>[   39.594363] Console: switching to colour dummy device 80x25
>[   39.594462] [IGT] gem_cpu_reloc: executing
>[   39.619199] [IGT] gem_cpu_reloc: starting subtest basic
>[   39.625980] [IGT] gem_cpu_reloc: exiting, ret=0
>[   39.668553] Console: switching to colour frame buffer device 240x75
>[   39.814448] Console: switching to colour dummy device 80x25
>[   39.814744] [IGT] gem_cs_tlb: executing
>[   39.842391] [IGT] gem_cs_tlb: starting subtest basic-default
>[   41.928947] [IGT] gem_cs_tlb: exiting, ret=0
>[   41.970161] Console: switching to colour frame buffer device 240x75
>[   42.278605] Console: switching to colour dummy device 80x25
>[   42.278701] [IGT] gem_ctx_basic: executing
>[   44.822418] [IGT] gem_ctx_basic: exiting, ret=0
>[   44.917172] Console: switching to colour frame buffer device 240x75
>[   45.248356] Console: switching to colour dummy device 80x25
>[   45.248460] [IGT] gem_ctx_create: executing
>[   45.289811] [IGT] gem_ctx_create: starting subtest basic
>[   45.290802] [IGT] gem_ctx_create: exiting, ret=0
>[   45.356303] Console: switching to colour frame buffer device 240x75
>[   45.443287] Console: switching to colour dummy device 80x25
>[   45.443393] [IGT] gem_ctx_create: executing
>[   45.466930] [IGT] gem_ctx_create: starting subtest basic-files
>[   50.519725] [IGT] gem_ctx_create: exiting, ret=0
>[   50.600914] Console: switching to colour frame buffer device 240x75
>[   50.831142] Console: switching to colour dummy device 80x25
>[   50.831436] [IGT] gem_ctx_exec: executing
>[   50.858365] [IGT] gem_ctx_exec: starting subtest basic
>[   50.861002] [IGT] gem_ctx_exec: exiting, ret=0
>[   50.901389] Console: switching to colour frame buffer device 240x75
>[   51.020451] Console: switching to colour dummy device 80x25
>[   51.020642] [IGT] gem_ctx_param: executing
>[   51.046398] [IGT] gem_ctx_param: starting subtest basic
>[   51.046714] [IGT] gem_ctx_param: exiting, ret=0
>[   51.084650] Console: switching to colour frame buffer device 240x75
>[   51.226161] Console: switching to colour dummy device 80x25
>[   51.226381] [IGT] gem_ctx_param: executing
>[   51.241067] [IGT] gem_ctx_param: starting subtest basic-default
>[   51.241304] [IGT] gem_ctx_param: exiting, ret=0
>[   51.295071] Console: switching to colour frame buffer device 240x75
>[   51.445247] Console: switching to colour dummy device 80x25
>[   51.445469] [IGT] gem_ctx_switch: executing
>[   51.467498] [IGT] gem_ctx_switch: starting subtest basic-default
>[   56.980085] [IGT] gem_ctx_switch: exiting, ret=0
>[   57.051315] Console: switching to colour frame buffer device 240x75
>[   57.175768] Console: switching to colour dummy device 80x25
>[   57.175880] [IGT] gem_ctx_switch: executing
>[   57.210025] [IGT] gem_ctx_switch: starting subtest basic-default-heavy
>[   75.368949] [IGT] gem_ctx_switch: exiting, ret=0
>[   75.452312] Console: switching to colour frame buffer device 240x75
>[   75.779623] Console: switching to colour dummy device 80x25
>[   75.779752] [IGT] gem_exec_basic: executing
>[   75.793882] [IGT] gem_exec_basic: starting subtest basic-blt
>[   75.796206] [IGT] gem_exec_basic: exiting, ret=0
>[   75.852728] Console: switching to colour frame buffer device 240x75
>[   75.979004] Console: switching to colour dummy device 80x25
>[   75.979174] [IGT] gem_exec_basic: executing
>[   76.006417] [IGT] gem_exec_basic: starting subtest basic-bsd
>[   76.009524] [IGT] gem_exec_basic: exiting, ret=0
>[   76.065572] Console: switching to colour frame buffer device 240x75
>[   76.212835] Console: switching to colour dummy device 80x25
>[   76.213209] [IGT] gem_exec_basic: executing
>[   76.233325] [IGT] gem_exec_basic: starting subtest basic-bsd1
>[   76.236605] [IGT] gem_exec_basic: exiting, ret=0
>[   76.286055] Console: switching to colour frame buffer device 240x75
>[   76.433831] Console: switching to colour dummy device 80x25
>[   76.434194] [IGT] gem_exec_basic: executing
>[   76.463706] [IGT] gem_exec_basic: starting subtest basic-bsd2
>[   76.467117] [IGT] gem_exec_basic: exiting, ret=0
>[   76.519432] Console: switching to colour frame buffer device 240x75
>[   76.672008] Console: switching to colour dummy device 80x25
>[   76.672302] [IGT] gem_exec_basic: executing
>[   76.707477] [IGT] gem_exec_basic: starting subtest basic-default
>[   76.710855] [IGT] gem_exec_basic: exiting, ret=0
>[   76.766283] Console: switching to colour frame buffer device 240x75
>[   76.889972] Console: switching to colour dummy device 80x25
>[   76.890109] [IGT] gem_exec_basic: executing
>[   76.917130] [IGT] gem_exec_basic: starting subtest basic-render
>[   76.920186] [IGT] gem_exec_basic: exiting, ret=0
>[   76.969386] Console: switching to colour frame buffer device 240x75
>[   77.113419] Console: switching to colour dummy device 80x25
>[   77.113526] [IGT] gem_exec_basic: executing
>[   77.131209] [IGT] gem_exec_basic: starting subtest basic-vebox
>[   77.132450] [IGT] gem_exec_basic: exiting, ret=0
>[   77.186150] Console: switching to colour frame buffer device 240x75
>[   77.327808] Console: switching to colour dummy device 80x25
>[   77.328114] [IGT] gem_exec_basic: executing
>[   77.356804] [IGT] gem_exec_basic: starting subtest gtt-blt
>[   77.359833] [IGT] gem_exec_basic: exiting, ret=0
>[   77.416786] Console: switching to colour frame buffer device 240x75
>[   77.565346] Console: switching to colour dummy device 80x25
>[   77.565654] [IGT] gem_exec_basic: executing
>[   77.594424] [IGT] gem_exec_basic: starting subtest gtt-bsd
>[   77.598144] [IGT] gem_exec_basic: exiting, ret=0
>[   77.652747] Console: switching to colour frame buffer device 240x75
>[   77.779049] Console: switching to colour dummy device 80x25
>[   77.779162] [IGT] gem_exec_basic: executing
>[   77.805721] [IGT] gem_exec_basic: starting subtest gtt-bsd1
>[   77.808332] [IGT] gem_exec_basic: exiting, ret=0
>[   77.852770] Console: switching to colour frame buffer device 240x75
>[   77.999500] Console: switching to colour dummy device 80x25
>[   77.999801] [IGT] gem_exec_basic: executing
>[   78.030532] [IGT] gem_exec_basic: starting subtest gtt-bsd2
>[   78.033975] [IGT] gem_exec_basic: exiting, ret=0
>[   78.086246] Console: switching to colour frame buffer device 240x75
>[   78.234058] Console: switching to colour dummy device 80x25
>[   78.234362] [IGT] gem_exec_basic: executing
>[   78.267624] [IGT] gem_exec_basic: starting subtest gtt-default
>[   78.271054] [IGT] gem_exec_basic: exiting, ret=0
>[   78.319491] Console: switching to colour frame buffer device 240x75
>[   78.446114] Console: switching to colour dummy device 80x25
>[   78.446260] [IGT] gem_exec_basic: executing
>[   78.474486] [IGT] gem_exec_basic: starting subtest gtt-render
>[   78.477836] [IGT] gem_exec_basic: exiting, ret=0
>[   78.536284] Console: switching to colour frame buffer device 240x75
>[   78.688295] Console: switching to colour dummy device 80x25
>[   78.688602] [IGT] gem_exec_basic: executing
>[   78.718556] [IGT] gem_exec_basic: starting subtest gtt-vebox
>[   78.722230] [IGT] gem_exec_basic: exiting, ret=0
>[   78.769527] Console: switching to colour frame buffer device 240x75
>[   78.915215] Console: switching to colour dummy device 80x25
>[   78.915440] [IGT] gem_exec_basic: executing
>[   78.946481] [IGT] gem_exec_basic: starting subtest readonly-blt
>[   78.949717] [IGT] gem_exec_basic: exiting, ret=0
>[   79.002852] Console: switching to colour frame buffer device 240x75
>[   79.125011] Console: switching to colour dummy device 80x25
>[   79.125143] [IGT] gem_exec_basic: executing
>[   79.148784] [IGT] gem_exec_basic: starting subtest readonly-bsd
>[   79.151815] [IGT] gem_exec_basic: exiting, ret=0
>[   79.202837] Console: switching to colour frame buffer device 240x75
>[   79.343862] Console: switching to colour dummy device 80x25
>[   79.344027] [IGT] gem_exec_basic: executing
>[   79.359088] [IGT] gem_exec_basic: starting subtest readonly-bsd1
>[   79.360453] [IGT] gem_exec_basic: exiting, ret=0
>[   79.419344] Console: switching to colour frame buffer device 240x75
>[   79.526926] Console: switching to colour dummy device 80x25
>[   79.527036] [IGT] gem_exec_basic: executing
>[   79.538150] [IGT] gem_exec_basic: starting subtest readonly-bsd2
>[   79.540780] [IGT] gem_exec_basic: exiting, ret=0
>[   79.586014] Console: switching to colour frame buffer device 240x75
>[   79.715807] Console: switching to colour dummy device 80x25
>[   79.716351] [IGT] gem_exec_basic: executing
>[   79.746618] [IGT] gem_exec_basic: starting subtest readonly-default
>[   79.750110] [IGT] gem_exec_basic: exiting, ret=0
>[   79.802871] Console: switching to colour frame buffer device 240x75
>[   79.951124] Console: switching to colour dummy device 80x25
>[   79.951330] [IGT] gem_exec_basic: executing
>[   79.981354] [IGT] gem_exec_basic: starting subtest readonly-render
>[   79.984602] [IGT] gem_exec_basic: exiting, ret=0
>[   80.036260] Console: switching to colour frame buffer device 240x75
>[   80.161100] Console: switching to colour dummy device 80x25
>[   80.161407] [IGT] gem_exec_basic: executing
>[   80.193348] [IGT] gem_exec_basic: starting subtest readonly-vebox
>[   80.196424] [IGT] gem_exec_basic: exiting, ret=0
>[   80.252998] Console: switching to colour frame buffer device 240x75
>[   80.406059] Console: switching to colour dummy device 80x25
>[   80.406362] [IGT] gem_exec_create: executing
>[   80.437745] [IGT] gem_exec_create: starting subtest basic
>[   85.741040] [IGT] gem_exec_create: exiting, ret=0
>[   85.790144] Console: switching to colour frame buffer device 240x75
>[   86.064815] Console: switching to colour dummy device 80x25
>[   86.065416] [IGT] gem_exec_fence: executing
>[   86.095684] [IGT] gem_exec_fence: starting subtest basic-busy-default
>[   86.136480] [IGT] gem_exec_fence: exiting, ret=0
>[   86.186639] Console: switching to colour frame buffer device 240x75
>[   86.301539] Console: switching to colour dummy device 80x25
>[   86.301841] [IGT] gem_exec_fence: executing
>[   86.330586] [IGT] gem_exec_fence: starting subtest basic-wait-default
>[   86.367459] [IGT] gem_exec_fence: exiting, ret=0
>[   86.407597] Console: switching to colour frame buffer device 240x75
>[   86.547797] Console: switching to colour dummy device 80x25
>[   86.548130] [IGT] gem_exec_fence: executing
>[   86.564613] [IGT] gem_exec_fence: starting subtest basic-await-default
>[   87.576201] [IGT] gem_exec_fence: exiting, ret=0
>[   87.636623] Console: switching to colour frame buffer device 240x75
>[   87.721825] Console: switching to colour dummy device 80x25
>[   87.721988] [IGT] gem_exec_fence: executing
>[   87.735041] [IGT] gem_exec_fence: starting subtest await-hang-default
>[   98.737311] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[   98.737433] drm/i915: Resetting chip after gpu hang
>[   98.738360] [drm:i915_gem_reset [i915]] context gem_exec_fence[6352]/0 marked guilty (score 10) banned? no
>[   98.738415] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x35037
>[   98.738644] [drm] RC6 on
>[   98.754513] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[   98.754536] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x35039, 0x0]
>[   98.754614] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[   98.754677] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[   98.754739] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[   98.754803] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[   98.754846] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[   98.754853] [drm] GuC firmware load skipped
>[   98.755437] [IGT] gem_exec_fence: exiting, ret=0
>[   98.803972] Console: switching to colour frame buffer device 240x75
>[   99.114905] Console: switching to colour dummy device 80x25
>[   99.115009] [IGT] gem_exec_fence: executing
>[   99.129548] [IGT] gem_exec_fence: starting subtest nb-await-default
>[  100.132198] [IGT] gem_exec_fence: exiting, ret=0
>[  100.185610] Console: switching to colour frame buffer device 240x75
>[  100.311354] Console: switching to colour dummy device 80x25
>[  100.311465] [IGT] gem_exec_flush: executing
>[  100.337392] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-cmd
>[  100.339302] [IGT] gem_exec_flush: exiting, ret=77
>[  100.387463] Console: switching to colour frame buffer device 240x75
>[  100.526658] Console: switching to colour dummy device 80x25
>[  100.526884] [IGT] gem_exec_flush: executing
>[  100.543205] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-uc
>[  106.215092] [IGT] gem_exec_flush: exiting, ret=0
>[  106.271080] Console: switching to colour frame buffer device 240x75
>[  106.422176] Console: switching to colour dummy device 80x25
>[  106.422467] [IGT] gem_exec_flush: executing
>[  106.446551] [IGT] gem_exec_flush: starting subtest basic-batch-kernel-default-wb
>[  112.127269] [IGT] gem_exec_flush: exiting, ret=0
>[  112.178716] Console: switching to colour frame buffer device 240x75
>[  112.432020] Console: switching to colour dummy device 80x25
>[  112.432321] [IGT] gem_exec_flush: executing
>[  112.453605] [IGT] gem_exec_flush: starting subtest basic-uc-pro-default
>[  117.862716] [IGT] gem_exec_flush: exiting, ret=0
>[  117.916725] Console: switching to colour frame buffer device 240x75
>[  118.068675] Console: switching to colour dummy device 80x25
>[  118.069037] [IGT] gem_exec_flush: executing
>[  118.098885] [IGT] gem_exec_flush: starting subtest basic-uc-prw-default
>[  123.502281] [IGT] gem_exec_flush: exiting, ret=0
>[  123.555015] Console: switching to colour frame buffer device 240x75
>[  123.824952] Console: switching to colour dummy device 80x25
>[  123.825255] [IGT] gem_exec_flush: executing
>[  123.857545] [IGT] gem_exec_flush: starting subtest basic-uc-ro-default
>[  129.268074] [IGT] gem_exec_flush: exiting, ret=0
>[  129.321982] Console: switching to colour frame buffer device 240x75
>[  129.589011] Console: switching to colour dummy device 80x25
>[  129.589313] [IGT] gem_exec_flush: executing
>[  129.609622] [IGT] gem_exec_flush: starting subtest basic-uc-rw-default
>[  135.013274] [IGT] gem_exec_flush: exiting, ret=0
>[  135.064637] Console: switching to colour frame buffer device 240x75
>[  135.343304] Console: switching to colour dummy device 80x25
>[  135.343615] [IGT] gem_exec_flush: executing
>[  135.375662] [IGT] gem_exec_flush: starting subtest basic-uc-set-default
>[  140.778698] [IGT] gem_exec_flush: exiting, ret=0
>[  140.822969] Console: switching to colour frame buffer device 240x75
>[  141.116515] Console: switching to colour dummy device 80x25
>[  141.116810] [IGT] gem_exec_flush: executing
>[  141.136591] [IGT] gem_exec_flush: starting subtest basic-wb-pro-default
>[  146.535838] [IGT] gem_exec_flush: exiting, ret=0
>[  146.590979] Console: switching to colour frame buffer device 240x75
>[  146.878170] Console: switching to colour dummy device 80x25
>[  146.878473] [IGT] gem_exec_flush: executing
>[  146.908777] [IGT] gem_exec_flush: starting subtest basic-wb-prw-default
>[  152.307073] [IGT] gem_exec_flush: exiting, ret=0
>[  152.362305] Console: switching to colour frame buffer device 240x75
>[  152.629436] Console: switching to colour dummy device 80x25
>[  152.629742] [IGT] gem_exec_flush: executing
>[  152.648538] [IGT] gem_exec_flush: starting subtest basic-wb-ro-before-default
>[  158.046017] [IGT] gem_exec_flush: exiting, ret=0
>[  158.100547] Console: switching to colour frame buffer device 240x75
>[  158.255251] Console: switching to colour dummy device 80x25
>[  158.255560] [IGT] gem_exec_flush: executing
>[  158.285520] [IGT] gem_exec_flush: starting subtest basic-wb-ro-default
>[  163.685613] [IGT] gem_exec_flush: exiting, ret=0
>[  163.724277] Console: switching to colour frame buffer device 240x75
>[  164.011979] Console: switching to colour dummy device 80x25
>[  164.012285] [IGT] gem_exec_flush: executing
>[  164.043745] [IGT] gem_exec_flush: starting subtest basic-wb-rw-before-default
>[  169.444628] [IGT] gem_exec_flush: exiting, ret=0
>[  169.493309] Console: switching to colour frame buffer device 240x75
>[  169.768528] Console: switching to colour dummy device 80x25
>[  169.768827] [IGT] gem_exec_flush: executing
>[  169.790238] [IGT] gem_exec_flush: starting subtest basic-wb-rw-default
>[  175.197708] [IGT] gem_exec_flush: exiting, ret=0
>[  175.248119] Console: switching to colour frame buffer device 240x75
>[  175.525731] Console: switching to colour dummy device 80x25
>[  175.526182] [IGT] gem_exec_flush: executing
>[  175.557745] [IGT] gem_exec_flush: starting subtest basic-wb-set-default
>[  180.957511] [IGT] gem_exec_flush: exiting, ret=0
>[  181.008577] Console: switching to colour frame buffer device 240x75
>[  181.161890] Console: switching to colour dummy device 80x25
>[  181.162224] [IGT] gem_exec_gttfill: executing
>[  181.193522] [IGT] gem_exec_gttfill: starting subtest basic
>[  181.193991] gem_exec_gttfil (6540): drop_caches: 4
>[  185.278072] [IGT] gem_exec_gttfill: exiting, ret=0
>[  185.325211] Console: switching to colour frame buffer device 240x75
>[  185.431636] Console: switching to colour dummy device 80x25
>[  185.431735] [IGT] gem_exec_nop: executing
>[  185.443334] [IGT] gem_exec_nop: starting subtest basic-parallel
>[  195.694867] [IGT] gem_exec_nop: exiting, ret=0
>[  195.742590] Console: switching to colour frame buffer device 240x75
>[  196.018292] Console: switching to colour dummy device 80x25
>[  196.018601] [IGT] gem_exec_nop: executing
>[  196.047545] [IGT] gem_exec_nop: starting subtest basic-series
>[  206.315062] [IGT] gem_exec_nop: exiting, ret=0
>[  206.373833] Console: switching to colour frame buffer device 240x75
>[  206.743406] Console: switching to colour dummy device 80x25
>[  206.743514] [IGT] gem_exec_parallel: executing
>[  206.770285] [IGT] gem_exec_parallel: starting subtest basic
>[  207.564101] [IGT] gem_exec_parallel: exiting, ret=0
>[  207.610153] Console: switching to colour frame buffer device 240x75
>[  207.772469] Console: switching to colour dummy device 80x25
>[  207.772774] [IGT] gem_exec_parse: executing
>[  207.802657] [IGT] gem_exec_parse: exiting, ret=77
>[  207.826849] Console: switching to colour frame buffer device 240x75
>[  207.977453] Console: switching to colour dummy device 80x25
>[  207.977766] [IGT] gem_exec_parse: executing
>[  208.014604] [IGT] gem_exec_parse: exiting, ret=77
>[  208.043497] Console: switching to colour frame buffer device 240x75
>[  208.168542] Console: switching to colour dummy device 80x25
>[  208.168805] [IGT] gem_exec_reloc: executing
>[  208.195513] [IGT] gem_exec_reloc: starting subtest basic-cpu
>[  208.196889] [IGT] gem_exec_reloc: exiting, ret=0
>[  208.243504] Console: switching to colour frame buffer device 240x75
>[  208.392664] Console: switching to colour dummy device 80x25
>[  208.393036] [IGT] gem_exec_reloc: executing
>[  208.422516] [IGT] gem_exec_reloc: starting subtest basic-gtt
>[  208.424360] [IGT] gem_exec_reloc: exiting, ret=0
>[  208.476848] Console: switching to colour frame buffer device 240x75
>[  208.632254] Console: switching to colour dummy device 80x25
>[  208.632562] [IGT] gem_exec_reloc: executing
>[  208.661534] [IGT] gem_exec_reloc: starting subtest basic-softpin
>[  208.662977] [IGT] gem_exec_reloc: exiting, ret=0
>[  208.710232] Console: switching to colour frame buffer device 240x75
>[  208.851676] Console: switching to colour dummy device 80x25
>[  208.852183] [IGT] gem_exec_store: executing
>[  208.880886] [IGT] gem_exec_store: starting subtest basic-all
>[  208.918049] [IGT] gem_exec_store: exiting, ret=0
>[  208.960327] Console: switching to colour frame buffer device 240x75
>[  209.071612] Console: switching to colour dummy device 80x25
>[  209.071986] [IGT] gem_exec_store: executing
>[  209.100607] [IGT] gem_exec_store: starting subtest basic-blt
>[  209.140829] [IGT] gem_exec_store: exiting, ret=0
>[  209.193558] Console: switching to colour frame buffer device 240x75
>[  209.344877] Console: switching to colour dummy device 80x25
>[  209.345135] [IGT] gem_exec_store: executing
>[  209.357712] [IGT] gem_exec_store: starting subtest basic-bsd
>[  209.406635] [IGT] gem_exec_store: exiting, ret=0
>[  209.460280] Console: switching to colour frame buffer device 240x75
>[  209.582780] Console: switching to colour dummy device 80x25
>[  209.583236] [IGT] gem_exec_store: executing
>[  209.615387] [IGT] gem_exec_store: starting subtest basic-bsd1
>[  209.655631] [IGT] gem_exec_store: exiting, ret=0
>[  209.710269] Console: switching to colour frame buffer device 240x75
>[  209.861735] Console: switching to colour dummy device 80x25
>[  209.862183] [IGT] gem_exec_store: executing
>[  209.890434] [IGT] gem_exec_store: starting subtest basic-bsd2
>[  209.930643] [IGT] gem_exec_store: exiting, ret=0
>[  209.977095] Console: switching to colour frame buffer device 240x75
>[  210.117440] Console: switching to colour dummy device 80x25
>[  210.117544] [IGT] gem_exec_store: executing
>[  210.132139] [IGT] gem_exec_store: starting subtest basic-default
>[  210.173450] [IGT] gem_exec_store: exiting, ret=0
>[  210.227400] Console: switching to colour frame buffer device 240x75
>[  210.365948] Console: switching to colour dummy device 80x25
>[  210.366247] [IGT] gem_exec_store: executing
>[  210.397685] [IGT] gem_exec_store: starting subtest basic-render
>[  210.438098] [IGT] gem_exec_store: exiting, ret=0
>[  210.494306] Console: switching to colour frame buffer device 240x75
>[  210.647235] Console: switching to colour dummy device 80x25
>[  210.647405] [IGT] gem_exec_store: executing
>[  210.661777] [IGT] gem_exec_store: starting subtest basic-vebox
>[  210.710669] [IGT] gem_exec_store: exiting, ret=0
>[  210.761216] Console: switching to colour frame buffer device 240x75
>[  210.916592] Console: switching to colour dummy device 80x25
>[  210.916984] [IGT] gem_exec_suspend: executing
>[  210.952614] [IGT] gem_exec_suspend: starting subtest basic
>[  211.106799] [IGT] gem_exec_suspend: exiting, ret=0
>[  211.144432] Console: switching to colour frame buffer device 240x75
>[  211.248368] Console: switching to colour dummy device 80x25
>[  211.248465] [IGT] gem_exec_suspend: executing
>[  211.258110] [IGT] gem_exec_suspend: starting subtest basic-S3
>[  212.186094] PM: Syncing filesystems ... done.
>[  212.200358] PM: Preparing system for sleep (mem)
>[  212.213364] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  212.215449] Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done.
>[  212.217487] PM: Suspending system (mem)
>[  212.217834] Suspending console(s) (use no_console_suspend to debug)
>[  212.222518] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  212.226738] sd 0:0:0:0: [sda] Stopping disk
>[  212.227127] e1000e: EEE TX LPI TIMER: 00000011
>[  212.231335] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  212.231407] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  212.231448] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  212.231489] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  212.249391] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  212.249449] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  212.249510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  212.249573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  212.249621] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  212.249676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  212.249730] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  212.249778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  212.249827] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  212.249873] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  212.249918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  212.249966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  212.250011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  212.250018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  212.250063] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  212.250106] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  212.250147] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  212.250187] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  212.250226] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  212.250278] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  212.250321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  212.250366] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  212.250407] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  212.250448] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  212.250487] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  212.250549] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  212.250596] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  212.250649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  212.250707] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  212.250754] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  212.250803] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  212.250849] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  212.250892] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  212.250960] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  212.251002] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  212.251042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  212.251049] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  212.251089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  212.251095] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  212.251137] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  212.251178] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  212.251217] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  212.251258] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  212.251297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  212.251347] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  212.251388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  212.251431] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  212.251472] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  212.251510] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  212.251550] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  212.251614] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  212.251671] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  212.251719] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  212.251768] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  212.251814] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  212.253009] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  212.264341] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  212.264459] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  212.264546] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  212.264723] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  212.264826] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  212.277473] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  212.277502] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  212.277553] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  212.278015] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  212.278040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  212.278067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  212.278089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  212.278110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  212.278131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  212.278151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  212.278174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  212.278193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  212.278212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  212.278230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  212.278248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  212.278265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  212.278283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  212.278304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  212.278326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  212.278348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  212.278368] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  212.278417] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  212.278441] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  212.278467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  212.278493] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  212.278517] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  212.278543] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  212.278563] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  212.281340] PM: suspend of devices complete after 60.944 msecs
>[  212.282781] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  212.282807] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  212.282825] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  212.282842] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  212.282858] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  212.282874] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  212.282890] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  212.282925] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  212.282941] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  212.282989] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  212.283005] [drm:intel_power_well_disable [i915]] disabling DC off
>[  212.283022] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  212.283037] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  212.283456] [drm:intel_power_well_disable [i915]] disabling always-on
>[  212.283473] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  212.283877] [drm:intel_update_cdclk [i915]] Current CD clock rate: 24000 kHz, VCO: 0 kHz, ref: 24000 kHz
>[  212.283893] [drm:intel_power_well_disable [i915]] disabling MISC IO power well
>[  212.283927] [drm:skl_set_power_well [i915]] Disabling MISC IO power well
>[  212.283945] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for MISC IO power well forced on by DMC
>[  212.283963] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  212.283984] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  212.296077] PM: late suspend of devices complete after 14.734 msecs
>[  212.311258] e1000e 0000:00:1f.6: System wakeup enabled by ACPI
>[  212.311766] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  212.335946] PM: noirq suspend of devices complete after 39.866 msecs
>[  212.336248] ACPI: Preparing to enter system sleep state S3
>[  212.348226] PM: Saving platform NVS memory
>[  212.348412] Disabling non-boot CPUs ...
>[  212.364732] smpboot: CPU 1 is now offline
>[  212.381333] smpboot: CPU 2 is now offline
>[  212.401770] smpboot: CPU 3 is now offline
>[  212.418454] Broke affinity for irq 123
>[  212.420432] smpboot: CPU 4 is now offline
>[  212.439285] Broke affinity for irq 123
>[  212.440408] smpboot: CPU 5 is now offline
>[  212.459363] Broke affinity for irq 121
>[  212.459368] Broke affinity for irq 123
>[  212.460499] smpboot: CPU 6 is now offline
>[  212.474091] Broke affinity for irq 8
>[  212.474106] Broke affinity for irq 9
>[  212.474119] Broke affinity for irq 120
>[  212.474123] Broke affinity for irq 121
>[  212.474126] Broke affinity for irq 123
>[  212.475328] smpboot: CPU 7 is now offline
>[  212.479675] ACPI: Low-level resume complete
>[  212.479836] PM: Restoring platform NVS memory
>[  212.480748] Suspended for 15.093 seconds
>[  212.481383] Enabling non-boot CPUs ...
>[  212.481701] x86: Booting SMP configuration:
>[  212.481702] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  212.483513]  cache: parent cpu1 should not be sleeping
>[  212.484797] CPU1 is up
>[  212.484874] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  212.486045]  cache: parent cpu2 should not be sleeping
>[  212.487204] CPU2 is up
>[  212.487282] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  212.488441]  cache: parent cpu3 should not be sleeping
>[  212.489708] CPU3 is up
>[  212.489790] smpboot: Booting Node 0 Processor 4 APIC 0x1
>[  212.491109]  cache: parent cpu4 should not be sleeping
>[  212.492477] CPU4 is up
>[  212.492565] smpboot: Booting Node 0 Processor 5 APIC 0x3
>[  212.493829]  cache: parent cpu5 should not be sleeping
>[  212.495197] CPU5 is up
>[  212.495288] smpboot: Booting Node 0 Processor 6 APIC 0x5
>[  212.496556]  cache: parent cpu6 should not be sleeping
>[  212.498032] CPU6 is up
>[  212.498121] smpboot: Booting Node 0 Processor 7 APIC 0x7
>[  212.499396]  cache: parent cpu7 should not be sleeping
>[  212.500883] CPU7 is up
>[  212.507107] ACPI: Waking up from system sleep state S3
>[  212.594402] acpi LNXPOWER:16: Turning OFF
>[  212.594894] acpi LNXPOWER:15: Turning OFF
>[  212.595373] acpi LNXPOWER:14: Turning OFF
>[  212.595864] acpi LNXPOWER:13: Turning OFF
>[  212.596344] acpi LNXPOWER:12: Turning OFF
>[  212.596833] acpi LNXPOWER:11: Turning OFF
>[  212.597312] acpi LNXPOWER:10: Turning OFF
>[  212.597828] acpi LNXPOWER:0f: Turning OFF
>[  212.598308] acpi LNXPOWER:0e: Turning OFF
>[  212.598798] acpi LNXPOWER:0d: Turning OFF
>[  212.599278] acpi LNXPOWER:0c: Turning OFF
>[  212.599768] acpi LNXPOWER:0b: Turning OFF
>[  212.600248] acpi LNXPOWER:0a: Turning OFF
>[  212.600738] acpi LNXPOWER:09: Turning OFF
>[  212.601217] acpi LNXPOWER:08: Turning OFF
>[  212.601706] acpi LNXPOWER:07: Turning OFF
>[  212.602186] acpi LNXPOWER:06: Turning OFF
>[  212.602666] acpi LNXPOWER:05: Turning OFF
>[  212.603155] acpi LNXPOWER:04: Turning OFF
>[  212.603634] acpi LNXPOWER:03: Turning OFF
>[  212.616971] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  212.633024] PM: noirq resume of devices complete after 29.091 msecs
>[  212.633978] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  212.634065] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  212.634105] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  212.634197] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  212.636690] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  212.638162] [drm:intel_power_well_enable [i915]] enabling always-on
>[  212.638185] [drm:intel_power_well_enable [i915]] enabling DC off
>[  212.638209] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  212.638241] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  212.638267] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  212.638291] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  212.638313] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  212.638337] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  212.638358] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  212.638382] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  212.638403] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  212.638426] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  212.638450] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  212.685253] PM: early resume of devices complete after 52.130 msecs
>[  212.686248] e1000e 0000:00:1f.6: System wakeup disabled by ACPI
>[  212.686733] sd 0:0:0:0: [sda] Starting disk
>[  212.687519] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  212.687580] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  212.687610] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  212.697385] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  212.697429] [drm:intel_opregion_setup [i915]] ASLE supported
>[  212.697461] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  212.697491] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  212.699488] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  212.706422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.714929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.723377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.731804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.740243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.748667] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.757092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.765510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.773929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.782353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.790773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.799192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.807609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.816031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.824450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.832870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.841289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.849707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.858123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.866541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.874961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.883379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.891798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.900218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.908637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.917052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.925476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.933892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.942310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.950728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.959151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.967569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  212.967578] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  212.967594] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH down
>[  212.968305] [drm:lspcon_wait_mode [i915]] Current LSPCON mode LS
>[  212.994294] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  212.995653] [drm:drm_lspcon_set_mode] LSPCON mode changed to PCON
>[  212.995704] [drm:lspcon_change_mode.constprop.4 [i915]] LSPCON mode changed done
>[  212.995775] [drm:lspcon_resume [i915]] LSPCON resume success
>[  212.996289] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  212.996441] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  212.996568] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  212.996820] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  212.996957] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  212.996964] ata1.00: supports DRM functions and may not be fully accessible
>[  212.997046] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  212.997060] [drm] GuC firmware load skipped
>[  212.997414] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  212.997628] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  212.997681] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  212.997769] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  212.997815] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  212.997857] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  212.997898] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  212.997937] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  212.997978] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  212.998017] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  212.998050] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  212.998083] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  212.998115] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  212.998153] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  212.998186] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  212.998218] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  212.998249] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  212.998286] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  212.998318] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  212.998349] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  212.998380] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  212.998420] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  212.998458] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  212.998497] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  212.998535] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  212.998573] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  212.998611] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  212.998669] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  212.998741] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  212.998779] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  212.998815] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  212.998821] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  212.998856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  212.998861] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  212.998897] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  212.998933] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  212.998969] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  212.999003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  212.999036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  212.999077] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  212.999111] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  212.999147] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  212.999181] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  212.999216] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  212.999248] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  212.999285] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  212.999318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  212.999349] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  212.999380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  212.999385] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  212.999416] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  212.999421] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  212.999453] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  212.999485] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  212.999517] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  212.999548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  212.999578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  212.999619] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  212.999650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  212.999684] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  212.999741] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  212.999773] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  212.999804] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  212.999839] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  212.999869] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  212.999899] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  212.999929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  212.999934] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  212.999964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  212.999968] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  213.000000] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  213.000030] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  213.000059] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  213.000089] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  213.000119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  213.000159] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  213.000191] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  213.000221] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  213.000251] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  213.000281] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  213.000321] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  213.000474] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  213.000537] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  213.000574] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  213.000609] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  213.000643] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  213.000677] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  213.000740] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  213.000775] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  213.000809] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  213.000920] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  213.000955] [drm:intel_power_well_disable [i915]] disabling DC off
>[  213.000991] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  213.001022] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  213.001460] [drm:intel_power_well_disable [i915]] disabling always-on
>[  213.001571] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  213.001613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  213.001659] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  213.001736] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  213.001776] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  213.001819] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  213.001860] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  213.001898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  213.001936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  213.001971] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  213.002005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  213.002011] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  213.002044] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  213.002049] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  213.002084] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  213.002117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  213.002150] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  213.002184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  213.002216] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  213.002257] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  213.002292] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  213.002348] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  213.002381] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  213.002413] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  213.002445] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  213.002495] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  213.002533] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  213.002576] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  213.002626] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  213.002665] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  213.002705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  213.002769] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  213.002804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  213.002878] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  213.002919] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  213.002951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  213.002957] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  213.002989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  213.002994] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  213.003028] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  213.003060] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  213.003092] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  213.003124] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  213.003155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  213.003196] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  213.003229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  213.003263] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  213.003295] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  213.003327] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  213.003358] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  213.003400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  213.003448] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  213.003489] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  213.003530] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  213.003568] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  213.003605] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  213.004674] [drm:intel_power_well_enable [i915]] enabling always-on
>[  213.004730] [drm:intel_power_well_enable [i915]] enabling DC off
>[  213.005056] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  213.005058] ata1.00: supports DRM functions and may not be fully accessible
>[  213.005122] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  213.005155] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  213.005305] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  213.005354] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  213.005416] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  213.005466] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  213.005540] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  213.006545] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  213.006575] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  213.008677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  213.008754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  213.008792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  213.008828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  213.008864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  213.008897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  213.008932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  213.008963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  213.008995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  213.009026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  213.009057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  213.009088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  213.009118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  213.009153] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  213.009190] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  213.009226] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  213.009261] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  213.009302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  213.009341] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  213.009377] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  213.009413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  213.009473] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  213.009511] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  213.010707] ata1.00: configured for UDMA/133
>[  213.013522] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  213.015001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  213.015044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  213.015081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  213.015122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  213.020438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  213.020478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  213.025799] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  213.028486] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a5a41bf8
>[  213.029668] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  213.029876] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  213.029916] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  213.030085] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  213.030123] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  213.033602] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  213.033645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  213.033682] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  213.033756] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  213.034584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  213.034621] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  213.034655] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  213.035509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  213.035545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  213.035579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  213.036390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  213.036427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  213.037553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  213.039944] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a5a44a88
>[  213.041088] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  213.041157] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  213.041194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  213.041269] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  213.058039] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  213.058097] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  213.058190] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  213.058289] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  213.058341] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  213.058425] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  213.058473] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  213.058773] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  213.059515] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  213.070406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.079017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.087644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.096297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.104906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.113516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.122153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.130760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.133543] PM: resume of devices complete after 448.284 msecs
>[  213.136810] PM: Finishing wakeup.
>[  213.136814] Restarting tasks ... done.
>[  213.142349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.150964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.159535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.168069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.176577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.185070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.191227] video LNXVIDEO:00: Restoring backlight state
>[  213.192417] [drm] RC6 on
>[  213.193548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.202022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.210482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.218939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.227398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.235868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.244380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.252918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.261452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.269974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.278508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.287033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.295564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.304110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.312687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.321224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.329753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.338280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  213.338300] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  213.338304] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  213.338342] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  213.339348] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  213.341036] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  213.341068] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  213.341096] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  213.341117] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  213.341979] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  213.342788] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  213.343703] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  213.343734] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  213.343768] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  213.343832] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  213.345894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  213.345921] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  213.348128] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  213.348133] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  213.350370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  213.350385] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  213.352632] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  213.352636] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  213.352639] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  213.352655] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  213.353231] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  213.353583] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  213.353643] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  213.353665] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  213.353687] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  213.354184] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  213.354509] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  213.354913] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  213.354941] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  213.357152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  213.357169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  213.359401] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  213.359406] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  213.361650] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  213.361668] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  213.363861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  213.363865] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  213.363868] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  214.212158] [IGT] gem_exec_suspend: exiting, ret=0
>[  214.264589] Console: switching to colour frame buffer device 240x75
>[  214.419386] Console: switching to colour dummy device 80x25
>[  214.419646] [IGT] gem_exec_suspend: executing
>[  214.448071] [IGT] gem_exec_suspend: starting subtest basic-S4-devices
>[  215.465609] PM: Syncing filesystems ... 
>[  215.483061] done.
>[  215.483066] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  215.485669] PM: Marking nosave pages: [mem 0x00000000-0x00000fff]
>[  215.485705] PM: Marking nosave pages: [mem 0x00058000-0x00058fff]
>[  215.485707] PM: Marking nosave pages: [mem 0x0009f000-0x000fffff]
>[  215.485712] PM: Marking nosave pages: [mem 0x3310a000-0x33154fff]
>[  215.485716] PM: Marking nosave pages: [mem 0x3a1c2000-0x3b2fdfff]
>[  215.485870] PM: Marking nosave pages: [mem 0x3b2ff000-0xffffffff]
>[  215.489490] PM: Basic memory bitmaps created
>[  215.492396] PM: Preallocating image memory... done (allocated 227826 pages)
>[  215.784213] PM: Allocated 911304 kbytes in 0.29 seconds (3142.42 MB/s)
>[  215.784213] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  215.786615] Suspending console(s) (use no_console_suspend to debug)
>[  215.846219] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  215.846280] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  215.846331] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  215.846385] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  215.866175] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  215.866191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  215.866207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  215.866224] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  215.866237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  215.866251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  215.866266] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  215.866279] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  215.866292] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  215.866304] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  215.866315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  215.866319] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  215.866330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  215.866332] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  215.866343] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  215.866355] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  215.866365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  215.866376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  215.866387] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  215.866400] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  215.866412] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  215.866423] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  215.866434] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  215.866445] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  215.866455] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  215.866471] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  215.866483] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  215.866497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  215.866513] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  215.866526] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  215.866539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  215.866551] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  215.866562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  215.866573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  215.866584] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  215.866595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  215.866597] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  215.866607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  215.866609] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  215.866619] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  215.866630] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  215.866640] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  215.866650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  215.866660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  215.866675] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  215.866726] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  215.866758] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  215.866789] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  215.866800] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  215.866810] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  215.866827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  215.866843] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  215.866857] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  215.866870] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  215.866882] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  215.866942] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  215.884095] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  215.884123] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  215.884142] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  215.884184] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  215.884211] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  215.892902] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  215.892930] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  215.892981] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  215.893392] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  215.893416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  215.893443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  215.893464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  215.893485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  215.893504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  215.893523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  215.893544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  215.893562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  215.893579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  215.893597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  215.893614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  215.893630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  215.893647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  215.893666] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  215.893713] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  215.893735] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  215.893755] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  215.893797] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  215.893820] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  215.893845] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  215.893869] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  215.893892] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  215.893916] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  215.893935] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  215.897918] PM: freeze of devices complete after 111.279 msecs
>[  215.897919] hibernation debug: Waiting for 5 seconds.
>[  221.092049] usb usb1: root hub lost power or was reset
>[  221.092050] usb usb2: root hub lost power or was reset
>[  221.093291] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  221.093326] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  221.093341] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  221.093640] sd 0:0:0:0: [sda] Starting disk
>[  221.100326] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  221.100789] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  221.100808] [drm:intel_opregion_setup [i915]] ASLE supported
>[  221.100823] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  221.100836] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  221.111421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.119846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.128267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.136694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.145120] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.153540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.161958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.170375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.178879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.187298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.195726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.204146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.212567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.220989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.229406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.237828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.246245] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.254663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.263111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  221.263833] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  221.263880] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  221.264608] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  221.281516] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  221.281667] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  221.281816] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  221.281932] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  221.282045] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  221.282157] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  221.282240] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  221.282252] [drm] GuC firmware load skipped
>[  221.282551] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  221.282769] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  221.282817] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  221.282862] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  221.282906] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  221.282945] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  221.282983] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  221.283019] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  221.283056] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  221.283092] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  221.283124] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  221.283155] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  221.283186] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  221.283221] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  221.283251] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  221.283281] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  221.283311] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  221.283345] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  221.283375] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  221.283405] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  221.283434] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  221.283471] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  221.283506] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  221.283542] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  221.283578] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  221.283615] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  221.283650] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  221.283691] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  221.283758] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  221.283793] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  221.283827] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  221.283833] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  221.283867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  221.283871] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  221.283905] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  221.283939] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  221.283972] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  221.284004] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  221.284036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  221.284074] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  221.284106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  221.284140] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  221.284172] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  221.284203] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  221.284233] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  221.284267] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  221.284297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  221.284326] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  221.284355] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  221.284360] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  221.284389] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  221.284393] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  221.284423] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  221.284452] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  221.284482] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  221.284511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  221.284540] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  221.284577] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  221.284608] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  221.284639] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  221.284670] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  221.284721] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  221.284750] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  221.284783] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  221.284812] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  221.284841] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  221.284869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  221.284874] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  221.284902] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  221.284906] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  221.284935] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  221.284964] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  221.284993] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  221.285021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  221.285049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  221.285086] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  221.285117] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  221.285146] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  221.285176] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  221.285205] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  221.285242] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  221.285383] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  221.285417] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  221.285451] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  221.285482] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  221.285514] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  221.285544] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  221.285576] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  221.285607] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  221.285639] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  221.285686] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  221.285739] [drm:intel_power_well_disable [i915]] disabling DC off
>[  221.285773] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  221.285802] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  221.286240] [drm:intel_power_well_disable [i915]] disabling always-on
>[  221.286328] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  221.286365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  221.286407] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  221.286452] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  221.286487] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  221.286526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  221.286564] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  221.286599] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  221.286634] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  221.286668] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  221.286753] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  221.286758] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  221.286790] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  221.286795] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  221.286827] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  221.286858] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  221.286889] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  221.286919] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  221.286949] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  221.286987] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  221.287019] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  221.287051] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  221.287082] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  221.287112] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  221.287141] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  221.287186] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  221.287221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  221.287261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  221.287304] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  221.287339] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  221.287376] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  221.287409] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  221.287441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  221.287473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  221.287503] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  221.287532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  221.287537] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  221.287566] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  221.287571] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  221.287601] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  221.287631] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  221.287660] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  221.287689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  221.287739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  221.287776] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  221.287806] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  221.287836] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  221.287865] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  221.287894] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  221.287922] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  221.287959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  221.288003] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  221.288040] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  221.288076] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  221.288110] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  221.288349] [drm:intel_power_well_enable [i915]] enabling always-on
>[  221.288378] [drm:intel_power_well_enable [i915]] enabling DC off
>[  221.288667] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  221.288742] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  221.288773] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  221.288855] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  221.288893] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  221.288932] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  221.288962] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  221.289010] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  221.289231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  221.289260] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  221.289305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  221.289346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  221.289381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  221.289416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  221.289449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  221.289483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  221.289517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  221.289549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  221.289579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  221.289609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  221.289639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  221.289668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  221.289725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  221.289760] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  221.289796] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  221.289831] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  221.289865] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  221.289904] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  221.289942] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  221.289977] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  221.290011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  221.290056] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  221.290094] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  221.293614] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  221.295084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  221.295123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  221.295160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  221.295199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  221.300518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  221.300556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  221.305878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  221.308368] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804452cc138
>[  221.309693] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  221.309789] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  221.309827] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  221.309950] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  221.309986] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  221.313359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  221.313394] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  221.313426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  221.313460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  221.314283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  221.314316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  221.314348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  221.315187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  221.315220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  221.315252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  221.316044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  221.316078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  221.317326] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  221.318993] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804452cca88
>[  221.320150] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  221.320214] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  221.320248] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  221.320296] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  221.337034] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  221.337087] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  221.337174] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  221.337266] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  221.337314] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  221.337393] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  221.337436] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  221.337752] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  221.337850] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  221.348321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.356921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.365583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.374170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.382765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.391359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.399952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.402606] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  221.405210] ata1.00: supports DRM functions and may not be fully accessible
>[  221.408517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.413268] ata1.00: supports DRM functions and may not be fully accessible
>[  221.417037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.418559] ata1.00: configured for UDMA/133
>[  221.425533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.434008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.442470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.450926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.459382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.467836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.473947] usb 1-9: reset full-speed USB device number 2 using xhci_hcd
>[  221.476293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.484749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.493207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.501662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.510136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.518592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.527049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.535506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.543962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.552418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.560871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.569327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.577786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.586243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.594700] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.603156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.611612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  221.611621] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  221.611624] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  221.611640] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  221.612477] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  221.614005] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  221.614022] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  221.614036] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  221.614049] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  221.614850] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  221.615561] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  221.616372] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  221.616388] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  221.616423] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  221.616458] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  221.618758] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  221.618774] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  221.621035] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  221.621039] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  221.623299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  221.623314] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  221.625572] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  221.625576] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  221.625578] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  221.625594] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  221.626051] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  221.626370] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  221.626386] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  221.626418] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  221.626431] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  221.626843] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  221.627162] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  221.627519] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  221.627536] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  221.629861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  221.629882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  221.632175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  221.632178] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  221.634438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  221.634453] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  221.636709] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  221.636726] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  221.636728] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  221.643738] PM: restore of devices complete after 552.155 msecs
>[  221.645222] PM: Image restored successfully.
>[  221.645492] PM: Basic memory bitmaps freed
>[  221.645493] Restarting tasks ... done.
>[  221.690804] video LNXVIDEO:00: Restoring backlight state
>[  221.691149] [drm] RC6 on
>[  222.694082] [IGT] gem_exec_suspend: exiting, ret=0
>[  222.754062] Console: switching to colour frame buffer device 240x75
>[  222.898134] Console: switching to colour dummy device 80x25
>[  222.898386] [IGT] gem_flink_basic: executing
>[  222.927257] [IGT] gem_flink_basic: starting subtest bad-flink
>[  222.927383] [IGT] gem_flink_basic: exiting, ret=0
>[  222.961619] Console: switching to colour frame buffer device 240x75
>[  223.085817] Console: switching to colour dummy device 80x25
>[  223.085921] [IGT] gem_flink_basic: executing
>[  223.111165] [IGT] gem_flink_basic: starting subtest bad-open
>[  223.111306] [IGT] gem_flink_basic: exiting, ret=0
>[  223.145103] Console: switching to colour frame buffer device 240x75
>[  223.264755] Console: switching to colour dummy device 80x25
>[  223.265030] [IGT] gem_flink_basic: executing
>[  223.294152] [IGT] gem_flink_basic: starting subtest basic
>[  223.294373] [IGT] gem_flink_basic: exiting, ret=0
>[  223.328561] Console: switching to colour frame buffer device 240x75
>[  223.477750] Console: switching to colour dummy device 80x25
>[  223.477960] [IGT] gem_flink_basic: executing
>[  223.502243] [IGT] gem_flink_basic: starting subtest double-flink
>[  223.502441] [IGT] gem_flink_basic: exiting, ret=0
>[  223.537445] Console: switching to colour frame buffer device 240x75
>[  223.683301] Console: switching to colour dummy device 80x25
>[  223.683421] [IGT] gem_flink_basic: executing
>[  223.696368] [IGT] gem_flink_basic: starting subtest flink-lifetime
>[  223.696724] [IGT] gem_flink_basic: exiting, ret=0
>[  223.729021] Console: switching to colour frame buffer device 240x75
>[  223.871069] Console: switching to colour dummy device 80x25
>[  223.871169] [IGT] gem_linear_blits: executing
>[  223.883087] [IGT] gem_linear_blits: starting subtest basic
>[  223.906165] [IGT] gem_linear_blits: exiting, ret=0
>[  223.937653] Console: switching to colour frame buffer device 240x75
>[  224.104425] Console: switching to colour dummy device 80x25
>[  224.104634] [IGT] gem_mmap: executing
>[  224.132426] [IGT] gem_mmap: starting subtest basic
>[  224.133265] [IGT] gem_mmap: exiting, ret=0
>[  224.187652] Console: switching to colour frame buffer device 240x75
>[  224.342758] Console: switching to colour dummy device 80x25
>[  224.343054] [IGT] gem_mmap: executing
>[  224.371284] [IGT] gem_mmap: starting subtest basic-small-bo
>[  224.584416] [IGT] gem_mmap: exiting, ret=0
>[  224.621044] Console: switching to colour frame buffer device 240x75
>[  224.739078] e1000e: eno1 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  224.766667] Console: switching to colour dummy device 80x25
>[  224.766988] [IGT] gem_mmap_gtt: executing
>[  224.796946] [IGT] gem_mmap_gtt: starting subtest basic
>[  224.797246] [IGT] gem_mmap_gtt: exiting, ret=0
>[  224.829646] Console: switching to colour frame buffer device 240x75
>[  224.967173] Console: switching to colour dummy device 80x25
>[  224.967350] [IGT] gem_mmap_gtt: executing
>[  224.993179] [IGT] gem_mmap_gtt: starting subtest basic-copy
>[  225.178977] [IGT] gem_mmap_gtt: exiting, ret=0
>[  225.237385] Console: switching to colour frame buffer device 240x75
>[  225.340348] Console: switching to colour dummy device 80x25
>[  225.340470] [IGT] gem_mmap_gtt: executing
>[  225.367314] [IGT] gem_mmap_gtt: starting subtest basic-read
>[  225.408098] [IGT] gem_mmap_gtt: exiting, ret=0
>[  225.470740] Console: switching to colour frame buffer device 240x75
>[  225.626804] Console: switching to colour dummy device 80x25
>[  225.627107] [IGT] gem_mmap_gtt: executing
>[  225.662360] [IGT] gem_mmap_gtt: starting subtest basic-read-no-prefault
>[  225.662619] Setting dangerous option prefault_disable - tainting kernel
>[  225.704830] Setting dangerous option prefault_disable - tainting kernel
>[  225.705021] [IGT] gem_mmap_gtt: exiting, ret=0
>[  225.705105] Setting dangerous option prefault_disable - tainting kernel
>[  225.763858] Console: switching to colour frame buffer device 240x75
>[  225.898593] Console: switching to colour dummy device 80x25
>[  225.898750] [IGT] gem_mmap_gtt: executing
>[  225.919901] [IGT] gem_mmap_gtt: starting subtest basic-read-write
>[  225.928269] [IGT] gem_mmap_gtt: exiting, ret=0
>[  225.997609] Console: switching to colour frame buffer device 240x75
>[  226.114575] Console: switching to colour dummy device 80x25
>[  226.114722] [IGT] gem_mmap_gtt: executing
>[  226.140271] [IGT] gem_mmap_gtt: starting subtest basic-read-write-distinct
>[  226.165919] [IGT] gem_mmap_gtt: exiting, ret=0
>[  226.220798] Console: switching to colour frame buffer device 240x75
>[  226.366158] Console: switching to colour dummy device 80x25
>[  226.366268] [IGT] gem_mmap_gtt: executing
>[  226.379069] [IGT] gem_mmap_gtt: starting subtest basic-short
>[  226.413952] [IGT] gem_mmap_gtt: exiting, ret=0
>[  226.464400] Console: switching to colour frame buffer device 240x75
>[  226.606464] Console: switching to colour dummy device 80x25
>[  226.606623] [IGT] gem_mmap_gtt: executing
>[  226.620190] [IGT] gem_mmap_gtt: starting subtest basic-small-bo
>[  226.721579] [IGT] gem_mmap_gtt: exiting, ret=0
>[  226.814557] Console: switching to colour frame buffer device 240x75
>[  226.998545] Console: switching to colour dummy device 80x25
>[  226.998974] [IGT] gem_mmap_gtt: executing
>[  227.016741] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledX
>[  227.104610] [IGT] gem_mmap_gtt: exiting, ret=0
>[  227.187480] Console: switching to colour frame buffer device 240x75
>[  227.344157] Console: switching to colour dummy device 80x25
>[  227.344470] [IGT] gem_mmap_gtt: executing
>[  227.369273] [IGT] gem_mmap_gtt: starting subtest basic-small-bo-tiledY
>[  227.462183] [IGT] gem_mmap_gtt: exiting, ret=0
>[  227.570898] Console: switching to colour frame buffer device 240x75
>[  227.775153] Console: switching to colour dummy device 80x25
>[  227.775607] [IGT] gem_mmap_gtt: executing
>[  227.808029] [IGT] gem_mmap_gtt: starting subtest basic-small-copy
>[  228.096192] [IGT] gem_mmap_gtt: exiting, ret=0
>[  228.137468] Console: switching to colour frame buffer device 240x75
>[  228.266636] Console: switching to colour dummy device 80x25
>[  228.266915] [IGT] gem_mmap_gtt: executing
>[  228.297066] [IGT] gem_mmap_gtt: starting subtest basic-small-copy-XY
>[  228.660623] [IGT] gem_mmap_gtt: exiting, ret=0
>[  228.716246] Console: switching to colour frame buffer device 240x75
>[  228.896434] Console: switching to colour dummy device 80x25
>[  228.896852] [IGT] gem_mmap_gtt: executing
>[  228.926400] [IGT] gem_mmap_gtt: starting subtest basic-wc
>[  229.556302] [IGT] gem_mmap_gtt: exiting, ret=0
>[  229.604622] Console: switching to colour frame buffer device 240x75
>[  229.730615] Console: switching to colour dummy device 80x25
>[  229.731223] [IGT] gem_mmap_gtt: executing
>[  229.759211] [IGT] gem_mmap_gtt: starting subtest basic-write
>[  229.863134] [IGT] gem_mmap_gtt: exiting, ret=0
>[  229.920953] Console: switching to colour frame buffer device 240x75
>[  230.071379] Console: switching to colour dummy device 80x25
>[  230.071538] [IGT] gem_mmap_gtt: executing
>[  230.085104] [IGT] gem_mmap_gtt: starting subtest basic-write-cpu-read-gtt
>[  230.254772] [IGT] gem_mmap_gtt: exiting, ret=0
>[  230.317500] Console: switching to colour frame buffer device 240x75
>[  230.440041] Console: switching to colour dummy device 80x25
>[  230.440320] [IGT] gem_mmap_gtt: executing
>[  230.469354] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt
>[  230.576304] [IGT] gem_mmap_gtt: exiting, ret=0
>[  230.637715] Console: switching to colour frame buffer device 240x75
>[  230.776906] Console: switching to colour dummy device 80x25
>[  230.777223] [IGT] gem_mmap_gtt: executing
>[  230.809351] [IGT] gem_mmap_gtt: starting subtest basic-write-gtt-no-prefault
>[  230.809606] Setting dangerous option prefault_disable - tainting kernel
>[  230.916595] Setting dangerous option prefault_disable - tainting kernel
>[  230.916826] [IGT] gem_mmap_gtt: exiting, ret=0
>[  230.916946] Setting dangerous option prefault_disable - tainting kernel
>[  230.971078] Console: switching to colour frame buffer device 240x75
>[  231.087474] Console: switching to colour dummy device 80x25
>[  231.087836] [IGT] gem_mmap_gtt: executing
>[  231.104222] [IGT] gem_mmap_gtt: starting subtest basic-write-no-prefault
>[  231.104359] Setting dangerous option prefault_disable - tainting kernel
>[  231.216140] Setting dangerous option prefault_disable - tainting kernel
>[  231.216243] [IGT] gem_mmap_gtt: exiting, ret=0
>[  231.216316] Setting dangerous option prefault_disable - tainting kernel
>[  231.271039] Console: switching to colour frame buffer device 240x75
>[  231.421893] Console: switching to colour dummy device 80x25
>[  231.422199] [IGT] gem_mmap_gtt: executing
>[  231.452254] [IGT] gem_mmap_gtt: starting subtest basic-write-read
>[  231.477147] [IGT] gem_mmap_gtt: exiting, ret=0
>[  231.521372] Console: switching to colour frame buffer device 240x75
>[  231.687046] Console: switching to colour dummy device 80x25
>[  231.687270] [IGT] gem_mmap_gtt: executing
>[  231.716183] [IGT] gem_mmap_gtt: starting subtest basic-write-read-distinct
>[  231.734361] [IGT] gem_mmap_gtt: exiting, ret=0
>[  231.787824] Console: switching to colour frame buffer device 240x75
>[  231.930816] Console: switching to colour dummy device 80x25
>[  231.931105] [IGT] gem_pread: executing
>[  231.961180] [IGT] gem_pread: starting subtest basic
>[  232.759473] [IGT] gem_pread: exiting, ret=0
>[  232.804457] Console: switching to colour frame buffer device 240x75
>[  232.912823] Console: switching to colour dummy device 80x25
>[  232.912923] [IGT] gem_pwrite: executing
>[  232.926105] [IGT] gem_pwrite: starting subtest basic
>[  233.897653] [IGT] gem_pwrite: exiting, ret=0
>[  233.954720] Console: switching to colour frame buffer device 240x75
>[  234.070653] Console: switching to colour dummy device 80x25
>[  234.071116] [IGT] gem_render_linear_blits: executing
>[  234.102257] [IGT] gem_render_linear_blits: starting subtest basic
>[  234.122124] [IGT] gem_render_linear_blits: exiting, ret=0
>[  234.154557] Console: switching to colour frame buffer device 240x75
>[  234.300057] Console: switching to colour dummy device 80x25
>[  234.300224] [IGT] gem_render_tiled_blits: executing
>[  234.326020] [IGT] gem_render_tiled_blits: starting subtest basic
>[  234.339082] [IGT] gem_render_tiled_blits: exiting, ret=0
>[  234.371239] Console: switching to colour frame buffer device 240x75
>[  234.496802] Console: switching to colour dummy device 80x25
>[  234.497109] [IGT] gem_ringfill: executing
>[  234.526370] [IGT] gem_ringfill: starting subtest basic-default
>[  235.062937] [IGT] gem_ringfill: exiting, ret=0
>[  235.105068] Console: switching to colour frame buffer device 240x75
>[  235.225113] Console: switching to colour dummy device 80x25
>[  235.225405] [IGT] gem_ringfill: executing
>[  235.256421] [IGT] gem_ringfill: starting subtest basic-default-interruptible
>[  239.783925] [IGT] gem_ringfill: exiting, ret=0
>[  239.825737] Console: switching to colour frame buffer device 240x75
>[  239.950627] Console: switching to colour dummy device 80x25
>[  239.951010] [IGT] gem_ringfill: executing
>[  239.977188] [IGT] gem_ringfill: starting subtest basic-default-forked
>[  243.995063] [IGT] gem_ringfill: exiting, ret=0
>[  244.038772] Console: switching to colour frame buffer device 240x75
>[  244.217315] Console: switching to colour dummy device 80x25
>[  244.217600] [IGT] gem_ringfill: executing
>[  244.247307] [IGT] gem_ringfill: starting subtest basic-default-fd
>[  249.906264] [IGT] gem_ringfill: exiting, ret=0
>[  249.955607] Console: switching to colour frame buffer device 240x75
>[  250.166948] Console: switching to colour dummy device 80x25
>[  250.167249] [IGT] gem_ringfill: executing
>[  250.197300] [IGT] gem_ringfill: starting subtest basic-default-hang
>[  260.789351] drm/i915: Resetting chip after gpu hang
>[  260.789459] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  260.790804] [drm:i915_gem_reset [i915]] context gem_ringfill[8144]/0 marked guilty (score 10) banned? no
>[  260.790876] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x32239d
>[  260.791114] [drm] RC6 on
>[  260.803187] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  260.803244] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x322418, 0x0]
>[  260.803392] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  260.803514] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  260.803633] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  260.804279] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  260.804370] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  260.804382] [drm] GuC firmware load skipped
>[  261.308931] [IGT] gem_ringfill: exiting, ret=0
>[  261.343406] Console: switching to colour frame buffer device 240x75
>[  261.461612] Console: switching to colour dummy device 80x25
>[  261.462285] [IGT] gem_sync: executing
>[  261.495033] [IGT] gem_sync: starting subtest basic-all
>[  266.615812] [IGT] gem_sync: exiting, ret=0
>[  266.664470] Console: switching to colour frame buffer device 240x75
>[  266.912622] Console: switching to colour dummy device 80x25
>[  266.912814] [IGT] gem_sync: executing
>[  266.941133] [IGT] gem_sync: starting subtest basic-each
>[  272.081888] [IGT] gem_sync: exiting, ret=0
>[  272.123649] Console: switching to colour frame buffer device 240x75
>[  272.414576] Console: switching to colour dummy device 80x25
>[  272.414949] [IGT] gem_sync: executing
>[  272.448322] [IGT] gem_sync: starting subtest basic-many-each
>[  277.961633] [IGT] gem_sync: exiting, ret=0
>[  278.007589] Console: switching to colour frame buffer device 240x75
>[  278.289408] Console: switching to colour dummy device 80x25
>[  278.289615] [IGT] gem_sync: executing
>[  278.321083] [IGT] gem_sync: starting subtest basic-store-all
>[  283.773923] [IGT] gem_sync: exiting, ret=0
>[  283.824230] Console: switching to colour frame buffer device 240x75
>[  284.093186] Console: switching to colour dummy device 80x25
>[  284.093286] [IGT] gem_sync: executing
>[  284.105861] [IGT] gem_sync: starting subtest basic-store-each
>[  289.429056] [IGT] gem_sync: exiting, ret=0
>[  289.483782] Console: switching to colour frame buffer device 240x75
>[  289.745418] Console: switching to colour dummy device 80x25
>[  289.745525] [IGT] gem_tiled_blits: executing
>[  289.756353] [IGT] gem_tiled_blits: starting subtest basic
>[  289.769167] [IGT] gem_tiled_blits: exiting, ret=0
>[  289.808057] Console: switching to colour frame buffer device 240x75
>[  289.984453] Console: switching to colour dummy device 80x25
>[  289.984846] [IGT] gem_tiled_fence_blits: executing
>[  290.022365] [IGT] gem_tiled_fence_blits: starting subtest basic
>[  290.038189] [IGT] gem_tiled_fence_blits: exiting, ret=0
>[  290.101090] Console: switching to colour frame buffer device 240x75
>[  290.219185] Console: switching to colour dummy device 80x25
>[  290.219341] [IGT] gem_tiled_pread_basic: executing
>[  290.370818] [IGT] gem_tiled_pread_basic: exiting, ret=0
>[  290.424770] Console: switching to colour frame buffer device 240x75
>[  290.563309] Console: switching to colour dummy device 80x25
>[  290.563414] [IGT] gem_wait: executing
>[  290.582627] [IGT] gem_wait: starting subtest basic-busy-all
>[  291.103793] [IGT] gem_wait: exiting, ret=0
>[  291.151840] Console: switching to colour frame buffer device 240x75
>[  291.264036] Console: switching to colour dummy device 80x25
>[  291.264141] [IGT] gem_wait: executing
>[  291.281015] [IGT] gem_wait: starting subtest basic-wait-all
>[  292.326965] [IGT] gem_wait: exiting, ret=0
>[  292.374821] Console: switching to colour frame buffer device 240x75
>[  292.527535] Console: switching to colour dummy device 80x25
>[  292.527886] [IGT] gem_workarounds: executing
>[  292.551422] [IGT] gem_workarounds: starting subtest basic-read
>[  292.567288] [IGT] gem_workarounds: exiting, ret=0
>[  292.591508] Console: switching to colour frame buffer device 240x75
>[  292.740881] Console: switching to colour dummy device 80x25
>[  292.740984] [IGT] kms_addfb_basic: executing
>[  292.753402] [drm:drm_mode_addfb2] [FB:68]
>[  292.754022] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
>[  292.754095] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  292.767991] [drm:drm_mode_addfb2] [FB:68]
>[  292.768160] [IGT] kms_addfb_basic: exiting, ret=0
>[  292.824725] Console: switching to colour frame buffer device 240x75
>[  292.985824] Console: switching to colour dummy device 80x25
>[  292.986131] [IGT] kms_addfb_basic: executing
>[  293.003401] [drm:drm_mode_addfb2] [FB:110]
>[  293.003947] [IGT] kms_addfb_basic: starting subtest addfb25-framebuffer-vs-set-tiling
>[  293.004007] [drm:drm_mode_addfb2] [FB:110]
>[  293.017882] [drm:drm_mode_addfb2] [FB:110]
>[  293.018062] [IGT] kms_addfb_basic: exiting, ret=0
>[  293.074934] Console: switching to colour frame buffer device 240x75
>[  293.194465] Console: switching to colour dummy device 80x25
>[  293.194830] [IGT] kms_addfb_basic: executing
>[  293.214335] [drm:drm_mode_addfb2] [FB:68]
>[  293.214818] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
>[  293.214876] [drm:drm_internal_framebuffer_create] bad fb modifier 72057594037927937 for plane 0
>[  293.228649] [drm:drm_mode_addfb2] [FB:68]
>[  293.228886] [IGT] kms_addfb_basic: exiting, ret=0
>[  293.291561] Console: switching to colour frame buffer device 240x75
>[  293.428470] Console: switching to colour dummy device 80x25
>[  293.428574] [IGT] kms_addfb_basic: executing
>[  293.442416] [drm:drm_mode_addfb2] [FB:110]
>[  293.442955] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled
>[  293.443014] [drm:drm_mode_addfb2] [FB:110]
>[  293.456964] [drm:drm_mode_addfb2] [FB:110]
>[  293.457143] [IGT] kms_addfb_basic: exiting, ret=0
>[  293.508089] Console: switching to colour frame buffer device 240x75
>[  293.658030] Console: switching to colour dummy device 80x25
>[  293.658294] [IGT] kms_addfb_basic: executing
>[  293.675278] [drm:drm_mode_addfb2] [FB:68]
>[  293.675775] [IGT] kms_addfb_basic: starting subtest addfb25-X-tiled-mismatch
>[  293.675844] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  293.687834] [drm:drm_mode_addfb2] [FB:68]
>[  293.688000] [IGT] kms_addfb_basic: exiting, ret=0
>[  293.741545] Console: switching to colour frame buffer device 240x75
>[  293.858087] Console: switching to colour dummy device 80x25
>[  293.858195] [IGT] kms_addfb_basic: executing
>[  293.869473] [drm:drm_mode_addfb2] [FB:110]
>[  293.870140] [IGT] kms_addfb_basic: starting subtest addfb25-Yf-tiled
>[  293.870204] [drm:drm_mode_addfb2] [FB:110]
>[  293.883617] [drm:drm_mode_addfb2] [FB:110]
>[  293.883851] [IGT] kms_addfb_basic: exiting, ret=0
>[  293.941596] Console: switching to colour frame buffer device 240x75
>[  294.104425] Console: switching to colour dummy device 80x25
>[  294.105169] [IGT] kms_addfb_basic: executing
>[  294.122337] [drm:drm_mode_addfb2] [FB:68]
>[  294.123281] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled
>[  294.123345] [drm:drm_mode_addfb2] [FB:68]
>[  294.137406] [drm:drm_mode_addfb2] [FB:68]
>[  294.137581] [IGT] kms_addfb_basic: exiting, ret=0
>[  294.191360] Console: switching to colour frame buffer device 240x75
>[  294.351790] Console: switching to colour dummy device 80x25
>[  294.352081] [IGT] kms_addfb_basic: executing
>[  294.367348] [drm:drm_mode_addfb2] [FB:110]
>[  294.368032] [IGT] kms_addfb_basic: starting subtest addfb25-Y-tiled-small
>[  294.368107] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  294.381254] [drm:drm_mode_addfb2] [FB:110]
>[  294.381428] [IGT] kms_addfb_basic: exiting, ret=0
>[  294.437981] Console: switching to colour frame buffer device 240x75
>[  294.614835] Console: switching to colour dummy device 80x25
>[  294.614980] [IGT] kms_addfb_basic: executing
>[  294.628328] [drm:drm_mode_addfb2] [FB:68]
>[  294.628534] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
>[  294.628580] [drm:drm_internal_framebuffer_create] bad pitch 0 for plane 0
>[  294.643058] [drm:drm_mode_addfb2] [FB:68]
>[  294.643239] [IGT] kms_addfb_basic: exiting, ret=0
>[  294.704813] Console: switching to colour frame buffer device 240x75
>[  294.835963] Console: switching to colour dummy device 80x25
>[  294.836091] [IGT] kms_addfb_basic: executing
>[  294.848264] [drm:drm_mode_addfb2] [FB:110]
>[  294.848464] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
>[  294.848509] [drm:drm_internal_framebuffer_create] bad pitch 1024 for plane 0
>[  294.863134] [drm:drm_mode_addfb2] [FB:110]
>[  294.863315] [IGT] kms_addfb_basic: exiting, ret=0
>[  294.924868] Console: switching to colour frame buffer device 240x75
>[  295.053136] Console: switching to colour dummy device 80x25
>[  295.053306] [IGT] kms_addfb_basic: executing
>[  295.067518] [drm:drm_mode_addfb2] [FB:68]
>[  295.067961] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
>[  295.068015] [drm:drm_internal_framebuffer_create] bad pitch 128 for plane 0
>[  295.081823] [drm:drm_mode_addfb2] [FB:68]
>[  295.081950] [IGT] kms_addfb_basic: exiting, ret=0
>[  295.124836] Console: switching to colour frame buffer device 240x75
>[  295.304543] Console: switching to colour dummy device 80x25
>[  295.305018] [IGT] kms_addfb_basic: executing
>[  295.320445] [drm:drm_mode_addfb2] [FB:110]
>[  295.320665] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
>[  295.321081] [drm:drm_internal_framebuffer_create] bad pitch 256 for plane 0
>[  295.335682] [drm:drm_mode_addfb2] [FB:110]
>[  295.336017] [IGT] kms_addfb_basic: exiting, ret=0
>[  295.391544] Console: switching to colour frame buffer device 240x75
>[  295.535141] Console: switching to colour dummy device 80x25
>[  295.535266] [IGT] kms_addfb_basic: executing
>[  295.547363] [drm:drm_mode_addfb2] [FB:68]
>[  295.547575] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
>[  295.547623] [drm:drm_internal_framebuffer_create] bad pitch 32 for plane 0
>[  295.561227] [drm:drm_mode_addfb2] [FB:68]
>[  295.561409] [IGT] kms_addfb_basic: exiting, ret=0
>[  295.608190] Console: switching to colour frame buffer device 240x75
>[  295.748890] Console: switching to colour dummy device 80x25
>[  295.749058] [IGT] kms_addfb_basic: executing
>[  295.763491] [drm:drm_mode_addfb2] [FB:110]
>[  295.763793] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
>[  295.763849] [drm:drm_internal_framebuffer_create] bad pitch 63 for plane 0
>[  295.777962] [drm:drm_mode_addfb2] [FB:110]
>[  295.778142] [IGT] kms_addfb_basic: exiting, ret=0
>[  295.839162] Console: switching to colour frame buffer device 240x75
>[  295.991232] Console: switching to colour dummy device 80x25
>[  295.991341] [IGT] kms_addfb_basic: executing
>[  296.005069] [drm:drm_mode_addfb2] [FB:68]
>[  296.005182] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
>[  296.005208] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  296.011183] [drm:drm_mode_addfb2] [FB:68]
>[  296.011284] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.058268] Console: switching to colour frame buffer device 240x75
>[  296.204772] Console: switching to colour dummy device 80x25
>[  296.204893] [IGT] kms_addfb_basic: executing
>[  296.219270] [drm:drm_mode_addfb2] [FB:110]
>[  296.219474] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
>[  296.219520] [drm:drm_internal_framebuffer_create] bad pitch 999 for plane 0
>[  296.233578] [drm:drm_mode_addfb2] [FB:110]
>[  296.233821] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.291783] Console: switching to colour frame buffer device 240x75
>[  296.452796] Console: switching to colour dummy device 80x25
>[  296.453111] [IGT] kms_addfb_basic: executing
>[  296.474472] [drm:drm_mode_addfb2] [FB:68]
>[  296.474761] [IGT] kms_addfb_basic: starting subtest basic
>[  296.474857] [drm:drm_mode_addfb2] [FB:68]
>[  296.489380] [drm:drm_mode_addfb2] [FB:68]
>[  296.489561] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.541485] Console: switching to colour frame buffer device 240x75
>[  296.701575] Console: switching to colour dummy device 80x25
>[  296.701868] [IGT] kms_addfb_basic: executing
>[  296.716349] [drm:drm_mode_addfb2] [FB:110]
>[  296.730847] [IGT] kms_addfb_basic: starting subtest basic-X-tiled
>[  296.730923] [drm:drm_mode_addfb2] [FB:110]
>[  296.731099] [drm:drm_mode_addfb2] [FB:110]
>[  296.731250] [IGT] kms_addfb_basic: exiting, ret=0
>[  296.791770] Console: switching to colour frame buffer device 240x75
>[  296.936195] Console: switching to colour dummy device 80x25
>[  296.936308] [IGT] kms_addfb_basic: executing
>[  296.950345] [drm:drm_mode_addfb2] [FB:68]
>[  296.964467] [IGT] kms_addfb_basic: starting subtest basic-Y-tiled
>[  296.964541] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  296.965063] [drm:drm_mode_addfb2] [FB:68]
>[  296.965244] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.025113] Console: switching to colour frame buffer device 240x75
>[  297.166246] Console: switching to colour dummy device 80x25
>[  297.166359] [IGT] kms_addfb_basic: executing
>[  297.179325] [drm:drm_mode_addfb2] [FB:110]
>[  297.179647] [IGT] kms_addfb_basic: starting subtest bo-too-small
>[  297.179762] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  297.193913] [drm:drm_mode_addfb2] [FB:110]
>[  297.194091] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.241657] Console: switching to colour frame buffer device 240x75
>[  297.374526] Console: switching to colour dummy device 80x25
>[  297.374659] [IGT] kms_addfb_basic: executing
>[  297.388350] [drm:drm_mode_addfb2] [FB:68]
>[  297.388781] [IGT] kms_addfb_basic: starting subtest bo-too-small-due-to-tiling
>[  297.388912] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  297.402910] [drm:drm_mode_addfb2] [FB:68]
>[  297.403099] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.458389] Console: switching to colour frame buffer device 240x75
>[  297.600575] Console: switching to colour dummy device 80x25
>[  297.600778] [IGT] kms_addfb_basic: executing
>[  297.616362] [drm:drm_mode_addfb2] [FB:110]
>[  297.616465] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
>[  297.616546] [drm:drm_mode_addfb2] [FB:110]
>[  297.631104] [drm:drm_mode_addfb2] [FB:110]
>[  297.631286] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.691775] Console: switching to colour frame buffer device 240x75
>[  297.834426] Console: switching to colour dummy device 80x25
>[  297.834541] [IGT] kms_addfb_basic: executing
>[  297.848488] [drm:drm_mode_addfb2] [FB:68]
>[  297.856052] [IGT] kms_addfb_basic: starting subtest framebuffer-vs-set-tiling
>[  297.856086] [drm:drm_mode_addfb2] [FB:68]
>[  297.856168] [drm:drm_mode_addfb2] [FB:68]
>[  297.856215] [IGT] kms_addfb_basic: exiting, ret=0
>[  297.908488] Console: switching to colour frame buffer device 240x75
>[  298.089902] Console: switching to colour dummy device 80x25
>[  298.090039] [IGT] kms_addfb_basic: executing
>[  298.103351] [drm:drm_mode_addfb2] [FB:110]
>[  298.117340] [drm:drm_mode_addfb2] [FB:110]
>[  298.117445] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
>[  298.118101] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.175135] Console: switching to colour frame buffer device 240x75
>[  298.332619] Console: switching to colour dummy device 80x25
>[  298.333005] [IGT] kms_addfb_basic: executing
>[  298.346339] [drm:drm_mode_addfb2] [FB:68]
>[  298.360372] [drm:drm_mode_addfb2] [FB:68]
>[  298.360452] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
>[  298.360716] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.408326] Console: switching to colour frame buffer device 240x75
>[  298.587868] Console: switching to colour dummy device 80x25
>[  298.588169] [IGT] kms_addfb_basic: executing
>[  298.606347] [drm:drm_mode_addfb2] [FB:110]
>[  298.620679] [drm:drm_mode_addfb2] [FB:110]
>[  298.620816] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
>[  298.621310] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.674895] Console: switching to colour frame buffer device 240x75
>[  298.804944] Console: switching to colour dummy device 80x25
>[  298.805053] [IGT] kms_addfb_basic: executing
>[  298.819001] [drm:drm_mode_addfb2] [FB:68]
>[  298.824663] [drm:drm_mode_addfb2] [FB:68]
>[  298.824751] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
>[  298.825001] [IGT] kms_addfb_basic: exiting, ret=0
>[  298.874985] Console: switching to colour frame buffer device 240x75
>[  298.993652] Console: switching to colour dummy device 80x25
>[  298.994165] [IGT] kms_addfb_basic: executing
>[  299.011349] [drm:drm_mode_addfb2] [FB:110]
>[  299.011554] [IGT] kms_addfb_basic: starting subtest no-handle
>[  299.011599] [drm:drm_internal_framebuffer_create] no buffer object handle for plane 0
>[  299.026341] [drm:drm_mode_addfb2] [FB:110]
>[  299.026527] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.091820] Console: switching to colour frame buffer device 240x75
>[  299.261042] Console: switching to colour dummy device 80x25
>[  299.261166] [IGT] kms_addfb_basic: executing
>[  299.274336] [drm:drm_mode_addfb2] [FB:68]
>[  299.274662] [IGT] kms_addfb_basic: starting subtest size-max
>[  299.274967] [drm:drm_mode_addfb2] [FB:68]
>[  299.274998] [drm:drm_mode_addfb2] [FB:68]
>[  299.275025] [drm:drm_mode_addfb2] [FB:68]
>[  299.289135] [drm:drm_mode_addfb2] [FB:68]
>[  299.289319] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.342009] Console: switching to colour frame buffer device 240x75
>[  299.516574] Console: switching to colour dummy device 80x25
>[  299.516931] [IGT] kms_addfb_basic: executing
>[  299.534354] [drm:drm_mode_addfb2] [FB:110]
>[  299.534743] [IGT] kms_addfb_basic: starting subtest small-bo
>[  299.534808] [drm:drm_mode_addfb2] [FB:110]
>[  299.547728] [drm:drm_mode_addfb2] [FB:110]
>[  299.547859] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.608954] Console: switching to colour frame buffer device 240x75
>[  299.736968] Console: switching to colour dummy device 80x25
>[  299.737264] [IGT] kms_addfb_basic: executing
>[  299.753406] [drm:drm_mode_addfb2] [FB:68]
>[  299.767098] [IGT] kms_addfb_basic: starting subtest tile-pitch-mismatch
>[  299.767176] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  299.767339] [drm:drm_mode_addfb2] [FB:68]
>[  299.767494] [IGT] kms_addfb_basic: exiting, ret=0
>[  299.809039] Console: switching to colour frame buffer device 240x75
>[  299.976123] Console: switching to colour dummy device 80x25
>[  299.976233] [IGT] kms_addfb_basic: executing
>[  299.987501] [drm:drm_mode_addfb2] [FB:110]
>[  299.987922] [IGT] kms_addfb_basic: starting subtest too-high
>[  299.987987] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  299.988007] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  299.988025] [drm:drm_internal_framebuffer_create] could not create framebuffer
>[  300.001724] [drm:drm_mode_addfb2] [FB:110]
>[  300.001897] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.059202] Console: switching to colour frame buffer device 240x75
>[  300.236512] Console: switching to colour dummy device 80x25
>[  300.236953] [IGT] kms_addfb_basic: executing
>[  300.254391] [drm:drm_mode_addfb2] [FB:68]
>[  300.254791] [IGT] kms_addfb_basic: starting subtest too-wide
>[  300.254841] [drm:drm_internal_framebuffer_create] bad pitch 4096 for plane 0
>[  300.254850] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  300.254857] [drm:drm_internal_framebuffer_create] bad pitch 2048 for plane 0
>[  300.268750] [drm:drm_mode_addfb2] [FB:68]
>[  300.268955] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.326136] Console: switching to colour frame buffer device 240x75
>[  300.506156] Console: switching to colour dummy device 80x25
>[  300.506460] [IGT] kms_addfb_basic: executing
>[  300.522443] [drm:drm_mode_addfb2] [FB:110]
>[  300.522548] [IGT] kms_addfb_basic: starting subtest unused-handle
>[  300.522603] [drm:drm_internal_framebuffer_create] buffer object handle for unused plane 1
>[  300.537069] [drm:drm_mode_addfb2] [FB:110]
>[  300.537243] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.592819] Console: switching to colour frame buffer device 240x75
>[  300.749896] Console: switching to colour dummy device 80x25
>[  300.750218] [IGT] kms_addfb_basic: executing
>[  300.770460] [drm:drm_mode_addfb2] [FB:68]
>[  300.770589] [IGT] kms_addfb_basic: starting subtest unused-modifier
>[  300.770646] [drm:drm_internal_framebuffer_create] non-zero modifier for unused plane 1
>[  300.785202] [drm:drm_mode_addfb2] [FB:68]
>[  300.785379] [IGT] kms_addfb_basic: exiting, ret=0
>[  300.842998] Console: switching to colour frame buffer device 240x75
>[  301.014898] Console: switching to colour dummy device 80x25
>[  301.015133] [IGT] kms_addfb_basic: executing
>[  301.040212] [drm:drm_mode_addfb2] [FB:110]
>[  301.040318] [IGT] kms_addfb_basic: starting subtest unused-offsets
>[  301.040373] [drm:drm_internal_framebuffer_create] non-zero offset for unused plane 1
>[  301.054919] [drm:drm_mode_addfb2] [FB:110]
>[  301.055092] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.109940] Console: switching to colour frame buffer device 240x75
>[  301.238805] Console: switching to colour dummy device 80x25
>[  301.239095] [IGT] kms_addfb_basic: executing
>[  301.257288] [drm:drm_mode_addfb2] [FB:68]
>[  301.257392] [IGT] kms_addfb_basic: starting subtest unused-pitches
>[  301.257447] [drm:drm_internal_framebuffer_create] non-zero pitch for unused plane 1
>[  301.271944] [drm:drm_mode_addfb2] [FB:68]
>[  301.272115] [IGT] kms_addfb_basic: exiting, ret=0
>[  301.326958] Console: switching to colour frame buffer device 240x75
>[  301.507483] Console: switching to colour dummy device 80x25
>[  301.507611] [IGT] kms_busy: executing
>[  301.532804] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  301.532829] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  301.541421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.549879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.558334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.566795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.575250] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.583705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.592160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.600613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.609069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.617523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.625978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.634445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.642901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.651353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.659808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.668267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.676727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.685183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.693640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.721143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.729603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.738075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.746533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.754989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.763531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.771987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.780443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.788900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.797356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.805812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.814267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.822722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  301.822731] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  301.822735] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  301.822993] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  301.823018] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  301.823858] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  301.825379] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  301.825396] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  301.825423] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  301.825436] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  301.826252] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  301.826964] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  301.827848] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  301.827967] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  301.827970] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  301.827971] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  301.827973] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  301.827974] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  301.827976] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  301.827977] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  301.827978] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  301.827980] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  301.827981] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  301.827982] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  301.827984] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  301.827985] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.828169] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  301.828185] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  301.828197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  301.828356] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  301.828372] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  301.829881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  301.829897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  301.831873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  301.831877] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  301.833869] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  301.833885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  301.835868] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  301.835872] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  301.835874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  301.836064] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  301.836082] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  301.836540] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  301.836982] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  301.836998] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  301.837013] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  301.837040] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  301.837443] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  301.837815] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  301.838313] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  301.838314] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  301.838388] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  301.838389] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  301.838393] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  301.838394] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  301.838397] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  301.838398] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  301.838404] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  301.838405] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  301.838407] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  301.838408] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  301.838409] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  301.838411] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  301.838412] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  301.838414] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  301.838415] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  301.838416] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  301.838418] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  301.838419] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  301.838420] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  301.838422] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  301.838423] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  301.838424] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  301.838426] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  301.838427] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  301.838429] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  301.838430] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  301.838431] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  301.838433] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  301.838434] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  301.838435] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  301.838437] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  301.838438] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  301.838439] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  301.838441] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  301.838442] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  301.838443] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  301.838445] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.838446] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  301.838447] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  301.838632] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  301.838647] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  301.839473] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  301.839487] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  301.840872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  301.840875] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  301.842873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  301.842888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  301.844870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  301.844874] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  301.844876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  301.845102] [IGT] kms_busy: starting subtest basic-flip-default-A
>[  301.849244] [drm:drm_mode_addfb2] [FB:70]
>[  301.989561] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  301.989580] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  302.010550] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  302.010624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  302.010650] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  302.010672] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  302.010973] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  302.028350] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  302.028409] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  302.028445] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  302.028480] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  302.028530] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  302.029016] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  302.043463] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  302.043506] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  302.043592] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  302.044642] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  302.044681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  302.044813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  302.044846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  302.044879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  302.044909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  302.044939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  302.044970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  302.044998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  302.045025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  302.045053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  302.045083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  302.045109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  302.045136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  302.045166] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  302.045201] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  302.045234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  302.045265] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  302.045295] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  302.045362] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  302.045393] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  302.058588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.067226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.075862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.084510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.093182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.101813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.110443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.119072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.127702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.136365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.144959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.153503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.162015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.170506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.178981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.187448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.195975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.204454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  302.210502] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  302.225856] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  302.225924] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  302.226030] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  302.227633] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  302.229711] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  302.232375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  302.232430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  302.232480] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  302.232532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  302.238074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  302.238129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  302.243517] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  302.246207] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  302.247776] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  302.247915] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  302.247968] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  302.281603] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  302.281682] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  302.282172] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  302.282236] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  302.282346] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  302.282431] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  302.282488] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  302.285898] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  302.300189] [drm:drm_mode_addfb2] [FB:68]
>[  303.004509] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.004636] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.005072] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  303.015891] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  303.049963] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  303.050064] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  303.050199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  303.050258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  303.050315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  303.050364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  303.050412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  303.050458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  303.050505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  303.050548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  303.050593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  303.050635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  303.050680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  303.051528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  303.051577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  303.051631] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  303.051692] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  303.052070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  303.052127] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  303.052181] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  303.052234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  303.052334] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  303.052416] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  303.052462] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  303.052596] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  303.052680] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  303.053305] [drm:intel_power_well_disable [i915]] disabling DC off
>[  303.053353] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  303.053396] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  303.054465] [drm:intel_power_well_disable [i915]] disabling always-on
>[  303.056037] [IGT] kms_busy: exiting, ret=0
>[  303.082058] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  303.082117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  303.082191] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  303.082236] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.082272] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.082310] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.082348] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  303.082384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  303.082419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.082452] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  303.082484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.082491] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  303.082522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.082526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  303.082558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  303.082589] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.082620] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  303.082650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.082679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.082746] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  303.082777] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.082807] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  303.082837] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  303.082867] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  303.082911] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  303.082945] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.082983] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  303.083026] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  303.083062] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  303.083098] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.083132] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  303.083164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  303.083195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  303.083225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  303.083255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.083260] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  303.083290] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.083294] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  303.083325] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  303.083354] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  303.083383] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  303.083412] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.083440] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.083476] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  303.083505] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.083534] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  303.083562] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  303.083591] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  303.083627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  303.083668] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  303.083704] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  303.083770] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  303.083803] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  303.083970] [drm:intel_power_well_enable [i915]] enabling always-on
>[  303.083999] [drm:intel_power_well_enable [i915]] enabling DC off
>[  303.084315] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  303.084363] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  303.084399] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  303.084542] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  303.084571] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  303.084607] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  303.084635] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  303.084680] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  303.088840] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  303.088871] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  303.090996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  303.091041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  303.091078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  303.091113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  303.091147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  303.091179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  303.091214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  303.091246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  303.091277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  303.091308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  303.091338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  303.091368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  303.091398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  303.091433] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  303.091473] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  303.091510] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  303.091547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  303.091607] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  303.091643] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  303.104650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.113189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.121706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.130222] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.138735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.147248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.155760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.164273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.172782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.181292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.189811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.198326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.206837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.215346] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.223857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.232365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.240873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.249400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.257374] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  303.272124] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  303.272143] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  303.272174] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  303.273002] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  303.275791] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  303.277151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.277166] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.277180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.277194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.282342] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.282356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  303.287505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.289987] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  303.290518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  303.290588] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  303.290603] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  303.290654] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  303.290668] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  303.293926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  303.293941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  303.293955] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  303.293970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  303.294629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  303.294643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  303.294656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  303.295304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  303.295317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  303.295330] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  303.295978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  303.295992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  303.296950] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  303.299211] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  303.299740] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  303.299777] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  303.299791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  303.299821] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  303.316581] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  303.316603] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  303.316642] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  303.316683] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  303.316719] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  303.316755] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  303.316908] Console: switching to colour frame buffer device 240x75
>[  303.464444] Console: switching to colour dummy device 80x25
>[  303.464663] [IGT] kms_busy: executing
>[  303.499590] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  303.499627] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  303.508128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.516592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.525054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.533514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.541970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.550426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.558883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.567338] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.575794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.584248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.592704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.601159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.609614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.618067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.626523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.634978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.643444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.651899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.660353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.668807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.677260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.685716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.694170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.702726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.711181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.719636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.728092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.736548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.745002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.753458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.761913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.770367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  303.770375] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  303.770379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  303.770570] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  303.770584] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  303.771420] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  303.772942] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  303.772958] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  303.772973] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  303.772987] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  303.773790] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  303.774498] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  303.775292] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  303.775316] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  303.775318] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  303.775320] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  303.775321] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  303.775323] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  303.775324] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  303.775325] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  303.775327] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  303.775328] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  303.775330] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  303.775331] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  303.775332] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  303.775334] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  303.775498] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  303.775513] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  303.775529] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  303.775720] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  303.775770] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  303.777873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  303.777889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  303.779920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  303.779924] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  303.782183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  303.782199] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  303.784459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  303.784463] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  303.784465] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  303.784652] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  303.784670] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  303.785210] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  303.785523] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  303.785553] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  303.785566] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  303.785579] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  303.786007] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  303.786318] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  303.786900] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  303.786901] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  303.786979] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  303.786980] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  303.786983] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  303.786984] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  303.786987] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  303.786988] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  303.786994] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  303.786995] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  303.786997] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  303.786998] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  303.786999] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  303.787001] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  303.787002] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  303.787003] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  303.787005] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  303.787006] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  303.787008] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  303.787009] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  303.787010] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  303.787012] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  303.787013] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  303.787014] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  303.787016] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  303.787017] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  303.787018] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  303.787020] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  303.787021] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  303.787022] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  303.787024] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  303.787025] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  303.787027] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  303.787028] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  303.787029] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  303.787031] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  303.787032] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  303.787033] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  303.787035] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  303.787036] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  303.787037] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  303.787227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  303.787242] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  303.788870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  303.788886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  303.790872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  303.790876] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  303.792874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  303.792890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  303.794875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  303.794879] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  303.794881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  303.795162] [IGT] kms_busy: starting subtest basic-flip-default-B
>[  303.799244] [drm:drm_mode_addfb2] [FB:110]
>[  303.831876] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  303.831922] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  303.832005] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  303.842451] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  303.842471] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  303.842489] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  303.842536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  303.842551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  303.842565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  303.842577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  303.842589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  303.842601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  303.842612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  303.842623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  303.842634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  303.842644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  303.842655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  303.842665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  303.842675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  303.842819] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  303.842836] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  303.842867] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  303.842882] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  303.842897] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  303.849875] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  303.849890] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  303.849913] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  303.849929] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  303.850003] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  303.850011] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  303.850054] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  303.850069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  303.850085] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  303.850103] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.850117] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  303.850131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.850146] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  303.850160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  303.850173] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  303.850186] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  303.850198] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.850200] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  303.850212] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.850214] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  303.850226] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  303.850238] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  303.850250] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  303.850262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.850273] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.850288] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  303.850299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.850312] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  303.850323] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  303.850335] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  303.850346] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  303.850366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.850382] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  303.850396] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  303.851450] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  303.851463] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  303.851483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  303.851502] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  303.851625] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  303.867547] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  303.867570] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  303.867593] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  303.869980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  303.870003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  303.870025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  303.870042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  303.870059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  303.870074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  303.870090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  303.870105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  303.870120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  303.870134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  303.870149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  303.870165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  303.870179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  303.870193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  303.870209] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  303.870229] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  303.870247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  303.870264] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  303.870281] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  303.870302] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  303.870319] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  303.883069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.891569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.900066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.908562] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.917060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.925555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.934050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.942545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.951056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.959550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.968039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.976513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.984981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  303.993449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.001916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.010396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.018865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.027332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.035800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.036890] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  304.050728] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  304.050745] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  304.050812] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  304.051651] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  304.052379] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  304.055028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.055045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.055060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.055076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.060541] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.060557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  304.065708] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.068185] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  304.068645] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  304.085501] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  304.085517] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  304.085558] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  304.085584] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  304.085620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  304.102247] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  304.106802] [drm:drm_mode_addfb2] [FB:70]
>[  304.775428] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.775552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  304.775610] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  304.786402] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  304.786427] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  304.786469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  304.786489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  304.786509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  304.786526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  304.786542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  304.786558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  304.786575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  304.786590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  304.786605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  304.786620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  304.786635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  304.786650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  304.786664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  304.786682] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  304.787006] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  304.787025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  304.787044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  304.787062] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  304.787080] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  304.787105] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  304.787122] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  304.787138] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  304.787161] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  304.787187] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  304.787205] [drm:intel_power_well_disable [i915]] disabling DC off
>[  304.787222] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  304.787236] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  304.787656] [drm:intel_power_well_disable [i915]] disabling always-on
>[  304.788370] [IGT] kms_busy: exiting, ret=0
>[  304.815515] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  304.815549] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  304.815584] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  304.815621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  304.815650] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  304.815682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.815737] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  304.815767] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  304.815795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  304.815823] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  304.815848] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.815854] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  304.815879] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.815883] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  304.815908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  304.815934] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  304.815959] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  304.815983] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.816007] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.816037] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  304.816061] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.816086] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  304.816109] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  304.816133] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  304.816169] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  304.816196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  304.816227] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  304.816262] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  304.816290] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  304.816319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  304.816347] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  304.816372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  304.816398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  304.816423] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  304.816446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  304.816450] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  304.816474] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  304.816478] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  304.816502] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  304.816526] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  304.816551] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  304.816574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  304.816598] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  304.816627] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  304.816651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  304.816675] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  304.816714] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  304.816738] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  304.816768] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  304.816802] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  304.816831] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  304.816860] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  304.816887] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  304.816983] [drm:intel_power_well_enable [i915]] enabling always-on
>[  304.817006] [drm:intel_power_well_enable [i915]] enabling DC off
>[  304.817290] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  304.817329] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  304.817354] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  304.817415] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  304.817451] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  304.817481] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  304.817504] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  304.817539] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  304.818789] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  304.818814] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  304.818853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  304.818887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  304.818916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  304.818943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  304.818970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  304.818996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  304.819023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  304.819048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  304.819073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  304.819098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  304.819122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  304.819146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  304.819170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  304.819198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  304.819236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  304.819272] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  304.819302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  304.819338] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  304.819367] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  304.831365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.839895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.848412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.856929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.865443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.873953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.882462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.890972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.899478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.907997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.916511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.925022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.933533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.942042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.950550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.959059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.967568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.976095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  304.983985] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  304.999072] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  304.999088] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  304.999113] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  304.999937] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  305.002206] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  305.003616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.003631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.003644] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.003659] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.008807] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.008821] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  305.013968] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.016447] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  305.016986] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  305.017029] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  305.017044] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  305.017094] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  305.017107] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  305.020352] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.020368] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.020383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.020398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.021058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  305.021072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  305.021085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  305.021735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  305.021748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  305.021761] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  305.022415] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.022429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  305.023385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.025650] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  305.026182] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  305.026213] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  305.026227] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  305.026248] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  305.043013] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  305.043036] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  305.043074] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  305.043115] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  305.043135] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  305.043170] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  305.043324] Console: switching to colour frame buffer device 240x75
>[  305.181280] Console: switching to colour dummy device 80x25
>[  305.181571] [IGT] kms_busy: executing
>[  305.227376] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  305.227418] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  305.235935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.244410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.252870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.261327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.269784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.278239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.286697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.295150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.303655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.312116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.320576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.329034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.337491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.345949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.354407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.362864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.371320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.379777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.388231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.396688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.405157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.413614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.422071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.430528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.438983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.447440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.455900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.464357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.472813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.481268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.489725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.498179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  305.498188] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  305.498191] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  305.498394] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  305.498411] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  305.499297] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  305.500820] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  305.500837] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  305.500851] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  305.500866] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  305.501657] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  305.502368] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  305.503199] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  305.503235] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  305.503237] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  305.503239] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  305.503241] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  305.503242] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  305.503243] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  305.503245] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  305.503246] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  305.503247] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  305.503249] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  305.503250] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  305.503252] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  305.503253] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  305.503417] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  305.503433] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  305.503450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  305.503605] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  305.503620] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  305.505872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  305.505888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  305.507893] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  305.507897] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  305.510159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  305.510175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  305.512437] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  305.512441] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  305.512443] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  305.512640] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  305.512658] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  305.513172] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  305.513485] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  305.513501] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  305.513516] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  305.513530] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  305.514056] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  305.514368] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  305.514908] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  305.514910] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  305.514985] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  305.514986] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  305.514989] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  305.514990] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  305.514993] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  305.514994] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  305.515000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  305.515001] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  305.515003] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  305.515004] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  305.515006] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  305.515007] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  305.515008] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  305.515010] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  305.515011] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  305.515012] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  305.515014] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  305.515015] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  305.515016] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  305.515018] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  305.515019] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  305.515020] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  305.515022] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  305.515023] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  305.515024] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  305.515026] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  305.515027] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  305.515029] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  305.515030] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  305.515031] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  305.515033] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  305.515034] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  305.515035] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  305.515037] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  305.515038] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  305.515039] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  305.515041] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  305.515042] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  305.515043] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  305.515224] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  305.515239] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  305.516854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  305.516868] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  305.518876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  305.518879] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  305.520881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  305.520897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  305.522864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  305.522867] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  305.522870] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  305.523219] [IGT] kms_busy: starting subtest basic-flip-default-C
>[  305.527227] [drm:drm_mode_addfb2] [FB:69]
>[  305.559738] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  305.559801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  305.559880] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  305.568364] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  305.568383] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  305.568401] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  305.568446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  305.568461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  305.568476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  305.568489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  305.568501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  305.568513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  305.568526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  305.568537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  305.568548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  305.568559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  305.568570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  305.568581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  305.568592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  305.568605] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  305.568620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  305.568633] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  305.568646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  305.568660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  305.576356] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  305.576371] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  305.576394] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  305.576411] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  305.576487] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  305.576528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.576578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  305.576597] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  305.576787] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  305.593234] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  305.593256] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  305.593292] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  305.595479] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  305.595499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  305.595519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  305.595535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  305.595550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  305.595564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  305.595578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  305.595593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  305.595606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  305.595619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  305.595633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  305.595648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  305.595661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  305.595673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  305.595957] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  305.595978] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  305.595995] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  305.596011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  305.596026] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  305.596051] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  305.596066] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  305.596080] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  305.596145] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  305.596169] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  305.596186] [drm:intel_power_well_disable [i915]] disabling DC off
>[  305.596201] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  305.596214] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  305.596629] [drm:intel_power_well_disable [i915]] disabling always-on
>[  305.596966] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  305.596976] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  305.597025] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  305.597041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  305.597060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  305.597079] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  305.597094] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  305.597110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  305.597126] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  305.597141] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  305.597156] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  305.597170] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  305.597183] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  305.597186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  305.597199] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  305.597201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  305.597215] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  305.597228] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  305.597241] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  305.597254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  305.597267] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  305.597283] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  305.597295] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  305.597308] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  305.597321] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  305.597334] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  305.597349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  305.597368] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  305.597383] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  305.598161] [drm:intel_power_well_enable [i915]] enabling always-on
>[  305.598174] [drm:intel_power_well_enable [i915]] enabling DC off
>[  305.598447] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  305.598467] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  305.598480] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  305.598533] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  305.598546] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  305.598566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  305.598582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  305.598596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  305.598609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  305.598622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  305.598635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  305.598648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  305.598660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  305.598672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  305.598913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  305.598928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  305.598941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  305.598954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  305.598969] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  305.598986] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  305.599002] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  305.599017] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  305.599035] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  305.599050] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  305.611782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.620253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.628722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.637190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.645658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.654161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.662629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.671097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.679564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.688033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.716083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.724551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.733017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.741483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.749950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.758466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  305.764600] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  305.779463] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  305.779481] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  305.779516] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  305.780341] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  305.781880] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  305.784114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  305.784130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  305.784144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  305.784159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  305.789298] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  305.789313] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  305.794508] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  305.796984] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  305.797472] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  305.814327] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  305.814349] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  305.814385] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  305.835435] [drm:drm_mode_addfb2] [FB:110]
>[  306.503552] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.503678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.503996] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  306.516871] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  306.516910] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  306.516960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  306.516976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  306.516991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  306.517005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  306.517018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  306.517031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  306.517044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  306.517056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  306.517068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  306.517079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  306.517091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  306.517103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  306.517114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  306.517127] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  306.517143] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  306.517156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  306.517170] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  306.517184] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  306.517197] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  306.517218] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  306.517231] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  306.517243] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  306.517262] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  306.517282] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  306.517295] [drm:intel_power_well_disable [i915]] disabling DC off
>[  306.517308] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  306.517320] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  306.518372] [drm:intel_power_well_disable [i915]] disabling always-on
>[  306.518619] [IGT] kms_busy: exiting, ret=0
>[  306.538345] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  306.538369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  306.538394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  306.538420] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  306.538441] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  306.538463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.538485] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  306.538505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  306.538525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  306.538545] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  306.538563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.538567] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  306.538585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.538588] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  306.538606] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  306.538624] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  306.538641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  306.538658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.538674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.538710] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  306.538728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.538745] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  306.538762] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  306.538778] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  306.538804] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  306.538823] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.538845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  306.538869] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  306.538888] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  306.538909] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.538928] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  306.538946] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  306.538964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  306.538981] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.538997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.539000] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  306.539016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.539019] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  306.539036] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  306.539053] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  306.539069] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  306.539086] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.539102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.539123] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  306.539140] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.539156] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  306.539173] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  306.539189] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  306.539210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  306.539234] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  306.539254] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  306.539274] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  306.539293] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  306.539372] [drm:intel_power_well_enable [i915]] enabling always-on
>[  306.539388] [drm:intel_power_well_enable [i915]] enabling DC off
>[  306.539666] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  306.539707] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  306.539725] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  306.539765] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  306.539790] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  306.539811] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  306.539827] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  306.539852] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  306.541919] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  306.541937] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  306.541964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  306.541988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  306.542008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  306.542027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  306.542046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  306.542064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  306.542083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  306.542101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  306.542118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  306.542135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  306.542151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  306.542168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  306.542185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  306.542205] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  306.542227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  306.542248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  306.542269] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  306.542294] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  306.542314] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  306.554299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.562825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.571341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.579858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.588373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.596889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.605402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.613916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.622428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.630940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.639450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.647958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.656483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.664991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.673500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.682041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.690550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  306.715454] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  306.722020] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  306.722035] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  306.722060] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  306.722883] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  306.724735] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  306.726618] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.726633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.726659] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.726673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.731827] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.731842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  306.736989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.739476] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  306.739996] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  306.740048] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  306.740062] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  306.740109] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  306.740122] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  306.743377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.743392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.743407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.743421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.744081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  306.744095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  306.744108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  306.744756] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  306.744769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  306.744782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  306.745428] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.745442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  306.746400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.748661] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  306.749191] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  306.749227] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  306.749241] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  306.749262] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.766030] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  306.766053] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  306.766091] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  306.766133] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  306.766153] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  306.766188] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  306.766340] Console: switching to colour frame buffer device 240x75
>[  306.918032] Console: switching to colour dummy device 80x25
>[  306.918333] [IGT] kms_cursor_legacy: executing
>[  306.959615] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  306.959647] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  306.968148] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  306.976616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  306.985073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  306.993528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.001983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.010438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.018893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.027363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.035817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.044271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.052727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.061180] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.069635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.078089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.086585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.095040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.103495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.111950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.120404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.128859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.137312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.145766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.154221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.162676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.171144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.179598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.188054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.196518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.204979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.213435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.221892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.230347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  307.230356] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  307.230359] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  307.230553] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  307.230569] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  307.231406] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  307.232928] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  307.232944] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  307.232958] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  307.232972] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  307.233805] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  307.234511] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  307.235307] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  307.235332] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  307.235335] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  307.235336] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  307.235338] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  307.235340] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  307.235341] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.235355] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  307.235357] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  307.235358] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  307.235359] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  307.235361] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  307.235362] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  307.235363] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.235522] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  307.235537] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  307.235553] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  307.235799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  307.235816] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  307.237884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.237900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.239882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  307.239886] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  307.242122] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.242137] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  307.244397] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  307.244401] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.244403] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  307.244592] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  307.244610] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  307.245140] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  307.245456] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  307.245472] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  307.245486] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  307.245512] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  307.245924] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  307.246235] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  307.246778] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  307.246780] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  307.246879] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  307.246881] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  307.246884] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.246885] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.246888] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  307.246889] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  307.246895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  307.246897] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  307.246898] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  307.246900] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  307.246901] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  307.246903] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.246905] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  307.246906] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.246908] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  307.246909] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  307.246910] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  307.246912] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.246913] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  307.246915] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  307.246917] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  307.246918] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.246919] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  307.246921] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  307.246923] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  307.246924] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.246925] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  307.246927] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  307.246929] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  307.246930] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  307.246932] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  307.246933] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  307.246934] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  307.246936] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.246937] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  307.246939] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  307.246941] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.246942] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  307.246956] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  307.247126] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  307.247142] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  307.248873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  307.248889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  307.250875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  307.250878] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  307.252872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  307.252888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  307.255151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  307.255155] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  307.255157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  307.255378] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-atomic
>[  307.255597] [drm:drm_mode_addfb2] [FB:68]
>[  307.291234] [drm:drm_mode_addfb2] [FB:110]
>[  307.292736] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.292757] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  307.292772] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  307.293175] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  307.307639] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  307.307658] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  307.307676] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  307.307882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  307.307921] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  307.308240] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  307.316154] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  307.316175] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  307.316221] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  307.316833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  307.316853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  307.316871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  307.316885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  307.316898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  307.316911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  307.316923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  307.316936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  307.316948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  307.316960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  307.316971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  307.316985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  307.316996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  307.317007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  307.317020] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  307.317033] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  307.317046] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  307.317058] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  307.317073] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  307.317086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  307.317100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  307.317126] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  307.317138] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  307.317161] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  307.317175] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  307.329970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.338452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.346920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.355385] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.363851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.372314] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.380782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.389251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.397722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.406185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.414710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.423174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.431638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.440102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.448568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.457033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.465498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.473963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.482428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.483497] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  307.497593] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  307.497613] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  307.497749] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  307.499248] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  307.501033] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  307.502907] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.502923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.502937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.502952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.508098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.508113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  307.513251] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.515725] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  307.516169] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  307.516246] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  307.516261] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  307.549693] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  307.549738] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  307.549776] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  307.549794] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  307.549810] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  307.549834] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  307.549852] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  307.604598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.605257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  307.605443] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  307.618925] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  307.618993] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  307.619054] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  307.619161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  307.619218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  307.619274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  307.619321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  307.619366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  307.619411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  307.619458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  307.619501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  307.619543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  307.619585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  307.619629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  307.619669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  307.619710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  307.620569] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  307.620628] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  307.620680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  307.620979] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  307.621030] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  307.621078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  307.621146] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  307.621191] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  307.621234] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  307.621294] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  307.621366] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  307.621423] [drm:intel_power_well_disable [i915]] disabling DC off
>[  307.621468] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  307.621508] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  307.622857] [drm:intel_power_well_disable [i915]] disabling always-on
>[  307.623308] [IGT] kms_cursor_legacy: exiting, ret=0
>[  307.654051] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  307.654110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  307.654173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  307.654238] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  307.654290] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  307.654345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.654398] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  307.654450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  307.654500] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  307.654548] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  307.654593] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.654603] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  307.654648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.654654] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  307.654701] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  307.654784] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  307.654829] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  307.654873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.654915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.654969] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  307.655014] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.655057] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  307.655100] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  307.655142] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  307.655206] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  307.655257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  307.655312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  307.655374] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  307.655425] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  307.655478] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  307.655527] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  307.655572] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  307.655618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  307.655661] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  307.655703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  307.655734] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  307.655778] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  307.655784] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  307.655829] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  307.655872] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  307.655914] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  307.655955] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  307.655996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  307.656049] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  307.656092] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  307.656134] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  307.656175] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  307.656216] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  307.656270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  307.656332] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  307.656384] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  307.656437] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  307.656486] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  307.656674] [drm:intel_power_well_enable [i915]] enabling always-on
>[  307.656750] [drm:intel_power_well_enable [i915]] enabling DC off
>[  307.657055] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  307.657123] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  307.657175] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  307.657276] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  307.657339] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  307.657407] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  307.657447] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  307.657511] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  307.658133] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  307.658171] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  307.658232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  307.658286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  307.658333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  307.658378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  307.658421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  307.658463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  307.658508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  307.658549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  307.658591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  307.658632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  307.658673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  307.658735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  307.658774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  307.658821] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  307.658874] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  307.658925] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  307.658974] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  307.659034] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  307.659082] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  307.672042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.680844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.689625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.716120] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.724903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.733714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.742538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.751316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.760094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.768793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.777438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.786019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.794582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.803117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.811632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.820141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  307.824625] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  307.839152] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  307.839170] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  307.839199] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  307.840324] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  307.842150] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  307.844031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.844046] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.844060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.844086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.849234] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.849248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  307.854395] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.856876] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  307.857399] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  307.857456] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  307.857471] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  307.857523] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  307.857537] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  307.860797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  307.860814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  307.860828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  307.860843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  307.861502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  307.861516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  307.861529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  307.862179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  307.862192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  307.862205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  307.862853] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  307.862867] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  307.863824] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  307.866159] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  307.866678] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  307.866729] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  307.866743] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  307.866764] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  307.883533] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  307.883555] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  307.883593] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  307.883635] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  307.883655] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  307.883706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  307.883864] Console: switching to colour frame buffer device 240x75
>[  308.039504] Console: switching to colour dummy device 80x25
>[  308.039947] [IGT] kms_cursor_legacy: executing
>[  308.085406] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  308.085443] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  308.093965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.102454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.110914] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.119370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.127826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.136279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.144734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.153189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.161647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.170102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.178648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.187102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.195558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.204021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.212483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.220943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.229398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.237855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.246309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.254765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.263221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.271678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.280146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.288602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.297070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.305528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.313985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.322441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.330897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.339352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.347808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.356263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  308.356272] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  308.356275] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  308.356463] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  308.356488] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  308.357325] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  308.358868] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  308.358885] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  308.358900] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  308.358926] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  308.359751] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  308.360458] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  308.361255] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  308.361282] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  308.361284] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  308.361286] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  308.361287] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  308.361289] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  308.361290] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.361292] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  308.361293] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  308.361295] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  308.361296] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  308.361298] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  308.361299] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  308.361301] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.361477] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  308.361495] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  308.361511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  308.361664] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  308.361679] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  308.363879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.363895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.365890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  308.365893] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  308.368156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.368172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  308.370432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  308.370436] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.370439] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  308.370633] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  308.370651] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  308.371155] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  308.371468] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  308.371484] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  308.371498] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  308.371512] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  308.371923] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  308.372235] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  308.372892] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  308.372894] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  308.372985] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  308.372987] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  308.372990] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.372991] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.372993] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  308.372994] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  308.373000] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  308.373002] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  308.373003] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  308.373005] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  308.373006] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  308.373007] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.373009] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  308.373010] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.373012] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  308.373013] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  308.373014] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  308.373016] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.373017] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  308.373018] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  308.373020] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  308.373021] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.373022] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  308.373024] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  308.373025] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  308.373027] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.373028] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  308.373029] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  308.373031] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  308.373032] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  308.373033] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  308.373035] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  308.373036] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  308.373037] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.373039] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  308.373040] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  308.373041] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.373043] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  308.373044] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  308.373223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  308.373238] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  308.374805] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  308.374819] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  308.376873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  308.376877] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  308.378876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  308.378892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  308.380871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  308.380874] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  308.380877] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  308.381093] [IGT] kms_cursor_legacy: starting subtest basic-busy-flip-before-cursor-legacy
>[  308.381296] [drm:drm_mode_addfb2] [FB:70]
>[  308.416602] [drm:drm_mode_addfb2] [FB:110]
>[  308.418155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.418175] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  308.418188] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  308.418548] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.426152] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.426171] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  308.426202] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  308.426222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  308.426239] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  308.426359] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  308.433924] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  308.433944] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  308.433978] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  308.434224] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  308.434239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  308.434254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  308.434267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  308.434279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  308.434290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  308.434301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  308.434313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  308.434324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  308.434335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  308.434346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  308.434357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  308.434368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  308.434378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  308.434390] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  308.434403] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  308.434415] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  308.434427] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  308.434440] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  308.434453] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  308.434465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  308.434477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  308.434489] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  308.434512] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  308.434525] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  308.446227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.454712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.463270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.471737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.480201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.488666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.497170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.505635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.514102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.522567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.531031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.539494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.547957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.556422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.564888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.573351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.581818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.590281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.598759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.599877] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  308.613974] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  308.613990] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  308.614075] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  308.615614] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  308.618212] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  308.619548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.619563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.619577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.619592] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.624729] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.624744] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  308.629878] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.632263] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  308.632769] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.632798] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.632813] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.666319] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  308.666349] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  308.666387] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  308.666405] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  308.666421] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  308.666445] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  308.666462] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  308.721045] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.721530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.722231] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  308.722409] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  308.733542] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  308.733612] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  308.733672] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  308.734159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  308.734217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  308.734272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  308.734319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  308.734363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  308.734407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  308.734451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  308.734493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  308.734535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  308.734575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  308.734618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  308.734658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  308.734699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  308.735371] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  308.735436] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  308.735488] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  308.735543] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  308.735595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  308.735646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  308.736129] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  308.736175] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  308.736219] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  308.736279] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  308.736353] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  308.736412] [drm:intel_power_well_disable [i915]] disabling DC off
>[  308.736457] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  308.736496] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  308.737621] [drm:intel_power_well_disable [i915]] disabling always-on
>[  308.738366] [IGT] kms_cursor_legacy: exiting, ret=0
>[  308.769052] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  308.769111] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  308.769173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  308.769239] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  308.769291] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  308.769346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.769400] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  308.769452] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  308.769504] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  308.769553] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  308.769598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.769608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  308.769652] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.769659] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  308.769706] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  308.769782] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  308.769828] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  308.769873] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.769916] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.769971] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  308.770015] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.770059] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  308.770102] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  308.770145] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  308.770210] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  308.770260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  308.770315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  308.770378] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  308.770430] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  308.770482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  308.770531] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  308.770577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  308.770621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  308.770663] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  308.770705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  308.770732] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  308.770775] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  308.770781] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  308.770825] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  308.770867] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  308.770908] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  308.770950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  308.770991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  308.771043] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  308.771085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  308.771127] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  308.771168] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  308.771210] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  308.771263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  308.771324] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  308.771376] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  308.771429] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  308.771479] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  308.771646] [drm:intel_power_well_enable [i915]] enabling always-on
>[  308.771687] [drm:intel_power_well_enable [i915]] enabling DC off
>[  308.772033] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  308.772102] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  308.772154] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  308.772262] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  308.772330] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  308.772384] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  308.772434] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  308.772498] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  308.772751] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  308.772790] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  308.772851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  308.772906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  308.772956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  308.773004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  308.773049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  308.773093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  308.773140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  308.773183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  308.773224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  308.773267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  308.773308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  308.773349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  308.773389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  308.773436] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  308.773491] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  308.773541] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  308.773590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  308.773650] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  308.773698] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  308.786993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.795781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.804557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.813335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.822105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.830878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.839714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.848541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.857315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.866093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.874862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.883573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.892217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.900844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.909419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.917952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.926469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.934977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  308.939461] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  308.954176] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  308.954194] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  308.954225] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  308.955054] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  308.957651] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  308.958997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.959011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.959025] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.959040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.964187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.964202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  308.969348] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.971828] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  308.972355] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  308.972410] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  308.972424] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  308.972475] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  308.972488] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  308.975731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  308.975747] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  308.975762] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  308.975777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  308.976437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  308.976451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  308.976464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  308.977111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  308.977125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  308.977138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  308.977786] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  308.977800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  308.978758] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  308.981016] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  308.981538] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  308.981570] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  308.981584] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  308.981605] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  308.998376] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  308.998398] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  308.998437] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  308.998478] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  308.998498] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  308.998533] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  308.998837] Console: switching to colour frame buffer device 240x75
>[  309.166553] Console: switching to colour dummy device 80x25
>[  309.166974] [IGT] kms_cursor_legacy: executing
>[  309.216141] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  309.216199] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  309.224762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.233262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.241729] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.250186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.258641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.267098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.275552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.284007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.292462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.300917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.309369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.317823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.326275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.334729] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.343182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.351637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.360092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.368546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.377000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.385455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.393911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.402447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.410902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.419355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.427809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.436262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.444716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.453169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.461622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.470076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.478530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.486984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  309.486993] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  309.486996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  309.487193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  309.487208] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  309.488044] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  309.489565] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  309.489581] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  309.489607] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  309.489619] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  309.490417] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  309.491149] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  309.491978] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  309.492002] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  309.492004] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  309.492006] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  309.492007] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  309.492009] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  309.492010] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  309.492011] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  309.492013] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  309.492014] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  309.492015] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  309.492017] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  309.492018] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  309.492020] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  309.492183] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  309.492199] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  309.492215] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  309.492363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  309.492378] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  309.493876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  309.493892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  309.496151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  309.496154] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  309.498417] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  309.498433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  309.500691] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  309.500724] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  309.500727] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  309.500957] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  309.500975] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  309.501439] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  309.501859] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  309.501889] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  309.501919] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  309.501932] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  309.502339] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  309.502652] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  309.503188] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  309.503190] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  309.503266] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  309.503267] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  309.503270] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  309.503271] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  309.503274] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  309.503275] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  309.503281] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  309.503283] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  309.503285] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  309.503286] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  309.503287] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  309.503289] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  309.503290] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  309.503292] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  309.503293] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  309.503294] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  309.503296] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  309.503297] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  309.503298] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  309.503300] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  309.503301] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  309.503302] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  309.503304] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  309.503305] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  309.503306] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  309.503308] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  309.503309] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  309.503311] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  309.503312] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  309.503313] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  309.503315] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  309.503316] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  309.503317] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  309.503319] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  309.503320] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  309.503321] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  309.503323] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  309.503324] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  309.503325] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  309.503506] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  309.503522] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  309.504897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  309.504912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  309.506941] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  309.506945] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  309.508871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  309.508886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  309.510869] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  309.510873] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  309.510875] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  309.511130] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-atomic
>[  309.511373] [drm:drm_mode_addfb2] [FB:69]
>[  309.546478] [drm:drm_mode_addfb2] [FB:110]
>[  309.547995] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.548023] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  309.548037] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  309.548395] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.558287] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.558306] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  309.558336] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  309.558356] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  309.558375] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  309.558495] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  309.565959] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  309.565990] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  309.566022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  309.567824] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  309.567841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  309.567858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  309.567871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  309.567884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  309.567897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  309.567909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  309.567922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  309.567935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  309.567947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  309.567958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  309.567972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  309.567984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  309.567995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  309.568009] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  309.568023] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  309.568036] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  309.568049] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  309.568064] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  309.568079] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  309.568093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  309.568106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  309.568119] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  309.568140] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  309.568154] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  309.580870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.589341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.597811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.606278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.614748] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.623215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.631771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.640237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.648705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.657170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.665639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.674105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.682572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.691040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.719440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.727907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.734037] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  309.748485] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  309.748504] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  309.748593] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  309.749598] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  309.752191] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  309.753530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  309.753546] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  309.753559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  309.753574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  309.758713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  309.758728] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  309.763865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  309.766332] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  309.766857] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  309.766884] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  309.766899] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  309.800409] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  309.800438] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  309.800476] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  309.800494] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  309.800509] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  309.800533] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  309.800550] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  309.855484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  309.855683] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  309.869268] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  309.869338] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  309.869398] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  309.869505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  309.869563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  309.869618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  309.869666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  309.869712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  309.870445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  309.870499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  309.870548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  309.870594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  309.870640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  309.870687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  309.871303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  309.871353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  309.871406] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  309.871466] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  309.871516] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  309.871567] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  309.871615] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  309.871663] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  309.872313] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  309.872360] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  309.872402] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  309.872463] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  309.872540] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  309.872598] [drm:intel_power_well_disable [i915]] disabling DC off
>[  309.872643] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  309.872682] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  309.873813] [drm:intel_power_well_disable [i915]] disabling always-on
>[  309.874615] [IGT] kms_cursor_legacy: exiting, ret=0
>[  309.911053] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  309.911114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  309.911177] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  309.911242] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  309.911294] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  309.911349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.911404] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  309.911456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  309.911506] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  309.911554] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  309.911599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.911608] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  309.911653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.911660] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  309.911707] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  309.911789] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  309.911835] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  309.911880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.911923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  309.911979] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  309.912030] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.912089] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  309.912148] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  309.912188] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  309.912251] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  309.912298] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  309.912351] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  309.912411] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  309.912460] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  309.912511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  309.912557] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  309.912600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  309.912643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  309.912684] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  309.912756] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  309.912763] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  309.912804] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  309.912810] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  309.912852] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  309.912892] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  309.912932] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  309.912972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  309.913010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  309.913061] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  309.913101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  309.913140] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  309.913179] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  309.913218] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  309.913269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  309.913328] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  309.913377] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  309.913427] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  309.913473] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  309.913667] [drm:intel_power_well_enable [i915]] enabling always-on
>[  309.913705] [drm:intel_power_well_enable [i915]] enabling DC off
>[  309.914076] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  309.914142] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  309.914192] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  309.914300] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  309.914344] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  309.914396] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  309.914436] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  309.914500] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  309.914786] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  309.914825] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  309.916873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  309.916939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  309.916993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  309.917044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  309.917091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  309.917139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  309.917191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  309.917236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  309.917280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  309.917324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  309.917368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  309.917412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  309.917454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  309.917505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  309.917563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  309.917618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  309.917670] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  309.917849] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  309.917902] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  309.931296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.940083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.948861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.957640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.966531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.975310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.984081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  309.992955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.001772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.010553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.019331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.028107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.036789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.045399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.053986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.062531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.071056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.079568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.084052] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  310.098388] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  310.098407] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  310.098435] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  310.099730] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  310.102451] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  310.103798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.103813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.103827] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.103841] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.108990] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.109004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  310.114151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.116592] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  310.117131] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.117162] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.117177] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.117230] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  310.117243] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  310.120492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.120508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.120522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.120537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.121199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  310.121212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  310.121225] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  310.121873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  310.121887] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  310.121900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  310.122546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.122560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  310.123519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.125786] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  310.126305] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  310.126331] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  310.126346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  310.126367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  310.143138] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  310.143161] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  310.143199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  310.143241] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  310.143261] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  310.143296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  310.143466] Console: switching to colour frame buffer device 240x75
>[  310.298585] Console: switching to colour dummy device 80x25
>[  310.299048] [IGT] kms_cursor_legacy: executing
>[  310.339752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  310.339786] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  310.348278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.356760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.365216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.373671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.382187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.390642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.399096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.407551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.416008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.424463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.432918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.441386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.449841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.458295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.466750] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.475205] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.483660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.492161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.500621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.509081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.517540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.525996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.534455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.542913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.551370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.559827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.568283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.576741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.585199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.593656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.602201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.610659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  310.610668] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  310.610671] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  310.610946] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  310.610967] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  310.611808] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  310.613328] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  310.613344] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  310.613372] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  310.613397] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  310.614271] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  310.614982] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  310.615847] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  310.615873] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  310.615875] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  310.615877] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  310.615878] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  310.615879] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  310.615881] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  310.615882] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  310.615884] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  310.615885] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  310.615886] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  310.615888] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  310.615889] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  310.615890] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  310.616163] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  310.616179] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  310.616197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  310.616345] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  310.616360] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  310.617875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  310.617891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  310.619873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  310.619877] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  310.621873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  310.621889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  310.623869] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  310.623872] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  310.623875] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  310.624064] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  310.624082] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  310.624529] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  310.624866] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  310.624883] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  310.624899] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  310.624913] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  310.625316] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  310.625627] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  310.626151] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  310.626152] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  310.626227] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  310.626228] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  310.626231] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  310.626232] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  310.626235] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  310.626236] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  310.626241] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  310.626243] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  310.626245] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  310.626246] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  310.626247] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  310.626249] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  310.626250] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  310.626251] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  310.626253] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  310.626254] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  310.626256] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  310.626257] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  310.626258] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  310.626260] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  310.626261] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  310.626262] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  310.626264] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  310.626265] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  310.626266] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  310.626268] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  310.626269] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  310.626270] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  310.626272] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  310.626273] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  310.626275] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  310.626276] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  310.626277] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  310.626279] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  310.626280] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  310.626281] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  310.626283] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  310.626284] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  310.626285] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  310.626460] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  310.626475] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  310.627868] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  310.627884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  310.629869] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  310.629873] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  310.631933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  310.631949] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  310.633875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  310.633879] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  310.633881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  310.634107] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-legacy
>[  310.634336] [drm:drm_mode_addfb2] [FB:68]
>[  310.669644] [drm:drm_mode_addfb2] [FB:110]
>[  310.671182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.671201] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  310.671215] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  310.671575] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.685421] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.685443] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  310.685474] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  310.685499] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  310.685518] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  310.685657] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  310.695247] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  310.695268] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  310.695305] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  310.697492] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  310.697515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  310.697535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  310.697552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  310.697567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  310.697583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  310.697598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  310.697613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  310.697627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  310.697641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  310.697655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  310.697670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  310.697684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  310.697985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  310.698003] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  310.698020] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  310.698036] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  310.698051] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  310.698068] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  310.698084] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  310.698100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  310.698115] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  310.698129] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  310.698156] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  310.698171] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  310.710901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.719398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.727877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.736354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.744831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.753307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.761832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.770309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.778788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.787256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.795723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.804189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.812657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.821193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.829658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.838262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.846727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.855191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.863655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  310.864725] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  310.878582] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  310.878599] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  310.878672] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  310.879525] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  310.880244] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  310.882839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  310.882856] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  310.882871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  310.882887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  310.888289] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  310.888304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  310.893501] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  310.895980] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  310.896412] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  310.896439] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  310.896453] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  310.929944] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  310.929971] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  310.930007] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  310.930023] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  310.930037] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  310.930059] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  310.930075] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  310.984039] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.984356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  310.984505] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  310.997843] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  310.997913] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  310.997974] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  310.998081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  310.998138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  310.998193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  310.998241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  310.998287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  310.998332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  310.998379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  310.998422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  310.998464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  310.998505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  310.998548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  310.998589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  310.998629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  310.998677] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  310.999588] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  310.999641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  310.999694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  310.999999] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  311.000049] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  311.000122] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  311.000168] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  311.000212] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  311.000273] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  311.000345] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  311.000403] [drm:intel_power_well_disable [i915]] disabling DC off
>[  311.000447] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  311.000485] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  311.001745] [drm:intel_power_well_disable [i915]] disabling always-on
>[  311.002225] [IGT] kms_cursor_legacy: exiting, ret=0
>[  311.034159] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  311.034220] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  311.034284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  311.034349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.034400] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  311.034455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.034512] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  311.034564] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.034614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  311.034662] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  311.034709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.034763] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  311.034812] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.034819] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  311.034867] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  311.034914] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  311.034960] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  311.035003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.035046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  311.035100] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  311.035145] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.035188] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  311.035231] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  311.035273] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  311.035337] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  311.035388] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.035444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  311.035506] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  311.035558] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  311.035611] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.035660] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  311.035707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  311.035841] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  311.035886] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.035929] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.035936] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  311.035979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.035986] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  311.036031] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  311.036073] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  311.036115] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  311.036156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.036197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  311.036250] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  311.036294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.036336] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  311.036378] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  311.036419] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  311.036472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  311.036533] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  311.036585] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  311.036636] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  311.036684] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  311.036904] [drm:intel_power_well_enable [i915]] enabling always-on
>[  311.036945] [drm:intel_power_well_enable [i915]] enabling DC off
>[  311.037250] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  311.037319] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  311.037374] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  311.037476] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  311.037520] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  311.037572] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  311.037612] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  311.037675] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  311.039914] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  311.039958] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  311.040025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  311.040084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  311.040136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  311.040185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  311.040233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  311.040278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  311.040327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  311.040371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  311.040414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  311.040456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  311.040499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  311.040542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  311.040584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  311.040634] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  311.040692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  311.040835] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  311.040889] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  311.040953] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  311.041006] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  311.054304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.063094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.071876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.080712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.089559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.098339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.107115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.115894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.124701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.133582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.142356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.151080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.159720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.168305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.176874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.185452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.193975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.202485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.206991] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  311.221487] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  311.221502] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  311.221610] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  311.222777] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  311.225377] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  311.226880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.226894] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.226920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.226933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.232092] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.232107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  311.237252] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.239737] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  311.240240] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.240311] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.240324] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.240371] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  311.240383] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  311.243643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.243689] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.243715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.243729] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.244386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  311.244400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  311.244413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  311.245074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  311.245088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  311.245101] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  311.245748] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.245762] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  311.246721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.249082] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  311.250521] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  311.250592] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  311.250635] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  311.250698] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.267515] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  311.267594] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  311.267720] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  311.267921] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  311.267992] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  311.268110] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  311.268564] Console: switching to colour frame buffer device 240x75
>[  311.473293] Console: switching to colour dummy device 80x25
>[  311.473593] [IGT] kms_cursor_legacy: executing
>[  311.528908] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  311.528956] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  311.537513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.545993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.554452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.562907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.571360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.579816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.588270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.596724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.605179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.613633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.622088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.630542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.638996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.647451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.655905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.664358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.672812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.681265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.689720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.715967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.724422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.732875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.741329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.749784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.758238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.766703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.775157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.783612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.792066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.800519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.808974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.817439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  311.817448] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  311.817452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  311.817626] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  311.817641] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  311.818474] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  311.820079] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  311.820096] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  311.820110] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  311.820125] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  311.820922] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  311.821628] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  311.822410] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  311.822435] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  311.822438] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  311.822452] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  311.822453] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  311.822455] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  311.822456] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  311.822458] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  311.822459] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  311.822460] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  311.822462] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  311.822463] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  311.822465] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  311.822466] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  311.822624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  311.822639] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  311.822655] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  311.823192] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  311.823207] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  311.824877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  311.824893] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  311.826889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  311.826893] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  311.829157] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  311.829173] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  311.831435] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  311.831439] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  311.831441] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  311.831618] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  311.831636] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  311.832140] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  311.832455] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  311.832500] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  311.832514] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  311.832526] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  311.833051] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  311.833364] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  311.833902] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  311.833904] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  311.833983] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  311.833985] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  311.833988] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  311.833989] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  311.833991] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  311.833992] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  311.833998] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  311.834000] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  311.834002] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  311.834003] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  311.834004] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  311.834006] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  311.834007] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  311.834009] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  311.834010] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  311.834011] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  311.834013] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  311.834014] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  311.834016] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  311.834017] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  311.834018] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  311.834020] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  311.834021] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  311.834023] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  311.834024] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  311.834025] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  311.834027] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  311.834028] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  311.834030] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  311.834031] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  311.834032] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  311.834034] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  311.834035] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  311.834037] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  311.834038] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  311.834039] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  311.834041] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  311.834042] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  311.834043] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  311.834212] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  311.834227] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  311.835851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  311.835865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  311.837871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  311.837875] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  311.839873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  311.839888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  311.841878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  311.841881] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  311.841884] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  311.842109] [IGT] kms_cursor_legacy: starting subtest basic-flip-after-cursor-varying-size
>[  311.842307] [drm:drm_mode_addfb2] [FB:70]
>[  311.877691] [drm:drm_mode_addfb2] [FB:110]
>[  311.877783] [drm:drm_mode_addfb2] [FB:115]
>[  311.879272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.879292] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  311.879306] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  311.879658] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.891388] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.891409] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  311.891426] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  311.891459] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  311.891477] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  311.891508] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  311.901228] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  311.901248] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  311.901281] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  311.901414] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  311.901431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  311.901446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  311.901460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  311.901473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  311.901485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  311.901497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  311.901510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  311.901521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  311.901533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  311.901545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  311.901557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  311.901569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  311.901579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  311.901592] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  311.901606] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  311.901619] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  311.901633] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  311.901647] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  311.901661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  311.901675] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  311.901711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  311.901724] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  311.901747] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  311.901763] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  311.914486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.922955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.931421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.939888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.948351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.956818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.965281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.973761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.982259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.990725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  311.999189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.007656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.016144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.024609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.033075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.041539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.050005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.058471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.066938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.068023] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  312.082115] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  312.082133] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  312.082213] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  312.083620] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  312.086197] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  312.087829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.087844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.087858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.087873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.093008] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.093024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  312.098160] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.100620] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  312.101151] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.101180] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.101194] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.134720] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  312.134750] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  312.134788] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  312.134806] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  312.134821] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  312.134845] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  312.134863] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  312.188242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.188553] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  312.188700] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  312.202077] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  312.202134] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  312.202184] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  312.202273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  312.202320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  312.202366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  312.202405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  312.202443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  312.202481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  312.202519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  312.202555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  312.202589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  312.202623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  312.202659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  312.202693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  312.203386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  312.203429] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  312.203478] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  312.203519] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  312.203562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  312.203604] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  312.203645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  312.203702] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  312.204086] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  312.204122] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  312.204173] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  312.204234] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  312.204281] [drm:intel_power_well_disable [i915]] disabling DC off
>[  312.204319] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  312.204351] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  312.205390] [drm:intel_power_well_disable [i915]] disabling always-on
>[  312.206044] [IGT] kms_cursor_legacy: exiting, ret=0
>[  312.232161] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  312.232221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  312.232283] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  312.232349] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  312.232401] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  312.232456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.232513] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  312.232564] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  312.232615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  312.232662] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  312.232709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.232749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  312.232796] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.232803] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  312.232850] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  312.232896] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  312.232941] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  312.232985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.233029] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  312.233083] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  312.233128] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.233172] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  312.233215] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  312.233259] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  312.233324] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  312.233375] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  312.233431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  312.233492] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  312.233544] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  312.233597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  312.233646] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  312.233693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  312.233761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  312.233806] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  312.233849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  312.233857] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  312.233901] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  312.233907] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  312.233952] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  312.233995] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  312.234037] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  312.234079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  312.234121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  312.234174] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  312.234217] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  312.234261] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  312.234303] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  312.234344] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  312.234398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  312.234459] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  312.234512] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  312.234565] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  312.234615] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  312.234882] [drm:intel_power_well_enable [i915]] enabling always-on
>[  312.234923] [drm:intel_power_well_enable [i915]] enabling DC off
>[  312.235227] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  312.235296] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  312.235350] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  312.235455] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  312.235499] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  312.235550] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  312.235590] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  312.235653] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  312.235882] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  312.235920] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  312.235978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  312.236031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  312.236080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  312.236126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  312.236170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  312.236213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  312.236258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  312.236300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  312.236341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  312.236382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  312.236422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  312.236462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  312.236502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  312.236548] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  312.236602] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  312.236652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  312.236701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  312.236791] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  312.236840] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  312.249986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.258776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.267557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.276334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.285105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.293877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.302708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.311535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.320626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.329530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.338322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.347019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.355660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.364280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.372935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.381462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.389977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.398486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  312.402994] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  312.417138] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  312.417156] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  312.417190] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  312.418618] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  312.421232] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  312.422577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.422592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.422606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.422620] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.427769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.427784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  312.432931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.435411] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  312.435954] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  312.435992] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  312.436007] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  312.436058] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  312.436071] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  312.439315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  312.439331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  312.439345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  312.439359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  312.440019] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  312.440033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  312.440046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  312.440711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  312.440724] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  312.440737] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  312.441383] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  312.441397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  312.442354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  312.444546] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  312.445081] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  312.445106] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  312.445120] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  312.445140] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  312.461910] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  312.461932] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  312.461970] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  312.462012] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  312.462032] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  312.462066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  312.462217] Console: switching to colour frame buffer device 240x75
>[  312.622450] Console: switching to colour dummy device 80x25
>[  312.622860] [IGT] kms_cursor_legacy: executing
>[  312.673697] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  312.673744] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  312.682313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.690816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.717653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.726108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.734611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.743066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.751522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.759978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.768446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.776901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.785355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.793810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.802265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.810720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.819260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.827714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.836167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.844623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.853077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.861533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.869987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.878441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.886896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.895352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.903806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.912261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.920715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.929169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.937623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.946077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.954532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.962987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  312.962996] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  312.962999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  312.963183] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  312.963198] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  312.964034] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  312.965573] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  312.965590] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  312.965604] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  312.965618] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  312.966416] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  312.967129] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  312.967918] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  312.967943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  312.967947] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  312.967961] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  312.967963] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  312.967964] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  312.967965] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  312.967967] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  312.967968] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  312.967970] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  312.967971] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  312.967972] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  312.967974] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  312.967975] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  312.968139] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  312.968154] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  312.968168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  312.968322] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  312.968336] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  312.969871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  312.969886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  312.971870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  312.971874] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  312.973871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  312.973887] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  312.975870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  312.975874] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  312.975876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  312.976071] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  312.976089] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  312.976536] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  312.976888] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  312.976905] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  312.976932] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  312.976944] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  312.977364] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  312.977677] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  312.978216] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  312.978218] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  312.978295] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  312.978297] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  312.978300] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  312.978301] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  312.978303] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  312.978304] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  312.978310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  312.978312] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  312.978313] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  312.978314] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  312.978316] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  312.978317] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  312.978319] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  312.978320] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  312.978321] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  312.978323] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  312.978324] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  312.978325] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  312.978327] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  312.978328] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  312.978329] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  312.978331] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  312.978332] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  312.978333] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  312.978335] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  312.978336] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  312.978337] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  312.978339] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  312.978340] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  312.978342] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  312.978343] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  312.978344] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  312.978346] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  312.978347] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  312.978348] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  312.978350] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  312.978351] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  312.978352] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  312.978354] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  312.978543] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  312.978559] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  312.979858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  312.979873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  312.981877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  312.981881] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  312.983866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  312.983882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  312.985870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  312.985873] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  312.985876] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  312.986106] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-atomic
>[  312.986319] [drm:drm_mode_addfb2] [FB:69]
>[  313.021731] [drm:drm_mode_addfb2] [FB:110]
>[  313.023305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.023329] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  313.023342] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  313.023785] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.038471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.038491] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  313.038509] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  313.038530] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  313.038561] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  313.038682] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  313.047141] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  313.047160] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  313.047207] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  313.047363] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  313.047379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  313.047394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  313.047407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  313.047420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  313.047432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  313.047444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  313.047456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  313.047468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  313.047479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  313.047490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  313.047502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  313.047513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  313.047524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  313.047536] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  313.047549] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  313.047562] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  313.047574] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  313.047588] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  313.047601] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  313.047614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  313.047626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  313.047639] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  313.047662] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  313.047675] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  313.060864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.069331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.077798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.086264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.094730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.103194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.111660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.120193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.128659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.137192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.145660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.154189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.162655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.171120] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.179586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.188052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.196518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.204983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.213447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.214517] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  313.228477] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  313.228496] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  313.228548] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  313.230025] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  313.232324] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  313.233728] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.233743] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.233757] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.233772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.238907] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.238923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  313.244058] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.246535] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  313.247055] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.247084] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.247099] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.280647] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  313.280680] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  313.280867] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  313.280889] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  313.280906] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  313.280934] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  313.280954] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  313.335036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.335348] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  313.335492] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  313.348821] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  313.348890] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  313.348951] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  313.349058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  313.349115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  313.349169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  313.349217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  313.349263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  313.349309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  313.349356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  313.349400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  313.349442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  313.349484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  313.349527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  313.349568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  313.349608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  313.349656] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  313.349711] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  313.350983] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  313.351040] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  313.351092] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  313.351142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  313.351212] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  313.351258] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  313.351301] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  313.351361] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  313.351435] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  313.351493] [drm:intel_power_well_disable [i915]] disabling DC off
>[  313.351537] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  313.351577] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  313.352935] [drm:intel_power_well_disable [i915]] disabling always-on
>[  313.353418] [IGT] kms_cursor_legacy: exiting, ret=0
>[  313.380164] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  313.380224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  313.380287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  313.380353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  313.380405] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  313.380460] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.380516] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  313.380567] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  313.380617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  313.380665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  313.380712] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.380753] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  313.380800] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.380806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  313.380852] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  313.380898] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  313.380943] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  313.380986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.381029] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  313.381083] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  313.381127] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.381170] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  313.381213] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  313.381255] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  313.381319] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  313.381369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  313.381425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  313.381487] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  313.381538] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  313.381591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  313.381640] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  313.381686] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  313.381754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  313.381798] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  313.381841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  313.381848] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  313.381891] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  313.381897] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  313.381941] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  313.381984] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  313.382026] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  313.382069] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  313.382111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  313.382165] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  313.382207] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  313.382249] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  313.382291] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  313.382333] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  313.382387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  313.382450] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  313.382503] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  313.382555] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  313.382606] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  313.382941] [drm:intel_power_well_enable [i915]] enabling always-on
>[  313.382983] [drm:intel_power_well_enable [i915]] enabling DC off
>[  313.383287] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  313.383357] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  313.383410] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  313.383518] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  313.383563] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  313.383614] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  313.383654] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  313.383717] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  313.385916] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  313.385961] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  313.386029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  313.386090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  313.386142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  313.386192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  313.386241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  313.386287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  313.386335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  313.386381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  313.386425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  313.386468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  313.386512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  313.386556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  313.386599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  313.386648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  313.386706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  313.386849] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  313.386902] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  313.386968] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  313.387021] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  313.400392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.409183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.417966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.426793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.435643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.444491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.453264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.462042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.470867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.479644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.488509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.497208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.505856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.514430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.522979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.531513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.540036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.548551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  313.553036] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  313.567508] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  313.567552] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  313.567621] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  313.568571] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  313.569780] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  313.572783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.572826] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.572866] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.572909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.578427] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.578466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  313.583802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.586390] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  313.587635] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  313.587714] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  313.587783] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  313.587906] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  313.587942] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  313.591442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  313.591484] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  313.591521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  313.591560] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  313.592404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  313.592441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  313.592475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  313.593342] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  313.593378] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  313.593412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  313.594235] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  313.594272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  313.595405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  313.597797] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  313.599004] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  313.599069] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  313.599105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  313.599158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  313.615944] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  313.616003] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  313.616201] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  313.616305] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  313.616357] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  313.616446] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  313.616888] Console: switching to colour frame buffer device 240x75
>[  313.822317] Console: switching to colour dummy device 80x25
>[  313.822419] [IGT] kms_cursor_legacy: executing
>[  313.868004] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  313.868079] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  313.876657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.885210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.893680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.902149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.910605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.919073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.927530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.935986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.944440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.952896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.961350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.969806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.978260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.986716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  313.995172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.003628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.012083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.020537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.028993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.037448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.045904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.054358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.062814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.071268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.079724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.088251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.096707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.105163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.113619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.122075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.130531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.138987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  314.138996] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  314.138999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  314.139194] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  314.139209] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  314.140046] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  314.141576] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  314.141597] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  314.141612] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  314.141626] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  314.142425] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  314.143139] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  314.143923] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  314.143959] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  314.143961] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  314.143963] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  314.143964] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  314.143965] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  314.143967] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  314.143968] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  314.143969] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  314.143971] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  314.143972] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  314.143974] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  314.143975] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  314.143976] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  314.144134] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  314.144151] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  314.144168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  314.144317] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  314.144331] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  314.145876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  314.145891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  314.147866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  314.147870] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  314.149866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  314.149882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  314.151870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  314.151874] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  314.151877] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  314.152062] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  314.152080] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  314.152527] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  314.152876] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  314.152920] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  314.152934] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  314.152947] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  314.153352] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  314.153665] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  314.154225] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  314.154227] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  314.154304] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  314.154306] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  314.154310] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  314.154311] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  314.154313] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  314.154314] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  314.154321] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  314.154322] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  314.154324] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  314.154325] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  314.154327] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  314.154328] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  314.154329] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  314.154331] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  314.154332] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  314.154334] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  314.154335] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  314.154336] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  314.154338] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  314.154339] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  314.154341] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  314.154342] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  314.154343] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  314.154345] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  314.154346] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  314.154348] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  314.154349] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  314.154350] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  314.154352] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  314.154353] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  314.154355] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  314.154356] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  314.154357] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  314.154359] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  314.154360] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  314.154361] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  314.154363] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  314.154364] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  314.154365] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  314.154559] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  314.154574] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  314.155786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  314.155801] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  314.157873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  314.157877] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  314.159866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  314.159882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  314.161905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  314.161909] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  314.161911] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  314.162140] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-legacy
>[  314.162352] [drm:drm_mode_addfb2] [FB:68]
>[  314.198737] [drm:drm_mode_addfb2] [FB:110]
>[  314.200182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.200202] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  314.200216] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  314.200589] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.206526] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.206587] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  314.206642] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  314.206707] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  314.207167] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  314.207541] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  314.217121] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  314.217188] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  314.217294] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  314.219690] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  314.219807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  314.219869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  314.219921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  314.219972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  314.220021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  314.220067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  314.220116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  314.220161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  314.220205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  314.220249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  314.220298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  314.220341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  314.220384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  314.220434] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  314.220485] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  314.220537] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  314.220586] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  314.220641] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  314.220696] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  314.221420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  314.221500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  314.221577] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  314.221683] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  314.221822] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  314.235047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.243775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.252493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.261210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.269926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.278640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.287407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.295982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.304519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.313025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.321513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.329984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.338450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.346915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.355393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.363859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.372324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.380789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.386718] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  314.402341] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  314.402357] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  314.402408] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  314.403248] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  314.403968] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  314.406562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.406578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.406594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.406610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.412016] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.412031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  314.417179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.419709] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  314.421086] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.421190] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.421240] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.454816] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  314.454908] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  314.455022] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  314.455079] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  314.455129] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  314.455205] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  314.455260] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  314.510820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  314.511049] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  314.522249] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  314.522426] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  314.522488] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  314.522596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  314.522653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  314.522709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  314.523377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  314.523429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  314.523478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  314.523529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  314.523575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  314.523619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  314.523662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  314.523706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  314.524387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  314.524434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  314.524485] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  314.524544] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  314.524594] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  314.524647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  314.524697] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  314.525330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  314.525399] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  314.525445] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  314.525488] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  314.525548] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  314.525623] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  314.525680] [drm:intel_power_well_disable [i915]] disabling DC off
>[  314.526300] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  314.526341] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  314.527312] [drm:intel_power_well_disable [i915]] disabling always-on
>[  314.527991] [IGT] kms_cursor_legacy: exiting, ret=0
>[  314.554126] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  314.554186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  314.554249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  314.554315] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  314.554368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  314.554424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.554480] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  314.554533] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  314.554583] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  314.554631] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  314.554677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.554712] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  314.554759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.554766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  314.554814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  314.554860] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  314.554905] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  314.554949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.554992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  314.555047] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  314.555092] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.555136] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  314.555179] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  314.555223] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  314.555287] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  314.555337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  314.555394] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  314.555456] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  314.555508] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  314.555561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  314.555609] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  314.555654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  314.555701] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  314.555805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  314.555849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  314.555856] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  314.555899] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  314.555906] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  314.555951] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  314.555994] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  314.556036] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  314.556078] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  314.556119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  314.556172] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  314.556216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  314.556259] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  314.556300] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  314.556341] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  314.556395] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  314.556457] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  314.556510] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  314.556562] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  314.556612] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  314.556852] [drm:intel_power_well_enable [i915]] enabling always-on
>[  314.556894] [drm:intel_power_well_enable [i915]] enabling DC off
>[  314.557198] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  314.557267] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  314.557319] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  314.557424] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  314.557466] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  314.557519] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  314.557560] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  314.557623] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  314.558919] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  314.558963] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  314.559030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  314.559090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  314.559142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  314.559191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  314.559239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  314.559286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  314.559334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  314.559379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  314.559424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  314.559467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  314.559510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  314.559554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  314.559596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  314.559647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  314.559704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  314.559785] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  314.559838] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  314.559901] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  314.559952] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  314.572920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.581713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.590528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.599307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.608084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.616858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.625635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.634492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.643266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.652069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.660845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.669525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.678140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.686729] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.714378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.722890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  314.725793] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  314.740107] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  314.740125] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  314.740156] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  314.741426] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  314.744044] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  314.745388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.745403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.745416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.745431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.750579] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.750594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  314.755743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.758223] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  314.758766] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  314.758803] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  314.758817] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  314.758868] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  314.758882] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  314.762129] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  314.762145] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  314.762159] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  314.762174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  314.762834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  314.762847] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  314.762860] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  314.763508] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  314.763521] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  314.763534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  314.764181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  314.764195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  314.765151] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  314.767413] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  314.767949] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  314.767980] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  314.767994] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  314.768015] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  314.784784] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  314.784806] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  314.784843] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  314.784885] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  314.784904] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  314.784939] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  314.785090] Console: switching to colour frame buffer device 240x75
>[  314.971542] Console: switching to colour dummy device 80x25
>[  314.971928] [IGT] kms_cursor_legacy: executing
>[  315.020454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  315.020505] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  315.029041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.037527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.045986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.054440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.062894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.071347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.079799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.088301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.096756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.105209] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.113662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.122179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.130633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.139087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.147539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.155993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.164446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.172898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.181351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.189804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.198256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.206709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.215161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.223613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.232068] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.240531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.248992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.257449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.265905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.274362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.282819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.291373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  315.291381] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  315.291385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  315.291566] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  315.291581] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  315.292419] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  315.293943] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  315.293960] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  315.293975] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  315.294001] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  315.294823] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  315.295530] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  315.296319] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  315.296345] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  315.296348] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  315.296349] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  315.296351] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  315.296353] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  315.296367] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  315.296368] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  315.296369] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  315.296371] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  315.296372] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  315.296374] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  315.296375] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  315.296376] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  315.296555] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  315.296569] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  315.296586] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  315.296853] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  315.296874] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  315.298876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  315.298892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  315.300898] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  315.300902] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  315.303159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  315.303175] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  315.305433] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  315.305437] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  315.305439] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  315.305623] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  315.305641] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  315.306102] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  315.306416] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  315.306432] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  315.306446] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  315.306460] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  315.306868] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  315.307179] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  315.307666] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  315.307667] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  315.307842] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  315.307844] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  315.307847] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  315.307848] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  315.307852] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  315.307854] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  315.307874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  315.307875] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  315.307877] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  315.307878] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  315.307880] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  315.307881] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  315.307883] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  315.307884] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  315.307886] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  315.307887] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  315.307889] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  315.307890] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  315.307905] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  315.307906] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  315.307908] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  315.307909] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  315.307910] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  315.307912] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  315.307913] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  315.307915] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  315.307916] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  315.307917] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  315.307919] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  315.307920] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  315.307922] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  315.307923] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  315.307924] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  315.307926] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  315.307927] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  315.307928] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  315.307930] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  315.307931] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  315.307933] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  315.308119] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  315.308134] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  315.309872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  315.309888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  315.311866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  315.311869] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  315.313866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  315.313882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  315.315875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  315.315879] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  315.315881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  315.316104] [IGT] kms_cursor_legacy: starting subtest basic-flip-before-cursor-varying-size
>[  315.316330] [drm:drm_mode_addfb2] [FB:70]
>[  315.351625] [drm:drm_mode_addfb2] [FB:110]
>[  315.351864] [drm:drm_mode_addfb2] [FB:115]
>[  315.353513] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.353535] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  315.353549] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  315.354081] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.360254] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.360274] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  315.360291] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  315.360312] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  315.360346] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  315.360468] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  315.370185] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  315.370205] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  315.370251] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  315.372437] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  315.372457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  315.372474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  315.372488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  315.372501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  315.372514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  315.372527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  315.372540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  315.372552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  315.372564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  315.372575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  315.372588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  315.372600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  315.372612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  315.372625] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  315.372639] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  315.372653] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  315.372666] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  315.372681] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  315.373001] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  315.373019] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  315.373035] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  315.373050] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  315.373074] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  315.373088] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  315.385818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.394289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.402756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.411221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.419766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.428232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.436698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.445163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.453628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.462093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.470561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.479028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.487496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.495964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.504431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.512897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.521363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.529829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.538294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.539379] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  315.553440] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  315.553460] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  315.553493] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  315.555083] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  315.556868] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  315.558739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.558755] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.558769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.558797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.563930] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.563946] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  315.569096] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.571562] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  315.572105] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.572133] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.572146] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.605825] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  315.605919] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  315.606032] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  315.606089] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  315.606138] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  315.606213] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  315.606269] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  315.661942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.662422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  315.662646] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  315.673820] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  315.673889] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  315.673950] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  315.674057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  315.674114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  315.674169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  315.674218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  315.674265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  315.674312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  315.674359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  315.674403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  315.674445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  315.674487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  315.674530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  315.674572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  315.674612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  315.674660] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  315.674714] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  315.675720] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  315.675923] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  315.675976] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  315.676028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  315.676098] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  315.676144] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  315.676189] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  315.676250] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  315.676322] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  315.676380] [drm:intel_power_well_disable [i915]] disabling DC off
>[  315.676425] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  315.676466] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  315.677742] [drm:intel_power_well_disable [i915]] disabling always-on
>[  315.678249] [IGT] kms_cursor_legacy: exiting, ret=0
>[  315.732162] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  315.732224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  315.732286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  315.732351] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  315.732402] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  315.732458] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.732514] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  315.732566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  315.732617] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  315.732664] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  315.732710] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.732751] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  315.732799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.732806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  315.732854] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  315.732901] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  315.732946] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  315.732991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.733034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.733089] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  315.733133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.733176] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  315.733219] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  315.733261] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  315.733325] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  315.733374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  315.733430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  315.733492] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  315.733543] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  315.733596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  315.733645] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  315.733691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  315.733761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  315.733805] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  315.733847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  315.733854] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  315.733896] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  315.733902] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  315.733946] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  315.733988] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  315.734030] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  315.734072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  315.734113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  315.734165] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  315.734208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  315.734251] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  315.734292] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  315.734334] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  315.734387] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  315.734448] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  315.734500] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  315.734551] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  315.734600] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  315.734877] [drm:intel_power_well_enable [i915]] enabling always-on
>[  315.734919] [drm:intel_power_well_enable [i915]] enabling DC off
>[  315.735223] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  315.735291] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  315.735343] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  315.735452] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  315.735497] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  315.735549] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  315.735589] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  315.735652] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  315.736309] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  315.736347] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  315.736408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  315.736463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  315.736510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  315.736556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  315.736600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  315.736643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  315.736689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  315.736760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  315.736802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  315.736843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  315.736885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  315.736925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  315.736965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  315.737011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  315.737066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  315.737116] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  315.737165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  315.737226] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  315.737275] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  315.749884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.758710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.767527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.776304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.785081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.793853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.802635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.811495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.820275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.829056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.837758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.846379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.854961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.863511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.872423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.880944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.889455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.897965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  315.902479] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  315.917118] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  315.917136] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  315.917168] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  315.918133] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  315.920752] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  315.922097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.922112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.922125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.922140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.927288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.927302] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  315.932448] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.934929] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  315.935453] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  315.935510] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  315.935524] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  315.935575] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  315.935589] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  315.938846] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  315.938862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  315.938876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  315.938891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  315.939549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  315.939563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  315.939576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  315.940225] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  315.940238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  315.940251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  315.940914] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  315.940928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  315.941898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  315.944258] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  315.944791] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  315.944817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  315.944831] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  315.944851] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  315.961619] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  315.961641] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  315.961679] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  315.961739] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  315.961759] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  315.961794] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  315.961929] Console: switching to colour frame buffer device 240x75
>[  316.119922] Console: switching to colour dummy device 80x25
>[  316.120238] [IGT] kms_flip: executing
>[  316.138643] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  316.138755] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  316.147544] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.156238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.164920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.173652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.182412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.191095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.199779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.208499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.217221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.225879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.234443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.242988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.251506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.259993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.268463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.276922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.285391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.293847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.302302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.310759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.319251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.327707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.336163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.344618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.353074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.361530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.369985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.378442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.386897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.395351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.403807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.412262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  316.412271] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  316.412274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  316.412287] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  316.412304] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  316.413173] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  316.414706] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  316.414723] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  316.414749] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  316.414763] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  316.415554] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  316.416266] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  316.417048] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  316.417072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  316.417076] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  316.417078] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  316.417079] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  316.417081] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  316.417082] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  316.417084] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  316.417085] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  316.417087] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  316.417088] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  316.417090] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  316.417091] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  316.417093] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  316.417107] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  316.417123] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  316.417152] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  316.417159] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  316.417173] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  316.418871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  316.418887] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  316.420873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  316.420877] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  316.422868] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  316.422883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  316.424868] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  316.424872] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  316.424874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  316.424884] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  316.424901] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  316.425351] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  316.425664] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  316.425679] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  316.425734] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  316.425755] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  316.426168] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  316.426480] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  316.426977] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  316.426979] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  316.427056] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  316.427057] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  316.427061] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  316.427062] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  316.427065] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  316.427066] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  316.427071] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  316.427073] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  316.427074] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  316.427076] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  316.427077] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  316.427079] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  316.427080] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  316.427081] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  316.427083] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  316.427084] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  316.427085] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  316.427087] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  316.427088] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  316.427089] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  316.427091] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  316.427092] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  316.427093] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  316.427095] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  316.427096] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  316.427098] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  316.427099] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  316.427100] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  316.427102] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  316.427103] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  316.427104] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  316.427106] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  316.427107] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  316.427108] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  316.427110] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  316.427111] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  316.427112] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  316.427114] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  316.427115] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  316.427142] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  316.427157] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  316.428781] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  316.428795] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  316.430830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  316.430834] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  316.432879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  316.432895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  316.434875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  316.434879] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  316.434881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  316.435089] [IGT] kms_flip: starting subtest basic-flip-vs-dpms
>[  316.435763] [drm:drm_mode_addfb2] [FB:69]
>[  316.435823] [drm:drm_mode_addfb2] [FB:110]
>[  316.485918] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  316.485988] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  316.486064] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  316.503150] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  316.503184] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  316.503200] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  316.503232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  316.503247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  316.503261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  316.503275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  316.503287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  316.503300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  316.503312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  316.503323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  316.503335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  316.503346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  316.503357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  316.503368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  316.503379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  316.503393] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  316.503408] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  316.503422] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  316.503435] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  316.503448] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  316.511646] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  316.511663] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  316.511690] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  316.511926] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  316.511992] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  316.512040] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.512101] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  316.512122] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  316.512276] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  316.528443] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  316.528465] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  316.528500] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  316.532866] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  316.532889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  316.532911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  316.532929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  316.532945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  316.532961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  316.532977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  316.532993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  316.533007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  316.533022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  316.533036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  316.533052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  316.533066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  316.533080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  316.533097] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  316.533116] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  316.533134] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  316.533151] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  316.533167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  316.533197] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  316.533214] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  316.533230] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  316.533253] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  316.533278] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  316.533296] [drm:intel_power_well_disable [i915]] disabling DC off
>[  316.533312] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  316.533326] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  316.534447] [drm:intel_power_well_disable [i915]] disabling always-on
>[  316.534537] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  316.535079] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  316.535089] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  316.535140] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  316.535158] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  316.535177] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  316.535197] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.535213] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.535230] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.535247] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  316.535263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  316.535278] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.535293] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  316.535307] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.535310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  316.535324] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.535326] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  316.535340] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  316.535354] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.535368] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  316.535381] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.535394] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.535411] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  316.535425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.535438] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  316.535451] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  316.535464] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  316.535480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.535499] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  316.535515] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  316.536381] [drm:intel_power_well_enable [i915]] enabling always-on
>[  316.536394] [drm:intel_power_well_enable [i915]] enabling DC off
>[  316.536668] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  316.536771] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  316.536794] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  316.536832] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  316.536846] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  316.536868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  316.536886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  316.536903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  316.536919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  316.536933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  316.536948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  316.536964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  316.536978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  316.536992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  316.537005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  316.537019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  316.537033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  316.537046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  316.537062] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  316.537080] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  316.537096] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  316.537113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  316.537132] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  316.537148] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  316.549945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.558446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.566947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.575448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.583945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.592441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.600937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.609432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.617927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.626421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.634909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.643397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.651867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.660334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.668805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.677274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.685742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.714370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.715468] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  316.719971] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  316.719988] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  316.720084] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  316.720916] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  316.721636] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  316.724231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.724248] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.724264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.724280] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.729687] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.729714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  316.734865] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.737331] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  316.737962] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  316.738027] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  316.738040] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  316.754837] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  316.754858] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  316.754891] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  316.788327] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  316.788349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  316.788370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  316.788392] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.788409] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.788428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.788446] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  316.788463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  316.788480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.788495] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  316.788511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.788515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  316.788530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.788532] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  316.788548] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  316.788562] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.788577] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  316.788591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.788605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.788623] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  316.788637] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.788652] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.788666] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  316.788680] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  316.789205] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  316.789225] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.789245] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  316.789262] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  316.805267] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  316.822423] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  316.822463] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  316.822499] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  316.822563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  316.822595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  316.822623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  316.822650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  316.822675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  316.823095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  316.823128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  316.823156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  316.823183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  316.823209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  316.823236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  316.823261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  316.823285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  316.823314] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  316.823345] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  316.823374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  316.823402] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  316.823442] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  316.823468] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  316.823493] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  316.823529] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  316.823561] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  316.823590] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  316.823622] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  316.823653] [drm:intel_power_well_disable [i915]] disabling DC off
>[  316.823678] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  316.824367] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  316.824893] [drm:intel_power_well_disable [i915]] disabling always-on
>[  316.825633] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  316.825664] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  316.825697] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  316.825935] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  316.825964] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  316.825995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.826025] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  316.826053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  316.826080] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  316.826105] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  316.826129] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.826135] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  316.826158] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.826162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  316.826187] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  316.826211] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  316.826234] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  316.826257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.826280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.826309] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  316.826332] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.826357] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  316.826381] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  316.826404] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  316.826427] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  316.826455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.826488] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  316.826515] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  316.826620] [drm:intel_power_well_enable [i915]] enabling always-on
>[  316.826642] [drm:intel_power_well_enable [i915]] enabling DC off
>[  316.827799] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  316.828096] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  316.828142] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  316.828215] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  316.828248] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  316.828293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  316.828333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  316.828367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  316.828399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  316.828431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  316.828462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  316.828493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  316.828524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  316.828553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  316.828581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  316.828612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  316.828640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  316.828668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  316.828701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  316.829523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  316.829562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  316.829598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  316.829641] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  316.829676] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  316.843002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.851723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.860506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.869230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.877956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.886678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.895501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.904329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.913083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.921811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.930527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.939203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.947792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.956331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.964940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.973430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.981906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.990374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  316.996509] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  317.010410] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  317.010428] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  317.010483] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  317.011322] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  317.012033] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  317.013821] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.013839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.013855] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.013871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.019783] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.019799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  317.024957] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.027390] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  317.027927] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  317.027968] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  317.027983] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  317.044831] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.044853] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.044888] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.045823] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.045840] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.045857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.045874] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.045889] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.045904] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.045919] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.045932] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.045946] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.045958] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.045971] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.045973] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.045985] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.045987] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.045999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.046011] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.046023] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.046035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.046046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.046060] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.046072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.046085] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.046096] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.046107] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.046119] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.046133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.046149] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.046163] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.061479] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  317.078644] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  317.078670] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  317.078830] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  317.078887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.078908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.078925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.078942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.078957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.078973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.078989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.079004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.079018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.079033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.079048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.079062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.079076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.079093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.079112] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.079129] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.079146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.079173] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  317.079189] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  317.079204] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  317.079227] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  317.079248] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.079266] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.079285] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.079304] [drm:intel_power_well_disable [i915]] disabling DC off
>[  317.079320] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  317.079334] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  317.080581] [drm:intel_power_well_disable [i915]] disabling always-on
>[  317.080935] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.080957] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.080980] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.081004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.081023] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.081044] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.081065] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.081084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.081103] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.081121] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.081138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.081142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.081158] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.081161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.081178] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.081194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.081210] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.081226] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.081241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.081261] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.081277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.081294] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.081310] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.081326] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.081341] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.081361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.081384] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.081403] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.081478] [drm:intel_power_well_enable [i915]] enabling always-on
>[  317.081493] [drm:intel_power_well_enable [i915]] enabling DC off
>[  317.082435] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  317.082771] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  317.082797] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  317.082851] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  317.082878] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  317.082906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.082928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.082948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.082967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.082986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.083004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.083023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.083039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.083056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.083073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.083090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.083106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.083123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.083141] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.083163] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.083183] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.083203] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.083226] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  317.083245] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  317.096044] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.104600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.113162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.121720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.130279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.138835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.147402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.155958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.164514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.173071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.181630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.190173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.198688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.207205] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.216136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.224607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.233080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.241551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.249376] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  317.263648] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  317.263715] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  317.263837] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  317.264907] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  317.266045] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  317.268282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.268344] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.268398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.268456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.274687] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.274783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  317.280253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.282901] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  317.284428] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  317.284539] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  317.284591] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  317.301452] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.301529] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.301645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.303278] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.303333] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.303391] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.303454] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.303504] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.303558] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.303611] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.303660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.303708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.304304] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.304351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.304361] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.304406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.304412] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.304459] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.304502] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.304546] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.304588] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.304629] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.304682] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.305309] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.305359] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.305404] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.305447] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.305488] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.305540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.305597] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.305648] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.318317] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  317.336002] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  317.336071] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  317.336131] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  317.336241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.336298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.336347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.336394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.336439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.336484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.336530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.336572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.336613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.336653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.336697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.337588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.337634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.337685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.337971] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.338025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.338076] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.338147] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  317.338194] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  317.338238] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  317.338300] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  317.338356] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.338411] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.338468] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.338523] [drm:intel_power_well_disable [i915]] disabling DC off
>[  317.338569] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  317.338609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  317.339976] [drm:intel_power_well_disable [i915]] disabling always-on
>[  317.340588] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.340641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.340699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.341048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.341097] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.341152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.341205] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.341256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.341304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.341350] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.341393] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.341403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.341446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.341452] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.341499] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.341543] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.341586] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.341629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.341671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.341722] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.342655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.342704] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.342943] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.342988] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.343034] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.343088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.343149] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.343199] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.343383] [drm:intel_power_well_enable [i915]] enabling always-on
>[  317.343422] [drm:intel_power_well_enable [i915]] enabling DC off
>[  317.344182] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  317.344504] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  317.344556] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  317.344650] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  317.344692] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  317.345062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.345119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.345169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.345218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.345262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.345308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.345354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.345400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.345442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.345485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.345529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.345572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.345612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.345661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.345715] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.346459] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.346511] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.346573] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  317.346623] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  317.359874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.368600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.377320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.386043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.394766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.403484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.412203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.420923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.429733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.438497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.447160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.455749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.464287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.472794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.481279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.489771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.498239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.506749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.512886] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  317.527050] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  317.527068] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  317.527114] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  317.528381] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  317.529871] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  317.531781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.531798] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.531813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.531830] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.537260] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.537277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  317.542413] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.544888] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  317.545367] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  317.545424] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  317.545438] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  317.562230] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.562252] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.562288] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.563178] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.563195] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.563212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.563230] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.563243] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.563258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.563273] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.563286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.563300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.563313] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.563325] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.563327] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.563339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.563341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.563354] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.563367] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.563379] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.563390] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.563402] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.563417] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.563429] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.563441] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.563453] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.563465] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.563476] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.563491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.563507] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.563520] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.578990] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  317.596232] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  317.596260] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  317.596285] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  317.596332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.596354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.596374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.596392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.596410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.596428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.596447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.596464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.596480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.596496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.596513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.596529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.596545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.596565] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.596586] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.596606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.596626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.596657] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  317.596676] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  317.597211] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  317.597239] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  317.597264] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.597287] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.597312] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.597334] [drm:intel_power_well_disable [i915]] disabling DC off
>[  317.597352] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  317.597368] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  317.598297] [drm:intel_power_well_disable [i915]] disabling always-on
>[  317.598557] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.598578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.598601] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.598625] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.598645] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.598665] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.598686] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.598920] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.598940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.598959] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.598976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.598980] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.598997] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.599000] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.599017] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.599034] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.599051] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.599067] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.599083] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.599104] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.599120] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.599138] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.599154] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.599170] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.599186] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.599206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.599229] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.599248] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.599323] [drm:intel_power_well_enable [i915]] enabling always-on
>[  317.599338] [drm:intel_power_well_enable [i915]] enabling DC off
>[  317.599614] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  317.599639] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  317.599655] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  317.599688] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  317.599748] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  317.599784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.599817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.599849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.599878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.599907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.599933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.599962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.599989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.600013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.600040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.600069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.600093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.600119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.600145] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.600178] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.600210] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.600240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.600275] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  317.600305] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  317.613164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.621724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.630278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.638832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.647401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.655953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.664534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.673089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.681644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.690312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.717763] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.726243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.734713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.743179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.751646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.760121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.766274] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  317.780681] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  317.780700] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  317.780744] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  317.781933] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  317.784185] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  317.785592] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  317.785607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  317.785621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  317.785635] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  317.790776] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  317.790791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  317.795930] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  317.798395] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  317.798940] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  317.798992] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  317.799007] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  317.815803] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.815825] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.815861] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.816814] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.816830] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.816846] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.816864] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.816877] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.816893] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.816907] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.816921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.816935] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.816948] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.816960] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.816963] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.816975] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.816977] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.816990] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.817002] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.817014] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.817025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.817037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.817052] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.817063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.817076] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.817087] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.817099] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.817110] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.817124] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.817140] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.817154] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.832567] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  317.849824] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  317.849849] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  317.849871] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  317.849913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.849933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.849950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.849966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.849983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.849998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.850014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.850029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.850043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.850057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.850072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.850086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.850100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.850117] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.850136] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.850153] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.850170] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.850198] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  317.850215] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  317.850230] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  317.850254] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  317.850274] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  317.850291] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  317.850311] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.850329] [drm:intel_power_well_disable [i915]] disabling DC off
>[  317.850346] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  317.850359] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  317.851611] [drm:intel_power_well_disable [i915]] disabling always-on
>[  317.851918] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  317.851937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  317.851958] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  317.851980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  317.851997] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  317.852015] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  317.852033] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  317.852050] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  317.852066] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  317.852081] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  317.852096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  317.852100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.852115] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  317.852117] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  317.852132] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  317.852147] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  317.852161] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  317.852175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  317.852189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  317.852207] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  317.852221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  317.852236] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  317.852250] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  317.852264] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  317.852278] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  317.852296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  317.852316] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  317.852333] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  317.852400] [drm:intel_power_well_enable [i915]] enabling always-on
>[  317.852413] [drm:intel_power_well_enable [i915]] enabling DC off
>[  317.853189] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  317.853472] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  317.853489] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  317.853525] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  317.853544] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  317.853567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  317.853586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  317.853603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  317.853619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  317.853635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  317.853651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  317.853666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  317.853681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  317.853918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  317.853934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  317.853951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  317.853966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  317.853982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  317.853998] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  317.854018] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  317.854036] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  317.854054] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  317.854075] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  317.854092] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  317.866866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.875419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.883950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.892497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.901023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.909548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.918117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.926643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.935173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.943722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.952245] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.960753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.969237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.977709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.986175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  317.994642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.003109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.011575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.019411] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  318.034493] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  318.034511] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  318.034544] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  318.035370] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  318.036850] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  318.038751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.038768] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.038783] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.038799] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.044253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.044269] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  318.049405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.051882] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  318.052360] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  318.052416] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  318.052431] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  318.069325] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.069347] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.069382] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.070277] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.070293] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.070310] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.070328] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.070343] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.070358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.070373] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.070386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.070400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.070412] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.070425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.070427] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.070439] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.070441] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.070454] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.070466] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.070478] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.070489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.070500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.070515] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.070527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.070539] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.070551] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.070562] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.070573] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.070588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.070603] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.070617] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.085925] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  318.102972] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  318.102995] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  318.103017] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  318.103057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.103076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.103093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.103109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.103125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.103140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.103156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.103171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.103185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.103200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.103215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.103229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.103243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.103260] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.103279] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.103296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.103313] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.103337] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  318.103352] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  318.103368] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  318.103391] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  318.103411] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.103428] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.103447] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.103466] [drm:intel_power_well_disable [i915]] disabling DC off
>[  318.103482] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  318.103495] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  318.104635] [drm:intel_power_well_disable [i915]] disabling always-on
>[  318.104904] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.104923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.104943] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.104964] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.104981] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.104999] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.105017] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.105034] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.105050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.105065] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.105080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.105083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.105097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.105100] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.105115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.105130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.105144] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.105159] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.105173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.105190] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.105205] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.105219] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.105234] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.105247] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.105261] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.105279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.105298] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.105315] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.105376] [drm:intel_power_well_enable [i915]] enabling always-on
>[  318.105390] [drm:intel_power_well_enable [i915]] enabling DC off
>[  318.105664] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  318.106223] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  318.106241] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  318.106274] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  318.106300] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  318.106327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.106349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.106368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.106387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.106405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.106422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.106440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.106457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.106473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.106489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.106505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.106521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.106537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.106555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.106576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.106596] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.106615] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.106638] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  318.106657] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  318.119538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.128086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.136645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.145296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.153850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.162428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.170982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.179535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.188090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.196644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.205303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.213820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.222319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.230800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.239268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.247735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.256202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.264669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.272663] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  318.287027] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  318.287047] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  318.287092] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  318.288221] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  318.290019] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  318.291897] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.291912] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.291926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.291954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.297103] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.297118] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  318.302269] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.304749] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  318.305215] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  318.305279] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  318.305293] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  318.322090] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.322110] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.322143] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.323283] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.323299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.323315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.323331] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.323344] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.323357] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.323371] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.323384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.323397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.323409] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.323420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.323423] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.323434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.323436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.323447] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.323458] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.323469] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.323480] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.323490] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.323503] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.323514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.323526] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.323536] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.323546] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.323557] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.323570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.323585] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.323597] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.338858] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  318.355996] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  318.356020] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  318.356040] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  318.356079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.356098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.356114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.356130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.356145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.356159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.356174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.356188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.356202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.356215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.356229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.356242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.356255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.356271] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.356288] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.356304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.356320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.356346] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  318.356362] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  318.356377] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  318.356399] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  318.356417] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.356434] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.356452] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.356469] [drm:intel_power_well_disable [i915]] disabling DC off
>[  318.356485] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  318.356498] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  318.357644] [drm:intel_power_well_disable [i915]] disabling always-on
>[  318.357899] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.357917] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.357936] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.357956] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.357972] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.357989] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.358005] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.358020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.358036] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.358050] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.358064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.358067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.358081] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.358083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.358097] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.358111] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.358138] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.358153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.358167] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.358186] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.358201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.358217] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.358231] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.358245] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.358260] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.358278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.358300] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.358317] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.358386] [drm:intel_power_well_enable [i915]] enabling always-on
>[  318.358400] [drm:intel_power_well_enable [i915]] enabling DC off
>[  318.358675] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  318.359473] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  318.359489] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  318.359520] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  318.359544] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  318.359569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.359589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.359606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.359623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.359640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.359656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.359672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.359687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.359940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.359957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.359975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.359990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.360006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.360024] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.360045] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.360063] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.360081] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.360103] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  318.360121] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  318.372916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.381449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.389986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.398522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.407060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.415594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.424127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.432661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.441319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.449855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.458388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.466913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.475501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.483987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.492461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.500929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.509399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.517867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.525689] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  318.540523] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  318.540538] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  318.540583] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  318.541423] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  318.542872] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  318.544803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.544846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.544875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.544891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.550289] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.550305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  318.555489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.557974] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  318.558439] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  318.558498] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  318.558511] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  318.575304] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.575323] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.575355] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.576246] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.576260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.576276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.576292] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.576305] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.576318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.576332] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.576344] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.576357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.576368] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.576380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.576382] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.576393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.576395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.576407] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.576418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.576428] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.576439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.576449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.576463] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.576474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.576485] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.576496] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.576506] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.576516] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.576530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.576544] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.576557] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.592005] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  318.609235] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  318.609259] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  318.609279] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  318.609318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.609337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.609353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.609369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.609384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.609399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.609414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.609428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.609442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.609455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.609469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.609482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.609495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.609510] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.609528] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.609544] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.609560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.609586] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  318.609602] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  318.609616] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  318.609639] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  318.609657] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.609674] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.609740] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.609768] [drm:intel_power_well_disable [i915]] disabling DC off
>[  318.609794] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  318.609816] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  318.610244] [drm:intel_power_well_disable [i915]] disabling always-on
>[  318.610587] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.610615] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.610645] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.610677] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.610729] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.610755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.610786] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.610816] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.610844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.610872] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.610898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.610906] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.610929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.610937] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.610962] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.610987] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.611014] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.611039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.611064] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.611094] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.611121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.611149] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.611174] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.611201] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.611225] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.611254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.611286] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.611313] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.611418] [drm:intel_power_well_enable [i915]] enabling always-on
>[  318.611441] [drm:intel_power_well_enable [i915]] enabling DC off
>[  318.611746] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  318.611783] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  318.611808] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  318.611851] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  318.611873] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  318.611906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.611935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.611962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.611989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.612015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.612040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.612066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.612091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.612114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.612136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.612161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.612184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.612207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.612234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.612263] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.612290] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.612318] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.612349] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  318.612376] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  318.625132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.633666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.642300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.650834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.659366] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.667899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.676432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.684968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.693502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.721168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.729665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.738214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.746682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.755161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.763627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.772095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.778231] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  318.792715] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  318.792734] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  318.792779] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  318.793847] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  318.796099] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  318.797504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  318.797520] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  318.797534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  318.797549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  318.802689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  318.802714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  318.807853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  318.810315] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  318.810862] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  318.810914] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  318.810929] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  318.827732] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.827754] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.827790] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.828648] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.828663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.828680] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.828841] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.828855] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.828871] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.828886] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.828900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.828914] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.828927] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.828940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.828942] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.828954] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.828956] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.828969] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.828981] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.828992] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.829004] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.829016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.829030] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.829042] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.829054] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.829065] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.829077] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.829088] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.829102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.829117] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.829131] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.844496] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  318.861615] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  318.861641] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  318.861663] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  318.861887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.861911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.861930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.861948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.861965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.861982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.861999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.862015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.862030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.862044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.862060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.862074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.862088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.862105] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.862125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.862142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.862173] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.862202] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  318.862220] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  318.862238] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  318.862264] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  318.862286] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  318.862306] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  318.862328] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.862349] [drm:intel_power_well_disable [i915]] disabling DC off
>[  318.862367] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  318.862383] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  318.863643] [drm:intel_power_well_disable [i915]] disabling always-on
>[  318.863967] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  318.863988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  318.864011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  318.864036] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  318.864055] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  318.864075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  318.864095] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  318.864114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  318.864132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  318.864149] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  318.864165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  318.864169] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.864185] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  318.864188] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  318.864205] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  318.864221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  318.864237] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  318.864253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  318.864268] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  318.864288] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  318.864304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  318.864320] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  318.864336] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  318.864351] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  318.864367] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  318.864386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  318.864409] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  318.864429] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  318.864504] [drm:intel_power_well_enable [i915]] enabling always-on
>[  318.864519] [drm:intel_power_well_enable [i915]] enabling DC off
>[  318.865344] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  318.865630] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  318.865647] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  318.865818] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  318.865845] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  318.865881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  318.865911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  318.865940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  318.865966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  318.865992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  318.866110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  318.866129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  318.866146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  318.866162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  318.866179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  318.866196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  318.866213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  318.866229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  318.866247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  318.866268] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  318.866288] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  318.866307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  318.866330] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  318.866350] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  318.879058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.887615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.896172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.904728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.913281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.921836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.930390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.938945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.947526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.956083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.964638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.973181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.981691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.990197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  318.998672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.007208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.015676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.024156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.031992] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  319.046645] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  319.046664] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  319.046714] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  319.047720] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  319.049974] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  319.051376] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.051392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.051406] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.051421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.056582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.056597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  319.061738] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.064213] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  319.064772] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  319.064850] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  319.064866] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  319.081663] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.081685] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.081825] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.082682] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.082792] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.082815] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.082840] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.082859] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.082881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.082902] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.082922] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.082941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.082960] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.082978] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.082982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.082999] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.083002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.083021] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.083038] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.083056] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.083073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.083091] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.083110] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.083128] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.083146] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.083164] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.083180] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.083197] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.083217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.083240] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.083258] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.098363] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  319.115665] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  319.115693] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  319.115886] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  319.115948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.115971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.115991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.116110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.116128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.116145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.116164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.116181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.116197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.116213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.116230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.116246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.116262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.116281] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.116302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.116322] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.116342] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.116371] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  319.116389] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  319.116407] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  319.116433] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  319.116455] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.116475] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.116497] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.116518] [drm:intel_power_well_disable [i915]] disabling DC off
>[  319.116536] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  319.116552] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  319.118021] [drm:intel_power_well_disable [i915]] disabling always-on
>[  319.118290] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.118312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.118335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.118359] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.118379] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.118400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.118420] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.118439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.118458] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.118476] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.118492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.118496] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.118513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.118515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.118532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.118549] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.118565] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.118581] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.118597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.118617] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.118633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.118650] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.118666] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.118681] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.119464] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.119486] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.119511] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.119531] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.119605] [drm:intel_power_well_enable [i915]] enabling always-on
>[  319.119620] [drm:intel_power_well_enable [i915]] enabling DC off
>[  319.120121] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  319.120408] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  319.120428] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  319.120467] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  319.120483] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  319.120509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.120531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.120551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.120570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.120588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.120605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.120624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.120641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.120658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.120674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.121133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.121159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.121185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.121212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.121243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.121274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.121303] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.121337] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  319.121363] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  319.134234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.142798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.151361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.159920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.168473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.177031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.185590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.194147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.202832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.211386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.219944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.228502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.237009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.245495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.253970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.262452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.270922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.279389] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.287213] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  319.301742] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  319.301762] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  319.301796] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  319.302912] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  319.305166] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  319.306574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.306589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.306603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.306618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.311759] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.311775] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  319.316915] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.319384] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  319.319946] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  319.319976] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  319.319991] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  319.336783] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.336805] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.336841] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.337858] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.337874] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.337891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.337913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.337927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.337942] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.337957] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.337971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.337984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.337996] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.338008] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.338012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.338023] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.338025] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.338038] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.338049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.338061] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.338073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.338084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.338099] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.338110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.338122] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.338134] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.338145] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.338156] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.338170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.338186] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.338200] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.353551] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  319.370851] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  319.370878] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  319.370901] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  319.370944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.370965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.370983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.371000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.371017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.371033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.371050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.371065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.371080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.371095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.371110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.371125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.371139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.371157] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.371176] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.371195] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.371212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.371241] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  319.371258] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  319.371275] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  319.371303] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  319.371324] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.371343] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.371364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.371384] [drm:intel_power_well_disable [i915]] disabling DC off
>[  319.371401] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  319.371415] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  319.372721] [drm:intel_power_well_disable [i915]] disabling always-on
>[  319.372959] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.372979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.373000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.373022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.373039] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.373058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.373076] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.373093] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.373110] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.373126] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.373141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.373145] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.373160] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.373163] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.373179] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.373194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.373208] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.373222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.373236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.373255] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.373270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.373285] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.373300] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.373314] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.373329] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.373347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.373368] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.373386] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.373455] [drm:intel_power_well_enable [i915]] enabling always-on
>[  319.373469] [drm:intel_power_well_enable [i915]] enabling DC off
>[  319.374403] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  319.374769] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  319.374793] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  319.374823] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  319.374838] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  319.374863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.374884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.374902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.374919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.374936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.374953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.374970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.374985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.375001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.375015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.375031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.375046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.375061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.375078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.375097] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.375130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.375150] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.375175] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  319.375195] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  319.387981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.396525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.405065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.413602] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.422140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.430679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.439241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.447778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.456313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.464851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.473386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.481898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.490405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.498882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.507351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.515819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.524288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.532758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.540580] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  319.555604] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  319.555621] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  319.555663] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  319.556508] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  319.557971] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  319.560219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.560235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.560249] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.560265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.565404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.565420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  319.570560] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.573054] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  319.573533] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  319.573571] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  319.573586] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  319.590378] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.590400] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.590435] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.591285] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.591301] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.591318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.591336] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.591350] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.591365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.591380] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.591394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.591408] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.591421] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.591433] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.591436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.591448] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.591450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.591462] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.591474] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.591486] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.591497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.591509] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.591523] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.591535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.591547] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.591559] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.591570] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.591582] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.591596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.591612] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.591626] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.607151] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  319.624433] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  319.624458] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  319.624480] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  319.624522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.624541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.624559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.624576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.624592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.624608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.624624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.624638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.624653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.624667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.624682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.625042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.625061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.625079] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.625099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.625117] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.625134] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.625161] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  319.625177] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  319.625192] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  319.625216] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  319.625235] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.625254] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.625274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.625293] [drm:intel_power_well_disable [i915]] disabling DC off
>[  319.625309] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  319.625323] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  319.626329] [drm:intel_power_well_disable [i915]] disabling always-on
>[  319.626555] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.626574] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.626594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.626615] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.626632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.626650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.626668] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.626685] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.626980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.626998] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.627014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.627018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.627033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.627036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.627052] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.627067] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.627082] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.627097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.627126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.627147] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.627163] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.627180] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.627197] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.627212] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.627228] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.627248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.627272] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.627291] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.627366] [drm:intel_power_well_enable [i915]] enabling always-on
>[  319.627382] [drm:intel_power_well_enable [i915]] enabling DC off
>[  319.627658] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  319.627683] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  319.628231] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  319.628275] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  319.628297] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  319.628322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.628344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.628364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.628383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.628402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.628419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.628438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.628454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.628471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.628487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.628504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.628520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.628536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.628554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.628575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.628594] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.628614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.628637] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  319.628656] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  319.641435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.649986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.658546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.667128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.675686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.684267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.692824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.721199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.729740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.738251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.746740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.755214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.763683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.772165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.780634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.789103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.795241] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  319.809094] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  319.809113] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  319.809162] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  319.810005] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  319.810733] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  319.812579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.812596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.812611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.812627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.818537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.818553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  319.823712] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.826173] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  319.826646] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  319.826815] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  319.826830] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  319.843532] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.843555] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.843591] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.844466] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.844482] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.844499] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.844517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.844531] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.844546] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.844561] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.844575] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.844588] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.844601] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.844613] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.844616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.844628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.844630] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.844643] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.844655] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.844666] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.844678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.844711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.844725] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.844739] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.844754] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.844766] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.844779] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.844792] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.844808] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.844825] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.844841] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.860234] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  319.877242] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  319.877265] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  319.877286] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  319.877326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.877345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.877362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.877378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.877394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.877410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.877426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.877441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.877455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.877470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.877485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.877499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.877513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.877529] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.877548] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.877565] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.877582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.877606] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  319.877622] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  319.877638] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  319.877661] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  319.877680] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  319.878431] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  319.878465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.878495] [drm:intel_power_well_disable [i915]] disabling DC off
>[  319.878521] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  319.878544] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  319.879000] [drm:intel_power_well_disable [i915]] disabling always-on
>[  319.879360] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  319.879392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  319.879426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  319.879461] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  319.879490] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  319.879522] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.879553] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  319.879582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  319.879611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  319.879638] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.879662] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.879667] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.879692] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.879725] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  319.879751] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  319.879777] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  319.879803] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.879830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.879853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.879883] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.879909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.879936] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  319.879959] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  319.879985] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  319.880010] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  319.880038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.880071] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  319.880101] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  319.880193] [drm:intel_power_well_enable [i915]] enabling always-on
>[  319.880218] [drm:intel_power_well_enable [i915]] enabling DC off
>[  319.880503] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  319.880541] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  319.880567] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  319.880634] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  319.880660] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  319.880696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  319.880746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  319.880775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  319.880803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  319.880830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  319.880857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  319.880884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  319.880910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  319.880936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  319.880961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  319.880988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  319.881013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  319.881038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  319.881066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  319.881097] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  319.881127] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  319.881157] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  319.881191] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  319.881220] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  319.894006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.902559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.911123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.919684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.928270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.936830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.945387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.953945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.962527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.971091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.979651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.988241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  319.996755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.005247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.013725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.022195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.030664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.039201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.047022] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  320.061559] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  320.061578] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  320.061608] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  320.062678] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  320.065304] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  320.066643] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.066659] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.066673] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.066848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.071987] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.072003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  320.077141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.079619] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  320.080166] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  320.080200] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  320.080215] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  320.097011] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.097033] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  320.097068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.097925] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.097941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.097957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.097975] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.097989] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.098003] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.098018] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  320.098032] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  320.098045] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.098057] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.098069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.098071] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.098083] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.098085] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.098097] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.098109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.098121] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.098133] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.098144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.098159] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.098170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.098183] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.098194] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  320.098205] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  320.098216] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  320.098230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.098246] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  320.098260] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  320.113731] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  320.130950] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  320.130975] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  320.130997] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  320.131039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.131059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.131076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.131093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.131124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.131142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.131160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.131177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.131193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.131209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.131226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.131242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.131259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.131278] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.131299] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.131319] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.131338] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.131369] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  320.131387] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  320.131405] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  320.131432] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  320.131454] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.131474] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  320.131496] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.131517] [drm:intel_power_well_disable [i915]] disabling DC off
>[  320.131535] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  320.131551] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  320.133201] [drm:intel_power_well_disable [i915]] disabling always-on
>[  320.133587] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.133956] [drm:intel_power_well_enable [i915]] enabling always-on
>[  320.133972] [drm:intel_power_well_enable [i915]] enabling DC off
>[  320.134261] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  320.134295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.134319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.134340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.134359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.134377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.134395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.134414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.134431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.134448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.134464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.134482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.134498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.134513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.134532] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.134551] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.134578] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.134598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.134617] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.134654] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  320.134679] [drm:intel_power_well_disable [i915]] disabling DC off
>[  320.134729] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  320.134752] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  320.135185] [drm:intel_power_well_disable [i915]] disabling always-on
>[  320.135487] [drm:drm_mode_addfb2] [FB:69]
>[  320.135533] [drm:drm_mode_addfb2] [FB:110]
>[  320.180413] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  320.180983] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  320.181340] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  320.181427] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  320.181440] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  320.181516] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.181541] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.181568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.181597] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.181620] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.181645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.181669] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  320.181691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.182258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.182281] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.182302] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.182306] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.182326] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.182329] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.182350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.182370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.182389] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.182408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.182426] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.182450] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.182469] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.182489] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  320.182507] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  320.182526] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  320.182550] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.182577] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  320.182599] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  320.183581] [drm:intel_power_well_enable [i915]] enabling always-on
>[  320.183601] [drm:intel_power_well_enable [i915]] enabling DC off
>[  320.183988] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  320.184394] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  320.184413] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  320.184460] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  320.184486] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  320.184519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.184545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.184567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.184589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.184610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.184631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.184652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.184673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.184994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.185016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.185037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.185057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.185077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.185098] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.185123] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.185146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.185169] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.185196] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  320.185218] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  320.198014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.206548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.215077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.223608] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.232134] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.240662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.249265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.257777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.266254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.274722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.283189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.291657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.300215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.308683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.317164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.325633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.334102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.342570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.351038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.352255] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  320.366875] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  320.366894] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  320.366936] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  320.367906] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  320.370159] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  320.371567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.371583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.371610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.371624] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.376765] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.376780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  320.381919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.384353] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  320.384953] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.401839] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.401860] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  320.401894] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.435419] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.435440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.435460] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.435481] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.435498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.435515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.435533] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  320.435549] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.435565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.435580] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.435595] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.435598] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.435612] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.435614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.435629] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.435643] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.435657] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.435670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.435683] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.435894] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.435912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.435931] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.435948] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  320.435964] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  320.435980] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  320.436001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.436023] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  320.436042] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  320.451999] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.469301] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  320.469337] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  320.469398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.469429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.469455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.469479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.469503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.469526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.469550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.469573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.469596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.469619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.469642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.469664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.469685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.470133] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.470165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.470194] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.470222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.470261] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  320.470286] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  320.470311] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  320.470345] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  320.470374] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.470404] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  320.470431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.470458] [drm:intel_power_well_disable [i915]] disabling DC off
>[  320.470483] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  320.470504] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  320.471542] [drm:intel_power_well_disable [i915]] disabling always-on
>[  320.471951] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.471979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.472011] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.472044] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.472070] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.472099] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.472126] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  320.472153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.472178] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.472203] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.472226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.472232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.472254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.472258] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.472282] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.472304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.472326] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.472348] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.472369] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.472397] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.472420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.472443] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.472465] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  320.472486] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  320.472508] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  320.472534] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.472565] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  320.472591] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  320.472690] [drm:intel_power_well_enable [i915]] enabling always-on
>[  320.473686] [drm:intel_power_well_enable [i915]] enabling DC off
>[  320.474101] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  320.474140] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  320.474168] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  320.474241] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  320.474274] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  320.474316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.474352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.474384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.474413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.474442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.474471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.474500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.474527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.474554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.474581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.474608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.474634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.474660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.474690] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.475297] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.475331] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.475365] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.475508] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  320.475541] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  320.488561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.497275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.506004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.514730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.523500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.532223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.540942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.549662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.558633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.567597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.576312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.585030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.593691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.602312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.610855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.619363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.627855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.636329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.640578] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  320.656009] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  320.656024] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  320.656076] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  320.656912] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  320.657626] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  320.660252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.660282] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.660311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.660328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.665714] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.665760] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  320.670898] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.673368] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  320.673942] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.690815] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.690836] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  320.690869] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.691870] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.691886] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.691902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.691932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.691945] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.691958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.691972] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  320.691985] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.691997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.692009] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.692021] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.692023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.692034] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.692036] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.692047] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.692058] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.692069] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.692079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.692090] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.692103] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.692114] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.692126] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.692137] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  320.692147] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  320.692157] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  320.692170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.692185] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  320.692198] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  320.707591] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.724880] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  320.724903] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  320.724944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.724963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.724979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.724995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.725010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.725025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.725040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.725054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.725068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.725081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.725095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.725108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.725121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.725137] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.725168] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.725186] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.725204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.725234] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  320.725251] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  320.725268] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  320.725292] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  320.725313] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.725331] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  320.725350] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.725369] [drm:intel_power_well_disable [i915]] disabling DC off
>[  320.725490] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  320.725505] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  320.726962] [drm:intel_power_well_disable [i915]] disabling always-on
>[  320.727181] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.727200] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.727221] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.727244] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.727262] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.727280] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.727299] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  320.727317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.727333] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.727349] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.727365] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.727369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.727384] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.727387] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.727402] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.727418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.727433] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.727448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.727462] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.727480] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.727495] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.727511] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.727525] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  320.727540] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  320.727554] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  320.727572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.727592] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  320.727610] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  320.727679] [drm:intel_power_well_enable [i915]] enabling always-on
>[  320.728459] [drm:intel_power_well_enable [i915]] enabling DC off
>[  320.728807] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  320.728830] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  320.728846] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  320.728878] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  320.728901] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  320.728925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.728946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.728963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.728980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.728996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.729012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.729029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.729044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.729059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.729074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.729089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.729104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.729118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.729135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.729154] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.729172] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.729191] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.729212] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  320.729229] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  320.741989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.750527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.759066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.767607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.776146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.784682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.793242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.801782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.810422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.818959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.827518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.836043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.844542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.853022] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.861494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.869963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.878431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.886900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.895368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  320.896497] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  320.910880] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  320.910900] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  320.910943] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  320.912187] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  320.914074] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  320.915970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  320.915985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  320.916000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  320.916015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  320.921176] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  320.921191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  320.926350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  320.928833] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  320.929310] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  320.946168] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.946190] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  320.946226] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.947096] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.947114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.947132] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.947150] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.947164] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.947179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.947194] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  320.947207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.947221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.947234] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.947247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.947249] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.947261] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.947263] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.947275] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.947288] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.947299] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.947311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.947322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.947337] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.947348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.947361] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.947372] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  320.947384] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  320.947395] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  320.947409] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.947425] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  320.947439] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  320.962941] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.980214] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  320.980244] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  320.980292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.980314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.980334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.980353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.980371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.980389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.980408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.980426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.980443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.980460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.980478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.980494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.980511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.980530] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.980552] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.980571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.980591] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.980622] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  320.980641] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  320.980658] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  320.980685] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  320.981442] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  320.981473] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  320.981506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.981539] [drm:intel_power_well_disable [i915]] disabling DC off
>[  320.981567] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  320.981590] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  320.982526] [drm:intel_power_well_disable [i915]] disabling always-on
>[  320.982907] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  320.982929] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  320.982952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  320.982977] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  320.982996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  320.983016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.983037] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  320.983056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  320.983074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  320.983091] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.983108] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.983112] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.983128] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.983131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  320.983148] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  320.983165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  320.983181] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.983197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.983212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.983233] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.983249] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.983266] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  320.983281] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  320.983297] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  320.983312] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  320.983332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.983355] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  320.983374] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  320.983448] [drm:intel_power_well_enable [i915]] enabling always-on
>[  320.983463] [drm:intel_power_well_enable [i915]] enabling DC off
>[  320.984635] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  320.985017] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  320.985045] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  320.985092] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  320.985116] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  320.985152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  320.985181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  320.985210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  320.985236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  320.985263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  320.985287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  320.985314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  320.985338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  320.985363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  320.985386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  320.985412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  320.985435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  320.985460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  320.985485] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  320.985517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  320.985547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  320.985576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  320.985610] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  320.985636] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  320.998443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.007024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.015628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.024227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.032860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.041457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.050055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.058751] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.067350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.075948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.084551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.093148] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.101730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.110251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.118752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.127233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.135709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.144178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.151803] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  321.167333] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  321.167393] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  321.167484] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  321.168520] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  321.170578] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  321.173249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.173304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.173354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.173406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.178860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.178916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  321.184311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.186874] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  321.188395] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.205425] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  321.205503] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  321.205620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.207191] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  321.207248] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  321.207305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  321.207368] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.207418] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.207472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.207525] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  321.207574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.207621] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.207665] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.207709] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.207930] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.207997] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.208009] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.208080] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  321.208148] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.208215] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.208272] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.208314] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.208367] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.208411] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.208456] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.208499] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  321.208541] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  321.208582] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  321.208634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.208692] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  321.208974] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  321.222250] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.239219] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  321.239287] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  321.239396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  321.239453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  321.239502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  321.239550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  321.239594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  321.239638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  321.239683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  321.239947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  321.240013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  321.240080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  321.240136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  321.240179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  321.240222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  321.240270] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  321.240326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.240376] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  321.240426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  321.240496] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  321.240542] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  321.240587] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  321.240649] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  321.240705] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  321.240982] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  321.241168] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.241251] [drm:intel_power_well_disable [i915]] disabling DC off
>[  321.241324] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  321.241385] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  321.242369] [drm:intel_power_well_disable [i915]] disabling always-on
>[  321.243242] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  321.243298] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  321.243356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  321.243418] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.243468] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.243521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.243573] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  321.243621] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.243669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.243714] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.243962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.243976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.244045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.244056] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.244126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  321.244177] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.244222] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.244264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.244307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.244359] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.244403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.244448] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.244491] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  321.244532] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  321.244574] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  321.244626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.244686] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  321.244969] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  321.245239] [drm:intel_power_well_enable [i915]] enabling always-on
>[  321.245301] [drm:intel_power_well_enable [i915]] enabling DC off
>[  321.245625] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  321.245685] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  321.245900] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  321.246001] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  321.246060] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  321.246127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  321.246181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  321.246233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  321.246281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  321.246328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  321.246373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  321.246420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  321.246464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  321.246507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  321.246550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  321.246594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  321.246635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  321.246676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  321.246946] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  321.247028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.247105] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  321.247179] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  321.247250] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  321.247299] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  321.260297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.269023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.277794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.286515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.295227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.303947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.318621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.327520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.336246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.344877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.353441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.361972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.370477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.378963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.387435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.395904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.404371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.412840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.413922] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  321.429060] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  321.429076] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  321.429125] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  321.429953] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  321.431053] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  321.433647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.433663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.433677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.433794] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.438939] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.438954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  321.444103] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.446564] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  321.447142] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.464023] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  321.464043] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  321.464077] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.464948] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  321.464963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  321.464978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  321.464994] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.465006] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.465020] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.465034] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  321.465046] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.465059] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.465070] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.465082] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.465084] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.465095] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.465097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.465108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  321.465120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.465130] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.465141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.465151] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.465165] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.465176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.465187] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.465198] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  321.465209] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  321.465219] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  321.465232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.465246] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  321.465259] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  321.480771] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.499672] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  321.499770] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  321.499811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  321.499831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  321.499848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  321.499866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  321.499881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  321.499897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  321.499913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  321.499928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  321.499942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  321.499956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  321.499971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  321.499986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  321.500000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  321.500017] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  321.500036] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.500054] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  321.500071] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  321.500095] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  321.500111] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  321.500126] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  321.500149] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  321.500169] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  321.500186] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  321.500204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.500222] [drm:intel_power_well_disable [i915]] disabling DC off
>[  321.500238] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  321.500252] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  321.500671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  321.501588] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  321.501606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  321.501626] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  321.501647] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.501664] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.501682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.501833] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  321.501851] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.501868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.501883] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.501898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.501901] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.501917] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.501919] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.501934] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  321.501949] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.501963] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.501978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.501992] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.502010] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.502025] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.502041] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.502055] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  321.502069] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  321.502084] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  321.502101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.502121] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  321.502138] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  321.502200] [drm:intel_power_well_enable [i915]] enabling always-on
>[  321.502214] [drm:intel_power_well_enable [i915]] enabling DC off
>[  321.502489] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  321.502510] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  321.502525] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  321.502568] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  321.502583] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  321.502604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  321.502622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  321.502638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  321.502654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  321.502669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  321.502683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  321.503254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  321.503270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  321.503285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  321.503300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  321.503316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  321.503330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  321.503344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  321.503361] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  321.503379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.503396] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  321.503413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  321.503434] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  321.503450] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  321.516306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.524834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.533362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.541890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.550414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.558940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.567463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.576036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.584561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.593107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.601633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.610147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.618639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.627114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.635582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.644049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.652515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.660982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.668802] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  321.683857] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  321.683872] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  321.683915] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  321.684744] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  321.685831] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  321.688420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.688436] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.688449] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.688464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.693601] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.693616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  321.718087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.720560] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  321.721171] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.738043] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  321.738065] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  321.738101] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.738997] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  321.739014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  321.739030] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  321.739047] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.739061] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.739076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.739090] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  321.739103] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.739117] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.739129] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.739140] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.739144] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.739155] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.739157] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.739169] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  321.739180] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.739191] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.739202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.739213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.739227] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.739237] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.739249] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.739260] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  321.739271] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  321.739281] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  321.739295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.739311] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  321.739324] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  321.754801] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  321.771909] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  321.771935] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  321.771979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  321.772000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  321.772017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  321.772035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  321.772051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  321.772067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  321.772083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  321.772099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  321.772113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  321.772128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  321.772144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  321.772159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  321.772173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  321.772190] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  321.772209] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.772227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  321.772245] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  321.772377] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  321.772394] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  321.772410] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  321.772435] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  321.772455] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  321.772474] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  321.772493] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.772512] [drm:intel_power_well_disable [i915]] disabling DC off
>[  321.772528] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  321.772543] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  321.773727] [drm:intel_power_well_disable [i915]] disabling always-on
>[  321.773960] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  321.773979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  321.774000] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  321.774022] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.774040] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.774059] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.774078] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  321.774095] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.774112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.774128] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.774144] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.774148] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.774163] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.774165] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.774181] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  321.774197] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.774212] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.774227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.774241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.774260] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.774274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.774290] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.774305] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  321.774319] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  321.774333] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  321.774352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.774373] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  321.774390] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  321.774459] [drm:intel_power_well_enable [i915]] enabling always-on
>[  321.774474] [drm:intel_power_well_enable [i915]] enabling DC off
>[  321.775290] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  321.775574] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  321.775591] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  321.775635] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  321.775651] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  321.775674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  321.775819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  321.775838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  321.775856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  321.775872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  321.775889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  321.775906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  321.775922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  321.775937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  321.775952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  321.775968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  321.775983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  321.775997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  321.776015] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  321.776035] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.776054] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  321.776072] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  321.776094] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  321.776112] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  321.788911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.797452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.805988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.814523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.823056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.831592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.840125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.848658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.857290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.865826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.874358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.882873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.891364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.899840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.908307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.916773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.925240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.933707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  321.941528] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  321.956536] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  321.956552] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  321.956598] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  321.957437] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  321.958883] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  321.961111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.961126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.961140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.961155] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.966293] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.966308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  321.971459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.973937] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  321.974415] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  321.991237] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  321.991260] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  321.991297] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  321.992178] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  321.992194] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  321.992210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  321.992227] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  321.992242] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  321.992257] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.992271] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  321.992285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  321.992299] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  321.992311] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.992323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.992325] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.992337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.992339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  321.992352] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  321.992364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  321.992376] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.992387] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.992398] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.992413] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.992424] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.992437] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  321.992448] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  321.992459] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  321.992470] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  321.992485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.992500] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  321.992514] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.008021] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.025117] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  322.025142] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  322.025185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.025205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.025223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.025239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.025255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.025270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.025287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.025301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.025316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.025330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.025345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.025359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.025374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.025391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.025409] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.025427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.025444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.025470] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  322.025487] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  322.025502] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  322.025526] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  322.025545] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  322.025564] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  322.025582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.025600] [drm:intel_power_well_disable [i915]] disabling DC off
>[  322.025616] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  322.025631] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  322.026782] [drm:intel_power_well_disable [i915]] disabling always-on
>[  322.027012] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  322.027031] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  322.027051] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  322.027073] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.027090] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.027108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.027125] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  322.027142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.027159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.027175] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  322.027190] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.027194] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.027209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.027211] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.027227] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  322.027242] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.027256] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  322.027271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.027285] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.027302] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  322.027317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.027332] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.027347] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  322.027362] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  322.027376] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  322.027393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.027414] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  322.027431] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.027495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  322.027509] [drm:intel_power_well_enable [i915]] enabling DC off
>[  322.028311] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  322.028594] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  322.028610] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  322.028650] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  322.028667] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  322.028689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.028822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.028840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.028857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.028873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.028888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.028905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.028919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.028934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.028948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.028964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.028978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.028992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.029009] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.029027] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.029045] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.029062] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.029083] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  322.029100] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  322.041894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.050424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.058952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.067499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.076033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.084559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.093086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.101612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.110139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.118662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.127308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.135816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.144301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.152772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.161237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.169733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.178198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.186664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.195188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.196317] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  322.210755] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  322.210774] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  322.210804] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  322.211912] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  322.214179] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  322.215585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.215600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.215615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.215629] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.220768] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.220783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  322.225920] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.228398] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  322.228950] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.245787] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  322.245810] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  322.245846] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.246689] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  322.246817] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  322.246833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  322.246851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.246866] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.246881] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.246896] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  322.246911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.246924] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.246937] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  322.246950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.246952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.246965] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.246967] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.246979] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  322.246991] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.247003] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  322.247015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.247026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.247041] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  322.247052] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.247065] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.247077] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  322.247088] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  322.247100] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  322.247114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.247130] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  322.247144] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.262561] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.279734] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  322.279758] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  322.279801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.279822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.279839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.279856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.279871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.279887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.279903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.279918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.279933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.279947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.279962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.279976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.279990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.280007] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.280025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.280043] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.280060] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.280088] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  322.280105] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  322.280120] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  322.280144] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  322.280164] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  322.280181] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  322.280199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.280217] [drm:intel_power_well_disable [i915]] disabling DC off
>[  322.280233] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  322.280247] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  322.280666] [drm:intel_power_well_disable [i915]] disabling always-on
>[  322.281376] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  322.281394] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  322.281414] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  322.281435] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.281453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.281471] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.281489] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  322.281505] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.281521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.281537] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  322.281552] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.281556] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.281571] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.281573] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.281589] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  322.281604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.281618] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  322.281632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.281646] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.281665] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  322.281679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.282078] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.282095] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  322.282110] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  322.282140] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  322.282161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.282185] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  322.282205] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.282280] [drm:intel_power_well_enable [i915]] enabling always-on
>[  322.282295] [drm:intel_power_well_enable [i915]] enabling DC off
>[  322.282572] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  322.282596] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  322.282616] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  322.282661] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  322.282678] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  322.282982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.283003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.283023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.283042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.283059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.283076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.283094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.283110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.283127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.283143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.283160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.283175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.283191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.283209] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.283230] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.283249] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.283268] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.283291] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  322.283310] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  322.296122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.304669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.313342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.321897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.330450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.339002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.347555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.356132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.364685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.373259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.381816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.390356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.398874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.407371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.415851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.424319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.432785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.441251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.449072] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  322.463678] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  322.463698] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  322.463744] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  322.464661] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  322.467288] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  322.468627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.468643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.468657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.468671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.473929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.473945] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  322.479096] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.481563] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  322.482136] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.499018] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  322.499039] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  322.499073] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.499958] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  322.499973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  322.499988] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  322.500004] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.500017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.500031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.500045] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  322.500058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.500070] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.500082] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  322.500093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.500096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.500107] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.500109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.500120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  322.500131] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.500141] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  322.500152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.500162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.500176] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  322.500187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.500198] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.500209] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  322.500220] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  322.500230] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  322.500243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.500258] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  322.500270] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.515817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.533095] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  322.533121] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  322.533167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.533189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.533208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.533226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.533244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.533260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.533278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.533294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.533310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.533325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.533342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.533357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.533372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.533390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.533411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.533429] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.533448] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.533479] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  322.533496] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  322.533513] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  322.533538] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  322.533560] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  322.533579] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  322.533599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.533619] [drm:intel_power_well_disable [i915]] disabling DC off
>[  322.533637] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  322.533652] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  322.534906] [drm:intel_power_well_disable [i915]] disabling always-on
>[  322.535170] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  322.535192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  322.535217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  322.535243] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.535264] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.535287] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.535309] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  322.535330] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.535350] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.535370] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  322.535389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.535394] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.535412] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.535415] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.535434] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  322.535453] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.535470] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  322.535488] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.535505] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.535527] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  322.535545] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.535564] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.535582] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  322.535599] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  322.535616] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  322.535638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.535663] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  322.535684] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.536376] [drm:intel_power_well_enable [i915]] enabling always-on
>[  322.536393] [drm:intel_power_well_enable [i915]] enabling DC off
>[  322.536672] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  322.536796] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  322.536817] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  322.536863] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  322.536888] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  322.536918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.536942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.536964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.536985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.537005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.537024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.537045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.537063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.537081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.537100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.537119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.537136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.537154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.537175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.537199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.537221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.537242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.537267] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  322.537288] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  322.550094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.558753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.567334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.575916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.584493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.593069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.601644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.610319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.618895] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.627470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.636050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.644608] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.653132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.661631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.670111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.678610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.687077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.714345] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.715458] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  322.720092] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  322.720109] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  322.720161] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  322.720992] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  322.722082] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  322.724672] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.724694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.724720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.724734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.729875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.729891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  322.735030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.737498] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  322.738101] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  322.754948] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  322.754968] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  322.755001] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.755898] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  322.755912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  322.755928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  322.755944] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.755957] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.755970] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.755984] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  322.755997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.756009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.756021] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  322.756032] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.756034] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.756045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.756047] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.756058] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  322.756069] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.756080] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  322.756091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.756101] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.756114] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  322.756125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.756136] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.756147] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  322.756157] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  322.756167] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  322.756180] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.756194] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  322.756207] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.771725] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  322.789046] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  322.789069] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  322.789110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.789129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.789146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.789162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.789177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.789191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.789206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.789220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.789234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.789247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.789261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.789274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.789287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.789302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.789319] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.789335] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.789351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.789378] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  322.789393] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  322.789408] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  322.789430] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  322.789448] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  322.789464] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  322.789481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.789498] [drm:intel_power_well_disable [i915]] disabling DC off
>[  322.789513] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  322.789526] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  322.789978] [drm:intel_power_well_disable [i915]] disabling always-on
>[  322.790204] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  322.790221] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  322.790240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  322.790260] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  322.790275] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  322.790292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  322.790309] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  322.790325] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  322.790341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  322.790356] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  322.790369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  322.790374] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.790387] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  322.790390] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  322.790404] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  322.790418] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  322.790432] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  322.790446] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  322.790459] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  322.790476] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  322.790490] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  322.790504] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  322.790518] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  322.790531] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  322.790545] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  322.790561] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  322.790580] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  322.790596] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  322.790649] [drm:intel_power_well_enable [i915]] enabling always-on
>[  322.790662] [drm:intel_power_well_enable [i915]] enabling DC off
>[  322.790948] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  322.790968] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  322.790982] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  322.791026] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  322.791039] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  322.791059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  322.791076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  322.791091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  322.791106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  322.791121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  322.791135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  322.791150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  322.791163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  322.791177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  322.791190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  322.791204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  322.791217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  322.791231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  322.791246] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  322.791263] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  322.791279] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  322.791294] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  322.791314] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  322.791329] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  322.804067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.812581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.821095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.829609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.838125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.846638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.855150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.863661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.872256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.880769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.889280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.897780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.906261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.914731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.923196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.931663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.940186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.948653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.957118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  322.958192] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  322.973052] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  322.973069] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  322.973114] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  322.973940] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  322.976228] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  322.977634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.977649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.977663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.977678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.982916] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.982931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  322.988069] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.990526] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  322.991158] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  323.008037] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.008059] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.008095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.008962] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.008978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.008994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.009012] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.009026] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.009041] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.009056] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  323.009070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  323.009083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.009097] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.009109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.009111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.009124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.009126] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.009139] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.009151] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.009163] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.009174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.009186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.009200] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.009212] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.009224] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.009236] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  323.009247] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  323.009258] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  323.009273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.009288] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  323.009302] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  323.024814] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  323.042034] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  323.042059] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  323.042102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.042122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.042140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.042157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.042173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.042189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.042205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.042220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.042235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.042250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.042265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.042279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.042294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.042311] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.042330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.042348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.042365] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.042394] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  323.042411] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  323.042426] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  323.042450] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  323.042470] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.042488] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.042506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.042525] [drm:intel_power_well_disable [i915]] disabling DC off
>[  323.042541] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  323.042555] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  323.043777] [drm:intel_power_well_disable [i915]] disabling always-on
>[  323.043987] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.044006] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.044026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.044048] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.044065] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.044083] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.044101] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  323.044118] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  323.044134] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.044150] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.044165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.044168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.044183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.044186] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.044201] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.044215] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.044230] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.044244] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.044257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.044275] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.044290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.044305] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.044319] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  323.044333] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  323.044347] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  323.044365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.044385] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  323.044402] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  323.044469] [drm:intel_power_well_enable [i915]] enabling always-on
>[  323.044483] [drm:intel_power_well_enable [i915]] enabling DC off
>[  323.045302] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  323.045584] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  323.045599] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  323.045637] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  323.045660] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  323.045682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.045839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.045858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.045875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.045892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.045908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.045925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.045940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.045955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.045970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.045986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.046001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.046015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.046032] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.046051] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.046068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.046086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.046107] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  323.046124] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  323.058893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.067426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.076033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.084561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.093111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.101639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.110167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.118695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.127243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.135771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.144299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.152808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.161294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.169766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.178233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.186701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.195168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.203636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.212103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.213181] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  323.227781] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  323.227800] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  323.227831] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  323.228801] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  323.231052] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  323.232486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.232528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.232541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.232554] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.237707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.237722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  323.242860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.245339] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  323.245883] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  323.262739] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.262761] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.262797] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.263655] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.263670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.263687] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.263857] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.263873] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.263888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.263904] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  323.263918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  323.263932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.263945] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.263957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.263960] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.263972] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.263974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.263986] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.263999] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.264010] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.264022] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.264033] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.264048] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.264060] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.264072] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.264083] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  323.264095] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  323.264106] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  323.264120] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.264136] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  323.264150] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  323.279490] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  323.296890] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  323.296914] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  323.296957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.296977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.296994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.297011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.297026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.297041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.297057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.297071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.297086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.297100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.297115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.297129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.297143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.297160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.297178] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.297195] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.297212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.297241] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  323.297257] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  323.297272] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  323.297296] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  323.297315] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.297333] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.297351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.297369] [drm:intel_power_well_disable [i915]] disabling DC off
>[  323.297386] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  323.297400] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  323.298615] [drm:intel_power_well_disable [i915]] disabling always-on
>[  323.298910] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.298931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.298952] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.298974] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.298991] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.299010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.299027] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  323.299045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  323.299061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.299077] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.299092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.299109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.299126] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.299128] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.299146] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.299162] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.299178] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.299194] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.299210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.299231] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.299248] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.299266] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.299282] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  323.299298] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  323.299313] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  323.299333] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.299356] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  323.299375] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  323.299450] [drm:intel_power_well_enable [i915]] enabling always-on
>[  323.299466] [drm:intel_power_well_enable [i915]] enabling DC off
>[  323.300342] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  323.300627] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  323.300644] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  323.300694] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  323.300865] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  323.300891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.300914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.300934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.300953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.300971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.300989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.301007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.301024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.301041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.301057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.301074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.301090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.301106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.301125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.301145] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.301165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.301184] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.301207] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  323.301226] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  323.314005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.322658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.331340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.339980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.348536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.357092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.365647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.374324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.382881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.391436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.399990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.408534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.417048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.425538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.434015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.442485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.450981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.459449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.467271] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  323.481559] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  323.481578] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  323.481628] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  323.482852] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  323.485103] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  323.486509] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.486524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.486539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.486553] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.491707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.491751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  323.496890] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.499355] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  323.499923] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  323.516810] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.516831] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.516865] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.517850] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.517865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.517881] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.517898] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.517924] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.517939] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.517953] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  323.517966] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  323.517979] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.517991] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.518003] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.518005] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.518016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.518018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.518030] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.518042] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.518053] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.518064] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.518074] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.518088] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.518099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.518110] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.518121] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  323.518131] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  323.518142] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  323.518155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.518169] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  323.518182] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  323.533588] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  323.550862] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  323.550885] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  323.550925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.550944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.550960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.550976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.550990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.551005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.551020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.551033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.551047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.551060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.551074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.551087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.551099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.551115] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.551147] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.551165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.551183] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.551212] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  323.551229] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  323.551245] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  323.551270] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  323.551291] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.551309] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.551328] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.551347] [drm:intel_power_well_disable [i915]] disabling DC off
>[  323.551364] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  323.551379] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  323.552606] [drm:intel_power_well_disable [i915]] disabling always-on
>[  323.552903] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.552923] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.552945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.552967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.552985] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.553004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.553023] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  323.553041] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  323.553058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.553075] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.553092] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.553096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.553111] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.553114] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.553130] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.553145] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.553160] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.553175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.553190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.553209] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.553225] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.553241] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.553256] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  323.553271] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  323.553285] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  323.553303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.553324] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  323.553342] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  323.553410] [drm:intel_power_well_enable [i915]] enabling always-on
>[  323.553424] [drm:intel_power_well_enable [i915]] enabling DC off
>[  323.554329] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  323.554613] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  323.554630] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  323.554672] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  323.554808] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  323.554832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.554853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.554871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.554889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.554906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.554923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.554940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.554955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.554971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.554986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.555002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.555017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.555031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.555049] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.555068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.555086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.555104] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.555125] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  323.555143] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  323.567901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.576437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.584974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.593516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.602053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.610589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.619123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.627658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.636300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.644838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.653371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.661894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.670392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.678871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.687339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.716027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.720477] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  323.735543] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  323.735560] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  323.735614] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  323.736444] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  323.737887] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  323.740141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  323.740156] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  323.740170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  323.740185] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  323.745326] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  323.745341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  323.750490] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  323.752967] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  323.753444] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  323.770309] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.770331] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.770367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.771236] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.771253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.771269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.771287] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.771301] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.771317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.771331] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  323.771345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  323.771359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.771371] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.771384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.771386] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.771398] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.771400] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.771413] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.771425] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.771437] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.771449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.771460] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.771474] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.771486] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.771498] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  323.771510] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  323.771521] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  323.771532] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  323.771546] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.771562] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  323.771576] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  323.787016] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  323.804216] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  323.804244] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  323.804292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.804314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.804334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.804353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.804371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.804389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.804408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.804425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.804441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.804457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.804474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.804490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.804506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.804525] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.804547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.804566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.804585] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.804617] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  323.804635] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  323.804653] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  323.804679] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  323.804862] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.804894] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.804924] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.804958] [drm:intel_power_well_disable [i915]] disabling DC off
>[  323.804987] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  323.805009] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  323.805430] [drm:intel_power_well_disable [i915]] disabling always-on
>[  323.805640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.805679] [drm:intel_power_well_enable [i915]] enabling always-on
>[  323.805720] [drm:intel_power_well_enable [i915]] enabling DC off
>[  323.806003] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  323.806049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.806081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.806111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.806138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.806164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.806182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.806200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.806216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.806232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.806248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.806265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.806280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.806296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.806314] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  323.806333] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.806354] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.806373] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.806392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.806418] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  323.806437] [drm:intel_power_well_disable [i915]] disabling DC off
>[  323.806455] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  323.806471] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  323.806917] [drm:intel_power_well_disable [i915]] disabling always-on
>[  323.807145] [drm:drm_mode_addfb2] [FB:69]
>[  323.807190] [drm:drm_mode_addfb2] [FB:110]
>[  323.848266] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  323.848827] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  323.849232] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  323.849847] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  323.849865] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  323.849976] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  323.850014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  323.850055] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  323.850099] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  323.850133] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  323.850169] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.850205] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  323.850239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  323.850272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  323.850303] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.850334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.850339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.850369] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.850373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  323.850404] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  323.850434] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  323.850463] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  323.850491] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.850519] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.850555] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.850584] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.850612] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  323.850640] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  323.850668] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  323.850703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.851594] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  323.851629] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  323.852470] [drm:intel_power_well_enable [i915]] enabling always-on
>[  323.852498] [drm:intel_power_well_enable [i915]] enabling DC off
>[  323.852911] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  323.853304] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  323.853333] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  323.853401] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  323.853437] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  323.853480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  323.853516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  323.853547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  323.853577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  323.853607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  323.853634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  323.853664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  323.853691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  323.854114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  323.854144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  323.854176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  323.854204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  323.854231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  323.854263] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  323.854299] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  323.854333] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  323.854366] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  323.854405] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  323.854436] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  323.867396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.875999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.884596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.893191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.901788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.910381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.918975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.927569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.936161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.944722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.953254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.961761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.970248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.978722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.987191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  323.995661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.004181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.012649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.020474] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  324.034809] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  324.034829] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  324.034873] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  324.036033] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  324.038298] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  324.039724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.039740] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.039754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.039768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.044908] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.044924] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  324.050062] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.052538] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  324.053097] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.069983] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.070006] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.070042] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.103590] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.103614] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.103637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.103661] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.103680] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.103805] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.103835] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.103863] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.103889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.103910] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.103928] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.103932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.103949] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.103952] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.103971] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.103988] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.104005] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.104021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.104037] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.104059] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.104075] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.104094] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.104111] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.104127] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.104143] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.104164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.104186] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.104204] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.120163] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.137520] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  324.137567] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  324.137648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.137688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.137901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.137953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.138005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.138052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.138091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.138123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.138156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.138187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.138220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.138249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.138280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.138314] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.138354] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.138390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.138426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.138481] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  324.138514] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  324.138546] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  324.138591] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  324.138632] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.138669] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.138872] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.138929] [drm:intel_power_well_disable [i915]] disabling DC off
>[  324.138980] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  324.139023] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  324.139477] [drm:intel_power_well_disable [i915]] disabling always-on
>[  324.140111] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.140149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.140189] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.140233] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.140267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.140304] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.140340] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.140373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.140406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.140437] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.140468] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.140474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.140505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.140510] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.140540] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.140568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.140597] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.140625] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.140652] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.140688] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.140889] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.141004] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.141052] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.141098] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.141143] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.141188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.141231] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.141267] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.141396] [drm:intel_power_well_enable [i915]] enabling always-on
>[  324.141425] [drm:intel_power_well_enable [i915]] enabling DC off
>[  324.141839] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  324.142254] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  324.142299] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  324.142372] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  324.142417] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  324.142480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.142523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.142558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.142590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.142621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.142650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.142682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.142860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.142908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.142954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.143002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.143033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.143064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.143098] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.143138] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.143175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.143212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.143254] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  324.143290] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  324.156550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.165281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.174007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.182731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.191507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.200231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.208953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.217673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.226414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.235142] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.243864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.252579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.261211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.269779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.278302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.286806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.295290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.303761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.309897] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  324.323816] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  324.323832] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  324.323894] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  324.324738] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  324.325434] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  324.327214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.327231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.327247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.327263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.333189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.333205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  324.338371] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.340801] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  324.341291] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.358134] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.358156] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.358192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.359065] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.359081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.359098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.359117] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.359132] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.359147] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.359162] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.359176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.359190] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.359202] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.359214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.359217] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.359230] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.359232] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.359244] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.359256] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.359268] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.359279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.359291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.359305] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.359317] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.359329] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.359341] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.359352] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.359363] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.359378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.359394] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.359408] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.374903] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.392276] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  324.392301] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  324.392346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.392367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.392385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.392402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.392419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.392435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.392452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.392468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.392483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.392497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.392513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.392528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.392542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.392559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.392579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.392597] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.392614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.392644] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  324.392661] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  324.392677] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  324.393276] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  324.393309] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.393339] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.393368] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.393397] [drm:intel_power_well_disable [i915]] disabling DC off
>[  324.393424] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  324.393447] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  324.394381] [drm:intel_power_well_disable [i915]] disabling always-on
>[  324.394620] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.394639] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.394661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.394683] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.394862] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.394892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.394921] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.394948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.394975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.395001] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.395026] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.395032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.395056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.395061] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.395085] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.395110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.395132] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.395155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.395179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.395205] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.395229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.395253] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.395277] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.395298] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.395321] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.395346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.395377] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.395405] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.395508] [drm:intel_power_well_enable [i915]] enabling always-on
>[  324.395530] [drm:intel_power_well_enable [i915]] enabling DC off
>[  324.396268] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  324.396552] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  324.396568] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  324.396614] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  324.396631] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  324.396655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.396675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.396893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.396921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.396947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.396973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.396999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.397024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.397048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.397072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.397097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.397121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.397160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.397189] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.397223] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.397255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.397389] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.397425] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  324.397456] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  324.410246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.418816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.427356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.435891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.444426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.452962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.461572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.470110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.478646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.487313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.495850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.504361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.512852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.521328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.529798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.538265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.546734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.555291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.563128] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  324.577798] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  324.577817] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  324.577851] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  324.578813] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  324.581081] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  324.582503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.582519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.582533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.582559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.587709] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.587724] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  324.592863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.595332] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  324.595904] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.612790] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.612813] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.612849] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.613825] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.613841] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.613858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.613876] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.613890] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.613905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.613920] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.613934] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.613947] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.613960] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.613972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.613974] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.613986] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.613988] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.614001] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.614012] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.614024] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.614036] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.614047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.614061] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.614073] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.614086] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.614097] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.614108] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.614119] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.614133] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.614149] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.614163] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.629557] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.646957] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  324.646982] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  324.647025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.647045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.647062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.647078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.647094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.647109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.647125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.647139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.647154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.647168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.647183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.647197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.647210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.647227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.647345] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.647362] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.647379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.647407] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  324.647424] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  324.647439] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  324.647463] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  324.647482] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.647500] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.647518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.647536] [drm:intel_power_well_disable [i915]] disabling DC off
>[  324.647552] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  324.647567] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  324.649027] [drm:intel_power_well_disable [i915]] disabling always-on
>[  324.649308] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.649329] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.649352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.649376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.649396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.649416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.649437] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.649456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.649475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.649492] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.649509] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.649514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.649530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.649533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.649550] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.649566] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.649582] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.649597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.649613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.649633] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.649649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.649666] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.649682] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.649742] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.649765] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.649793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.649825] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.649852] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.649948] [drm:intel_power_well_enable [i915]] enabling always-on
>[  324.649970] [drm:intel_power_well_enable [i915]] enabling DC off
>[  324.650255] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  324.650292] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  324.650318] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  324.650369] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  324.650395] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  324.650430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.650459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.650488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.650515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.650542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.650566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.650594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.650618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.650644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.650667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.650694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.650742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.650765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.650792] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.650824] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.650854] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.650883] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.650917] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  324.650944] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  324.663773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.672325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.680888] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.689446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.715992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.724556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.733118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.741676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.750262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.758811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.767325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.775817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.784295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.792767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.801236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.809708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.817532] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  324.831391] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  324.831409] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  324.831450] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  324.832288] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  324.833082] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  324.836029] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.836045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.836059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.836074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.841214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.841229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  324.846368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.848845] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  324.849336] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  324.866229] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.866253] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.866290] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.867180] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.867196] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.867213] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.867231] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.867246] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.867261] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.867275] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.867290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.867305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.867317] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.867330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.867333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.867345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.867347] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.867359] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.867371] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.867383] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.867395] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.867406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.867420] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.867432] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.867444] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.867456] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.867468] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.867479] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.867493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.867509] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.867523] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.882889] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  324.900009] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  324.900033] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  324.900077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.900098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.900115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.900132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.900148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.900164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.900181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.900195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.900210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.900224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.900239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.900253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.900267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.900284] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.900303] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.900320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.900338] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.900367] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  324.900383] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  324.900399] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  324.900423] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  324.900442] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  324.900460] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  324.900478] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.900496] [drm:intel_power_well_disable [i915]] disabling DC off
>[  324.900512] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  324.900526] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  324.901882] [drm:intel_power_well_disable [i915]] disabling always-on
>[  324.902138] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  324.902159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  324.902182] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  324.902207] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  324.902226] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  324.902246] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  324.902266] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  324.902285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  324.902304] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  324.902321] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  324.902338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  324.902342] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.902359] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  324.902362] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  324.902379] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  324.902395] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  324.902412] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  324.902427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  324.902443] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  324.902463] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  324.902479] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  324.902496] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  324.902512] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  324.902528] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  324.902544] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  324.902564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  324.902587] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  324.902606] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  324.902681] [drm:intel_power_well_enable [i915]] enabling always-on
>[  324.903388] [drm:intel_power_well_enable [i915]] enabling DC off
>[  324.903664] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  324.903805] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  324.903827] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  324.903865] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  324.903887] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  324.903913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  324.903936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  324.903956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  324.903975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  324.903992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  324.904010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  324.904028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  324.904045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  324.904062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  324.904078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  324.904096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  324.904112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  324.904128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  324.904146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  324.904167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  324.904187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  324.904206] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  324.904229] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  324.904249] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  324.917023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.925579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.934141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.942701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.951285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.959883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.968439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.976996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.985553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  324.994115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.002673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.011226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.019740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.028232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.036708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.045176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.053645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.062112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.069936] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  325.084585] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  325.084605] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  325.084657] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  325.085714] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  325.087968] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  325.089384] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.089400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.089414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.089428] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.094599] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.094628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  325.099802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.102233] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  325.102764] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.119677] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.119714] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.119750] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.120651] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.120667] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.120683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.120816] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.120831] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.120846] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.120862] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.120876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.120890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.120902] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.120915] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.120918] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.120930] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.120932] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.120945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.120957] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.120968] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.120980] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.120991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.121006] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.121018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.121030] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.121042] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.121054] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.121065] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.121079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.121095] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.121109] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.136335] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.153632] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  325.153659] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  325.153856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.153892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.153922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.153951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.153977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.153996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.154015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.154033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.154050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.154067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.154085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.154102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.154119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.154139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.154161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.154182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.154201] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.154234] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  325.154252] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  325.154270] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  325.154296] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  325.154318] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.154339] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.154359] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.154379] [drm:intel_power_well_disable [i915]] disabling DC off
>[  325.154397] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  325.154413] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  325.155591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  325.155909] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.155931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.155954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.155978] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.155998] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.156018] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.156038] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.156058] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.156076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.156093] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.156109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.156113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.156130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.156133] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.156150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.156166] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.156182] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.156198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.156214] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.156234] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.156250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.156267] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.156283] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.156298] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.156314] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.156334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.156357] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.156377] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.156453] [drm:intel_power_well_enable [i915]] enabling always-on
>[  325.156468] [drm:intel_power_well_enable [i915]] enabling DC off
>[  325.157315] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  325.157601] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  325.157618] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  325.157655] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  325.157679] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  325.157822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.157854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.157882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.157903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.157921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.157939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.157958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.157975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.157992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.158009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.158026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.158043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.158059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.158078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.158099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.158119] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.158139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.158163] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  325.158183] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  325.170968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.179530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.188161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.196764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.205363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.213959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.222559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.231157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.239757] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.248353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.256952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.265553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.274124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.282655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.291354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.299840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.308313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.316783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.324605] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  325.338578] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  325.338595] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  325.338629] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  325.339466] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  325.340213] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  325.342815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.342832] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.342848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.342864] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.348270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.348286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  325.353432] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.355914] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  325.356405] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.373248] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.373271] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.373307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.374286] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.374302] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.374319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.374337] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.374351] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.374366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.374380] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.374394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.374407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.374420] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.374432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.374434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.374446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.374448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.374460] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.374472] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.374484] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.374495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.374506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.374521] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.374533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.374545] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.374556] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.374567] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.374578] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.374592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.374608] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.374621] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.390029] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.407326] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  325.407354] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  325.407403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.407426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.407446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.407465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.407483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.407501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.407519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.407537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.407553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.407570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.407587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.407603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.407619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.407638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.407659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.407678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.408135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.408166] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  325.408184] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  325.408202] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  325.408228] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  325.408253] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.408276] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.408298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.408318] [drm:intel_power_well_disable [i915]] disabling DC off
>[  325.408336] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  325.408352] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  325.409326] [drm:intel_power_well_disable [i915]] disabling always-on
>[  325.409584] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.409606] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.409629] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.409653] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.409672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.409693] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.409914] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.409935] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.409954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.409972] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.409989] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.409994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.410011] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.410013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.410031] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.410048] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.410064] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.410080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.410096] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.410117] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.410133] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.410151] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.410167] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.410183] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.410199] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.410219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.410242] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.410262] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.410336] [drm:intel_power_well_enable [i915]] enabling always-on
>[  325.410351] [drm:intel_power_well_enable [i915]] enabling DC off
>[  325.410627] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  325.410651] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  325.410667] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  325.411342] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  325.411360] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  325.411386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.411408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.411428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.411446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.411464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.411482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.411500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.411517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.411533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.411550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.411567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.411583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.411599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.411618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.411639] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.411659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.411678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.412118] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  325.412139] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  325.424941] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.433532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.442093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.450657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.459353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.467911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.476470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.485029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.493587] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.502147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.510705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.519268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.527774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.536260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.544733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.553203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.561673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.570149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.578005] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  325.592477] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  325.592496] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  325.592539] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  325.593762] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  325.596022] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  325.597462] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.597478] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.597492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.597507] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.602645] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.602660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  325.607801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.610266] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  325.610805] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.627670] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.627751] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.627788] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.628648] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.628664] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.628680] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.628767] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.628787] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.628810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.628831] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.628852] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.628871] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.628891] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.628909] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.628913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.628931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.628935] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.628954] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.628971] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.628990] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.629007] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.629024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.629046] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.629063] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.629082] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.629100] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.629118] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.629134] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.629155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.629177] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.629198] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.644438] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.661751] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  325.661775] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  325.661818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.661839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.661856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.661872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.661888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.661903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.661919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.661933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.661948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.661961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.661976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.661990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.662004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.662020] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.662039] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.662056] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.662073] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.662103] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  325.662119] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  325.662134] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  325.662158] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  325.662178] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.662196] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.662214] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.662232] [drm:intel_power_well_disable [i915]] disabling DC off
>[  325.662248] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  325.662262] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  325.662681] [drm:intel_power_well_disable [i915]] disabling always-on
>[  325.663522] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.663546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.663575] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.663605] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.663627] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.663654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.663678] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.663778] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.663802] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.663826] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.663847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.663853] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.663874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.663878] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.663901] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.663922] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.663944] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.663965] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.663987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.664012] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.664035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.664056] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.664079] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.664100] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.664122] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.664147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.664177] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.664201] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.664298] [drm:intel_power_well_enable [i915]] enabling always-on
>[  325.664320] [drm:intel_power_well_enable [i915]] enabling DC off
>[  325.664602] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  325.664634] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  325.664657] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  325.664812] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  325.664835] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  325.664866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.664892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.664917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.664939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.664963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.664984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.665008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.665028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.665050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.665070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.665093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.665113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.665135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.665158] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.665185] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.665211] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.665235] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.665265] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  325.665289] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  325.678067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.686600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.714375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.722905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.731430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.739959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.748510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.757038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.765557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.774056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.782540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.791009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.799477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.807944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.816410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.824877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.831015] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  325.845658] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  325.845677] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  325.845728] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  325.846603] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  325.849200] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  325.850540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.850555] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.850569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.850584] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.855725] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.855741] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  325.860879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.863344] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  325.863886] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  325.880754] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.880777] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.880814] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.881851] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.881867] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.881884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.881903] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.881917] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.881932] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.881947] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.881961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.881975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.881987] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.881999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.882003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.882015] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.882017] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.882029] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.882041] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.882053] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.882065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.882076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.882091] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.882103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.882115] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.882127] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.882139] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.882150] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.882164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.882180] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.882194] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.897577] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  325.914873] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  325.914899] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  325.914942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.914963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.914980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.914997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.915013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.915029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.915046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.915063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.915080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.915097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.915112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.915127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.915141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.915158] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.915177] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.915194] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.915211] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.915240] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  325.915257] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  325.915273] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  325.915297] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  325.915317] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  325.915335] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  325.915352] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.915370] [drm:intel_power_well_disable [i915]] disabling DC off
>[  325.915387] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  325.915401] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  325.916329] [drm:intel_power_well_disable [i915]] disabling always-on
>[  325.916673] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  325.916742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  325.916773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  325.916804] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.916827] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  325.916854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.916879] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  325.916904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  325.916928] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  325.916951] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.916973] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.916979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.917000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.917004] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  325.917027] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  325.917048] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  325.917071] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  325.917091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.917113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.917138] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.917161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.917183] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  325.917206] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  325.917226] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  325.917248] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  325.917273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.917303] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  325.917326] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  325.917423] [drm:intel_power_well_enable [i915]] enabling always-on
>[  325.917445] [drm:intel_power_well_enable [i915]] enabling DC off
>[  325.917857] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  325.918239] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  325.918275] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  325.918318] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  325.918341] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  325.918376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  325.918406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  325.918433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  325.918458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  325.918484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  325.918507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  325.918534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  325.918557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  325.918583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  325.918606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  325.918632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  325.918654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  325.918679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  325.918821] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  325.918853] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  325.918884] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  325.918914] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  325.918949] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  325.918976] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  325.931752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.940299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.948858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.957442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.965998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.974551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.983133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  325.991684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.000266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.008819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.017365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.025882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.034380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.042860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.051328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.059795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.068261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.076728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.084549] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  326.099313] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  326.099332] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  326.099381] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  326.100260] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  326.102060] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  326.103935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.103964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.103990] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.104004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.109141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.109157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  326.114306] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.116714] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  326.117190] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.134076] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.134096] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.134130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.134993] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.135008] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.135023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.135039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.135052] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.135065] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.135079] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.135092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.135104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.135116] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.135127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.135129] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.135140] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.135142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.135153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.135164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.135175] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.135185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.135196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.135209] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.135220] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.135231] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.135242] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.135252] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.135262] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.135275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.135290] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.135302] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.150845] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.167992] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  326.168014] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  326.168054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.168073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.168088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.168103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.168118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.168132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.168147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.168160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.168173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.168185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.168199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.168211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.168224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.168238] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.168255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.168270] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.168286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.168313] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  326.168328] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  326.168342] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  326.168364] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  326.168381] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.168397] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.168413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.168429] [drm:intel_power_well_disable [i915]] disabling DC off
>[  326.168444] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  326.168456] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  326.169785] [drm:intel_power_well_disable [i915]] disabling always-on
>[  326.170016] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.170033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.170052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.170071] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.170087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.170104] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.170135] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.170152] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.170169] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.170185] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.170201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.170204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.170219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.170222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.170237] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.170252] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.170266] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.170281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.170295] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.170313] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.170328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.170343] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.170358] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.170372] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.170386] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.170403] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.170423] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.170440] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.170508] [drm:intel_power_well_enable [i915]] enabling always-on
>[  326.170521] [drm:intel_power_well_enable [i915]] enabling DC off
>[  326.171602] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  326.171964] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  326.171981] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  326.172020] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  326.172037] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  326.172060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.172080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.172097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.172114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.172130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.172146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.172162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.172176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.172191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.172205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.172221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.172235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.172249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.172265] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.172283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.172300] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.172317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.172337] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  326.172354] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  326.184984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.193509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.202037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.210564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.219115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.227643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.236170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.244695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.253245] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.261825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.270351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.278870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.287364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.295846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.304316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.312784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.321253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.329723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.338223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.339364] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  326.354032] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  326.354098] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  326.354199] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  326.356476] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  326.359086] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  326.361495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.361550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.361600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.361652] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.367145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.367199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  326.372628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.375274] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  326.376665] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.393736] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.393869] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.393985] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.395369] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.395425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.395484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.395547] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.395596] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.395648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.395700] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.395819] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.395872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.395922] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.395967] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.395978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.396023] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.396032] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.396078] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.396123] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.396168] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.396210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.396254] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.396307] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.396351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.396396] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.396441] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.396484] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.396526] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.396578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.396637] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.396689] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.410498] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.427443] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  326.427511] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  326.427624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.427681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.427819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.427874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.427928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.427973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.428022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.428068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.428111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.428156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.428201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.428244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.428287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.428338] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.428394] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.428446] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.428496] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.428578] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  326.428626] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  326.428671] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  326.428752] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  326.428810] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.428863] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.428918] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.428970] [drm:intel_power_well_disable [i915]] disabling DC off
>[  326.429018] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  326.429059] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  326.429513] [drm:intel_power_well_disable [i915]] disabling always-on
>[  326.430222] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.430273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.430329] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.430390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.430438] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.430490] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.430542] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.430589] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.430636] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.430681] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.430779] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.430789] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.430836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.430847] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.430892] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.430940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.430983] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.431025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.431070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.431123] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.431169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.431216] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.431263] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.431305] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.431348] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.431400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.431461] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.431511] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.431697] [drm:intel_power_well_enable [i915]] enabling always-on
>[  326.431780] [drm:intel_power_well_enable [i915]] enabling DC off
>[  326.432081] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  326.432140] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  326.432182] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  326.432255] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  326.432295] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  326.432357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.432410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.432460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.432508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.432555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.432599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.432647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.432690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.432773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.432817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.432867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.432911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.432957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.433005] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.433062] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.433115] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.433168] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.433228] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  326.433280] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  326.446497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.455229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.463951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.472675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.481440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.490163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.498885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.507606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.516349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.525088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.533763] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.542354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.550899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.559410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.567902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.576395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.584866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.593336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.601181] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  326.615081] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  326.615097] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  326.615142] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  326.615979] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  326.616695] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  326.618563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.618580] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.618614] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.618630] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.624527] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.624543] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  326.629713] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.632147] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  326.632634] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.649529] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.649549] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.649584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.650509] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.650524] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.650540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.650557] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.650571] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.650586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.650601] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.650614] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.650628] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.650641] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.650653] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.650655] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.650667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.650669] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.650682] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.650713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.650725] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.650737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.650751] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.650767] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.650781] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.650796] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.650809] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.650823] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.650835] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.650852] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.650869] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.650884] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.666243] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.683294] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  326.683321] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  326.683372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.683396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.683415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.683433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.683450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.683467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.683485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.683501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.683517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.683533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.683549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.683565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.683580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.683599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.683621] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.683640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.683659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.683814] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  326.683836] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  326.683855] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  326.683884] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  326.683907] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.683931] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.683952] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.683973] [drm:intel_power_well_disable [i915]] disabling DC off
>[  326.683992] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  326.684009] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  326.684431] [drm:intel_power_well_disable [i915]] disabling always-on
>[  326.684685] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.684778] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.684802] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.684828] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.684848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.684870] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.684891] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.684911] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.684930] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.684948] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.684966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.684972] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.684989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.684992] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.685010] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.685027] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.685044] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.685061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.685078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.685099] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.685116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.685134] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.685151] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.685168] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.685185] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.685205] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.685230] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.685250] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.685327] [drm:intel_power_well_enable [i915]] enabling always-on
>[  326.685343] [drm:intel_power_well_enable [i915]] enabling DC off
>[  326.685620] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  326.685644] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  326.685660] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  326.685812] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  326.685829] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  326.685855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.685876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.685896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.685915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.685932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.685949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.685967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.685985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.686002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.686018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.686036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.686052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.686068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.686087] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.686109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.686128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.686148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.686172] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  326.686191] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  326.715989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.724553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.733137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.741694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.750289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.758853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.767443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.776001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.784558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.793099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.801613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.810103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.818578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.827045] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.835512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.843980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.852448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.853525] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  326.867882] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  326.867902] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  326.867954] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  326.869117] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  326.870919] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  326.872828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.872843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.872857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.872871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.878010] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.878026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  326.883164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.885640] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  326.886192] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  326.903036] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.903059] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.903096] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.903973] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.903989] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.904007] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.904025] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.904038] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.904054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.904069] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.904083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.904097] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.904109] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.904122] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.904125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.904138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.904140] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.904153] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.904165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.904177] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.904188] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.904200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.904215] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.904227] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.904240] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.904251] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.904263] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.904274] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.904288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.904304] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.904318] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.919817] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  326.937046] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  326.937073] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  326.937121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.937144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.937163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.937182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.937200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.937217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.937235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.937252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.937269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.937285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.937302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.937317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.937333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.937352] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.937373] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.937393] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.937412] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.937444] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  326.937463] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  326.937480] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  326.937507] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  326.937529] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  326.937550] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  326.937569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.937589] [drm:intel_power_well_disable [i915]] disabling DC off
>[  326.937608] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  326.937623] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  326.938555] [drm:intel_power_well_disable [i915]] disabling always-on
>[  326.938985] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  326.939016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  326.939050] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  326.939085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  326.939114] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  326.939145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.939175] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  326.939204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  326.939233] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  326.939260] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.939287] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.939293] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.939318] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.939323] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  326.939350] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  326.939376] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  326.939403] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  326.939430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.939453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.939484] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.939511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.939539] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  326.939565] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  326.939590] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  326.939613] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  326.939643] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.939676] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  326.939854] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  326.939963] [drm:intel_power_well_enable [i915]] enabling always-on
>[  326.939987] [drm:intel_power_well_enable [i915]] enabling DC off
>[  326.940273] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  326.940309] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  326.940335] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  326.940384] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  326.940410] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  326.940446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  326.940478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  326.940506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  326.940534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  326.940562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  326.940588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  326.940615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  326.940641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  326.940666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  326.940691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  326.940836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  326.940862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  326.940888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  326.940917] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  326.940950] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  326.940981] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  326.941011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  326.941045] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  326.941075] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  326.953931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.962493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.971051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.979608] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.988165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  326.996745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.005298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.013851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.022428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.030983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.039542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.048079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.056586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.065088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.073561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.082029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.090496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.098965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.107432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.108507] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  327.122793] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  327.122841] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  327.122978] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  327.123948] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  327.125113] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  327.128447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.128490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.128527] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.128566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.133879] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.133920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  327.139226] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.141810] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  327.143027] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.160005] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  327.160065] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  327.160155] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.161383] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  327.161425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  327.161470] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  327.161516] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.161554] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.161594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.161634] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  327.161671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.161706] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.161938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  327.161992] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.162003] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  327.162051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.162060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  327.162114] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  327.162167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.162219] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  327.162270] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.162322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.162382] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.162434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.162487] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.162540] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  327.162583] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  327.162634] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  327.162692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.163065] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  327.163123] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  327.176874] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.194533] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  327.194601] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  327.194714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.195052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.195132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.195207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.195280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.195351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.195426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.195494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.195562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.195630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.195700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.195989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.196056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.196125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.196209] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.196289] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.196366] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.196476] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  327.196549] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  327.196620] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  327.196720] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  327.196929] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  327.197010] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  327.197093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.197173] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.197247] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.197311] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.197869] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.198945] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  327.198999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  327.199057] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  327.199119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.199168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.199221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.199273] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  327.199321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.199370] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.199415] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  327.199459] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.199469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  327.199512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.199519] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  327.199564] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  327.199607] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.199649] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  327.199691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.199824] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.199903] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.199974] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.200048] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.200110] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  327.200178] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  327.200239] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  327.200318] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.200404] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  327.200482] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  327.200810] [drm:intel_power_well_enable [i915]] enabling always-on
>[  327.200872] [drm:intel_power_well_enable [i915]] enabling DC off
>[  327.201194] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  327.201288] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  327.201355] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  327.201457] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  327.201525] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  327.201617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.201701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.201839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.201913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.201984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.202054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.202129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.202198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.202267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.202337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.202409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.202475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.202534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.202607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.202689] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.202807] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.202883] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.202970] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  327.203044] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  327.216341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.225073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.233797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.242516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.251238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.259956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.268674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.277544] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.286262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.294973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.303645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.312350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.320932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.329433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.337917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.346388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.354856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.363323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  327.369459] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  327.383534] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  327.383567] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  327.383600] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  327.385168] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  327.386954] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  327.388829] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.388844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.388859] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.388873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.394013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.394029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  327.399168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.401645] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  327.402198] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  327.419036] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  327.419059] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  327.419096] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.419963] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  327.419979] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  327.419996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  327.420014] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  327.420028] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  327.420043] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.420058] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  327.420072] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  327.420085] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  327.420098] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  327.420111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.420113] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  327.420125] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.420127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  327.420140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  327.420152] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  327.420163] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  327.420175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.420186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.420201] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.420213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.420225] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[  327.420237] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  327.420248] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  327.420259] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  327.420273] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.420289] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  327.420303] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  327.435811] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  327.453171] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  327.453196] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  327.453240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.453260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.453278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.453294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.453310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.453325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.453341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.453356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.453370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.453385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.453400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.453414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.453428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.453445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.453464] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.453481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.453498] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.453527] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  327.453543] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  327.453559] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  327.453582] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  327.453602] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  327.453621] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  327.453638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.453656] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.453672] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.453851] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.454279] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.454547] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.454599] [drm:intel_power_well_enable [i915]] enabling always-on
>[  327.454621] [drm:intel_power_well_enable [i915]] enabling DC off
>[  327.454934] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  327.454975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.455004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.455031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.455057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.455081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.455105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.455130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.455155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.455178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.455201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.455226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.455249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.455272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.455297] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  327.455323] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.455351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.455378] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.455404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.455440] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  327.455466] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.455492] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.455514] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.455971] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.456359] [drm:drm_mode_addfb2] [FB:69]
>[  327.456385] [drm:drm_mode_addfb2] [FB:110]
>[  327.601942] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  327.602278] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  327.602329] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  327.602886] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  327.602895] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  327.602959] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.602975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.602992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.603022] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.603035] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.603050] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.603064] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.603077] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.603090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.603102] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.603113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.603116] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.603127] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.603129] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.603141] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.603152] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.603164] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.603175] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.603186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.603200] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.603211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.603222] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  327.603233] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.603244] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.603263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  327.603279] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.603292] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.604330] [drm:intel_power_well_enable [i915]] enabling always-on
>[  327.604340] [drm:intel_power_well_enable [i915]] enabling DC off
>[  327.604612] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  327.604629] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  327.604640] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  327.604665] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  327.604683] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  327.604749] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.605171] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.605187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.605201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.605215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.605227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.605239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.605251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.605263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.605274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.605285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.605296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.605307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.605317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.605328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.605340] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.605354] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.605367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.605379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.605395] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  327.605408] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  327.608598] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.608614] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.608628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.608643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.609295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  327.609309] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  327.609322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.609997] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  327.610011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.610024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.610659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.610673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  327.611769] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.614038] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  327.614477] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  327.614505] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  327.614518] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  327.614536] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.614592] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  327.614606] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  327.631365] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.631385] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.631417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.664869] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.664889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.664909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.664929] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.664946] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.664963] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.664981] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.664997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.665012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.665027] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.665041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.665044] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.665058] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.665060] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.665075] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.665088] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.665102] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.665115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.665128] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.665145] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.665172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.665191] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.665206] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.665220] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.665235] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.665260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  327.665280] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.665298] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.681429] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  327.681463] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  327.681669] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  327.698895] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  327.698947] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  327.698993] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  327.699075] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.701445] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.701512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.701578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.701633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.701684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.702135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.702190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.702247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.702299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.702349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.702397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.702445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.702492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.702539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.702593] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.702654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.702710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.703095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.703172] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  327.703222] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  327.703270] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  327.703336] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  327.703396] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.703453] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.703513] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.703571] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.703620] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.703663] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.704880] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.706171] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.706232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.706294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.706360] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.706414] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.706469] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.706524] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.706576] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.706625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.706672] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.706718] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.707077] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.707129] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.707139] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.707189] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.707238] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.707287] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.707335] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.707382] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.707439] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.707488] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.707537] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.707585] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.707630] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.707674] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.708215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  327.708279] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.708333] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.708504] [drm:intel_power_well_enable [i915]] enabling always-on
>[  327.708546] [drm:intel_power_well_enable [i915]] enabling DC off
>[  327.709158] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  327.709487] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  327.709543] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  327.709644] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  327.709687] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  327.710105] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.710289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.710345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.710399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.710450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.710497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.710543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.710586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.710631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.710673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.711014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.711059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.711104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.711147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.711191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.711238] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.711295] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.711346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.711395] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.711457] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  327.711507] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  327.715178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.715237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.715289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.715341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.716717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  327.716818] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  327.716868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.717840] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  327.717890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.717940] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.718867] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.718919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  327.720194] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.722586] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  327.724043] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  327.724123] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  327.724174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  327.724241] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.724674] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  327.724952] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  327.741022] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.741204] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.741320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.742239] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.742299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.742363] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.742429] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.742482] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.742537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.742593] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.742645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.742696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.742918] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.742969] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.742983] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.743029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.743037] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.743088] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.743134] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.743183] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.743229] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.743277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.743333] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.743381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.743430] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.743477] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.743523] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.743566] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.743640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  327.743702] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.743944] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.757906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  327.757981] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  327.758421] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  327.774957] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  327.775028] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  327.775088] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  327.775195] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.777586] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.777653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.777716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.777960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.778020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.778075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.778130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.778183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.778233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.778281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.778329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.778376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.778423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.778468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.778523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.778582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.778638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.778692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.778940] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  327.778990] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  327.779039] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  327.779106] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  327.779166] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.779223] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.779284] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.779342] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.779391] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.779434] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.780394] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.781086] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.781144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.781205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.781270] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.781322] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.781377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.781433] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.781484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.781534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.781581] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.781627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.781636] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.781681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.781864] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.781916] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.781967] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.782015] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.782061] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.782107] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.782165] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.782213] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.782264] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.782311] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.782358] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.782403] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.782478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  327.782542] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.782596] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.782935] [drm:intel_power_well_enable [i915]] enabling always-on
>[  327.782980] [drm:intel_power_well_enable [i915]] enabling DC off
>[  327.783286] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  327.783352] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  327.783406] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  327.783502] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  327.783547] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  327.783611] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.783944] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.784000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.784054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.784104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.784151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.784195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.784238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.784283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.784324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.784366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.784407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.784449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.784489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.784529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.784576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.784629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.784678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.784951] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.785014] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  327.785065] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  327.788655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.788713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.788928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.788987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.789941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  327.789992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  327.790040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.790940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  327.790992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.791041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.791961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.792014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  327.793351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.795832] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  327.797278] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  327.797368] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  327.797419] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  327.797487] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.798061] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  327.798117] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  327.814269] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.814346] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.814460] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.815462] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.815521] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.815582] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.815648] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.815701] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.816116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.816178] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.816233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.816286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.816334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.816381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.816392] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.816438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.816446] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.816495] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.816542] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.816589] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.816634] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.816678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.817504] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.817557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.817609] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.817658] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.817706] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.818073] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.818148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  327.818210] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.818262] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.831014] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  327.831085] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  327.831475] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  327.847741] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  327.847843] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  327.847905] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  327.848010] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.848256] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.848311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.848366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.848416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.848462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.848507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.848551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.848596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.848639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.848681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.849467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.849514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.849558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.849601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.849650] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.849705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.850104] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.850156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.850225] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  327.850272] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  327.850317] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  327.850378] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  327.850543] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.850597] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.850656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.850709] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.851311] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.851353] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.852307] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.853039] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.853095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.853154] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.853215] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.853264] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.853317] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.853370] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.853418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.853466] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.853512] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.853557] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.853566] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.853608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.853615] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.853660] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.853702] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.854563] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.854609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.854651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.854705] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.855018] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.855066] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.855112] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.855155] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.855199] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.855269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  327.855328] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.855378] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.855540] [drm:intel_power_well_enable [i915]] enabling always-on
>[  327.855579] [drm:intel_power_well_enable [i915]] enabling DC off
>[  327.856413] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  327.856855] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  327.856909] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  327.857009] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  327.857051] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  327.857117] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.857284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.857340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.857395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.857445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.857492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.857538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.857584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.857630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.857674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.858489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.858535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.858579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.858622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.858664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.858712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.859113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.859167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.859216] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.859279] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  327.859329] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  327.862919] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.862978] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.863029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.863082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.864086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  327.864139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  327.864188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.865124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  327.865172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.865218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.866196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.866246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  327.867433] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.869821] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  327.871171] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  327.871248] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  327.871299] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  327.871365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.871848] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  327.871904] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  327.888150] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.888228] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.888342] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.889075] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.889132] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.889196] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.889262] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.889315] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.889371] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.889427] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.889480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.889533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.889582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.889629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.889637] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.889683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.889746] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.889796] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.889851] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.889898] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.889950] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.889997] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.890057] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.890105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.890156] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.890204] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.890252] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.890298] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.890371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  327.890434] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.890491] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.905022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  327.905096] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  327.905537] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  327.922010] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  327.922079] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  327.922140] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  327.922248] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.924506] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.924571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.924634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.924689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.925067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.925123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.925175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.925230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.925278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.925325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.925370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.925416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.925461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.925505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.925557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.925615] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.925669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.926243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.926323] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  327.926372] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  327.926422] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  327.926488] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  327.926549] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.926610] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.926670] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.927076] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.927127] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.927171] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.927626] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.928450] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.928507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.928678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.928949] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.929005] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.929063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.929119] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.929173] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.929224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.929273] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.929321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.929332] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.929377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.929386] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.929433] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.929480] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.929526] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.929572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.929617] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.929673] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.930337] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.930390] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.930439] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.930486] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.930532] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.930607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  327.930670] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.930724] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.931260] [drm:intel_power_well_enable [i915]] enabling always-on
>[  327.931303] [drm:intel_power_well_enable [i915]] enabling DC off
>[  327.931609] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  327.931673] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  327.931960] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  327.932051] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  327.932093] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  327.932158] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  327.932448] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  327.932504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  327.932557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  327.932607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  327.932651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  327.932695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  327.933198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  327.933248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  327.933292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  327.933336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  327.933378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  327.933421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  327.933463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  327.933505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  327.933555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  327.933609] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.933661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  327.933711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  327.934240] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  327.934291] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  327.937880] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.937939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.937989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.938042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.939104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  327.939157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  327.939205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.940295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  327.940346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  327.940395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  327.941449] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.941503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  327.942859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.945300] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  327.946810] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  327.946892] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  327.946944] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  327.947012] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  327.947448] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  327.947502] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  327.963826] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  327.963904] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  327.964019] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  327.964664] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  327.964722] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  327.965109] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  327.965177] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  327.965232] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  327.965292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  327.965349] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  327.965403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  327.965454] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  327.965504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  327.965552] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  327.965560] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.965608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  327.965616] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  327.965663] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  327.965711] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  327.966308] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  327.966357] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  327.966404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  327.966461] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  327.966509] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  327.966559] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  327.966605] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  327.966650] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  327.966694] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  327.967152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  327.967217] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  327.967271] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  327.980538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  327.980610] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  327.981077] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  327.997895] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  327.997964] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  327.998024] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  327.998134] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.000343] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.000410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.000471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.000526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.000574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.000621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.000667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.000715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.000960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.001012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.001062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.001113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.001166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.001215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.001270] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.001333] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.001390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.001444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.001523] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.001574] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.001624] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.001692] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.001927] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.001987] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.002050] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.002110] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.002159] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.002202] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.002657] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.003429] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.003484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.003546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.003610] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.003662] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.003718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.003921] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.003976] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.004030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.004080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.004127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.004139] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.004186] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.004195] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.004243] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.004291] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.004339] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.004384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.004430] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.004488] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.004535] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.004583] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.004631] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.004677] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.004903] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.004977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.005041] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.005096] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.005271] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.005315] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.005623] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.005687] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.005907] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.006008] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.006056] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.006120] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.006287] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.006342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.006395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.006445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.006490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.006535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.006579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.006624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.006963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.007005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.007051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.007093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.007136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.007177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.007227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.007283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.007335] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.007385] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.007447] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.007498] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.011121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.011180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.011229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.011282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.012176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.012226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.012271] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.013146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.013195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.013242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.014112] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.014162] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.015352] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.017780] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  328.019131] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.019215] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.019265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.019331] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.019852] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.019914] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.036118] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.036194] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.036308] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.037005] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.037066] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.037129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.037197] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.037250] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.037308] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.037364] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.037418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.037471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.037520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.037569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.037579] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.037626] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.037634] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.037682] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.037783] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.037834] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.037996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.038043] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.038106] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.038159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.038206] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.038254] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.038299] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.038344] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.038419] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.038481] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.038537] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.053000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.053074] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.053515] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.069749] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.069850] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.069912] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.070020] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.072458] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.072524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.072587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.072643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.072693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.073238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.073294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.073349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.073399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.073447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.073494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.073541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.073586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.073631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.073683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.074337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.074397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.074451] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.074525] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.074574] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.074622] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.074687] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.075300] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.075363] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.075428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.075485] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.075535] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.075578] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.076699] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.077345] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.077401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.077463] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.077529] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.077581] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.077636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.077692] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.078302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.078355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.078405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.078452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.078462] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.078509] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.078515] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.078564] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.078610] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.078655] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.078700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.079319] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.079381] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.079434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.079485] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.079532] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.079578] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.079624] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.079701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.080210] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.080264] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.080434] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.080477] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.081045] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.081372] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.081422] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.081520] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.081562] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.081627] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.084249] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.084315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.084379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.084435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.084487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.084534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.084582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.084631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.084676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.085350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.085399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.085446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.085492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.085537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.085588] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.085648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.085702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.086177] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.086248] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.086302] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.089936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.089995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.090046] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.090099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.091333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.091387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.091435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.092579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.092631] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.092678] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.093844] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.093898] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.095277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.097668] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  328.099145] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.099231] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.099281] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.099346] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.100078] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.100131] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.116240] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.116316] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.116432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.117387] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.117446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.117510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.117576] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.117630] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.117686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.118192] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.118247] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.118300] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.118349] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.118396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.118406] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.118451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.118458] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.118507] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.118552] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.118598] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.118643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.118686] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.119391] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.119444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.119501] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.119554] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.119602] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.119650] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.120092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.120156] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.120210] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.133004] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.133078] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.133521] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.149877] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.149948] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.150009] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.150118] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.150324] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.150379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.150436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.150486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.150532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.150576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.150620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.150665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.150708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.151515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.151563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.151610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.151654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.151697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.152075] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.152133] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.152185] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.152236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.152306] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.152352] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.152398] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.152461] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.152517] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.152572] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.152629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.152683] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.153309] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.153350] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.154305] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.155135] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.155192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.155251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.155314] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.155364] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.155417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.155469] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.155517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.155566] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.155611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.155654] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.155664] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.155707] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.156340] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.156391] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.156439] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.156485] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.156530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.156575] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.156629] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.156675] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.157158] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.157204] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.157248] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.157291] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.157363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.157422] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.157472] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.157637] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.157677] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.158470] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.158531] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.158576] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.158679] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.159011] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.159077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.161345] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.161410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.161471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.161526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.161576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.161624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.161671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.161915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.161964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.162011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.162056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.162102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.162147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.162192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.162244] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.162304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.162360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.162415] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.162480] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.162532] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.166167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.166229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.166282] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.166335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.167530] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.167584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.167633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.168665] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.168715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.168959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.169958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.170012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.171405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.173801] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  328.175256] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.175347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.175397] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.175464] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.176185] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.176245] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.192241] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.192317] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.192432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.192983] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.193042] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.193106] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.193173] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.193228] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.193284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.193341] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.193393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.193444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.193492] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.193539] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.193550] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.193595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.193604] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.193651] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.193698] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.193780] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.193824] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.193870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.193925] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.193972] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.194019] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.194065] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.194110] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.194152] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.194224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.194283] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.194336] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.209050] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.209123] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.209239] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.226718] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.226851] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.226912] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.227020] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.233534] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.233600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.233665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.233721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.233865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.233920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.233970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.234021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.234070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.234117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.234162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.234208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.234254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.234299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.234351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.234410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.234465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.234518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.234598] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.234649] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.234698] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.234799] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.234860] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.234913] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.234973] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.235031] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.235081] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.235125] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.235579] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.236253] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.236308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.236369] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.236434] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.236487] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.236543] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.236597] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.236650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.236699] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.236780] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.236826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.236837] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.236882] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.236890] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.236937] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.236983] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.237028] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.237072] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.237116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.237169] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.237216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.237262] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.237306] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.237349] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.237392] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.237464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.237525] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.237578] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.237781] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.237824] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.238129] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.238193] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.238239] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.238311] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.238355] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.238421] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.241174] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.241240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.241301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.241356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.241407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.241455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.241501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.241550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.241596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.241641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.241685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.241787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.241837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.241883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.241933] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.241995] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.242049] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.242106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.242170] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.242228] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.245916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.245976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.246027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.246080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.247063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.247116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.247167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.248099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.248147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.248192] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.249090] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.249140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.250364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.252792] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  328.254132] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.254212] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.254262] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.254329] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.254452] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.254503] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.271138] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.271215] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.271330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.272033] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.272092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.272156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.272228] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.272285] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.272340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.272397] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.272450] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.272499] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.272550] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.272598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.272611] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.272658] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.272666] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.272713] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.272795] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.272839] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.272887] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.272940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.272997] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.273051] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.273100] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.273152] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.273198] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.273249] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.273323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.273385] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.273446] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.287871] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.287943] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.288057] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.305507] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.305576] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.305639] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.305837] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.308098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.308163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.308226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.308280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.308329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.308377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.308423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.308471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.308515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.308558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.308601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.308645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.308688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.308794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.308859] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.308923] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.308979] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.309037] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.309121] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.309492] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.309544] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.309610] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.309671] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.309754] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.309816] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.309881] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.309937] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.310353] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.310851] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.311897] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.311954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.312016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.312082] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.312133] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.312188] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.312243] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.312297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.312348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.312396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.312441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.312451] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.312497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.312504] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.312552] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.312597] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.312641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.312686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.312778] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.312837] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.312887] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.312937] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.312987] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.313031] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.313079] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.313152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.313219] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.313274] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.313449] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.313493] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.313841] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.313909] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.313956] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.314024] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.314070] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.314133] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.316411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.316478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.316540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.316595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.316645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.316693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.316796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.316852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.316900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.316951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.316996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.317047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.317093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.317141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.317192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.317250] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.317304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.317357] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.317422] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.317476] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.321161] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.321218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.321267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.321319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.322367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.322417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.322464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.323495] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.323544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.323590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.324473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.324526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.325819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.328244] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  328.329683] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.329794] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.329845] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.329914] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.330038] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.330090] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.346712] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.346846] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.346961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.347510] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.347567] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.347628] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.347694] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.347920] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.347979] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.348038] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.348090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.348145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.348193] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.348245] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.348254] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.348303] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.348313] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.348359] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.348406] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.348452] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.348495] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.348541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.348595] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.348642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.348691] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.348923] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.348971] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.349014] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.349090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.349149] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.349203] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.363515] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.363589] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.363705] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.381361] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.381430] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.381490] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.381600] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.382199] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.382258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.382315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.382365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.382413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.382458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.382502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.382548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.382590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.382631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.382671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.382712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.383409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.383457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.383506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.383563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.383614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.383664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.384113] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.384160] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.384206] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.384268] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.384328] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.384383] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.384442] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.384495] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.384541] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.384580] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.385863] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.386490] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.386542] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.386599] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.386660] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.386708] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.387193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.387247] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.387296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.387343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.387389] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.387432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.387442] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.387484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.387491] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.387534] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.387576] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.387617] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.387657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.387696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.388441] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.388493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.388544] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.388591] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.388635] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.388678] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.389111] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.389172] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.389222] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.389385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.389424] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.390088] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.390412] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.390459] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.390559] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.390602] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.390679] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.391268] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.391326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.391381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.391432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.391479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.391525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.391570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.391616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.391659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.391701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.392282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.392330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.392376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.392421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.392470] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.392527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.392579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.392629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.392691] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.392890] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.396486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.396544] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.396594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.396646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.397795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.397845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.397892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.398952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.399003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.399050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.399945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.399996] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.401292] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.403799] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  328.405145] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.405232] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.405282] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.405350] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.405473] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.405524] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.422152] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.422229] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.422343] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.423007] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.423067] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.423131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.423200] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.423252] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.423311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.423368] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.423423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.423476] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.423527] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.423577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.423589] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.423636] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.423645] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.423694] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.423787] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.423841] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.423890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.423943] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.424004] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.424057] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.424110] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.424160] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.424208] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.424258] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.424335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.424400] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.424460] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.439015] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.439090] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.439211] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.456707] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.456838] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.456899] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.457008] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.457219] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.457276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.457330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.457379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.457424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.457468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.457511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.457555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.457596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.457638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.457679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.457793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.457839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.457892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.457943] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.458002] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.458062] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.458116] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.458200] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.458253] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.458303] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.458367] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.458424] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.458477] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.458536] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.458593] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.458639] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.458682] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.459176] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.459805] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.459858] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.459922] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.459991] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.460051] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.460105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.460161] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.460217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.460268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.460322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.460371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.460384] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.460433] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.460443] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.460488] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.460534] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.460579] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.460621] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.460665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.460719] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.460798] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.460849] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.460902] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.460950] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.460997] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.461070] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.461135] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.461189] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.461358] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.461399] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.461702] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.461806] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.461852] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.461925] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.461967] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.462030] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.464373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.464440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.464501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.464556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.464605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.464653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.464700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.464809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.464866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.464919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.464968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.465018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.465072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.465121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.465178] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.465240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.465300] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.465357] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.465430] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.465487] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.469043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.469096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.469145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.469196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.470177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.470236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.470288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.471199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.471250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.471300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.472201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.472255] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.473450] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.475881] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  328.477329] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.477411] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.477462] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.477531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.478141] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.478197] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.494309] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.494386] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.494501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.495318] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.495373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.495431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.495493] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.495542] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.495594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.495646] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.495694] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.495844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.495917] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.495979] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.495993] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.496057] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.496070] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.496139] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.496200] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.496267] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.496327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.496391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.496462] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.496527] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.496589] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.496656] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.496714] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.496819] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.496921] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.496999] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.497074] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.511102] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.511177] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.511629] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.527795] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.527863] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.527924] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.528032] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.530456] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.530523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.530588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.530644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.530694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.530996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.531066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.531137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.531211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.531275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.531344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.531405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.531472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.531530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.531603] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.531685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.531992] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.532066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.532171] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.532243] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.532316] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.532412] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.532495] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.532570] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.532655] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.532981] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.533053] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.533112] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.533589] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.534501] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.534557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.534617] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.534680] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.534933] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.535011] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.535093] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.535160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.535236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.535299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.535367] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.535382] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.535446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.535459] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.535527] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.535588] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.535654] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.535714] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.536027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.536101] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.536168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.536236] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.536302] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.536361] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.536426] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.536530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.536614] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.536683] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.537138] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.537195] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.537520] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.537611] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.537670] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.538016] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.538084] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.538177] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.538466] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.538542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.538622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.538691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.538977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.539027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.539072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.539122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.539165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.539209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.539250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.539293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.539334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.539375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.539424] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.539480] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.539531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.539581] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.539642] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.539692] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.543596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.543655] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.543707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.544009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.544951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.545004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.545054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.545990] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.546063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.546137] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.547219] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.547273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.548473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.550822] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  328.552300] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.552385] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.552435] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.552503] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.553143] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.553215] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.569400] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.569477] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.569592] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.570505] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.570561] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.570621] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.570683] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.570832] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.570915] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.570988] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.571059] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.571132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.571200] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.571262] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.571279] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.571339] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.571352] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.571414] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.571476] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.571537] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.571597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.571655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.571733] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.571844] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.571915] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.571978] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.572039] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.572096] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.572203] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.572292] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.572362] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.586025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.586096] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.586487] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.602741] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.602841] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.602902] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.603007] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.603255] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.603311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.603366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.603417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.603464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.603509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.603552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.603597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.603640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.603682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.604473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.604522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.604568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.604612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.604664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.605045] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.605101] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.605154] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.605224] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.605272] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.605319] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.605382] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.605442] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.605498] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.605557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.605611] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.605658] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.605699] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.607258] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.608014] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.608069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.608128] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.608190] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.608240] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.608292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.608345] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.608393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.608440] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.608486] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.608530] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.608538] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.608582] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.608589] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.608634] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.608676] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.609499] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.609548] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.609595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.609649] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.609696] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.610060] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.610108] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.610153] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.610198] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.610272] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.610332] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.610384] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.610546] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.610586] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.611376] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.611701] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.611960] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.612058] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.612101] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.612167] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.614556] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.614621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.614682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.615058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.615111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.615159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.615207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.615256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.615302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.615345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.615388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.615430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.615472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.615514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.615563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.615618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.615669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.616492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.616557] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.616608] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.620146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.620201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.620250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.620301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.621310] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.621361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.621409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.622296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.622346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.622393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.623294] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.623346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.624537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.627008] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  328.628549] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.628630] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.628680] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.629059] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.629458] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.629512] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.645526] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.645602] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.645716] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.646714] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.646988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.647048] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.647109] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.647158] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.647210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.647262] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.647420] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.647467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.647511] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.647554] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.647562] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.647604] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.647611] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.647654] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.647695] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.648612] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.648659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.648704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.649056] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.649107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.649156] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.649202] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.649245] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.649287] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.649360] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.649418] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.649467] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.662276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.662348] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.663163] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.679867] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.679937] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.680000] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.680109] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.680315] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.680371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.680428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.680478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.680524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.680567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.680611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.680655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.680698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.681661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.681711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.682010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.682059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.682104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.682156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.682213] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.682265] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.682315] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.682388] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.682434] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.682480] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.682543] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.682598] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.682651] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.682707] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.683525] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.683572] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.683613] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.684622] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.685425] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.685479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.685536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.685598] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.685646] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.685697] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.686214] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.686267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.686315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.686361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.686406] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.686415] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.686459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.686466] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.686511] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.686554] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.686596] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.686638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.686679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.687501] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.687552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.687602] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.687648] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.687692] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.688176] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.688250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.688311] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.688362] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.688527] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.688566] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.689313] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.689636] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.689681] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.690025] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.690067] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.690132] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.692399] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.692465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.692528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.692583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.692634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.692681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.693262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.693314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.693361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.693407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.693451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.693494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.693537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.693579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.693626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.693681] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.714390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.714428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.714472] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.714506] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.717951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.717983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.718011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.718039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.718794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.718828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.718854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.719569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.719595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.719620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.720401] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.720425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.721425] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.723747] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  328.724374] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.724415] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.724437] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.724468] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.724670] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.724693] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.741226] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.741255] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.741299] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.741543] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.741564] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.741586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.741610] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.741629] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.741650] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.741670] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.741688] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.741929] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.741948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.741965] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.741983] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.742000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.742003] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.742020] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.742037] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.742053] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.742068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.742084] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.742103] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.742119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.742135] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.742151] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.742166] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.742180] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.742207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.742230] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.742248] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.757988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.758021] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.758212] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.774784] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.774833] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.774876] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.774953] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.777159] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.777220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.777276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.777324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.777369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.777412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.777455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.777499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.777539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.777579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.777618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.777658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.777698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.778378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.778426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.778478] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.778526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.778572] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.778639] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.778681] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.779098] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.779156] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.779210] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.779262] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.779317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.779366] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.779407] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.779443] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.780569] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.781383] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.781440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.781498] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.781560] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.781610] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.781661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.781713] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.782184] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.782236] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.782283] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.782328] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.782338] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.782383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.782391] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.782436] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.782480] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.782523] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.782566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.782607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.782660] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.782704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.783418] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.783466] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.783509] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.783552] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.783624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.783684] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.784106] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.784276] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.784316] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.784617] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.784677] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.785061] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.785152] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.785194] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.785260] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.785511] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.785569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.785625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.785677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.786182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.786232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.786279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.786328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.786373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.786417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.786462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.786505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.786548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.786591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.786640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.786694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.787320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.787374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.787436] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.787487] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.791043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.791097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.791147] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.791200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.792388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.792439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.792487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.793634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.793685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.793967] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.794965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.795020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.796444] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.798839] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  328.800328] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.800415] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.800466] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.800532] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.801170] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.801247] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.817316] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.817393] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.817508] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.818378] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.818434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.818494] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.818557] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.818607] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.818660] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.818712] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.818867] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.818938] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.819009] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.819072] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.819088] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.819256] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.819268] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.819338] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.819400] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.819461] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.819527] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.819586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.819664] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.819729] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.819837] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.819900] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.819965] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.820024] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.820125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.820202] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.820276] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.834144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.834220] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.834666] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.851869] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.851939] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.852000] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.852109] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.852313] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.852370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.852425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.852477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.852524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.852569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.852613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.852659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.852702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.853090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.853155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.853224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.853286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.853352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.853419] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.853501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.853576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.853644] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.853956] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.854028] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.854100] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.854196] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.854283] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.854361] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.854449] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.854533] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.854604] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.854663] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.855642] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.856602] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.856657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.856716] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.856979] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.857048] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.857131] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.857205] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.857280] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.857347] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.857419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.857481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.857497] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.857559] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.857571] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.857638] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.857699] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.858001] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.858062] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.858127] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.858199] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.858265] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.858329] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.858394] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.858452] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.858515] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.858617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.858694] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.858996] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.859239] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.859294] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.859621] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.859715] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.859963] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.860057] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.860117] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.860208] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.860416] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.860490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.860569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.860638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.860707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.861014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.861077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.861149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.861210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.861276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.861336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.861400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.861459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.861523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.861588] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.861669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.861966] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.862043] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.862130] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.862199] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.865804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.865861] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.865911] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.865963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.867026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.867098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.867171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.868166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.868219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.868268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.869402] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.869457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.870949] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.873343] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  328.874878] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.874966] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.875016] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.875083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.875515] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.875567] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.891867] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.891943] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.892059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.892670] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.892726] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.893238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.893302] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.893352] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.893406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.893460] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.893510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.893559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.893605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.893650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.893659] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.893703] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.894390] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.894442] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.894489] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.894533] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.894577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.894620] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.894673] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.895196] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.895244] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.895290] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.895333] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.895375] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.895447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.895506] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.895557] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.908612] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.908682] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.909418] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  328.925826] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  328.925895] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  328.925957] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  328.926065] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.928451] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.928518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.928689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.929198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.929251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.929300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.929346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.929394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.929438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.929481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.929522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.929564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.929605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.929645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.929693] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.930437] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.930492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.930543] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.930614] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  328.930660] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  328.930706] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  328.931199] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  328.931261] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.931318] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.931378] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.931434] [drm:intel_power_well_disable [i915]] disabling DC off
>[  328.931480] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  328.931520] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  328.932701] [drm:intel_power_well_disable [i915]] disabling always-on
>[  328.933353] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.933406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.933463] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.933524] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.933573] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.933625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.933677] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.934272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.934323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.934368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.934414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.934423] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.934467] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.934474] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.934520] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.934563] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.934606] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.934648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.934689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.935460] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.935512] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.935563] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.935609] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.935654] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.935697] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.936271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  328.936333] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.936384] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.936551] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.936589] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.937283] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.937607] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  328.937659] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  328.938002] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  328.938045] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  328.938111] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  328.942487] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  328.942553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  328.942615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  328.942670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  328.942719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  328.943223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  328.943273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  328.943324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  328.943369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  328.943413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  328.943456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  328.943501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  328.943544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  328.943586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  328.943634] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  328.943690] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.944485] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  328.944540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  328.944603] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  328.944653] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  328.948593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.948652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.948702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.949113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.950250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  328.950304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  328.950353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.951540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  328.951592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  328.951640] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  328.952527] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.952579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  328.953963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.956357] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  328.957902] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.957981] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  328.958032] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  328.958100] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  328.958532] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  328.958584] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  328.974880] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  328.974957] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  328.975072] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  328.976198] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  328.976257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.976316] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  328.976379] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  328.976429] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  328.976482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.976534] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  328.976584] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  328.976632] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  328.976677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  328.977371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.977380] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.977428] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.977435] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  328.977484] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  328.977530] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  328.977575] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.977618] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.977660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.977713] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.978399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.978449] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  328.978496] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  328.978540] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  328.978583] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  328.978654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  328.978713] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  328.979263] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  328.991623] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  328.991696] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  328.992398] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.008715] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.008824] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.008884] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.008990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.011374] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.011439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.011500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.011555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.011605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.011653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.011700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.012337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.012385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.012429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.012473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.012516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.012558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.012599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.012646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.012701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.013314] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.013368] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.013435] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.013481] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.013526] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.013586] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.013646] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.013702] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.014270] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.014324] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.014371] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.014410] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.015459] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.016186] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.016242] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.016301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.016362] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.016411] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.016463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.016516] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.016565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.016613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.016658] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.016701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.017396] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.017446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.017453] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.017502] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.017547] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.017592] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.017637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.017680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.018278] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.018328] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.018378] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.018424] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.018468] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.018511] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.018581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.018639] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.018688] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.019471] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.019510] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.020062] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.020385] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.020440] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.020523] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.020564] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.020630] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.021146] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.021203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.021259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.021311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.021360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.021405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.021449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.021494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.021538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.021580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.021623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.021665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.021706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.022596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.022647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.022703] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.023046] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.023099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.023161] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.023212] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.026803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.026863] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.026914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.026966] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.028206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.028260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.028308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.029323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.029374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.029421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.030304] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.030357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.031548] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.033982] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  329.035380] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.035458] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.035508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.035575] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.036089] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.036144] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.052355] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.052432] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.052545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.053486] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.053649] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.053707] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.054050] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.054103] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.054158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.054214] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.054263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.054313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.054359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.054404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.054413] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.054457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.054465] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.054509] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.054553] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.054597] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.054639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.054681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.055458] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.055507] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.055556] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.055601] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.055643] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.055684] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.056135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.056197] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.056248] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.069077] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.069252] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.069642] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.085783] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.085851] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.085912] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.086018] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.088441] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.088506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.088567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.088621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.088671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.088720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.089183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.089236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.089283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.089328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.089372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.089416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.089460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.089503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.089553] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.089611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.089664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.089714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.090367] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.090416] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.090461] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.090522] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.090583] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.090640] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.090699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.091151] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.091199] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.091240] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.091694] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.092953] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.093008] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.093066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.093127] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.093176] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.093228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.093280] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.093328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.093375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.093419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.093462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.093470] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.093513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.093520] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.093565] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.093607] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.093649] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.093690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.094551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.094607] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.094655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.094702] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.095036] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.095083] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.095128] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.095200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.095259] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.095309] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.095468] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.095507] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.096253] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.096578] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.096627] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.096725] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.097061] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.097127] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.099331] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.099396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.099459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.099513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.099563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.099610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.099658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.099707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.100595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.100646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.100693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.101111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.101161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.101208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.101259] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.101317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.101370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.101420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.101480] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.101529] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.105160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.105218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.105269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.105322] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.106707] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.106796] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.106845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.107711] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.108222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.108275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.109355] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.109410] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.110614] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.113057] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  329.114638] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.114725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.115101] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.115174] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.115573] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.115627] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.131621] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.131846] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.131961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.132617] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.132676] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.133277] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.133345] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.133398] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.133453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.133508] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.133560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.133609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.133656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.133703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.134517] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.134583] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.134591] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.134642] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.134690] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.135284] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.135333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.135379] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.135435] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.135484] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.135533] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.135579] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.135624] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.135666] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.136530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.136593] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.136645] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.148368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.148440] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.149212] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.165807] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.165874] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.165934] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.166039] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.166285] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.166341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.166397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.166447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.166494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.166539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.166582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.166628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.166671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.166714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.167851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.167925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.167995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.168064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.168139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.168222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.168300] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.168375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.168475] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.168548] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.168620] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.168720] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.169531] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.169590] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.169651] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.169706] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.170138] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.170202] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.170683] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.171974] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.172029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.172088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.172150] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.172198] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.172251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.172303] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.172352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.172400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.172446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.172489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.172497] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.172539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.172546] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.172589] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.172631] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.172672] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.172712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.174025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.174109] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.174186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.174262] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.174336] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.174406] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.174474] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.174578] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.174662] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.174740] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.175641] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.175681] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.176248] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.176321] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.176376] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.176460] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.176502] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.176567] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.178863] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.178931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.178995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.179051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.179101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.179149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.179197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.179246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.179291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.179336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.179379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.179424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.179468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.179512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.179562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.179620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.179674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.181071] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.181166] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.181244] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.184832] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.184889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.184938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.184990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.186246] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.186301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.186351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.187616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.187669] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.187719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.189113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.189170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.190592] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.193036] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  329.194731] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.194856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.194907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.194974] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.195403] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.195457] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.211788] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.211864] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.211980] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.212668] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.212725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.213340] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.213410] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.213462] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.213519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.213575] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.213626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.213675] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.214410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.214460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.214470] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.214517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.214524] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.214572] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.214618] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.214664] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.214708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.215573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.215631] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.215681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.216102] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.216153] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.216201] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.216245] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.216319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.216380] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.216431] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.228498] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.228570] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.229336] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.245785] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.245853] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.245914] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.246019] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.248373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.248438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.248501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.248557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.248607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.248655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.248702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.249031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.249100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.249161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.249227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.249295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.249365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.249431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.249505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.249589] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.249668] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.249976] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.250078] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.250150] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.250222] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.250320] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.250408] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.250492] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.250580] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.250664] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.250938] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.251002] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.251481] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.252335] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.252390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.252448] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.252510] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.252559] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.252613] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.252666] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.252715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.253008] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.253083] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.253146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.253161] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.253228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.253241] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.253311] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.253380] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.253448] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.253515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.253582] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.253653] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.253722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.254025] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.254098] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.254160] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.254228] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.254332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.254415] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.254491] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.254918] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.254982] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.255321] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.255416] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.255481] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.255577] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.255642] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.255737] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.256448] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.256511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.256569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.256621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.257147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.257197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.257245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.257295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.257339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.257383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.257427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.257471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.257513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.257554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.257602] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.257657] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.257708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.258294] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.258386] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.258463] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.262162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.262222] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.262273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.262326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.263826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.263883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.263933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.265171] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.265225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.265274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.266453] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.266508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.268045] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.270487] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  329.272181] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.272264] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.272422] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.272489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.273140] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.273221] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.289162] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.289238] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.289354] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.290364] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.290421] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.290482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.290546] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.290595] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.290648] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.290700] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.291356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.291434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.291510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.291573] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.291588] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.291654] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.291667] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.291738] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.292327] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.292375] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.292420] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.292464] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.292518] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.292562] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.292608] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.292651] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.292692] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.293438] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.293546] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.293631] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.293708] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.305949] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.306020] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.306409] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.322655] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.322723] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.323098] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.323211] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.325692] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.325802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.325865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.325919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.325969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.326017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.326064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.326112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.326157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.326200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.326244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.326287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.326330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.326373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.326424] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.326482] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.326535] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.326587] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.326661] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.326710] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.328152] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.328252] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.328342] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.328424] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.328513] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.328598] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.328671] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.329140] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.329591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.330447] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.330501] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.330559] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.330621] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.330671] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.330722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.331301] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.331375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.331448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.331521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.331583] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.331597] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.331662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.331674] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.332259] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.332307] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.332353] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.332398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.332441] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.332495] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.332539] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.332584] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.332627] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.332669] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.332711] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.333595] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.333680] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.333988] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.334186] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.334226] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.334528] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.334588] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.334642] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.335287] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.335331] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.335397] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.335616] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.335673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.336178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.336256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.336329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.336399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.336468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.336539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.336606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.336672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.337122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.337168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.337212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.337255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.337303] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.337359] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.337409] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.337458] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.337518] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.337567] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.341157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.341215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.341267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.341320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.342642] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.342698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.343005] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.343951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.344003] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.344050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.345307] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.345361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.346566] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.349032] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  329.350712] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.350827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.350879] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.350946] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.351347] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.351401] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.367726] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.367846] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.367960] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.368602] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.368658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.368720] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.369201] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.369260] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.369318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.369377] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.369429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.369483] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.369532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.369580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.369588] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.369634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.369642] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.369690] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.370352] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.370402] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.370449] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.370494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.370551] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.370599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.370648] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.370694] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.371183] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.371236] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.371313] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.371377] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.371432] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.384468] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.384540] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.385174] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.401583] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.401650] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.401710] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.402102] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.404362] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.404427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.404488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.404542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.404591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.404639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.404687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.405189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.405239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.405287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.405334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.405380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.405426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.405470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.405522] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.405581] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.405635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.405688] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.406289] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.406341] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.406389] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.406456] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.406519] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.406578] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.406641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.406698] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.407166] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.407216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.407671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.408790] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.408848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.408909] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.408975] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.409026] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.409082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.409136] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.409186] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.409237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.409286] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.409332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.409340] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.409386] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.409393] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.409439] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.409484] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.409528] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.409572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.409616] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.409670] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.409715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.410871] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.410922] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.410970] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.411016] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.411090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.411153] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.411206] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.411369] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.411411] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.412204] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.412533] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.412582] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.412682] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.413097] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.413164] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.413384] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.413441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.413496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.413546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.413592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.413636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.413680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.414211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.414258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.414303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.414345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.414388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.414430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.414471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.414520] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.414574] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.414625] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.414674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.415258] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.415311] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.418898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.418956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.419007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.419060] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.420146] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.420197] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.420245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.421442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.421495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.421543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.422644] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.422699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.424131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.426519] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  329.428024] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.428102] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.428152] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.428219] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.428721] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.429124] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.444957] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.445029] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.445139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.445716] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.446066] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.446126] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.446191] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.446241] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.446295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.446348] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.446398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.446446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.446493] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.446538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.446547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.446590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.446597] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.446643] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.446685] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.447510] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.447556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.447599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.447652] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.447697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.448057] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.448103] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.448148] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.448190] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.448261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.448321] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.448372] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.461693] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.461806] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.462178] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.478458] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.478525] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.478584] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.478690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.479191] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.479248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.479305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.479357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.479405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.479450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.479494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.479539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.479581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.479623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.479665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.479706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.480375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.480421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.480472] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.480527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.480579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.480629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.480696] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.481141] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.481188] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.481251] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.481311] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.481368] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.481429] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.481483] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.481528] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.481569] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.482764] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.483357] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.483411] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.483468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.483530] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.483579] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.483631] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.483682] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.484195] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.484244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.484292] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.484335] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.484344] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.484389] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.484396] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.484439] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.484481] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.484524] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.484565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.484607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.484659] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.484704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.485515] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.485562] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.485607] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.485650] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.485721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.486098] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.486149] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.486307] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.486346] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.486648] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.486709] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.487103] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.487203] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.487249] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.487315] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.487479] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.487536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.487591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.487642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.487691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.488230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.488279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.488329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.488373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.488418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.488461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.488506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.488548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.488591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.488639] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.488694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.489275] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.489329] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.489391] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.489442] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.493063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.493121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.493172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.493224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.494436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.494490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.494540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.495779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.495831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.495880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.496831] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.496885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.498118] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.500505] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  329.501877] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.501968] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.502019] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.502084] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.502496] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.502548] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.518867] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.518943] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.519057] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.519708] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.519844] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.519917] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.519991] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.520050] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.520113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.520173] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.520231] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.520288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.520343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.520395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.520413] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.520461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.520476] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.520527] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.520577] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.520630] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.520676] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.520754] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.520808] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.520858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.520913] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.520963] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.521015] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.521063] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.521142] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.521205] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.521263] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.535622] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.535693] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.536150] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.552722] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.552824] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.552884] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.552990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.555368] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.555435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.555499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.555554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.555605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.555654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.555700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.555819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.555872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.555933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.555982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.556036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.556091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.556141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.556203] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.556268] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.556327] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.556389] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.556472] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.556525] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.556575] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.556643] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.556703] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.556818] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.556884] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.556947] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.556999] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.557045] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.557499] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.558152] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.558206] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.558269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.558335] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.558388] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.558443] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.558498] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.558548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.558597] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.558643] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.558687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.558751] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.558797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.558809] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.558871] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.558919] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.558968] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.559021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.559068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.559127] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.559181] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.559233] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.559283] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.559330] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.559381] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.559458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.559528] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.559585] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.559794] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.559840] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.560145] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.560210] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.560267] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.560366] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.560412] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.560479] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.560683] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.560778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.560836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.560893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.560943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.560994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.561042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.561097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.561147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.561198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.561243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.561287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.561334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.561378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.561434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.561494] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.561547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.561600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.561661] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.561717] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.565337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.565395] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.565446] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.565498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.566422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.566472] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.566520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.567419] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.567468] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.567514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.568406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.568455] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.569726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.572180] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  329.573540] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.573627] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.573676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.573796] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.574251] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.574305] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.590494] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.590570] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.590684] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.591395] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.591453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.591514] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.591578] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.591629] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.591684] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.591798] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.591856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.591921] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.591980] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.592032] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.592048] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.592097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.592109] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.592164] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.592214] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.592265] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.592315] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.592365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.592424] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.592476] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.592526] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.592575] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.592627] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.592675] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.592779] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.592841] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.592903] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.607275] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.607346] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.607835] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.624618] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.624685] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.624807] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.624926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.627390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.627456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.627518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.627572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.627622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.627670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.627717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.627827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.627883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.627937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.627986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.628035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.628085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.628136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.628193] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.628255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.628310] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.628369] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.628448] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.629047] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.629099] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.629164] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.629234] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.629294] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.629357] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.629414] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.629464] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.629507] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.630020] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.631057] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.631113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.631172] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.631236] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.631287] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.631341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.631396] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.631447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.631496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.631544] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.631590] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.631757] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.631806] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.631825] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.631876] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.631928] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.631977] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.632028] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.632081] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.632140] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.632193] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.632246] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.632300] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.632348] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.632398] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.632475] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.632541] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.632598] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.632799] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.632842] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.633152] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.633215] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.633270] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.633372] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.633417] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.633481] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.635866] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.635935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.635999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.636055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.636105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.636154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.636201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.636250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.636295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.636339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.636383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.636427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.636469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.636512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.636562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.636620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.636673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.636756] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.636825] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.636885] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.640483] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.640541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.640592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.640644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.641628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.641678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.641797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.642671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.642720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.642829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.643698] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.643809] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.645074] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.647458] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  329.648829] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.648907] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.648956] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.649025] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.649466] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.649517] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.665843] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.665921] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.666035] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.666797] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.666865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.666939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.667007] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.667067] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.667127] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.667187] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.667244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.667299] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.667353] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.667405] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.667422] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.667470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.667482] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.667533] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.667588] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.667638] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.667690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.667768] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.667825] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.667872] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.667925] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.667974] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.668020] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.668068] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.668144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.668205] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.668262] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.682556] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.682628] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.683088] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.714821] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.714888] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.714947] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.715052] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.715300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.715355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.715410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.715460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.715505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.715550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.715593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.715638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.715680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.715793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.715840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.715894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.715943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.715987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.716044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.716107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.716166] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.716220] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.716293] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.716347] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.716399] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.716462] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.716519] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.716571] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.716628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.716683] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.716766] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.716806] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.717258] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.717864] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.717915] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.717971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.718032] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.718079] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.718132] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.718182] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.718230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.718276] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.718321] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.718363] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.718372] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.718415] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.718422] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.718468] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.718510] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.718553] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.718594] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.718634] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.718685] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.718774] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.718831] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.718875] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.718921] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.718965] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.719034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.719095] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.719154] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.719321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.719360] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.719677] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.719778] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.719826] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.719929] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.719979] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.720044] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.722354] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.722399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.722442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.722480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.722514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.722547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.722580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.722613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.722645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.722676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.722749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.722780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.722821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.722858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.722898] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.722943] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.722986] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.723026] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.723076] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.723116] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.726553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.726593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.726627] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.726663] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.727494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.727528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.727561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.728339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.728373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.728405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.729181] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.729217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.730281] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.732572] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  329.733342] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.733383] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.733409] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.733446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.733662] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.733690] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.750201] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.750242] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.750304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.750646] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.750675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.750742] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.750783] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.750816] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.750848] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.750881] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.750913] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.750943] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.750972] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.750999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.751007] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.751033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.751040] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.751070] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.751096] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.751123] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.751150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.751176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.751209] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.751235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.751264] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.751291] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.751317] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.751342] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.751384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.751417] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.751446] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.766947] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.766993] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.767245] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.783719] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.783903] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.783965] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.784071] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.788567] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.788632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.788695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.789059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.789111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.789162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.789214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.789265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.789313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.789359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.789405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.789450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.789494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.789537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.789589] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.789646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.789702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.790440] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.790510] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.790560] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.790609] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.790674] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.791050] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.791112] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.791175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.791232] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.791281] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.791325] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.792381] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.793147] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.793204] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.793264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.793330] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.793381] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.793437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.793492] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.793544] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.793594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.793644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.793692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.794364] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.794418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.794426] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.794478] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.794530] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.794577] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.794626] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.794671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.795161] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.795215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.795267] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.795315] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.795361] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.795408] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.795482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.795545] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.795600] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.796267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.796311] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.796618] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.796682] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.797006] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.797103] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.797153] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.797222] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.799610] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.799676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.799992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.800051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.800103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.800154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.800205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.800255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.800302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.800350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.800396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.800442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.800485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.800529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.800580] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.800641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.800696] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.801470] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.801537] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.801591] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.805168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.805224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.805274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.805327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.806554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.806608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.806657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.807630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.807679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.807797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.808669] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.808720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.810059] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.812452] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  329.813957] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.814044] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.814095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.814161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.814560] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.814613] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.830944] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.831021] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.831135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.832102] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.832162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.832226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.832292] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.832346] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.832403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.832459] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.832512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.832562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.832611] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.832658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.832668] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.832713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.833396] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.833451] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.833503] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.833552] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.833598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.833645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.833701] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.834171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.834223] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.834272] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.834318] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.834365] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.834440] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.834502] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.834555] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.847696] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.847821] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.848212] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.864711] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.864817] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.864879] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.864985] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.867369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.867434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.867497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.867552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.867602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.867651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.867698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.868207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.868257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.868307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.868353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.868400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.868447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.868493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.868545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.868605] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.868660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.868714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.869332] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.869382] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.869430] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.869496] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.869558] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.869617] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.869682] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.870141] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.870191] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.870234] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.870690] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.871865] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.871924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.871986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.872052] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.872104] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.872159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.872214] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.872264] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.872315] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.872365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.872412] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.872420] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.872466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.872473] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.872520] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.872566] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.872609] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.872654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.872697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.873798] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.873854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.873907] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.873958] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.874007] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.874055] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.874130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.874193] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.874246] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.874411] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.874454] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.874857] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.875300] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.875352] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.875451] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.875503] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.875568] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.879953] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.880022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.880086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.880141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.880191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.880239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.880286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.880334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.880379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.880423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.880466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.880509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.880552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.880594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.880645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.880702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.880834] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.880899] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.880970] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.881027] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.884621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.884679] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.884946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.885005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.886011] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.886064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.886114] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.887498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.887554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.887604] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.888667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.888721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.890150] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.892595] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  329.894135] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.894217] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.894268] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.894336] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.895060] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.895119] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.911115] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.911192] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.911307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.912275] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.912335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.912398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.912463] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.912517] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.912573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.912629] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.912681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.913341] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.913393] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.913440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.913450] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.913496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.913504] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.913551] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.913597] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.913641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.913685] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.914307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.914365] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.914416] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.914466] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.914514] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.914560] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.914605] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.914679] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.915259] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.915314] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.927905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  329.927977] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  329.928368] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  329.944662] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  329.944730] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  329.945030] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  329.945139] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.945348] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.945403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.945458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.945508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.945555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.945600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.945644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.945691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.946277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.946323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.946367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.946411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.946453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.946495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.946543] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.946599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.946649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.946699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.947298] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  329.947345] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  329.947390] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  329.947451] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  329.947511] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.947566] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.947625] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.947677] [drm:intel_power_well_disable [i915]] disabling DC off
>[  329.948158] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  329.948199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  329.948650] [drm:intel_power_well_disable [i915]] disabling always-on
>[  329.949475] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.949530] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.949587] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.949649] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.949698] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.950101] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.950155] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.950204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.950253] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.950299] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.950342] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.950350] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.950393] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.950400] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.950444] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.950488] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.950530] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.950571] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.950611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.950662] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.950704] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.951588] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.951635] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.951679] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.951961] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.952034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  329.952094] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.952144] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  329.952305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  329.952344] [drm:intel_power_well_enable [i915]] enabling DC off
>[  329.952645] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  329.952706] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  329.953198] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  329.953296] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  329.953340] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  329.953404] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  329.955734] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  329.955861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  329.955925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  329.955981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  329.956030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  329.956078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  329.956124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  329.956173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  329.956217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  329.956262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  329.956306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  329.956349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  329.956393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  329.956436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  329.956488] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  329.956545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.956599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  329.956653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  329.956716] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  329.957794] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  329.961392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  329.961449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  329.961501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  329.961555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  329.962806] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  329.962859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  329.962907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.964083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  329.964135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  329.964183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  329.965335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  329.965389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  329.966582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  329.969024] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  329.970533] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  329.970615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  329.970666] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  329.971023] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  329.971455] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  329.971511] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  329.987516] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  329.987593] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  329.987708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  329.988627] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  329.988684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  329.988982] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  329.989049] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  329.989102] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  329.989162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  329.989218] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  329.989272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  329.989324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  329.989374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  329.989423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  329.989434] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.989481] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  329.989489] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  329.989538] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  329.989585] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  329.989630] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  329.989675] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  329.990530] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  329.990587] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  329.990637] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  329.990688] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  329.991177] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  329.991227] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  329.991274] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  329.991349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  329.991411] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  329.991464] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.004261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.004332] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.004722] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.021619] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.021685] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.021987] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.022096] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.022408] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.022465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.022520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.022570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.022617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.022662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.022708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.023282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.023330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.023374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.023417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.023460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.023502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.023543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.023591] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.023646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.023697] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.024255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.024322] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.024369] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.024415] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.024476] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.024536] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.024591] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.024648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.024701] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.025216] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.025257] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.025887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.026901] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.026956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.027016] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.027077] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.027127] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.027181] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.027234] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.027284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.027331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.027378] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.027421] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.027430] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.027472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.027479] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.027524] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.027565] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.027606] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.027646] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.027687] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.028714] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.028909] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.028958] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.029005] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.029049] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.029092] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.029162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.029220] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.029269] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.029429] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.029469] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.030315] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.030638] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.030685] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.030997] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.031040] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.031104] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.031308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.031364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.031418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.031470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.031518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.031563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.031607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.031652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.031694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.032373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.032421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.032466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.032511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.032554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.032604] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.032659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.032711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.033246] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.033308] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.033360] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.036946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.037005] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.037058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.037111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.038116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.038168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.038218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.039131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.039180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.039226] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.040102] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.040152] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.041338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.043724] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  330.045093] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.045169] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.045218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.045285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.045692] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.045846] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.062084] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.062161] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.062275] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.063169] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.063227] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.063289] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.063355] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.063406] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.063459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.063515] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.063565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.063615] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.063662] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.063708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.064196] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.064247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.064254] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.064307] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.064354] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.064402] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.064448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.064493] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.064550] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.064598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.064647] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.064694] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.065246] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.065296] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.065374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.065437] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.065493] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.078867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.078938] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.079328] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.095815] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.095882] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.095944] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.096051] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.098357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.098422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.098483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.098537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.098587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.098635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.098682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.099217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.099268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.099314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.099362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.099408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.099454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.099499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.099552] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.099611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.099667] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.099722] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.100336] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.100493] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.100543] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.100607] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.100670] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.101045] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.101112] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.101173] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.101224] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.101268] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.102282] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.103030] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.103087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.103149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.103215] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.103267] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.103322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.103378] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.103429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.103480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.103529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.103576] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.103585] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.103631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.103638] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.103685] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.104566] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.104617] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.104666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.104713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.105057] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.105108] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.105162] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.105209] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.105256] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.105303] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.105377] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.105440] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.105494] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.105659] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.105701] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.106617] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.106683] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.106921] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.107020] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.107062] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.107130] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.107342] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.107399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.107456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.107507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.107555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.107600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.107645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.107691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.108348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.108394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.108439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.108483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.108525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.108566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.108614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.108669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.109204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.109257] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.109320] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.109370] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.113032] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.113091] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.113143] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.113196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.114454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.114508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.114557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.115633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.115684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.115933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.116959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.117011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.118407] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.120863] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  330.122361] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.122444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.122495] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.122563] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.123278] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.123333] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.139340] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.139418] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.139532] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.140453] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.140512] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.140573] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.140640] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.140693] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.141109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.141166] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.141222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.141272] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.141322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.141369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.141380] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.141425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.141432] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.141481] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.141528] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.141575] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.141620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.141665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.141721] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.142593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.142646] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.142696] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.142976] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.143025] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.143104] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.143167] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.143222] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.156084] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.156155] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.156545] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.172739] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.172839] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.172901] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.173006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.173292] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.173348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.173405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.173455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.173502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.173545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.173589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.173635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.173679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.174442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.174490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.174536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.174581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.174625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.174674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.175079] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.175133] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.175183] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.175250] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.175296] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.175341] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.175403] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.175460] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.175513] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.175571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.175624] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.175670] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.175710] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.176874] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.178008] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.178062] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.178120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.178181] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.178230] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.178282] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.178335] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.178384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.178432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.178477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.178628] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.178637] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.178680] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.179439] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.179490] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.179537] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.179583] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.179627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.179671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.179723] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.180209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.180257] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.180301] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.180345] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.180388] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.180459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.180518] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.180569] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.181182] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.181221] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.181540] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.181600] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.181647] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.181825] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.181895] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.181990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.182259] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.182342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.182425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.182503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.182578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.182649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.182721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.182867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.182937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.183004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.183065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.183132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.183201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.183266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.183339] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.183420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.183499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.183575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.183662] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.183739] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.187436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.187494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.187545] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.187598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.188597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.188649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.188697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.189714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.189898] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.189946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.190935] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.190989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.192215] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.194571] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  330.196027] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.196112] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.196162] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.196230] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.196663] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.196717] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.213015] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.213092] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.213207] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.214253] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.214312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.214376] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.214441] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.214494] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.214551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.214607] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.214659] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.214709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.215278] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.215333] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.215345] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.215394] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.215403] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.215453] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.215502] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.215548] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.215595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.215641] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.215698] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.216414] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.216469] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.216518] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.216566] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.216612] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.216694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.217150] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.217206] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.229800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.229872] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.230264] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.246690] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.246793] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.246854] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.246960] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.247208] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.247265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.247320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.247370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.247417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.247462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.247506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.247552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.247594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.247636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.247678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.248507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.248553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.248600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.248650] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.248706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.249088] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.249140] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.249208] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.249255] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.249300] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.249363] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.249420] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.249474] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.249532] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.249584] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.249630] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.249670] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.250583] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.251277] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.251332] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.251390] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.251451] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.251500] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.251551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.251603] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.251650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.251697] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.252329] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.252377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.252387] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.252432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.252439] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.252485] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.252529] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.252572] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.252615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.252658] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.252711] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.253348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.253399] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.253445] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.253491] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.253532] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.253604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.253664] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.253714] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.254321] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.254360] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.254676] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.255220] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.255267] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.255366] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.255409] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.255474] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.255682] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.256116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.256173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.256226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.256274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.256321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.256365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.256413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.256456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.256499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.256540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.256582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.256622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.257441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.257492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.257547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.257598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.257646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.257706] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.258106] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.261612] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.261667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.261716] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.262021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.262983] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.263033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.263081] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.264114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.264165] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.264217] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.265343] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.265396] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.266595] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.269043] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  330.270550] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.270643] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.270693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.271005] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.271406] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.271460] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.287542] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.287619] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.288078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.288711] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.288991] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.289054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.289123] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.289176] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.289234] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.289291] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.289345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.289397] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.289447] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.289494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.289504] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.289550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.289558] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.289607] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.289653] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.289699] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.290629] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.290678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.290923] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.290980] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.291032] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.291080] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.291129] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.291173] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.291248] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.291308] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.291362] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.304289] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.304361] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.305022] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.321731] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.321833] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.321894] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.321999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.322247] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.322304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.322357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.322407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.322453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.322496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.322539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.322585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.322627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.322669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.322710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.323559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.323606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.323653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.323704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.324020] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.324074] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.324128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.324195] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.324241] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.324286] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.324348] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.324405] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.324460] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.324518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.324571] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.324617] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.324658] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.326030] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.326630] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.326682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.327043] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.327109] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.327159] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.327215] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.327267] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.327317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.327365] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.327411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.327454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.327464] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.327506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.327513] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.327558] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.327600] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.327643] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.327684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.328545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.328599] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.328647] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.328695] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.329007] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.329055] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.329098] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.329168] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.329227] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.329277] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.329439] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.329478] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.330233] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.330557] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.330604] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.330704] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.331009] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.331076] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.333393] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.333459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.333521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.333576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.333626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.333675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.334148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.334203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.334254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.334301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.334347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.334395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.334440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.334486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.334538] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.334598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.334654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.334706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.335521] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.335574] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.339264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.339322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.339372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.339425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.340480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.340534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.340585] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.341506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.341557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.341605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.342511] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.342565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.343790] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.346180] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  330.347607] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.347687] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.347826] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.347937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.348441] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.348497] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.364588] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.364665] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.364906] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.365687] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.365837] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.365925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.366026] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.366203] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.366284] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.366365] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.366440] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.366515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.366588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.366650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.366666] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.366730] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.366795] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.366868] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.366944] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.367007] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.367077] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.367146] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.367230] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.367303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.367381] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.367443] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.367516] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.367586] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.367693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.367821] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.367898] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.381333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.381403] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.382090] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.398592] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.398659] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.398719] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.398983] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.399281] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.399365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.399448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.399527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.399599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.399670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.399739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.399908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.399991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.400062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.400134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.400202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.400272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.400340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.400418] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.400502] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.400585] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.400667] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.400813] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.400887] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.400963] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.401061] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.401145] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.401225] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.401316] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.401400] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.401472] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.401537] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.402083] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.403141] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.403197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.403254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.403316] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.403364] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.403415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.403467] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.403515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.403561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.403606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.403650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.403658] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.403700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.403781] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.403849] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.403919] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.403998] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.404070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.404148] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.404229] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.404304] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.404380] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.404457] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.404527] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.404601] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.404705] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.404834] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.404911] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.405160] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.405223] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.405566] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.405661] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.405728] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.405887] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.405956] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.406051] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.406305] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.406388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.406470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.406545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.406617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.406686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.406831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.406911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.406981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.407053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.407121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.407194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.407264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.407337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.407411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.407496] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.407574] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.407654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.407744] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.407883] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.411480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.411538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.411589] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.411641] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.412671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.412769] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.412851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.413859] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.413911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.413960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.414875] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.414953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.416164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.418606] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  330.420085] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.420165] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.420215] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.420282] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.420686] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.420861] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.437063] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.437142] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.437256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.438083] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.438164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.438250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.438342] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.438417] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.438496] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.438575] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.438650] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.438726] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.438871] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.438949] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.438973] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.439040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.439057] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.439128] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.439201] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.439273] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.439336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.439409] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.439492] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.439567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.439646] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.439720] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.439839] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.439902] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.440009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.440095] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.440172] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.453846] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.453918] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.454310] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.470822] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.470892] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.470953] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.471061] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.471308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.471363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.471418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.471468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.471514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.471559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.471603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.471649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.471692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.472454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.472501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.472548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.472591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.472636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.472685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.473140] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.473195] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.473248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.473317] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.473364] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.473410] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.473472] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.473529] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.473583] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.473641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.473694] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.474339] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.474380] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.475335] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.476552] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.476607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.476665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.476960] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.477011] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.477068] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.477122] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.477171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.477221] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.477267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.477313] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.477323] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.477368] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.477375] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.477421] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.477463] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.477506] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.477546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.477587] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.477638] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.477680] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.478588] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.478634] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.478677] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.478957] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.479029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.479090] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.479144] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.479308] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.479348] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.479651] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.480106] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.480160] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.480257] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.480299] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.480363] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.480610] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.480667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.480722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.481227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.481276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.481326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.481372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.481421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.481465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.481509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.481552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.481595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.481637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.481680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.482337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.482392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.482443] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.482493] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.482553] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.482603] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.486151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.486205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.486255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.486307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.487559] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.487610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.487657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.488612] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.488661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.488707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.489621] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.489672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.490918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.493303] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  330.494656] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.494785] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.494840] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.494917] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.495352] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.495405] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.511639] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.511715] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.511898] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.512538] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.512595] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.512656] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.512722] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.512835] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.512898] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.512963] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.513024] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.513083] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.513137] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.513193] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.513206] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.513257] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.513270] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.513325] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.513378] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.513432] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.513482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.513529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.513583] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.513631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.513684] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.513761] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.513807] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.513857] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.513934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.513998] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.514053] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.528384] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.528457] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.528955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.545367] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.545434] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.545495] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.545601] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.549972] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.550039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.550103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.550158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.550207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.550255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.550301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.550350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.550395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.550440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.550483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.550525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.550568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.550611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.550661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.550719] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.550845] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.550906] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.550997] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.551053] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.551113] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.551181] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.551244] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.551303] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.551370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.551432] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.551483] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.551527] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.552025] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.553102] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.553159] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.553220] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.553286] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.553339] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.553393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.553446] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.553497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.553657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.553705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.553806] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.553820] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.553867] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.553889] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.553939] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.553991] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.554041] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.554093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.554141] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.554206] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.554259] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.554313] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.554362] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.554416] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.554464] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.554542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.554612] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.554676] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.554881] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.554924] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.555234] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.555300] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.555352] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.555451] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.555504] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.555571] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.555777] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.555838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.555898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.555955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.556007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.556055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.556104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.556157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.556203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.556250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.556296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.556345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.556393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.556439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.556493] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.556554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.556608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.556655] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.556718] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.556799] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.560388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.560447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.560498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.560551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.561734] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.561828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.561877] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.562871] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.562941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.563010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.563924] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.563978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.565199] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.567641] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  330.569099] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.569292] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.569343] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.569411] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.570052] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.570129] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.586190] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.586266] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.586381] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.587192] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.587249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.587309] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.587371] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.587421] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.587473] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.587525] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.587573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.587620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.587665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.587708] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.587784] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.587845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.587872] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.587940] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.588004] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.588074] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.588139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.588206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.588291] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.588364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.588440] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.588507] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.588574] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.588636] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.588787] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.588874] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.588943] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.602976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.603049] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.603440] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.619689] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.619804] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.619865] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.619971] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.620258] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.620313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.620367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.620418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.620464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.620508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.620552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.620597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.620639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.620680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.620821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.620902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.620964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.621033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.621113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.621200] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.621284] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.621365] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.621469] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.621541] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.621616] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.621714] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.621862] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.621937] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.622025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.622109] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.622181] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.622252] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.622786] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.624147] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.624219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.624301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.624388] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.624454] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.624530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.624599] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.624672] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.624804] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.624880] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.624950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.624968] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.625035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.625056] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.625123] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.625190] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.625261] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.625323] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.625391] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.625475] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.625541] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.625616] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.625680] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.625783] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.625846] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.625948] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.626025] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.626106] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.626344] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.626407] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.626729] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.627263] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.627331] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.627427] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.627495] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.627587] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.627881] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.627955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.628032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.628101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.628168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.628230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.628295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.628357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.628421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.628480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.628545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.628603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.628665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.628725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.629913] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.629972] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.630024] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.630072] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.630133] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.630185] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.633833] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.633891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.633942] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.633993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.635275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.635329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.635378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.636585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.636638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.636688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.637925] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.637979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.639204] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.641647] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  330.643104] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.643191] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.643242] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.643310] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.643905] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.643980] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.660097] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.660174] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.660289] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.661097] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.661153] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.661212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.661274] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.661324] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.661375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.661428] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.661476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.661525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.661570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.661614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.661623] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.661666] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.661673] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.661803] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.661884] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.661946] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.662016] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.662077] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.662160] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.662222] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.662296] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.662358] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.662425] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.662486] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.662588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.662665] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.662743] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.676869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.676941] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.677332] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.693654] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.693721] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.693879] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.694050] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.714500] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.714558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.714613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.714664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.714711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.714854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.714935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.715004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.715078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.715143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.715211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.715273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.715341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.715402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.715477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.715558] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.715635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.715711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.715869] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.715943] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.716017] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.716113] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.716197] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.716273] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.716358] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.716442] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.716513] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.716570] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.717118] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.718373] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.718428] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.718488] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.718549] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.718599] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.718651] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.718703] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.718835] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.718912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.718984] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.719050] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.719068] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.719131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.719145] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.719215] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.719279] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.719347] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.719410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.719478] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.719555] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.719623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.719688] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.719801] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.719864] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.719931] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.720034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.720111] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.720183] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.720347] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.720391] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.720695] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.720806] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.720859] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.720928] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.720975] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.721038] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.721411] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.721462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.721515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.721563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.721611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.721654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.721700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.721805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.721854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.721900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.721942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.721989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.722032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.722078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.722125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.722183] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.722237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.722291] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.722353] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.722401] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.725834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.725862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.725889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.725916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.726639] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.726664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.726689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.727451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.727477] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.727503] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.728253] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.728281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.729311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.731588] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  330.732302] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.732346] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.732367] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.732397] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.732569] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.732591] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.749153] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.749186] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.749236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.749515] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.749539] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.749566] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.749595] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.749617] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.749641] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.749665] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.749687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.750181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.750203] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.750223] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.750227] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.750247] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.750250] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.750270] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.750289] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.750308] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.750327] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.750346] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.750368] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.750387] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.750406] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.750424] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.750442] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.750460] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.750490] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.750515] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.750537] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.765869] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.765905] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.766100] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.782822] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.782891] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.782952] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.783061] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.783265] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.783322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.783378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.783430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.783477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.783522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.783566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.783612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.783655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.783696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.784873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.784949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.785023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.785094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.785170] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.785255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.785332] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.785410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.785515] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.785586] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.785659] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.785844] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.785933] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.786017] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.786107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.786193] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.786266] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.786328] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.786858] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.788005] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.788061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.788120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.788183] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.788232] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.788285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.788337] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.788386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.788434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.788478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.788521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.788530] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.788572] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.788579] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.788623] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.788666] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.788708] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.788839] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.788902] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.788985] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.789054] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.789120] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.789189] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.789250] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.789315] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.789417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.789502] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.789579] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.789869] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.789933] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.790276] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.790370] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.790438] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.790538] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.790605] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.790699] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.791946] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.792033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.792116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.792195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.792270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.792342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.792411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.792481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.792548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.792615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.792681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.792807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.792873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.792941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.793013] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.793095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.793172] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.793248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.793337] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.793411] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.797118] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.797178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.797230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.797283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.798196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.798273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.798348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.799301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.799352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.799401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.800310] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.800362] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.801567] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.804026] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  330.805567] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.805650] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.805701] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.806017] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.806169] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.806243] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.822537] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.822612] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.822723] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.823689] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.823912] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.823973] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.824038] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.824086] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.824141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.824194] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.824244] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.824293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.824340] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.824384] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.824395] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.824438] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.824445] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.824492] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.824534] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.824578] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.824620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.824663] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.824716] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.825768] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.825818] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.825865] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.825908] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.825951] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.826023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.826082] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.826132] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.839349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.839421] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.839558] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.856902] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.856973] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.857034] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.857142] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.857348] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.857403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.857458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.857508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.857554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.857599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.857642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.857687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.858463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.858512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.858559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.858603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.858647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.858690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.859096] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.859152] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.859204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.859254] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.859324] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.859369] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.859414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.859476] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.859531] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.859585] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.859641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.859693] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.860412] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.860454] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.861408] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.862171] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.862226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.862285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.862347] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.862396] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.862451] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.862503] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.862552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.862600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.862646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.862690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.863293] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.863340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.863348] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.863395] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.863440] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.863484] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.863526] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.863567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.863619] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.863663] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.863708] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.864356] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.864401] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.864444] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.864514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.864572] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.864622] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.865147] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.865187] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.865487] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.865548] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.865589] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.866037] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.866103] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.866168] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.868342] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.868409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.868471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.868524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.868574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.868621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.868667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.868715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.869264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.869312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.869358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.869403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.869448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.869493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.869543] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.869600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.869652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.869704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.870292] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.870347] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.874039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.874097] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.874148] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.874201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.875447] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.875500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.875549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.876641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.876692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.876970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.877955] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.878008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.879430] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.881832] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  330.883325] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.883405] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.883454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.883521] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.883671] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.884231] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.900294] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.900368] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.900481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.901475] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.901531] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.901588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.901650] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.901701] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.902189] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.902244] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.902294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.902342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.902386] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.902429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.902439] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.902482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.902489] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.902533] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.902577] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.902619] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.902661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.902703] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.903465] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.903514] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.903564] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.903610] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.903654] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.903697] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.904140] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.904200] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.904252] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.917039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.917107] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.917243] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.934513] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  330.934580] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  330.934640] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  330.935077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.937391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.937455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.937517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.937572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.937622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.937671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.937719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.938252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.938298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.938343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.938387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.938430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.938473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.938515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.938563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.938618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.938669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.939301] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.939370] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  330.939417] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  330.939463] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  330.939524] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  330.939584] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.939640] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.939699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.940186] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.940233] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.940273] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.941240] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.941942] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.941996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.942054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.942118] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.942166] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.942218] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.942271] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.942319] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.942366] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.942412] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.942456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.942464] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.942506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.942513] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.942557] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.942600] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.942641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.942683] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.943614] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.943669] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.943717] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.943985] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.944031] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.944079] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.944131] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.944226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  330.944287] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.944338] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.944500] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.944539] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.945338] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.945661] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  330.945703] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  330.946071] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  330.946113] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  330.946178] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  330.946347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  330.946404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  330.946458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  330.946509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  330.946556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  330.946602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  330.946646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  330.946691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  330.947313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  330.947358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  330.947402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  330.947444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  330.947486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  330.947527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  330.947575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  330.947629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.947680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  330.948195] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  330.948257] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  330.948308] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  330.952028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.952086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.952136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.952188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.953182] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  330.953235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  330.953285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.954351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  330.954403] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  330.954451] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  330.955616] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.955669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  330.957072] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.959463] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  330.961056] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.961138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  330.961189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  330.961255] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  330.961690] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.962093] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  330.978036] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  330.978113] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  330.978227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  330.979205] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  330.979263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.979325] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  330.979391] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  330.979443] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  330.979498] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.979554] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  330.979604] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  330.979654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  330.979701] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  330.980376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.980386] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.980436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.980443] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  330.980492] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  330.980540] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  330.980587] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.980632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.980676] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.981246] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.981300] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.981352] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  330.981401] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  330.981449] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  330.981494] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  330.981569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  330.981630] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  330.981683] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  330.994827] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  330.994899] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  330.995291] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.011677] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.011786] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  331.011846] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.011952] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.012239] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.012296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.012351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.012401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.012448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.012493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.012538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.012584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.012627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.012669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.012710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.013523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.013570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.013615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.013665] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.014051] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.014107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.014159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.014226] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.014271] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.014317] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.014379] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.014436] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.014490] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  331.014546] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.014598] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.014644] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.014683] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.015828] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.016694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.016880] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.016919] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.017224] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.017302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.017357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.017408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.017454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.017498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.017541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.017585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.017626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.017668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.017708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.017809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.017855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.017897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.017944] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.017996] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.018052] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.018103] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.018152] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.018220] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  331.018280] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.018330] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.018372] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.018859] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.019355] [drm:drm_mode_addfb2] [FB:69]
>[  331.019428] [drm:drm_mode_addfb2] [FB:110]
>[  331.108551] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  331.108946] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  331.109455] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  331.109972] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  331.109981] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  331.110048] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.110065] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.110084] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.110104] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.110119] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.110135] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.110151] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.110167] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.110181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.110195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.110208] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.110212] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.110224] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.110227] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.110240] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.110253] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.110266] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.110279] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.110292] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.110308] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.110321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.110334] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  331.110347] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.110359] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.110380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.110398] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.110413] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.111495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.111506] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.111819] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.111857] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.111869] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.111914] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.111931] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.111953] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.116412] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.116462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.116509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.116549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.116584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.116618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.116651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.116686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.117131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.117167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.117201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.117234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.117266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.117297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.117333] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.117375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.117412] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.117448] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.117495] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.117532] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.121026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.121059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.121087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.121116] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.121974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.122004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.122032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.122904] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.122934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.122960] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.123682] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.123877] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.125043] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.127324] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  331.128042] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.128083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.128106] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.128137] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.144883] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.144913] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.144959] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.178455] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.178485] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.178620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.178654] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.178680] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.178897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.178927] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.178955] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.178981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.179006] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.179030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.179036] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.179059] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.179063] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.179087] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.179110] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.179133] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.179155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.179178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.179209] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.179232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.179256] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.179279] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.179300] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.179322] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.179359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.179390] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.179416] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.195091] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.195175] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.195610] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.211849] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.211916] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.212026] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.214455] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.214521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.214584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.214639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.214689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.215111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.215164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.215217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.215265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.215311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.215356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.215401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.215446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.215490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.215542] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.215599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.215652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.215704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.216370] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.216421] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.216470] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.216535] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.216599] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.216660] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.216719] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.217140] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.217189] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.217232] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.217687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.218910] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.218968] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.219030] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.219097] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.219151] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.219206] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.219261] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.219313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.219363] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.219412] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.219458] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.219468] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.219515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.219521] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.219569] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.219615] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.219660] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.219704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.220657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.220715] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.220952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.221009] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.221058] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.221106] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.221152] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.221228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.221291] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.221346] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.221518] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.221560] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.222367] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.222692] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.222903] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.222976] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.223019] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.223087] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.223259] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.223318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.223375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.223428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.223477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.223525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.223572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.223622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.223668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.223713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.224407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.224456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.224502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.224548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.224600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.224657] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.224710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.225121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.225186] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.225238] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.228895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.228952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.229003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.229055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.230215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.230269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.230317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.231500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.231551] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.231598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.232635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.232689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.234135] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.236582] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  331.238094] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.238184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.238236] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.238304] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.255043] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.255115] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.255228] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.256109] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.256165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.256223] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.256285] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.256335] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.256388] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.256441] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.256489] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.256537] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.256582] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.256626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.257295] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.257343] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.257351] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.257399] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.257445] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.257490] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.257534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.257577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.257629] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.257672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.258226] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.258272] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.258316] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.258357] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.258429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.258486] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.258537] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.271823] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.271887] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.272259] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.288464] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.288528] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.288633] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.291059] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.291123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.291180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.291231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.291278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.291323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.291367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.291413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.291456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.291498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.291539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.291580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.291621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.291660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.291708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.292446] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.292499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.292549] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.292615] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.292660] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.292705] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.293097] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.293156] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.293211] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.293265] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.293317] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.293362] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.293401] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.294469] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.295175] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.295228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.295286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.295349] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.295398] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.295450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.295503] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.295552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.295600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.295646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.295690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.296256] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.296304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.296311] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.296359] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.296404] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.296448] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.296490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.296531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.296583] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.296626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.296670] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.296713] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.297405] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.297450] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.297521] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.297580] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.297629] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.298085] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.298124] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.298425] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.298484] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.298536] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.298636] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.298677] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.299116] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.301462] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.301530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.301591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.301647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.301697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.302108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.302161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.302213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.302261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.302307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.302353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.302398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.302442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.302486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.302537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.302595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.302647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.302700] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.303355] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.303409] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.307052] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.307110] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.307162] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.307214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.308473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.308526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.308576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.309638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.309690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.309952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.310966] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.311020] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.312419] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.314802] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  331.316250] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.316327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.316379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.316446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.333228] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.333306] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.333420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.334345] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.334404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.334466] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.334531] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.334584] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.334638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.334694] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.335295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.335348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.335398] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.335444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.335452] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.335498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.335505] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.335554] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.335600] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.335645] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.335690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.336338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.336396] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.336446] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.336499] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.336548] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.336595] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.336641] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.336716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.337290] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.337346] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.349976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.350047] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.350541] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.366678] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.366784] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.366892] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.367057] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.367114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.367171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.367223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.367269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.367314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.367358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.367403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.367446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.367489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.367531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.367573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.367614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.367655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.367702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.368638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.368692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.368934] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.369003] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.369050] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.369095] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.369157] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.369215] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.369270] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.369324] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.369376] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.369422] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.369462] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.370905] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.371625] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.371680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.371986] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.372049] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.372100] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.372153] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.372206] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.372255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.372303] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.372348] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.372391] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.372399] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.372441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.372448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.372493] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.372536] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.372578] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.372620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.372660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.372712] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.373695] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.373892] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.373939] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.373985] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.374029] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.374103] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.374163] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.374214] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.374372] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.374412] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.375220] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.375540] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.375590] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.375692] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.376116] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.376183] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.376389] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.376445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.376500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.376550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.376597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.376642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.376686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.377237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.377286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.377331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.377375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.377419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.377463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.377505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.377554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.377608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.377657] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.377707] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.378310] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.378360] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.382053] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.382112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.382163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.382215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.383443] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.383499] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.383549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.384735] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.384833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.384883] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.386056] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.386111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.387428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.389822] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  331.391275] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.391352] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.391402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.391467] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.408257] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.408336] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.408452] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.409331] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.409391] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.409454] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.409519] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.409571] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.409625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.409680] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.410176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.410228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.410276] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.410323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.410332] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.410377] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.410384] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.410431] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.410476] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.410520] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.410564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.410607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.410661] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.410705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.411479] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.411528] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.411574] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.411618] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.411692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.412087] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.412141] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.425005] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.425077] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.425469] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.441850] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.441918] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.442029] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.442273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.442329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.442386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.442436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.442482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.442526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.442570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.442615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.442658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.442701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.443473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.443519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.443564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.443607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.443656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.443712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.444119] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.444279] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.444351] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.444398] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.444443] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.444505] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.444562] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.444616] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.444669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.445200] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.445247] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.445288] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.446242] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.447017] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.447071] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.447129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.447191] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.447241] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.447293] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.447346] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.447394] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.447442] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.447488] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.447531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.447541] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.447585] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.447592] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.447637] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.447680] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.448608] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.448653] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.448697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.448980] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.449028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.449078] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.449122] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.449166] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.449207] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.449278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.449337] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.449385] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.449552] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.449592] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.450465] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.450932] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.450982] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.451083] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.451127] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.451192] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.453397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.453462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.453524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.453579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.453627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.453674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.453915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.453969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.454016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.454062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.454107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.454153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.454199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.454244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.454296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.454356] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.454411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.454465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.454529] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.454583] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.458168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.458226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.458277] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.458328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.459502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.459553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.459603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.460646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.460698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.460897] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.461852] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.461909] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.463122] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.465513] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  331.466940] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.467018] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.467068] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.467136] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.483952] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.484059] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.484231] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.485442] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.485521] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.485605] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.485695] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.485979] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.486063] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.486146] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.486222] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.486297] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.486369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.486441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.486456] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.486525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.486539] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.486609] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.486677] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.486981] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.487050] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.487119] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.487197] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.487269] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.487339] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.487409] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.487473] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.487541] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.487646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.487733] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.487993] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.500732] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.500913] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.501387] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.517551] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.517619] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.517727] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.520143] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.520208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.520270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.520325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.520376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.520425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.520473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.520522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.520567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.520611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.520656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.520700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.521529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.521580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.521634] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.521695] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.522087] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.522142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.522224] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.522382] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.522431] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.522497] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.522560] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.522618] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.522678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.523288] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.523338] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.523382] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.524379] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.525182] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.525242] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.525305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.525372] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.525426] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.525483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.525539] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.525591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.525643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.525691] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.526379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.526389] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.526440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.526448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.526499] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.526548] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.526595] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.526642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.526686] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.527408] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.527463] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.527519] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.527569] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.527616] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.527663] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.528171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.528237] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.528292] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.528458] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.528501] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.529190] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.529516] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.529566] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.529672] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.529990] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.530058] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.530310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.530369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.530424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.530474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.530521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.530567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.530611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.530657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.530700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.531422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.531469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.531514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.531557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.531600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.531649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.531705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.532210] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.532262] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.532324] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.532375] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.536022] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.536079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.536129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.536182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.537418] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.537471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.537520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.538817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.538869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.538917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.540126] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.540180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.541428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.543834] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  331.545290] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.545369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.545418] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.545484] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.562269] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.562347] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.562465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.563162] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.563219] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.563280] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.563346] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.563398] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.563454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.563508] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.563559] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.563609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.563656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.563702] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.563771] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.563819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.563838] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.563887] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.563933] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.563983] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.564031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.564077] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.564136] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.564184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.564234] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.564283] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.564329] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.564376] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.564451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.564515] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.564570] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.579013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.579085] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.579472] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.595809] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.595877] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.595985] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.596229] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.596285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.596340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.596390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.596436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.596480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.596523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.596568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.596609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.596651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.596692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.596954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.597000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.597044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.597093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.597148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.597200] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.597250] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.597321] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.597369] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.597416] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.597478] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.597536] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.597588] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.597641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.597695] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.597914] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.597956] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.598409] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.599135] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.599186] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.599243] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.599304] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.599354] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.599404] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.599455] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.599502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.599547] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.599591] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.599633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.599641] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.599682] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.599863] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.599909] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.599956] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.599998] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.600042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.600082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.600136] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.600180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.600227] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.600271] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.600314] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.600356] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.600532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.600591] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.600641] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.600962] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.601004] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.601306] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.601368] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.601417] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.601516] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.601559] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.601621] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.603827] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.603882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.603935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.603986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.604030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.604073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.604116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.604159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.604201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.604241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.604281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.604321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.604361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.604401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.604447] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.604500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.604549] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.604598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.604656] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.604705] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.608427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.608483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.608532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.608583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.609519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.609569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.609616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.610516] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.610565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.610611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.611532] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.611583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.612804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.615244] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  331.616818] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.616897] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.616949] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.617016] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.633826] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.633905] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.634020] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.634668] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.634725] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.634959] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.635028] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.635083] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.635143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.635200] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.635255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.635308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.635359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.635407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.635417] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.635464] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.635473] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.635521] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.635568] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.635616] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.635663] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.635710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.635945] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.635994] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.636046] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.636093] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.636139] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.636184] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.636260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.636322] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.636379] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.650538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.650610] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.651138] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.667664] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.667968] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.668078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.670285] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.670350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.670412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.670467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.670517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.670565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.670613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.670661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.670707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.671325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.671375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.671422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.671467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.671512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.671563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.671621] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.671676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.672183] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.672259] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.672310] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.672360] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.672426] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.672489] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.672548] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.672605] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.672661] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.672711] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.672916] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.673370] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.674050] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.674110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.674173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.674240] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.674294] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.674350] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.674405] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.674457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.674509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.674558] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.674605] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.674615] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.674660] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.674669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.674716] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.674949] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.674996] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.675043] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.675088] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.675144] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.675191] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.675241] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.675286] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.675331] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.675374] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.675449] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.675510] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.675563] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.675883] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.675926] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.676232] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.676297] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.676353] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.676455] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.676498] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.676561] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.678866] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.678934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.678999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.679054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.679104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.679153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.679200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.679250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.679295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.679339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.679384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.679427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.679471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.679515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.679566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.679623] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.679677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.680238] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.680308] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.680363] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.684039] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.684096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.684146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.684199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.685476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.685528] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.685577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.686691] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.686781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.686829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.687690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.688042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.689461] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.691864] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  331.693407] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.693493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.693544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.693610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.726919] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.726953] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.727006] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.727311] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.727336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.727362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.727390] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.727413] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.727437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.727461] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.727483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.727505] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.727526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.727547] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.727552] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.727571] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.727574] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.727595] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.727614] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.727633] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.727652] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.727671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.727728] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.727748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.727774] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.727795] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.727816] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.727836] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.727870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.727898] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.727923] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.743697] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.743762] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.743963] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.760518] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.760570] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.760655] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.760965] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.761010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.761053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.761093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.761128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.761162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.761194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.761227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.761258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.761289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.761319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.761349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.761379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.761407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.761443] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.761483] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.761521] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.761558] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.761616] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.761651] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.761685] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.762342] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.762389] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.762432] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.762474] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.762515] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.762550] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.762581] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.763537] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.764121] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.764161] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.764206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.764254] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.764292] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.764331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.764369] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.764406] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.764441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.764475] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.764508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.764515] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.764547] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.764552] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.764585] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.764617] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.764648] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.764678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.765313] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.765356] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.765393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.765430] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.765464] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.765496] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.765526] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.765582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.765627] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.765665] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.766116] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.766146] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.766453] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.766497] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.766531] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.766612] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.766644] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.766691] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.767190] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.767234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.767276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.767314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.767349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.767383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.767416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.767451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.767484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.767516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.767547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.767578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.767608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.767639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.767675] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.768162] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.768203] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.768242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.768289] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.768327] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.771823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.771866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.771904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.771943] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.772992] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.773032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.773069] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.773960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.774000] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.774036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.774935] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.774974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.776147] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.778510] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  331.779621] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.779691] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.779856] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.779911] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.796549] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.796609] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.796697] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.797391] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.797434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.797480] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.797529] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.797568] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.797609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.797650] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.797689] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.798021] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.798060] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.798096] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.798104] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.798138] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.798145] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.798181] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.798216] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.798250] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.798284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.798317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.798359] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.798393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.798429] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.798463] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.798496] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.798529] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.798584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.798630] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.798670] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.813427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.813502] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.814214] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.830623] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.830693] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.831223] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.833510] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.833569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.833626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.833679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.834296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.834347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.834393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.834441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.834485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.834527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.834569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.834610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.834651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.834691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.835370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.835426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.835479] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.835528] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.835600] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.835647] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.835692] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.836139] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.836198] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.836254] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.836307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.836359] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.836405] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.836446] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.837530] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.838250] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.838304] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.838363] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.838424] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.838472] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.838525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.838578] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.838626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.838674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.839230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.839278] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.839287] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.839332] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.839339] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.839386] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.839429] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.839472] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.839514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.839555] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.839608] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.839650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.839695] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.840441] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.840487] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.840531] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.840602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.840663] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.840715] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.841244] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.841284] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.841585] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.841643] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.841692] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.842101] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.842143] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.842209] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.842388] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.842444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.842498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.842548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.842593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.842636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.842678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.843249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.843296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.843341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.843384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.843428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.843471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.843513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.843562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.843617] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.843666] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.843716] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.844295] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.844344] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.847933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.847991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.848041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.848094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.849394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.849450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.849500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.850807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.850859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.850907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.852077] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.852132] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.853428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.855823] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  331.857276] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.857355] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.857405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.857472] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.874253] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.874332] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.874447] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.875175] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.875232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.875292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.875357] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.875408] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.875463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.875517] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.875569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.875619] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.875667] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.875714] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.875784] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.875832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.875853] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.875908] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.875957] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.876006] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.876062] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.876112] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.876177] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.876228] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.876287] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.876338] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.876389] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.876437] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.876518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.876581] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.876643] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.891074] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.891151] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.891594] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.907861] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.907930] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.908040] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.908290] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.908348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.908404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.908454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.908500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.908545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.908588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.908634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.908676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.908793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.908846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.908899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.908942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.908987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.909043] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.909104] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.909160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.909216] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.909293] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.909339] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.909388] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.909456] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.909513] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.909566] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.909619] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.909675] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.909774] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.909818] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.910270] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.910960] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.911012] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.911071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.911132] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.911182] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.911235] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.911289] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.911340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.911388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.911435] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.911479] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.911491] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.911534] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.911541] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.911588] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.911631] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.911674] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.911761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.911809] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.911869] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.911923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.911976] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.912029] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.912075] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.912125] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.912204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.912272] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.912330] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.912504] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.912545] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.912999] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.913370] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.913419] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.913520] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.913564] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.913626] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.916001] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.916070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.916133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.916187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.916236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.916284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.916331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.916379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.916424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.916467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.916510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.916555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.916599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.916642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.916692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.916837] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.916905] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.916967] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.917036] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.917095] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.920692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.920777] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.920828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.920881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.921826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.921880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.921933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.922841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.922889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.922935] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.923835] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.923887] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.925102] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.927488] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  331.928940] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  331.929026] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  331.929076] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  331.929141] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.945934] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.946012] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.946128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.946838] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.946902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.946974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.947048] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.947105] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.947167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.947228] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.947288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.947344] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.947395] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.947452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.947469] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.947516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.947525] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.947572] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.947625] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.947675] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.947756] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.947804] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.947864] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.947919] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.947970] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.948022] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.948070] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.948124] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.948200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  331.948263] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.948321] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.962674] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  331.962793] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  331.963184] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  331.979734] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  331.979832] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.979941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.980230] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.980288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.980343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.980394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.980440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.980485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.980530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.980575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.980618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.980660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.980701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.981554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.981604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.981648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.981699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.982014] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.982068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.982121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.982189] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  331.982235] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  331.982281] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.982343] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.982400] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  331.982454] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  331.982508] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.982560] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.982606] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.982646] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.984004] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.984601] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  331.984656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.984715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.985067] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.985119] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.985175] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.985229] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  331.985282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  331.985331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.985379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.985424] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.985434] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.985477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.985485] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.985530] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.985573] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.985616] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.985658] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.985700] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.986594] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.986643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.986693] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  331.986968] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  331.987014] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  331.987062] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  331.987134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.987196] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  331.987246] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  331.987406] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.987445] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.988245] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.988566] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.988618] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.988721] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  331.988875] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  331.988972] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.991306] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.991372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  331.991433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  331.991489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  331.991539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  331.991587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  331.991634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  331.991683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  331.992226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  331.992278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  331.992327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  331.992375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  331.992422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  331.992468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  331.992520] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  331.992581] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  331.992637] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  331.992691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  331.993271] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  331.993325] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.996918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.996976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.997027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.997080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.998197] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  331.998250] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.998299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  331.999190] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  331.999242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.999289] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.000348] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.000402] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.001600] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.004037] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  332.005524] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.005604] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.005654] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.005966] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.022603] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.022681] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.023099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.023737] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.024023] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.024088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.024158] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.024211] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.024270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.024326] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.024381] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.024433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.024484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.024531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.024541] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.024586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.024594] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.024642] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.024688] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.025508] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.025557] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.025603] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.025659] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.025707] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.026067] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.026115] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.026165] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.026210] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.026285] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.026347] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.026401] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.039324] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.039398] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.040131] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.056663] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.056962] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.057076] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.057325] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.057382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.057438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.057489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.057536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.057581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.057625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.057672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.057716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.058441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.058491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.058540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.058584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.058628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.058678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.059076] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.059130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.059182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.059254] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.059301] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.059346] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.059408] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.059465] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.059520] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.059573] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.059626] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.059672] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.060284] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.061239] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.062037] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.062091] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.062148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.062211] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.062260] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.062314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.062366] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.062414] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.062463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.062508] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.062552] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.062561] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.062603] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.062610] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.062654] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.062695] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.063568] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.063616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.063660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.063715] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.064043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.064091] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.064138] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.064181] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.064223] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.064295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.064354] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.064404] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.064571] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.064610] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.065518] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.065985] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.066042] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.066142] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.066185] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.066254] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.068433] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.068499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.068560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.068614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.068663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.068710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.069298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.069353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.069403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.069450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.069495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.069542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.069588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.069633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.069684] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.070227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.070282] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.070335] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.070400] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.070454] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.074018] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.074072] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.074122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.074176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.075412] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.075464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.075511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.076646] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.076697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.076962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.077972] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.078026] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.079424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.081818] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  332.083268] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.083347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.083396] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.083462] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.100255] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.100333] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.100560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.101498] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.101557] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.101620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.101685] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.102049] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.102108] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.102167] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.102219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.102271] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.102319] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.102366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.102375] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.102422] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.102429] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.102477] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.102522] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.102567] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.102612] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.102656] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.102710] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.103570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.103622] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.103669] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.103715] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.104038] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.104113] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.104175] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.104231] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.116993] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.117065] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.117454] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.133815] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.133883] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.133993] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.136205] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.136272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.136334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.136389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.136438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.136486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.136532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.136580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.136624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.136667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.136711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.137463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.137513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.137563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.137617] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.137678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.138042] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.138097] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.138174] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.138223] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.138272] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.138336] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.138395] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.138452] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.138509] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.138564] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.138613] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.138656] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.139987] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.140619] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.140675] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.140977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.141045] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.141101] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.141157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.141213] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.141267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.141318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.141368] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.141414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.141425] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.141471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.141478] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.141527] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.141573] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.141620] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.141666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.141711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.142620] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.142673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.142910] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.142961] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.143012] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.143060] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.143135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.143199] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.143256] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.143427] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.143470] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.144326] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.144650] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.144705] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.145030] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.145073] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.145141] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.145441] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.145497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.145552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.145602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.145649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.145693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.146248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.146299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.146347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.146390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.146432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.146476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.146517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.146559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.146606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.146660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.146711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.147427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.147489] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.147539] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.151167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.151224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.151274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.151327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.152547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.152600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.152650] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.153632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.153681] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.153796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.154668] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.154718] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.155961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.158381] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  332.159832] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.159921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.159974] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.160043] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.176848] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.176926] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.177042] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.177694] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.177921] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.177987] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.178055] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.178110] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.178168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.178225] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.178281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.178334] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.178385] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.178432] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.178444] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.178490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.178604] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.178653] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.178700] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.178925] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.178974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.179020] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.179076] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.179126] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.179178] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.179226] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.179274] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.179319] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.179396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.179458] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.179515] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.193564] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.193636] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.194094] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.210732] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.210839] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.210947] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.211113] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.211169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.211225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.211276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.211323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.211368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.211411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.211456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.211498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.211540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.211581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.211622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.211663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.211703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.212476] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.212534] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.212589] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.212640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.212713] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.213024] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.213070] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.213131] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.213190] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.213247] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.213300] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.213351] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.213396] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.213436] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.214546] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.215249] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.215303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.215359] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.215420] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.215470] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.215523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.215574] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.215622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.215669] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.215714] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.216213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.216224] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.216271] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.216280] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.216327] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.216372] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.216416] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.216460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.216502] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.216556] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.216601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.216647] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.216691] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.217263] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.217307] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.217379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.217437] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.217487] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.217645] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.217684] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.218322] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.218381] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.218434] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.218526] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.218567] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.218630] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.223018] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.223087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.223152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.223207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.223257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.223306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.223353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.223402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.223448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.223493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.223539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.223583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.223627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.223670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.223721] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.224489] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.224548] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.224602] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.224670] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.224725] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.228575] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.228633] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.228685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.229087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.230239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.230292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.230340] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.231501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.231552] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.231599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.232525] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.232579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.233820] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.236260] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  332.237708] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.237826] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.237878] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.237946] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.254725] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.254845] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.254962] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.255632] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.255689] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.255928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.256002] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.256057] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.256117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.256175] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.256232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.256283] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.256332] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.256381] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.256394] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.256440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.256449] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.256496] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.256543] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.256591] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.256922] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.256968] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.257029] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.257077] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.257128] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.257174] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.257221] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.257265] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.257342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.257406] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.257463] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.271544] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.271620] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.272158] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.288849] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.288918] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.289027] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.289277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.289333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.289389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.289440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.289488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.289534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.289580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.289626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.289669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.289711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.289833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.289880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.289925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.289966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.290016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.290075] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.290128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.290180] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.290257] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.290306] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.290352] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.290416] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.290474] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.290529] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.290583] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.290637] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.290684] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.290764] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.291218] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.291911] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.291961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.292019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.292080] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.292130] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.292182] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.292233] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.292281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.292328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.292373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.292416] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.292426] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.292468] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.292475] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.292518] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.292559] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.292600] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.292641] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.292681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.292789] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.292836] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.292885] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.292926] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.292970] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.293012] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.293082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.293142] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.293193] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.293362] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.293403] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.293762] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.293823] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.293870] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.293974] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.294023] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.294088] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.294494] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.294554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.294610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.294664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.294712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.294889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.294936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.294986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.295028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.295071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.295116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.295158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.295201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.295244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.295291] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.295345] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.295395] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.295444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.295505] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.295555] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.299187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.299245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.299295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.299347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.300421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.300474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.300523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.301524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.301576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.301625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.302718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.302816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.304288] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.306687] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  332.308169] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.308251] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.308300] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.308367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.325153] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.325231] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.325347] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.326413] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.326470] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.326529] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.326591] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.326640] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.326694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.327315] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.327367] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.327418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.327464] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.327508] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.327517] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.327561] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.327568] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.327614] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.327657] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.327700] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.328535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.328584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.328640] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.328688] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.329109] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.329160] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.329208] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.329252] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.329326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.329385] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.329436] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.341942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.342015] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.342404] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.358664] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.358970] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.359126] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.359379] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.359435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.359492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.359544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.359592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.359640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.359685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.360371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.360421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.360468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.360514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.360560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.360604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.360648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.360697] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.361409] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.361465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.361517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.361586] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.361632] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.361677] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.362209] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.362273] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.362330] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.362384] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.362437] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.362484] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.362524] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.363767] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.364317] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.364372] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.364430] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.364493] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.364542] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.364595] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.364647] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.364697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.365380] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.365429] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.365474] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.365483] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.365526] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.365533] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.365578] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.365621] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.365664] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.365705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.366538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.366593] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.366642] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.366692] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.367120] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.367169] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.367215] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.367288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.367348] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.367399] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.367557] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.367597] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.368467] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.368983] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.369050] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.369152] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.369216] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.369283] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.369495] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.369553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.369608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.369660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.369707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.370417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.370466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.370517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.370562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.370606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.370649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.370691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.371238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.371284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.371335] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.371391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.371442] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.371492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.371552] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.371602] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.375151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.375205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.375253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.375305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.376314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.376366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.376414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.377319] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.377371] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.377419] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.378320] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.378373] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.379570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.382112] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  332.383569] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.383649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.383700] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.383828] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.400552] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.400630] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.401074] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.401730] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.402009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.402094] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.402183] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.402236] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.402292] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.402346] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.402396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.402446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.402491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.402537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.402545] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.402589] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.402597] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.402641] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.402685] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.403570] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.403619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.403664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.403719] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.404059] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.404134] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.404196] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.404241] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.404286] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.404361] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.404419] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.404470] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.417290] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.417364] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.418052] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.434877] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.434945] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.435055] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.435260] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.435317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.435372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.435423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.435471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.435516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.435559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.435604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.435646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.435688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.436666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.436718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.436987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.437060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.437137] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.437201] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.437256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.437307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.437380] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.437427] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.437474] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.437537] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.437596] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.437651] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.437705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.438440] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.438487] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.438527] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.439504] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.440381] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.440437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.440495] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.440559] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.440609] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.440662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.440714] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.441273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.441324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.441369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.441413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.441423] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.441466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.441473] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.441516] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.441558] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.441599] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.441640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.441680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.442473] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.442525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.442577] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.442624] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.442668] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.442710] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.443198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.443261] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.443312] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.443479] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.443518] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.444295] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.444627] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.444680] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.445047] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.445090] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.445155] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.447362] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.447429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.447492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.447547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.447596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.447643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.447688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.448271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.448320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.448367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.448412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.448457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.448500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.448542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.448591] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.448647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.448697] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.449398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.449463] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.449515] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.453249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.453310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.453361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.453414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.454657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.454711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.455029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.456003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.456063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.456113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.457304] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.457360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.458571] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.461052] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  332.462623] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.462712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.462987] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.463095] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.479639] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.479717] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.480154] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.481057] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.481121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.481181] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.481244] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.481292] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.481344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.481398] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.481446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.481493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.481538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.481582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.481591] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.481634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.481641] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.481685] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.482612] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.482663] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.482710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.483001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.483084] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.483154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.483204] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.483251] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.483295] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.483336] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.483412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.483471] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.483523] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.496359] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.496431] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.497126] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.513383] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.513450] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.513557] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.514029] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.514110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.514192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.514266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.514316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.514362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.514405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.514451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.514493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.514535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.514576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.514618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.514660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.514702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.515443] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.515528] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.515607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.515685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.516211] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.516271] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.516319] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.516381] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.516442] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.516500] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.516556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.516608] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.516653] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.516692] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.517721] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.518937] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.518994] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.519052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.519114] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.519163] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.519214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.519267] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.519315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.519363] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.519408] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.519452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.519460] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.519502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.519509] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.519553] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.519595] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.519636] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.519677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.520627] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.520706] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.521074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.521151] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.521219] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.521265] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.521308] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.521378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.521436] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.521485] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.521645] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.521684] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.522644] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.522944] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.523012] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.523116] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.523180] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.523252] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.525635] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.525702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.526031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.526110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.526183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.526254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.526304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.526352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.526394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.526436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.526478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.526519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.526560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.526601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.526648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.526703] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.527416] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.527470] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.527540] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.527614] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.531271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.531330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.531380] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.531432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.532471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.532523] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.532571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.533725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.533822] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.533870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.534825] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.534885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.536129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.538504] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  332.539969] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.540055] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.540105] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.540171] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.556964] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.557042] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.557160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.557959] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.558041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.558130] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.558221] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.558297] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.558371] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.558427] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.558480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.558529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.558578] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.558621] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.558632] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.558677] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.558737] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.558786] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.558833] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.558883] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.558931] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.558979] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.559036] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.559087] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.559136] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.559185] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.559232] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.559279] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.559356] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.559437] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.559517] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.573702] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.573814] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.574205] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.590703] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.590813] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.590921] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.591127] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.591183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.591237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.591289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.591335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.591379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.591423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.591468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.591511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.591552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.591594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.591636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.591676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.591791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.591849] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.591911] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.591962] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.592014] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.592091] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.592141] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.592209] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.592310] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.592395] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.592471] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.592550] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.592632] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.592692] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.592783] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.593259] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.594103] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.594157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.594215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.594276] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.594325] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.594377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.594430] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.594477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.594525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.594570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.594612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.594621] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.594663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.594670] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.594714] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.594819] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.594875] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.594924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.594967] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.595025] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.595074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.595124] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.595174] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.595221] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.595267] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.595342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.595405] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.595460] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.595680] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.595804] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.596138] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.596232] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.596300] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.596403] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.596467] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.596556] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.598895] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.598963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.599027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.599082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.599132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.599182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.599230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.599277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.599323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.599368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.599412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.599455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.599498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.599541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.599591] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.599647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.599700] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.599832] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.599908] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.599967] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.603561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.603618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.603669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.603722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.604702] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.604812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.604867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.605839] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.605891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.605938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.606856] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.606933] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.608150] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.610536] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  332.612000] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.612090] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.612140] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.612208] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.628997] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.629076] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.629192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.629916] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.629996] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.630083] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.630170] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.630222] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.630278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.630332] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.630384] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.630433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.630481] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.630525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.630549] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.630592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.630599] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.630645] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.630690] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.630788] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.630836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.630886] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.630941] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.630988] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.631039] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.631082] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.631130] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.631174] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.631247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.631310] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.631363] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.645775] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.645846] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.646235] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.662688] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.662794] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.663005] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.665255] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.665320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.665381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.665435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.665484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.665532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.665580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.665629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.665675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.665786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.665836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.665889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.665941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.665992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.666049] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.666112] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.666169] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.666227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.666318] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.666394] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.666467] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.666566] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.666651] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.666709] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.666813] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.666873] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.666924] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.666969] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.667449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.668324] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.668378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.668436] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.668498] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.668546] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.668597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.668648] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.668696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.668814] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.668872] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.668922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.668932] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.668976] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.668990] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.669035] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.669079] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.669127] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.669170] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.669218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.669272] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.669319] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.669369] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.669417] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.669461] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.669507] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.669593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.669676] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.669796] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.670043] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.670104] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.670414] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.670476] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.670526] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.670623] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.670668] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.670779] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.671045] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.671125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.671206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.671283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.671340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.671386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.671433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.671480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.671526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.671570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.671613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.671655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.671697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.671783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.671833] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.671893] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.671949] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.672002] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.672064] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.672119] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.675779] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.675838] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.675888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.675940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.676870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.676944] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.677018] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.677944] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.678017] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.678071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.678981] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.679057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.680321] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.682708] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  332.684169] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.684252] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.684302] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.684370] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.714613] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.714693] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.714901] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.715534] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.715573] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.715615] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.715663] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.715698] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.715778] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.715818] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.715858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.715897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.715931] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.715963] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.715974] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.716004] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.716013] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.716047] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.716080] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.716115] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.716148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.716181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.716228] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.716274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.716325] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.716374] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.716422] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.716468] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.716540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.716600] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.716651] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.717826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.717876] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.718146] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.734475] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.734510] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.734568] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.738963] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.738999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.739034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.739063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.739090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.739115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.739140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.739166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.739191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.739214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.739238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.739261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.739284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.739307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.739334] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.739365] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.739393] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.739421] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.739468] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.739494] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.739520] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.739557] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.739589] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.739618] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.739647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.739676] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.739749] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.739776] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.740219] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.740654] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.740683] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.740749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.740785] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.740814] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.740847] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.740877] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.740906] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.740933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.740960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.741102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.741111] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.741145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.741152] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.741178] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.741200] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.741224] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.741245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.741266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.741294] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.741316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.741340] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.741361] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.741383] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.741404] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.741442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.741473] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.741500] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.741594] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.741615] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.741927] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.741960] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.741985] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.742027] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.742053] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.742087] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.742258] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.742300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.742342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.742382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.742420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.742455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.742484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.742509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.742532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.742554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.742577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.742599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.742621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.742643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.742669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.742727] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.742754] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.742784] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.742820] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.742847] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.746189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.746220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.746246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.746275] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.747021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.747049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.747076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.747808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.747848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.747880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.748592] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.748618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.749663] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.751932] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  332.752665] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.752755] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.752785] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.752830] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.769544] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.769585] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.769648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.770083] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.770114] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.770145] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.770178] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.770204] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.770231] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.770259] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.770284] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.770309] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.770333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.770356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.770361] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.770383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.770387] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.770411] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.770434] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.770456] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.770479] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.770500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.770528] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.770550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.770573] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.770595] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.770616] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.770638] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.770674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.770736] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.770765] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.786285] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.786331] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.786582] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.804177] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.804243] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.804351] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.804515] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.804571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.804625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.804677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.804789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.804838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.804890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.804943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.804993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.805038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.805088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.805134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.805180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.805223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.805276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.805337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.805414] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.805493] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.805599] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.805670] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.805767] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.805871] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.805957] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.806037] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.806117] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.806182] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.806229] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.806272] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.806782] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.807931] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.807986] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.808044] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.808107] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.808157] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.808210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.808263] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.808312] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.808360] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.808405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.808448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.808458] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.808500] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.808508] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.808552] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.808596] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.808638] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.808680] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.808768] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.808819] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.808868] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.808922] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.808969] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.809016] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.809066] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.809138] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.809200] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.809256] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.809468] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.809529] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.809907] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.810389] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.810452] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.810555] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.810619] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.810711] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.810967] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.811048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.811124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.811177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.811228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.811276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.811323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.811370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.811416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.811459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.811502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.811545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.811588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.811629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.811678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.811779] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.811837] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.811889] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.811954] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.812007] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.815223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.815283] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.815335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.815388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.816638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.816697] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.816999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.818020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.818073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.818123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.819100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.819262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.820477] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.822921] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  332.824380] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.824465] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.824517] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.824584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.841363] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.841441] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.841558] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.842388] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.842445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.842504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.842568] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.842618] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.842670] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.842722] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.842831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.842885] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.842938] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.842988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.843003] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.843047] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.843059] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.843107] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.843153] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.843201] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.843248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.843297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.843354] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.843399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.843449] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.843496] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.843543] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.843587] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.843670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.843769] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.843844] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.858188] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.858263] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.858704] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.875678] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.875782] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.875893] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.876098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.876155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.876210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.876261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.876308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.876352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.876394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.876440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.876482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.876522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.876564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.876606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.876646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.876686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.877865] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.877925] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.877977] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.878027] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.878097] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.878143] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.878188] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.878250] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.878306] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.878362] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.878414] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.878466] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.878511] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.878551] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.880077] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.880641] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.880696] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.881158] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.881223] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.881273] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.881328] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.881382] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.881432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.881481] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.881526] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.881569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.881579] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.881621] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.882496] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.882547] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.882595] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.882641] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.882686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.883190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.883269] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.883318] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.883367] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.883412] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.883457] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.883499] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.883570] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.883630] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.883680] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.884497] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.884536] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.885065] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.885438] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.885502] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.885591] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.885632] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.885699] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.886346] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.886405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.886461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.886514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.886561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.886608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.886653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.886699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.887307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.887356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.887403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.887448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.887492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.887534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.887583] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.887637] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.887688] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.888431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.888495] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.888545] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.892167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.892225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.892274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.892326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.893661] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.893714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.894038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.895028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.895081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.895129] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.896121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.896176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.897435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.899873] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  332.901331] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.901423] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.901475] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.901543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.918322] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.918401] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.918518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.919342] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.919399] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.919458] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.919521] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.919571] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.919623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.919674] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.919783] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.919837] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.919893] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.919950] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.919963] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.920010] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.920024] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.920073] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.920122] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.920172] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.920218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.920265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.920321] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.920368] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.920435] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.920504] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.920571] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.920636] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.920741] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.920876] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.920959] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.935144] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  332.935219] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  332.935658] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  332.952729] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  332.952836] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  332.952946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.953234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.953290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.953345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.953396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.953443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.953487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.953530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.953576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.953619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.953659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.953700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.953821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.953872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.953918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.953969] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.954028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.954082] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.954137] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.954219] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  332.954287] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  332.954364] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  332.954463] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  332.954548] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.954626] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.954705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.954860] [drm:intel_power_well_disable [i915]] disabling DC off
>[  332.954940] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  332.955008] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  332.955490] [drm:intel_power_well_disable [i915]] disabling always-on
>[  332.956286] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.956341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.956398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.956460] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.956509] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.956561] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.956612] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.956660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.956708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.956812] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.956869] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.956886] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.956931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.956943] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.956991] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.957037] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.957087] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.957134] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.957185] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.957241] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.957290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.957340] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.957391] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.957435] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.957481] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.957565] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  332.957650] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.957727] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.958019] [drm:intel_power_well_enable [i915]] enabling always-on
>[  332.958081] [drm:intel_power_well_enable [i915]] enabling DC off
>[  332.958409] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  332.958502] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.958568] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  332.958637] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  332.958681] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  332.958792] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  332.961065] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  332.961132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  332.961194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  332.961249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  332.961299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  332.961348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  332.961395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  332.961444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  332.961490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  332.961535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  332.961579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  332.961623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  332.961666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  332.961710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  332.962765] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  332.962826] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.962880] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  332.962932] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  332.962994] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  332.963045] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.966625] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.966683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.967053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.967130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.968351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  332.968404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  332.968455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.969712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  332.969805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  332.969854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  332.970714] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.971156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.972406] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.974805] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  332.976452] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.976533] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  332.976584] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  332.976650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  332.993429] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  332.993508] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  332.993623] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  332.994680] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  332.994770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.994830] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  332.994893] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  332.994942] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  332.994995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.995046] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  332.995096] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.995144] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  332.995191] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  332.995234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.995243] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.995284] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.995291] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  332.995335] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  332.995377] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  332.995419] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.995460] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.995501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.995553] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.995595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.995639] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  332.995680] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  332.997202] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  332.997251] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  332.997325] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  332.997385] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  332.997436] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.010174] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.010245] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.010633] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.028853] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.028918] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.029026] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.031370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.031436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.031497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.031552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.031603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.031652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.031699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.032335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.032384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.032429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.032475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.032518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.032561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.032603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.032652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.032706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.033351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.033406] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.033475] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.033521] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.033566] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.033627] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.033684] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.034245] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.034302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.034356] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.034402] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.034442] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.035556] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.036309] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.036364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.036423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.036485] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.036534] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.036587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.036639] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.036687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.037441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.037491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.037539] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.037547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.037594] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.037601] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.037647] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.037691] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.038396] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.038445] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.038491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.038546] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.038593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.038641] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.038686] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.039256] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.039304] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.039379] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.039438] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.039488] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.039647] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.039686] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.040520] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.040581] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.040631] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.041059] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.041114] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.041183] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.041433] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.041489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.041545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.041597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.041644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.041689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.042421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.042475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.042524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.042570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.042616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.042660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.042703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.043291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.043343] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.043401] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.043454] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.043505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.043566] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.043616] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.047252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.047311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.047363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.047417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.048359] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.048411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.048458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.049432] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.049483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.049531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.050676] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.050774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.052048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.054474] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  333.056061] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.056141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.056191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.056259] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.073015] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.073094] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.073209] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.074147] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.074203] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.074261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.074324] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.074373] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.074427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.074480] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.074528] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.074575] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.074620] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.074664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.074672] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.074716] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.075452] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.075511] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.075562] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.075612] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.075661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.075708] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.076148] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.076199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.076249] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.076296] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.076340] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.076384] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.076458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.076517] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.076567] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.089837] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.089909] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.090297] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.106660] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.106728] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.107183] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.107395] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.107452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.107508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.107560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.107607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.107653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.107697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.108341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.108390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.108435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.108480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.108524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.108568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.108610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.108657] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.108712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.109352] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.109406] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.109474] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.109520] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.109565] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.109626] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.109685] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.110243] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.110300] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.110354] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.110401] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.110441] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.111576] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.112419] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.112475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.112533] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.112596] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.112646] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.112699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.113313] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.113364] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.113412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.113457] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.113500] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.113508] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.113550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.113557] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.113601] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.113645] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.113687] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.114446] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.114494] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.114548] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.114595] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.114644] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.114689] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.115226] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.115273] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.115345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.115404] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.115455] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.115614] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.115653] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.116661] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.117163] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.117228] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.117332] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.117395] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.117463] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.119715] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.119832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.119893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.119949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.120000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.120049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.120096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.120145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.120191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.120235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.120279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.120324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.120369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.120413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.120464] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.120522] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.120577] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.120630] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.120693] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.121893] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.125471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.125531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.125582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.125634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.126571] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.126623] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.126670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.127663] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.127715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.127834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.128742] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.128860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.130131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.132526] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  333.134060] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.134146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.134197] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.134263] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.151046] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.151125] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.151240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.152103] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.152164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.152222] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.152284] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.152334] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.152386] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.152437] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.152485] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.152532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.152576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.152619] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.152627] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.152669] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.152676] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.152962] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.153032] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.153101] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.153168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.153234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.153301] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.153347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.153394] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.153439] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.153481] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.153524] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.153593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.153653] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.153705] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.167839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.167910] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.168299] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.184659] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.184724] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.185207] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.185465] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.185527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.185584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.185636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.185683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.186297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.186348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.186399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.186445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.186489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.186531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.186574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.186616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.186657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.186706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.187257] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.187313] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.187367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.187442] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.187513] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.187585] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.187684] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.188350] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.188409] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.188465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.188519] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.188565] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.188605] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.189826] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.190413] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.190466] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.190525] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.190586] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.190634] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.190685] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.191343] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.191395] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.191444] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.191488] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.191531] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.191539] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.191581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.191588] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.191632] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.191675] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.192392] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.192440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.192484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.192537] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.192583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.192630] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.192674] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.193248] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.193294] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.193367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.193426] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.193476] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.193634] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.193674] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.194635] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.194695] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.194968] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.195071] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.195119] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.195187] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.197579] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.197645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.197707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.198159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.198214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.198263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.198310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.198357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.198400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.198443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.198485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.198526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.198567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.198607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.198656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.198710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.199580] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.199635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.199698] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.200052] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.203647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.203704] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.204083] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.204150] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.205352] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.205405] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.205454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.206725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.206821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.206871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.207877] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.207957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.209179] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.211573] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  333.213089] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.213168] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.213218] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.213285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.230065] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.230144] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.230259] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.231247] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.231303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.231361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.231423] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.231473] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.231526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.231578] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.231626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.231674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.232358] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.232431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.232445] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.232516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.232528] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.232599] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.232668] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.232737] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.233336] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.233384] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.233439] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.233487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.233537] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.233583] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.233627] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.233669] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.234292] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.234381] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.234459] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.246861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.246932] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.247320] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.263649] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.263718] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.264076] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.268479] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.268545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.268607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.268663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.268713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.269244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.269297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.269349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.269397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.269443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.269489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.269533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.269578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.269621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.269671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.270229] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.270289] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.270345] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.270418] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.270468] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.270518] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.270582] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.270639] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.270695] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.271234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.271290] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.271340] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.271383] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.272889] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.273492] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.273547] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.273608] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.273673] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.274035] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.274096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.274154] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.274206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.274258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.274306] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.274354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.274363] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.274411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.274418] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.274466] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.274511] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.274557] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.274600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.274644] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.274698] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.275605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.275657] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.275705] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.275988] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.276036] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.276112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.276177] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.276231] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.276397] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.276439] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.277158] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.277491] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.277541] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.277643] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.277685] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.278063] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.280383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.280450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.280510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.280565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.280615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.280663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.280710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.281238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.281287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.281335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.281381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.281428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.281474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.281518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.281570] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.281628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.281683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.282259] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.282328] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.282383] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.286031] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.286089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.286141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.286195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.287439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.287492] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.287544] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.288813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.288865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.288913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.290082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.290137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.291424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.293813] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  333.295266] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.295349] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.295401] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.295467] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.312248] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.312329] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.312445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.313319] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.313380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.313443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.313509] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.313561] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.313615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.313671] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.313722] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.314260] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.314311] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.314360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.314369] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.314417] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.314425] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.314473] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.314519] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.314566] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.314611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.314657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.314713] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.315404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.315456] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.315505] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.315551] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.315595] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.315668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.316164] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.316221] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.328997] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.329068] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.329457] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.345811] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.345878] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.345986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.346231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.346287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.346342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.346394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.346442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.346486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.346529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.346575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.346617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.346659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.346701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.347503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.347550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.347595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.347645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.347701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.348057] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.348109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.348180] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.348225] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.348271] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.348332] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.348389] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.348444] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.348498] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.348550] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.348595] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.348635] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.349956] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.350653] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.350707] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.351002] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.351065] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.351116] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.351172] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.351227] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.351278] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.351327] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.351374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.351418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.351428] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.351472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.351480] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.351526] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.351569] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.351612] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.351654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.351696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.352640] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.352689] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.352927] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.352976] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.353023] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.353067] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.353139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.353200] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.353250] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.353409] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.353448] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.354242] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.354580] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.354628] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.354726] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.355046] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.355113] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.355291] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.355348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.355403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.355455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.355503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.355549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.355595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.355641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.355685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.356303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.356350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.356396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.356440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.356483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.356532] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.356587] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.356638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.356686] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.357210] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.357261] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.360809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.360862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.360912] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.360962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.362128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.362180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.362228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.363330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.363383] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.363431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.364306] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.364357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.365547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.368030] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  333.369467] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.369547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.369599] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.369667] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.386441] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.386518] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.386633] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.387442] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.387500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.387564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.387630] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.387683] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.387887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.387945] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.388002] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.388053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.388106] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.388152] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.388165] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.388210] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.388218] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.388265] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.388316] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.388362] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.388410] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.388454] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.388513] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.388557] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.388606] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.388653] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.388699] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.388932] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.389007] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.389071] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.389126] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.403196] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.403267] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.403654] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.421852] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.421922] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.422030] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.424281] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.424346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.424406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.424460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.424510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.424559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.424606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.424653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.424699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.424951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.424999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.425046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.425093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.425139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.425192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.425252] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.425308] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.425362] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.425435] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.425485] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.425535] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.425602] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.425663] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.425720] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.425944] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.426004] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.426055] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.426101] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.426557] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.427244] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.427300] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.427361] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.427427] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.427478] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.427533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.427588] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.427639] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.427689] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.427900] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.427948] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.427963] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.428008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.428016] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.428063] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.428114] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.428159] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.428209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.428252] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.428311] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.428356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.428407] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.428451] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.428601] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.428646] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.428719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.428953] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.429009] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.429176] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.429221] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.429527] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.429593] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.429648] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.429897] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.429939] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.430006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.430262] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.430321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.430375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.430430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.430476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.430526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.430570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.430619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.430662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.430706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.430923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.430968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.431012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.431055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.431105] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.431161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.431212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.431264] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.431324] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.431376] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.435048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.435106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.435157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.435209] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.436244] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.436296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.436344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.437346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.437398] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.437445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.438392] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.438444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.439691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.442103] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  333.443432] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.443520] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.443569] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.443636] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.460424] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.460502] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.460619] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.461355] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.461412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.461475] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.461542] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.461594] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.461649] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.461704] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.461816] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.461882] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.461938] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.461987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.462002] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.462056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.462065] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.462122] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.462171] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.462223] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.462271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.462323] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.462381] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.462434] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.462485] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.462537] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.462584] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.462634] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.462708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.462803] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.462859] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.477243] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.477319] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.477905] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.494690] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.494814] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.494923] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.497272] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.497339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.497403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.497458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.497507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.497556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.497604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.497653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.497697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.497960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.498013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.498065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.498116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.498169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.498226] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.498286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.498344] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.498397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.498479] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.498531] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.498583] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.498649] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.498711] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.498933] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.498990] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.499049] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.499101] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.499147] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.499602] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.500346] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.500401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.500462] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.500528] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.500580] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.500635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.500690] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.500888] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.500940] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.500992] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.501041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.501055] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.501103] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.501110] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.501157] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.501207] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.501253] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.501303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.501347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.501406] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.501452] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.501504] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.501549] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.501597] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.501640] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.501719] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.501961] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.502018] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.502192] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.502234] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.502542] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.502607] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.502661] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.502909] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.502953] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.503019] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.503280] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.503337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.503392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.503444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.503492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.503539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.503585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.503633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.503676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.503888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.503933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.503976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.504019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.504061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.504111] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.504166] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.504218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.504269] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.504331] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.504380] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.508166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.508225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.508276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.508329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.509405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.509457] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.509506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.510657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.510710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.510958] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.511955] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.512010] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.513410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.515799] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  333.517237] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.517322] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.517371] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.517437] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.534224] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.534302] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.534419] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.535383] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.535441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.535503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.535570] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.535623] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.535679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.536136] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.536191] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.536246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.536295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.536343] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.536353] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.536402] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.536409] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.536460] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.536506] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.536553] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.536598] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.536645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.536700] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.537458] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.537510] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.537559] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.537604] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.537649] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.537723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.538330] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.538384] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.551046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.551121] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.551562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.567809] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.567877] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.567987] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.568233] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.568290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.568346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.568398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.568444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.568489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.568533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.568578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.568620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.568662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.568704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.569613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.569661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.569707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.569981] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.570038] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.570092] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.570142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.570215] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.570261] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.570307] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.570369] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.570427] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.570481] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.570535] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.570587] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.570633] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.570672] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.571811] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.572909] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.572965] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.573022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.573084] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.573133] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.573184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.573236] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.573283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.573330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.573373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.573415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.573424] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.573465] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.573472] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.573515] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.573557] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.573598] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.573639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.573680] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.574720] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.574916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.574969] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.575021] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.575065] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.575109] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.575181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.575241] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.575291] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.575458] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.575497] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.576338] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.576660] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.576707] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.577015] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.577059] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.577124] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.579383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.579450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.579512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.579567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.579617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.579665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.579712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.580232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.580281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.580328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.580375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.580422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.580468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.580513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.580565] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.580623] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.580677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.581249] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.581317] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.581372] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.585120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.585178] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.585230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.585282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.586183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.586233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.586279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.587157] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.587206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.587253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.588124] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.588173] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.589365] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.591776] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  333.593101] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.593184] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.593234] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.593301] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.610087] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.610165] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.610281] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.610998] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.611059] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.611122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.611191] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.611244] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.611306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.611360] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.611415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.611469] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.611520] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.611569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.611581] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.611629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.611636] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.611684] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.611775] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.611821] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.611871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.611922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.611981] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.612033] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.612083] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.612136] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.612181] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.612231] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.612307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.612373] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.612432] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.626956] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.627030] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.627470] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.643803] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.643871] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.643981] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.644230] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.644287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.644343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.644393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.644439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.644483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.644527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.644572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.644614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.644656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.644697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.644982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.645028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.645072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.645121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.645175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.645229] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.645278] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.645355] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.645404] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.645450] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.645516] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.645576] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.645628] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.645681] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.645893] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.645942] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.645984] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.646436] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.647191] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.647245] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.647411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.647475] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.647525] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.647578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.647630] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.647678] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.647872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.647921] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.647968] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.647980] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.648025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.648033] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.648077] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.648125] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.648167] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.648211] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.648253] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.648308] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.648351] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.648399] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.648442] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.648482] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.648524] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.648596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.648655] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.648708] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.649055] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.649094] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.649398] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.649459] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.649510] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.649610] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.649656] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.649719] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.652131] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.652187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.652242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.652291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.652337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.652382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.652425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.652471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.652513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.652554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.652595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.652636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.652676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.652904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.652959] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.653014] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.653068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.653117] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.653181] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.653233] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.656921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.656981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.657032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.657084] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.658081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.658135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.658185] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.659227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.659276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.659323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.660277] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.660329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.661518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.663902] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  333.665231] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.665320] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.665369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.665435] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.682225] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.682304] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.682420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.683155] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.683214] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.683276] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.683342] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.683394] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.683450] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.683506] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.683558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.683609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.683659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.683707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.683782] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.683832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.683852] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.683903] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.683957] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.684005] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.684057] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.684108] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.684168] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.684216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.684271] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.684318] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.684370] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.684415] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.684496] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.684559] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.684616] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.699045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.699119] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.699562] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.715839] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.715907] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.716018] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.718364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.718436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.718500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.718555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.718605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.718654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.718701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.718959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.719011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.719063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.719116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.719170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.719218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.719269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.719324] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.719385] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.719440] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.719496] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.719574] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.719626] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.719675] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.719913] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.719978] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.720035] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.720093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.720152] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.720201] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.720248] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.720700] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.721830] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.721887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.721949] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.722015] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.722067] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.722121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.722174] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.722226] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.722275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.722322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.722368] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.722377] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.722423] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.722430] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.722477] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.722523] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.722567] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.722611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.722655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.722710] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.722993] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.723042] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.723093] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.723138] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.723186] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.723259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.723327] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.723380] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.723556] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.723601] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.724052] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.724430] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.724479] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.724587] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.724633] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.724696] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.727187] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.727255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.727316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.727371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.727421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.727469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.727516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.727565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.727609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.727654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.727698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.727950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.727999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.728045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.728099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.728159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.728214] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.728269] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.728336] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.728392] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.732068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.732128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.732179] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.732232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.733254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.733307] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.733354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.734362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.734413] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.734460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.735496] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.735549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.736930] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.739314] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  333.740792] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.740873] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.740924] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.740991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.757807] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.757885] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.758002] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.758690] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.759072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.759135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.759204] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.759259] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.759319] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.759375] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.759428] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.759480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.759531] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.759580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.759591] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.759639] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.759646] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.759695] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.760471] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.760521] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.760568] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.760614] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.760671] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.760720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.761130] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.761179] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.761227] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.761272] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.761349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.761413] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.761467] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.774594] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.774669] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.775401] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.791777] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.791846] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.791956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.792122] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.792178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.792234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.792285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.792332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.792377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.792421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.792467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.792509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.792551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.792592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.792633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.792673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.793548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.793600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.793657] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.793708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.794025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.794095] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.794144] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.794190] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.794251] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.794308] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.794363] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.794417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.794469] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.794515] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.794555] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.795852] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.796478] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.796532] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.796589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.796651] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.796700] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.797141] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.797195] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.797246] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.797295] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.797343] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.797387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.797398] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.797441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.797448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.797495] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.797538] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.797581] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.797622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.797665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.797718] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.798563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.798613] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.798659] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.798702] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.799017] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.799090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.799150] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.799201] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.799364] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.799402] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.799703] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.800435] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.800485] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.800582] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.800625] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.800689] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.803354] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.803421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.803482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.803646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.803696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.804063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.804117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.804171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.804220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.804268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.804315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.804362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.804407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.804453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.804505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.804566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.804621] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.804675] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.805228] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.805282] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.808917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.808975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.809026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.809078] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.810009] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.810063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.810113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.811072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.811120] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.811166] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.812119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.812170] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.813355] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.815801] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  333.817206] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.817295] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.817346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.817414] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.834201] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.834281] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.834398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.835289] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.835348] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.835411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.835478] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.835532] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.835588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.835644] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.835696] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.835907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.835960] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.836012] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.836022] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.836071] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.836081] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.836130] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.836179] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.836227] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.836274] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.836321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.836377] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.836426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.836475] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.836523] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.836569] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.836615] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.836690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.836929] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.836984] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.850976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.851048] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.851437] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.867731] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.867835] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.867946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.870253] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.870318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.870382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.870436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.870486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.870534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.870581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.870631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.870676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.870927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.870978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.871025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.871074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.871120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.871174] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.871235] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.871293] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.871348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.871427] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.871478] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.871529] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.871597] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.871658] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.871715] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.871942] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.872002] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.872054] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.872100] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.872555] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.873307] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.873363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.873426] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.873492] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.873544] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.873599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.873654] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.873705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.873913] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.873965] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.874015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.874027] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.874075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.874084] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.874133] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.874181] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.874229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.874276] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.874324] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.874379] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.874427] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.874475] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.874522] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.874567] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.874613] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.874687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.874929] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.874983] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.875158] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.875200] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.875508] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.875573] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.875624] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.875884] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.875927] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.875990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.878389] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.878455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.878517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.878571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.878621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.878669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.878717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.878956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.879004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.879052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.879098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.879144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.879189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.879235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.879287] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.879346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.879404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.879457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.879524] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.879577] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.883260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.883319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.883371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.883425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.884429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.884479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.884526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.885540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.885590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.885637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.886514] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.886565] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.887786] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.890200] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  333.891536] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.891620] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.891671] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.891793] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.908519] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.908596] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.908712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.909446] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.909502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.909562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.909628] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.909681] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.909796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.909863] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.909926] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.909981] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.910044] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.910093] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.910112] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.910161] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.910172] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.910230] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.910280] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.910333] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.910382] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.910433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.910488] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.910541] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.910594] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.910648] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.910692] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.910774] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.910848] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.910909] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.910963] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.925339] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.925413] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.925959] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.942460] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  333.942528] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.942638] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.945006] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.945071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.945134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.945189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.945239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.945288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.945335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.945384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.945429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.945473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.945517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.945561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.945605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.945648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.945698] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.945844] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.945912] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.945971] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.946055] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  333.946107] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  333.946166] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.946233] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  333.946293] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.946347] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.946411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.946468] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.946518] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.946563] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.947058] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.948128] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.948183] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.948244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.948310] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.948363] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.948417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.948471] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.948521] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.948571] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.948618] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.948664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.948674] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.948774] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.948793] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.948844] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.948899] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.948947] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.949003] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.949049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.949113] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.949161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.949216] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.949264] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.949316] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.949362] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.949443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  333.949514] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.949572] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.949781] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.949823] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.950141] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.950205] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  333.950252] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  333.950325] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  333.950372] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  333.950438] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  333.950651] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  333.950711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  333.950823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  333.950885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  333.950942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  333.950992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  333.951046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  333.951096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  333.951148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  333.951196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  333.951245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  333.951293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  333.951343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  333.951389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  333.951444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  333.951513] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.951575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  333.951630] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  333.951696] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  333.951783] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  333.955368] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.955427] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.955479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.955531] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.956437] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  333.956487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  333.956534] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.957689] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  333.957771] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  333.957819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  333.958678] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.959011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  333.960379] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.962797] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  333.964198] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  333.964278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  333.964328] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  333.964396] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  333.981174] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  333.981251] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  333.981367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  333.982122] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  333.982181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.982242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  333.982307] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  333.982359] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  333.982415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.982471] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  333.982523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  333.982573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  333.982621] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  333.982667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.982676] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.982901] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.982914] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  333.982962] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  333.983011] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  333.983060] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.983106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.983152] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.983208] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.983257] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.983306] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  333.983353] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  333.983398] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  333.983443] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  333.983517] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  333.983579] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  333.983634] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  333.997964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  333.998036] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  333.998423] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.014677] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.014779] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.014888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.015092] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.015148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.015202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.015253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.015300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.015346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.015390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.015437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.015479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.015521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.015563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.015605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.015645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.015686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.015965] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.016022] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.016076] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.016125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.016195] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.016242] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.016289] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.016352] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.016410] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.016465] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.016520] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.016572] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.016618] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.016660] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.017616] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.018315] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.018367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.018425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.018486] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.018535] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.018586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.018638] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.018684] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.018886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.018934] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.018980] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.018990] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.019035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.019044] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.019089] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.019134] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.019179] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.019222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.019266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.019319] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.019364] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.019410] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.019456] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.019498] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.019542] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.019611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.019671] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.019902] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.020064] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.020104] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.020406] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.020467] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.020513] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.020618] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.020664] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.020864] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.021041] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.021096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.021150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.021200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.021247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.021292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.021335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.021379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.021421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.021461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.021500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.021540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.021581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.021620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.021667] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.021917] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.021972] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.022024] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.022082] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  334.022134] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.025715] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.025816] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.025868] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.025921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.026972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.027027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.027078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.027959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.028008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.028054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.028928] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.028979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.030176] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.032626] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  334.034075] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  334.034163] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.034212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  334.034279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.051061] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.051140] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.051255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.052059] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.052118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.052181] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.052246] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.052299] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.052354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.052409] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.052460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.052512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.052561] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.052607] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.052616] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.052662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.052669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.052717] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.052958] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.053007] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.053054] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.053102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.053160] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.053208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.053259] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.053308] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.053354] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.053396] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.053471] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.053639] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.053698] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.067834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  334.067906] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.068014] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.085252] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.085318] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.085426] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.087820] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.087887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.087950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.088003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.088052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.088100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.088147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.088195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.088239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.088283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.088327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.088371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.088414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.088457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.088508] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.088566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.088620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.088671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.088849] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.088918] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.088991] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.089086] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.089171] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.089246] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.089324] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.089405] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.089476] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.089533] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.090050] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.091350] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.091425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.091510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.091598] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.091665] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.091742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.091885] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.091962] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.092030] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.092100] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.092162] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.092178] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.092240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.092253] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.092321] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.092383] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.092448] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.092507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.092570] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.092643] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.092710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.092815] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.092876] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.092946] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.093005] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.093107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.093189] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.093263] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.093507] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.093570] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.093969] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.094435] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.094502] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.094605] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.094669] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.094819] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.095958] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.096025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.096090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.096145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.096195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.096243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.096291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.096341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.096388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.096432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.096477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.096521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.096566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.096609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.096660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.096717] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.096840] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.096894] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.096959] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  334.097012] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.100708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.100805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.100857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.100910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.101964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.102020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.102071] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.102960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.103010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.103058] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.103937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.103993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.105289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.107728] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  334.109189] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  334.109276] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.109326] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  334.109395] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.126170] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.126248] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.126365] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.127164] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.127222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.127284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.127350] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.127402] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.127458] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.127513] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.127565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.127616] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.127665] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.127711] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.127895] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.127946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.127957] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.128007] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.128054] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.128104] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.128150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.128199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.128255] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.128303] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.128353] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.128401] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.128447] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.128494] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.128568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.128630] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.128685] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.143000] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  334.143075] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.143519] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.159831] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.159899] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.160010] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.160300] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.160357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.160414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.160464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.160510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.160556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.160601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.160647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.160690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.160970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.161013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.161056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.161098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.161140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.161189] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.161245] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.161302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.161352] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.161427] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.161477] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.161525] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.161589] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.161648] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.161702] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.161924] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.161979] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.162027] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.162069] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.162536] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.163380] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.163433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.163490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.163552] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.163601] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.163654] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.163705] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.163905] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.163957] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.164005] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.164052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.164065] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.164107] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.164116] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.164161] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.164206] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.164249] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.164292] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.164334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.164387] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.164433] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.164480] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.164524] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.164568] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.164610] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.164681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.164909] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.164961] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.165130] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.165170] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.165490] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.165550] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.165597] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.165704] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.165897] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.165962] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.168251] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.168308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.168363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.168413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.168459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.168504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.168548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.168594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.168636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.168679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.168896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.168942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.168983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.169026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.169072] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.169128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.169182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.169233] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.169295] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  334.169347] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.173044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.173102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.173153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.173206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.174264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.174317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.174368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.175377] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.175428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.175475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.176494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.176548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.178041] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.180481] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  334.182052] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  334.182136] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.182187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  334.182255] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.199038] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.199116] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.199234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.200270] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.200330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.200392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.200458] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.200511] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.200568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.200624] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.200675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.201208] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.201261] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.201312] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.201322] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.201370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.201378] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.201427] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.201474] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.201521] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.201565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.201610] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.201666] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.201713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.202446] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.202496] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.202543] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.202589] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.202664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.202726] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.203155] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.215826] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  334.215898] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.216289] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.232688] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.232790] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.232899] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.233104] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.233160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.233214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.233265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.233310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.233354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.233397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.233441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.233484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.233525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.233566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.233607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.233648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.233690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.234636] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.234694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.234932] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.234984] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.235055] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.235103] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.235148] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.235210] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.235267] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.235322] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.235374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.235426] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.235471] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.235511] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.236831] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.237393] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.237446] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.237504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.237564] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.237612] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.237664] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.237716] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.238236] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.238286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.238333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.238377] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.238386] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.238429] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.238436] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.238481] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.238525] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.238568] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.238610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.238652] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.238704] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.239410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.239457] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.239502] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.239545] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.239587] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.239658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.239715] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.240226] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.240384] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.240423] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.240967] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.241395] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.241445] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.241543] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.241585] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.241650] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.246034] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.246102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.246167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.246222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.246272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.246320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.246369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.246419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.246465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.246510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.246554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.246598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.246642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.246685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.247509] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.247571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.247628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.247681] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.248008] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  334.248062] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.251651] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.251709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.252003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.252059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.253073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.253126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.253175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.254341] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.254392] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.254439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.255450] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.255505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.256819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.259263] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  334.260663] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  334.260837] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.260922] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  334.261024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.277649] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.277727] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.278092] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.278963] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.279021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.279082] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.279146] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.279196] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.279251] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.279305] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.279355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.279405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.279453] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.279499] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.279509] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.279553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.279562] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.279606] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.279651] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.279695] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.280032] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.280098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.280171] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.280238] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.280302] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.280367] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.280424] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.280486] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.280586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.280662] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.280736] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.294389] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  334.294461] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.295097] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.311561] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.311629] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.311957] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.314297] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.314363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.314424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.314479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.314528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.314577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.314624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.314673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.315503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.315555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.315602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.315648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.315692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.316300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.316355] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.316414] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.316467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.316517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.316586] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.316632] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.316677] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.317432] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.317495] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.317554] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.317609] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.317662] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.317708] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.318304] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.319807] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.320419] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.320473] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.320531] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.320593] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.320642] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.320694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.321420] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.321472] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.321521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.321568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.321612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.321620] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.321664] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.321671] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.321716] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.322565] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.322615] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.322661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.322706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.323201] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.323251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.323302] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.323350] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.323395] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.323439] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.323512] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.323569] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.323619] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.324625] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.324666] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.325258] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.325581] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.325632] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.326096] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.326141] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.326208] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.326379] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.326437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.326492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.326542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.326589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.326634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.326678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.327576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.327625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.327671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.327716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.328187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.328234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.328280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.328330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.328386] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.328437] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.328486] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.328546] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  334.328596] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.332178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.332236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.332287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.332340] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.333719] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.333821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.333872] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.334987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.335059] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.335132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.336145] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.336199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.337415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.339807] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  334.341264] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  334.341342] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.341393] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  334.341460] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.358238] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.358316] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.358431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.359239] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.359295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.359355] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.359418] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.359468] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.359519] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.359571] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.359619] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.359666] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.359710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.359847] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.359869] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.359931] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.359944] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.360009] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.360075] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.360133] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.360198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.360258] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.360332] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.360392] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.360457] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.360518] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.360578] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.360637] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.360739] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.360869] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.360939] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.375063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  334.375138] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.375578] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.391839] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.391908] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.392018] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.392269] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.392326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.392382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.392434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.392481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.392526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.392570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.392615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.392657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.392699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.393927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.393981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.394030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.394077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.394128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.394185] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.394237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.394286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.394357] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.394403] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.394448] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.394510] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.394565] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.394618] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.394669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.395919] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.395995] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.396061] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.396540] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.397327] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.397383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.397442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.397503] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.397552] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.397604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.397656] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.397704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.397822] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.397891] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.397957] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.397972] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.398039] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.398052] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.398122] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.398190] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.398250] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.398316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.398375] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.398455] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.398522] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.398593] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.398661] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.398719] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.398824] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.398923] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.399008] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.399084] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.399298] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.399355] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.399679] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.400220] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.400289] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.400425] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.400492] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.400586] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.401868] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.401929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.401986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.402039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.402088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.402136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.402182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.402229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.402272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.402314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.402354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.402395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.402435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.402475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.402522] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.402575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.402624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.402671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.402816] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  334.402891] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.406176] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.406232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.406284] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.406338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.407333] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.407386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.407435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.408442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.408495] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.408542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.409458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.409511] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.410782] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.413274] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  334.414697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  334.414815] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.414866] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  334.414934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.431703] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.431833] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.431946] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.432565] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.432619] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.432678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.433250] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.433302] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.433358] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.433412] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.433462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.433511] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.433556] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.433599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.433607] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.433649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.433656] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.433700] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.434392] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.434439] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.434486] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.434529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.434584] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.434629] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.434676] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.435128] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.435175] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.435219] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.435290] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.435348] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.435399] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.448520] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  334.448592] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.448731] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.466638] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.466706] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.467163] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.469421] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.469486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.469549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.469602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.469651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.469698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.470180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.470235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.470284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.470329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.470376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.470422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.470468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.470512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.470565] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.470623] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.470678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.471336] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.471413] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.471463] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.471512] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.471577] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.471641] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.471701] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.472150] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.472209] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.472259] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.472303] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.473301] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.474089] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.474146] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.474208] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.474273] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.474326] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.474381] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.474437] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.474488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.474540] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.474588] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.474633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.474643] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.474689] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.475407] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.475469] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.475518] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.475563] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.475609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.475652] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.475706] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.476163] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.476213] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.476259] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.476302] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.476343] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.476413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.476473] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.476523] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.476688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.477228] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.477529] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.477588] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.477629] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.478056] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.478098] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.478163] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.480428] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.480493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.480556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.480610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.480660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.480708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.481189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.481245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.481293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.481342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.481388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.481435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.481481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.481527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.481578] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.481637] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.481692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.482308] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.482374] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  334.482428] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.486063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.486123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.486175] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.486227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.487425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.487480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.487529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.488648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.488700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.489006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.489963] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.490016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.491454] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.493849] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  334.495301] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  334.495380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.495431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  334.495498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.512234] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.512307] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.512423] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.513268] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.513323] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.513382] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.513444] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.513494] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.513545] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.513598] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  334.513646] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  334.513693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.514339] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.514386] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.514396] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.514441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.514448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.514494] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.514537] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.514580] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.514620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.514663] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.514715] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.515330] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.515379] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.515425] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.515467] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  334.515510] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  334.515579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.515638] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  334.515689] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  334.529021] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  334.529090] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.529225] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  334.546625] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  334.546694] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.546970] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.547226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.547285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.547342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.547394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.547443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.547489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.547534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.547580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.547623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.547664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.547705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.547862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.547926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.547999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.548074] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.548160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.548241] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.548320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.548430] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.548504] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.548576] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.548675] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.548821] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.548912] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.548995] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.549081] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.549154] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.549218] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.549700] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.551036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.551213] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.551252] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.551554] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.551634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.551690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.551849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.551928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.552006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.552079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.552154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.552225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.552295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.552362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.552437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.552505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.552575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.552651] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.552727] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.552873] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.552948] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.553025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.553129] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  334.553212] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.553287] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.553352] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.554335] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.555011] [drm:drm_mode_addfb2] [FB:69]
>[  334.555083] [drm:drm_mode_addfb2] [FB:110]
>[  334.646884] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  334.647239] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  334.647293] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  334.647782] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  334.647791] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  334.647859] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.647875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.647892] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.647911] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.647926] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.647941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.647956] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.647971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.647984] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.647998] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.648011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.648014] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.648025] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.648027] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.648040] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.648052] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.648064] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.648075] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.648087] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.648102] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.648114] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.648126] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  334.648138] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.648150] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.648169] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.648187] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.648200] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.649274] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.649285] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.649571] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.649588] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.649599] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.649623] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.649642] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.649663] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.649948] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.649968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.649998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.650015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.650031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.650045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.650059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.650074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.650087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.650101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.650114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.650127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.650138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.650151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.650164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.650181] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.650196] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.650212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.650230] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  334.650244] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.653493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.653522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.653535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.653549] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.654204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.654219] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.654246] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.654903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.654930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.654959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.655590] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.655604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.656582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.658865] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  334.659310] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  334.659332] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.659345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  334.659364] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.676132] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.676153] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.676187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.709681] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.709834] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.709858] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.709883] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.709902] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.709922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.709944] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.709963] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.709982] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.709999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.710016] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.710020] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.710038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.710040] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.710058] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.710074] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.710090] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.710106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.710122] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.710157] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.710176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.710195] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.710213] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.710231] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.710252] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.710283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.710308] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.710330] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.726280] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  334.726324] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.726581] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  334.744927] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  334.744997] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.745108] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.745274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.745330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.745386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.745435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.745482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.745527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.745570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.745615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.745657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.745697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.746464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.746512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.746558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.746602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.746653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.746708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.747106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.747159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.747233] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.747279] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.747325] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.747388] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.747447] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.747501] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.747557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.747607] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.747653] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.747693] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.748795] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.749961] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.750015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.750074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.750135] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.750185] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.750236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.750287] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.750335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.750382] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.750426] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.750469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.750479] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.750522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.750529] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.750573] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.750616] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.750659] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.750702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.751695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.751894] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.751943] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.751995] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.752041] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.752086] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.752128] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.752199] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.752259] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.752309] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.752449] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.752488] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.753412] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.753864] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.753911] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.754016] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.754060] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.754125] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.758448] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.758514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.758576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.758631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.758679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.758918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.758968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.759020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.759067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.759113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.759158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.759204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.759249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.759293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.759345] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.759402] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.759457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.759510] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.759573] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  334.759627] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.763257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.763314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.763366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.763419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.764427] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.764479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.764526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.765541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.765591] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.765637] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.766515] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.766566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.767792] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.770205] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  334.771573] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  334.771659] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.771710] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  334.771835] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.788553] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.788633] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.788833] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.789493] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.789553] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.789614] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.789679] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.789794] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.789861] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.789922] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.789979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.790037] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.790090] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.790146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.790159] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.790209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.790224] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.790272] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.790323] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.790372] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.790421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.790469] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.790528] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.790577] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.790626] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.790674] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.790755] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.790800] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.790881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.790945] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.790998] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.805377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  334.805452] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.806123] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  334.822565] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  334.822635] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.822888] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.825266] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.825333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.825398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.825452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.825502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.825550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.825597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.825646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.825691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.826297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.826347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.826395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.826441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.826486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.826537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.826596] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.826652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.826704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.827260] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.827310] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.827359] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.827425] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.827487] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.827548] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.827607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.827661] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.827710] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.828236] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.828691] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.829729] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.829952] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.830017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.830085] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.830137] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.830194] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.830250] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.830303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.830355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.830405] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.830451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.830463] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.830508] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.830515] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.830562] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.830607] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.830653] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.830697] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.831661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.831720] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.831961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.832015] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.832065] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.832112] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.832161] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.832235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.832300] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.832354] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.832527] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.832569] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.833430] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.833880] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.833937] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.834034] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.834076] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.834141] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.834309] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.834365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.834418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.834469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.834517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.834563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.834606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.834650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.834692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.835545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.835593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.835638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.835683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.835990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.836041] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.836098] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.836151] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.836201] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.836262] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  334.836312] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.839901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.839959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.840010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.840061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.841253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.841305] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.841354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.842482] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.842534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.842582] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.843653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.843707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.845136] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.847521] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  334.849029] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  334.849108] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.849158] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  334.849226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.866003] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.866189] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.866305] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.867198] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.867257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.867318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.867385] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.867438] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.867492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.867546] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.867597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.867648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.867696] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.868311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.868320] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.868371] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.868378] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.868428] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.868476] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.868523] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.868569] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.868613] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.868668] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.868715] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.869350] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.869400] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.869449] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.869495] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.869571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.869634] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.869688] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.882800] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  334.882872] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.883260] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  334.899845] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  334.899914] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.900022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.900269] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.900324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.900379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.900431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.900478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.900523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.900567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.900612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.900655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.900697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.901454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.901502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.901547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.901591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.901640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.901697] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.902104] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.902156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.902225] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.902274] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.902319] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.902380] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.902437] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.902491] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.902545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.902593] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.902638] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.902677] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.903787] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.904909] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.904964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.905021] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.905083] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.905132] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.905184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.905236] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.905285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.905332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.905376] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.905420] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.905428] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.905471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.905478] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.905523] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.905567] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.905610] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.905651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.905692] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.906779] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.906830] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.906882] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.906929] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.906974] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.907018] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.907089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.907148] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.907198] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.907359] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.907398] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.908300] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.908621] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.908668] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.909003] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.909045] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.909109] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.909316] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.909372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.909427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.909478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.909525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.909570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.909613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.909659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.909701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.910367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.910413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.910457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.910499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.910541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.910589] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.910643] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.910693] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.911169] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.911232] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  334.911284] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.914918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.914976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.915026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.915079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.916081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.916134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.916183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.917239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.917289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.917336] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.918363] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.918414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.919606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.922045] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  334.923517] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  334.923608] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.923659] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  334.923864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  334.940509] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.940589] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.940705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.941507] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.941566] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.941630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.941696] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.941910] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.941969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.942030] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.942084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.942138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.942189] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.942238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.942249] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.942297] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.942306] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.942356] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.942404] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.942453] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.942499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.942545] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.942603] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.942652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.942700] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.942936] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.942984] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.943032] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.943108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  334.943174] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.943229] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.957326] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  334.957401] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  334.958011] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  334.974614] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  334.974683] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  334.974945] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.977161] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.977227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.977290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.977345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.977394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.977442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.977490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.977539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.977584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.977628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.977672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.977715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.977861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.977929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.978005] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.978093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.978171] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.978246] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.978358] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  334.978418] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  334.978466] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  334.978531] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  334.978588] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  334.978643] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  334.978695] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.978829] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.978899] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.978962] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.979442] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.980112] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  334.980165] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.980222] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  334.980283] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  334.980332] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  334.980383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.980434] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  334.980482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  334.980530] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  334.980574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  334.980617] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.980626] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.980669] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.980676] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  334.980813] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  334.980883] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  334.980949] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  334.981013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.981076] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.981154] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.981219] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.981285] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  334.981350] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  334.981414] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  334.981476] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  334.981580] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  334.981660] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  334.981731] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  334.981974] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.982015] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.982317] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.982376] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  334.982429] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  334.982526] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  334.982568] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  334.982631] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  334.982873] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  334.982930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  334.982986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  334.983036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  334.983084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  334.983130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  334.983175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  334.983220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  334.983265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  334.983307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  334.983350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  334.983392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  334.983435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  334.983476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  334.983526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  334.983580] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  334.983632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  334.983683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  334.983816] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  334.983886] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  334.987481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  334.987539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  334.987592] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  334.987644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  334.988648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  334.988700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  334.988840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.989723] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  334.989853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  334.989925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  334.990852] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  334.990903] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  334.992152] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  334.994594] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  334.996049] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  334.996140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  334.996191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  334.996259] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.013039] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.013121] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.013238] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.014021] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.014077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.014136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.014198] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.014248] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.014300] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.014353] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.014401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.014448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.014491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.014534] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.014542] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.014584] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.014591] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.014634] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.014675] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.014810] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.014880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.014945] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.015023] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.015091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.015163] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.015228] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.015293] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.015356] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.015459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.015544] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.015616] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.029911] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.029987] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.030427] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.046896] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.046965] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.047077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.047283] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.047340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.047397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.047448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.047496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.047541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.047584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.047629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.047672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.047713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.047880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.047943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.048006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.048073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.048145] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.048227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.048302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.048379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.048488] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.048560] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.048608] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.048672] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.048776] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.048854] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.048933] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.048988] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.049034] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.049077] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.049530] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.050258] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.050312] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.050370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.050431] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.050478] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.050531] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.050583] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.050631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.050678] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.050814] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.050886] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.050906] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.050970] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.050988] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.051058] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.051124] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.051190] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.051257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.051322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.051398] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.051465] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.051537] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.051601] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.051666] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.051731] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.051862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.051924] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.051975] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.052146] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.052187] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.052489] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.052549] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.052605] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.052707] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.052819] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.052908] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.053098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.053156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.053212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.053263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.053313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.053359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.053406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.053454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.053604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.053646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.053688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.053815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.053882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.053940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.054011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.054091] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.054165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.054237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.054322] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.054398] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.058079] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.058137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.058188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.058242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.059160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.059210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.059257] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.060160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.060209] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.060255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.061200] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.061253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.062445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.064889] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  335.066342] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.066433] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.066484] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.066552] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.083342] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.083421] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.083539] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.084353] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.084412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.084476] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.084542] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.084593] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.084652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.084707] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.085027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.085082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.085135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.085181] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.085194] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.085239] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.085248] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.085297] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.085344] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.085393] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.085438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.085484] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.085541] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.085588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.085638] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.085687] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.085905] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.085951] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.086027] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.086091] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.086147] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.100153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.100228] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.100977] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.117447] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.117517] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.117629] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.117909] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.117970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.118036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.118095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.118150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.118200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.118248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.118297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.118342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.118385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.118430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.118473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.118516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.118559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.118609] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.118664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.118715] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.118972] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.119048] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.119097] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.119143] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.119205] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.119263] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.119317] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.119372] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.119424] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.119471] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.119512] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.120469] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.121184] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.121236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.121294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.121356] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.121404] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.121455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.121506] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.121553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.121600] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.121644] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.121686] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.121861] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.121906] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.121917] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.121962] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.122007] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.122050] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.122093] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.122133] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.122188] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.122232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.122279] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.122323] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.122367] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.122407] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.122478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.122539] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.122590] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.122927] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.122966] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.123288] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.123350] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.123401] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.123505] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.123549] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.123614] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.126107] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.126175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.126239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.126295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.126345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.126394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.126440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.126489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.126535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.126580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.126624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.126669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.126714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.127017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.127074] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.127137] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.127194] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.127250] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.127317] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.127373] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.131059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.131116] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.131166] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.131218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.132400] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.132452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.132500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.133503] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.133553] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.133600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.134504] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.134556] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.135787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.138169] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  335.139607] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.139697] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.139868] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.139937] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.156606] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.156685] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.156964] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.157652] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.157709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.157926] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.157997] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.158052] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.158111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.158170] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.158227] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.158282] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.158333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.158382] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.158395] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.158443] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.158452] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.158500] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.158548] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.158596] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.158642] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.158688] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.158927] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.158976] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.159028] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.159076] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.159123] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.159166] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.159243] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.159308] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.159363] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.173342] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.173414] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.173963] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.190898] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.190965] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.191076] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.191326] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.191383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.191439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.191491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.191539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.191586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.191631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.191679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.191971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.192019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.192065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.192109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.192157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.192199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.192251] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.192308] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.192360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.192412] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.192486] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.192533] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.192580] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.192644] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.192703] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.192930] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.192984] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.193037] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.193085] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.193127] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.193579] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.194452] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.194504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.194562] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.194623] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.194672] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.194723] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.194923] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.194975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.195027] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.195072] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.195120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.195130] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.195176] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.195185] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.195231] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.195276] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.195320] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.195364] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.195406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.195460] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.195506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.195553] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.195598] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.195640] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.195681] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.195949] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.196012] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.196062] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.196231] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.196272] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.196583] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.196642] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.196692] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.196944] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.196986] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.197049] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.199360] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.199427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.199489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.199544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.199594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.199641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.199687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.199935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.199985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.200033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.200079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.200125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.200171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.200217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.200270] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.200328] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.200383] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.200437] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.200503] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.200558] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.204186] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.204244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.204295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.204348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.205394] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.205446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.205494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.206681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.206781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.206831] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.207691] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.208041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.209381] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.211819] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  335.213286] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.213365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.213415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.213482] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.230270] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.230349] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.230465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.231339] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.231398] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.231460] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.231525] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.231579] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.231633] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.231688] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.232182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.232238] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.232288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.232338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.232346] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.232394] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.232402] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.232451] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.232498] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.232545] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.232591] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.232636] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.232691] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.233430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.233481] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.233529] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.233574] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.233619] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.233692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.234127] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.234183] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.247013] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.247086] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.247475] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.263832] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.263901] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.264013] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.266270] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.266337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.266400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.266456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.266506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.266555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.266603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.266651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.266696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.267357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.267408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.267457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.267503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.267549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.267601] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.267660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.267714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.268208] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.268287] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.268336] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.268384] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.268450] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.268511] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.268568] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.268624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.268678] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.269173] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.269220] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.269684] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.270858] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.270916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.270978] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.271044] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.271096] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.271152] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.271206] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.271259] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.271310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.271359] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.271405] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.271415] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.271460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.271467] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.271514] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.271559] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.271604] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.271648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.271691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.272824] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.272878] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.272931] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.272980] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.273027] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.273073] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.273147] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.273210] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.273265] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.273435] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.273478] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.274453] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.274900] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.274958] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.275062] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.275106] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.275171] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.275378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.275436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.275491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.275543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.275590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.275635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.275680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.276341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.276388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.276433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.276476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.276519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.276561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.276602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.276650] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.276704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.277222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.277275] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.277337] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.277388] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.281023] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.281081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.281132] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.281184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.282426] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.282479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.282529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.283657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.283710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.283977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.284979] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.285031] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.286423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.288807] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  335.290340] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.290426] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.290476] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.290543] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.307326] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.307407] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.307523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.308445] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.308504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.308568] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.308633] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.308686] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.309092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.309150] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.309204] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.309256] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.309306] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.309352] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.309362] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.309408] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.309416] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.309466] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.309512] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.309557] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.309602] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.309647] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.309703] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.310513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.310566] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.310614] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.310660] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.310705] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.311095] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.311159] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.311213] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.324065] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.324136] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.324527] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.340813] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.340880] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.340992] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.345380] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.345446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.345511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.345567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.345618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.345666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.345714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.346344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.346394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.346442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.346488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.346535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.346581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.346625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.346677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.347175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.347234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.347288] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.347369] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.347418] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.347467] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.347533] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.347594] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.347652] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.347709] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.348262] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.348313] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.348357] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.349330] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.350087] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.350145] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.350206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.350273] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.350326] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.350494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.350551] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.350603] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.350654] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.350703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.351314] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.351325] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.351376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.351384] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.351435] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.351483] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.351531] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.351577] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.351623] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.351679] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.352266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.352318] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.352366] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.352411] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.352456] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.352530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.352593] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.352646] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.353322] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.353366] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.353671] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.353960] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.354017] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.354116] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.354159] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.354225] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.356527] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.356593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.356655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.356708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.357096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.357151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.357202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.357256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.357306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.357355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.357401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.357448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.357493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.357540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.357592] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.357651] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.357707] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.358385] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.358452] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.358507] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.362143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.362202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.362253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.362305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.363289] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.363342] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.363389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.364280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.364330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.364376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.365267] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.365318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.366591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.369028] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  335.370401] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.370487] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.370537] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.370604] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.387392] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.387472] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.387589] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.388193] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.388251] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.388312] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.388378] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.388430] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.388485] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.388540] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.388592] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.388643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.388690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.388797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.388820] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.388870] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.388880] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.388929] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.388976] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.389026] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.389073] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.389124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.389181] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.389231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.389282] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.389330] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.389376] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.389423] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.389497] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.389565] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.389625] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.404199] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.404270] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.404662] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.421845] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.421914] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.422022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.424286] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.424351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.424413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.424468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.424517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.424565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.424612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.424661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.424705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.425199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.425248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.425296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.425342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.425388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.425439] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.425499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.425554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.425607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.425685] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.426152] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.426201] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.426266] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.426328] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.426387] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.426445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.426498] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.426547] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.426589] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.427670] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.428845] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.428902] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.428964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.429028] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.429079] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.429133] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.429188] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.429240] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.429291] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.429340] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.429385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.429394] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.429440] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.429447] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.429494] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.429540] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.429585] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.429628] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.429671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.429724] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.430507] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.430561] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.430610] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.430656] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.430703] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.431023] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.431087] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.431144] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.431310] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.431352] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.431672] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.432289] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.432343] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.432439] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.432481] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.432545] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.432714] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.433081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.433137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.433188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.433234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.433278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.433324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.433371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.433415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.433458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.433500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.433543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.433585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.433628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.433676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.434247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.434298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.434346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.434407] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.434458] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.438134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.438192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.438244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.438296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.439298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.439350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.439398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.440290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.440339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.440385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.441280] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.441329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.442513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.444894] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  335.446256] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.446336] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.446386] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.446452] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.463242] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.463323] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.463440] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.464119] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.464178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.464240] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.464304] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.464356] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.464413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.464470] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.464522] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.464574] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.464623] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.464671] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.464681] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.464788] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.464816] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.464868] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.464917] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.464968] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.465026] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.465074] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.465139] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.465187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.465246] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.465294] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.465346] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.465392] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.465476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.465543] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.465601] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.480054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.480128] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.480519] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.496844] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.496912] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.497024] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.499413] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.499479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.499542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.499598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.499648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.499697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.499814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.499878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.499937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.499989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.500041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.500097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.500151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.500198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.500260] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.500327] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.500389] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.501031] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.501113] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.501164] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.501213] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.501280] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.501344] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.501405] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.501462] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.501517] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.501567] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.501611] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.502123] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.503135] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.503190] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.503252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.503318] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.503372] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.503426] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.503480] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.503531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.503581] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.503628] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.503673] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.503706] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.503753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.503766] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.503818] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.503870] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.503917] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.503971] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.504016] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.504083] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.504130] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.504190] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.504237] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.504287] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.504332] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.504412] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.504482] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.504545] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.504752] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.504796] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.505112] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.505174] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.505230] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.505327] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.505373] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.505438] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.505648] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.505706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.505800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.505856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.505902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.505946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.505991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.506047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.506093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.506144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.506188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.506235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.506279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.506329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.506379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.506438] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.506490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.506540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.506606] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.506793] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.510378] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.510435] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.510486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.510539] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.511680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.511763] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.511813] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.512678] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.512948] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.513000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.513980] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.514035] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.515382] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.517816] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  335.519245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.519324] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.519375] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.519442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.536225] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.536304] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.536421] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.537196] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.537255] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.537319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.537387] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.537441] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.537498] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.537554] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.537607] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.537660] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.537710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.538292] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.538301] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.538349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.538356] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.538406] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.538453] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.538498] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.538543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.538588] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.538642] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.538687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.539183] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.539236] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.539283] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.539330] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.539408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.539472] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.539525] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.553073] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.553148] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.553700] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.570809] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.570878] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.570990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.573204] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.573271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.573334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.573390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.573440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.573487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.573533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.573582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.573628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.573672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.573716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.574277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.574330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.574377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.574431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.574492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.574547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.574600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.574683] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.575093] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.575145] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.575211] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.575273] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.575332] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.575389] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.575444] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.575495] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.575539] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.576631] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.577382] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.577441] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.577502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.577567] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.577618] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.577674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.578020] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.578075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.578127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.578177] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.578224] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.578236] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.578281] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.578289] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.578336] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.578383] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.578428] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.578473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.578517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.578574] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.578620] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.578668] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.578713] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.579396] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.579444] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.579522] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.579588] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.579642] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.580052] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.580096] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.580399] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.580462] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.580516] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.580614] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.580655] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.580719] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.585565] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.585631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.585694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.585994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.586050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.586100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.586150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.586199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.586247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.586294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.586340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.586386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.586432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.586477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.586528] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.586586] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.586640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.586694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.587320] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.587372] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.591026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.591083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.591134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.591186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.592645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.592700] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.593084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.594007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.594058] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.594108] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.595307] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.595361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.596557] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.598989] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  335.600565] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.600649] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.600699] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.601004] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.617553] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.617632] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.617982] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.618545] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.618602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.618663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.618730] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.619212] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.619271] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.619327] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.619380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.619431] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.619479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.619527] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.619535] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.619581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.619588] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.619635] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.619680] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.620368] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.620416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.620462] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.620518] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.620565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.620614] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.620660] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.620704] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.621207] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.621283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.621344] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.621397] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.634368] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.634440] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.635108] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.651740] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.651848] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.651959] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.652207] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.652264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.652322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.652373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.652420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.652466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.652511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.652557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.652600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.652642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.652684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.653554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.653601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.653646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.653695] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.654031] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.654084] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.654134] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.654206] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.654252] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.654297] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.654360] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.654416] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.654470] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.654521] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.654572] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.654618] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.654657] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.656029] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.656617] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.656670] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.656728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.657090] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.657140] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.657194] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.657246] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.657295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.657343] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.657387] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.657431] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.657441] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.657483] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.657490] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.657535] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.657578] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.657619] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.657660] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.657701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.658540] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.658589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.658639] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.658685] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.659007] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.659051] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.659123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.659183] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.659234] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.659398] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.659437] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.660217] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.660557] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.660603] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.660707] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.661034] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.661099] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.665422] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.665486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.665546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.665598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.665647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.665693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.666171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.666222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.666268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.666313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.666357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.666401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.666443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.666485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.666534] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.666588] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.666640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.666690] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.667344] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.667397] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.671060] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.671119] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.671170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.671223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.672448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.672500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.672551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.673659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.673710] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.673973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.674968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.675023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.676435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.678924] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  335.680399] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.680480] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.680530] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.680597] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.714624] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.714704] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.714902] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.715400] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.715440] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.715482] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.715529] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.715566] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.715604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.715642] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.715677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.715754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.715790] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.715826] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.715840] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.715873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.715879] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.715913] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.715948] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.715983] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.716016] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.716048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.716090] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.716124] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.716158] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.716191] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.716224] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.716256] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.716310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.716352] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.716390] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.730813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.730863] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.731133] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.747706] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.747784] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.747863] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.750075] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.750140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.750198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.750248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.750294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.750338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.750380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.750425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.750466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.750506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.750546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.750586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.750625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.750663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.750709] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.751523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.751576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.751626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.751698] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.751981] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.752026] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.752086] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.752142] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.752196] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.752248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.752297] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.752340] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.752378] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.753495] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.754186] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.754236] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.754291] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.754351] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.754399] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.754449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.754498] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.754545] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.754590] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.754634] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.754677] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.755206] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.755254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.755263] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.755311] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.755356] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.755399] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.755442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.755483] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.755535] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.755579] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.755623] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.755665] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.755705] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.756339] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.756407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.756465] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.756513] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.757020] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.757059] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.757358] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.757414] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.757458] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.757550] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.757588] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.757648] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.760342] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.760403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.760460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.760509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.760554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.760597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.760639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.760684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.761201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.761247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.761292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.761334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.761375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.761416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.761463] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.761515] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.761564] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.761611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.761669] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.761716] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.765879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.765932] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.765978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.766025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.767134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.767182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.767227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.768460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.768508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.768552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.769805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.769855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.771363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.773799] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  335.775197] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.775271] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.775316] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.775376] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.792179] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.792251] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.792357] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.792911] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.792963] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.793022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.793087] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.793134] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.793186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.793237] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.793285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.793332] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.793376] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.793418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.793429] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.793470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.793477] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.793522] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.793562] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.793603] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.793643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.793682] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.793797] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.793843] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.793890] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.793929] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.793969] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.794006] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.794073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.794129] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.794174] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.808964] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.809036] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.809147] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.827622] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.827689] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.827860] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.828457] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.828514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.828569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.828621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.828666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.828711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.828810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.828861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.828908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.828951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.828995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.829040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.829083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.829126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.829175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.829231] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.829283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.829335] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.829408] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.829456] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.829503] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.829567] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.829624] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.829675] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.829800] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.829858] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.829905] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.829948] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.830403] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.831066] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.831117] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.831173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.831234] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.831282] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.831333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.831384] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.831432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.831480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.831525] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.831568] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.831576] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.831617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.831624] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.831668] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.831710] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.831805] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.831850] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.831890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.831946] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.831991] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.832038] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.832080] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.832123] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.832164] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.832236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.832295] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.832348] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.832511] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.832551] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.832903] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.832962] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.833006] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.833075] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.833119] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.833186] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.835424] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.835493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.835556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.835611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.835660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.835707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.835843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.835899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.835951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.836000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.836049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.836099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.836146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.836195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.836249] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.836312] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.836372] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.836427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.836495] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.836549] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.840264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.840322] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.840373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.840426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.841441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.841491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.841537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.842454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.842503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.842548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.843461] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.843512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.844788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.847181] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  335.848577] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.848667] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.848717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.848886] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.865587] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.865666] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.865901] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.866506] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.866560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.866618] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.866681] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.866823] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.866902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.866982] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.867057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.867129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.867195] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.867263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.867279] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.867345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.867359] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.867430] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.867476] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.867522] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.867562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.867604] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.867659] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.867703] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.867818] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.867884] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.867950] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.868013] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.868121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.868184] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.868840] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.882355] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.882427] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.882535] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.899845] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.899911] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.900018] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.900267] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.900323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.900379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.900430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.900476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.900520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.900563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.900608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.900649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.900691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.900810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.900858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.900903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.900944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.900995] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.901052] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.901105] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.901156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.901230] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.901278] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.901325] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.901389] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.901446] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.901500] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.901554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.901606] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.901653] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.901695] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.902182] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.902856] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.902909] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.902965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.903025] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.903075] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.903126] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.903177] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.903224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.903271] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.903316] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.903359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.903367] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.903410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.903417] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.903461] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.903503] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.903544] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.903585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.903625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.903676] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.903770] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.903820] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.903867] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.903910] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.903954] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.904025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.904086] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.904139] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.904304] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.904342] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.904653] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.904767] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.904816] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.904887] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.904930] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.904993] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.905239] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.905296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.905351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.905402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.905452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.905497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.905544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.905591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.905637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.905680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.905782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.905827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.905869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.905914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.905964] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.906019] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.906073] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.906126] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.906189] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.906243] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.909745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.909853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.909903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.909954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.910958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.911012] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.911060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.911946] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.911995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.912040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.912947] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.912999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.914324] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.916811] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  335.918334] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.918421] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.918473] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.918539] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  335.935321] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.935400] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.935518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.936284] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.936341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.936399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.936460] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.936509] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.936560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.936611] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.936660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.936707] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.936846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.936922] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.936937] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.937006] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.937021] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.937091] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.937156] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.937225] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.937287] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.937355] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.937428] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.937496] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.937560] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.937630] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.937690] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.937800] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.937902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  335.937979] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.938054] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.952061] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  335.952133] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  335.952521] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  335.968699] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  335.968816] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  335.968925] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.969129] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.969185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.969240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.969291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.969338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.969382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.969425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.969469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.969511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.969553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.969594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.969635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.969676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.969815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.969897] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.969979] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.970058] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.970130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.970239] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  335.970880] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  335.970938] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  335.971007] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  335.971081] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  335.971147] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  335.971213] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.971270] [drm:intel_power_well_disable [i915]] disabling DC off
>[  335.971321] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  335.971366] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  335.971906] [drm:intel_power_well_disable [i915]] disabling always-on
>[  335.972930] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  335.972987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  335.973049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  335.973115] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  335.973169] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  335.973224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  335.973279] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  335.973332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  335.973384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  335.973433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  335.973481] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  335.973491] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.973536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  335.973545] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  335.973592] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  335.973639] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  335.973686] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  335.973791] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  335.973838] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  335.973901] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  335.973948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  335.973999] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  335.974050] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  335.974097] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  335.974144] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  335.974218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  335.974281] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  335.974336] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  335.974542] [drm:intel_power_well_enable [i915]] enabling always-on
>[  335.974588] [drm:intel_power_well_enable [i915]] enabling DC off
>[  335.974950] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  335.975016] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  335.975063] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  335.975136] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  335.975184] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  335.975251] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  335.975482] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  335.975541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  335.975603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  335.975657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  335.975708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  335.975816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  335.975865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  335.975919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  335.975966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  335.976016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  335.976062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  335.976111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  335.976156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  335.976204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  335.976256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  335.976314] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  335.976365] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  335.976423] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  335.976485] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  335.976541] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  335.980179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.980236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.980288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.980341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.981299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  335.981352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  335.981399] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.982298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  335.982348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  335.982395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  335.983284] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.983334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  335.984522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.986903] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  335.988256] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  335.988340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  335.988389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  335.988455] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.005255] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.005335] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.005449] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.006097] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.006152] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.006217] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.006283] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.006336] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.006393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.006448] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.006500] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.006552] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.006601] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.006648] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.006662] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.006708] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.006769] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.006823] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.006876] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.006921] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.006966] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.007013] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.007072] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.007121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.007172] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.007218] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.007263] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.007312] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.007389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.007453] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.007509] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.021996] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.022068] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.022177] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.039422] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.039489] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.039596] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.039946] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.040006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.040067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.040121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.040172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.040220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.040269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.040317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.040364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.040409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.040455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.040499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.040543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.040585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.040636] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.040692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.040795] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.040847] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.040920] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.040967] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.041014] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.041077] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.041133] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.041187] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.041240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.041292] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.041340] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.041380] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.041881] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.042892] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.042944] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.043004] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.043067] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.043117] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.043170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.043223] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.043271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.043318] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.043365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.043408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.043416] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.043461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.043469] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.043513] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.043557] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.043598] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.043639] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.043681] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.043781] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.043825] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.043877] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.043921] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.043965] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.044009] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.044078] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.044140] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.044192] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.044356] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.044395] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.044699] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.044806] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.044848] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.044922] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.044963] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.045026] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.045275] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.045331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.045385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.045439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.045486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.045533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.045577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.045625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.045669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.045714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.045814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.045859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.045903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.045946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.045998] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.046055] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.046108] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.046160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.046225] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.046276] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.049917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.049977] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.050029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.050082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.051095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.051146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.051194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.052353] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.052413] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.052464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.053878] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.053936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.055420] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.057817] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  336.059443] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.059530] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.059582] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.059650] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.076400] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.076480] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.076598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.077659] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.077715] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.078123] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.078189] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.078240] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.078296] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.078349] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.078399] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.078449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.078496] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.078540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.078550] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.078593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.078600] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.078644] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.078686] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.079282] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.079349] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.079420] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.079494] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.079563] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.079630] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.079701] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.080214] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.080280] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.080388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.080469] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.080543] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.093167] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.093239] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.093628] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.111830] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.111898] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.112008] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.114381] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.114448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.114512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.114568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.114619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.114667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.114715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.115339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.115405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.115474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.115535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.115601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.115662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.115727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.116287] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.116345] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.116397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.116446] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.116522] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.116567] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.116613] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.116675] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.117234] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.117313] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.117395] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.117477] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.117550] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.117609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.118694] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.119347] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.119402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.119461] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.119524] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.119574] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.119626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.119679] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.120351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.120403] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.120450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.120495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.120504] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.120548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.120555] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.120600] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.120644] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.120686] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.121235] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.121300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.121382] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.121449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.121523] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.121585] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.121652] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.121712] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.122238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.122325] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.122392] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.122624] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.122663] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.123332] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.123655] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.123712] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.124197] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.124240] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.124307] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.126552] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.126620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.126680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.127173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.127227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.127277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.127324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.127370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.127415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.127458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.127501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.127543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.127585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.127626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.127674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.128265] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.128346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.128425] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.128516] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.128585] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.132267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.132327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.132378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.132431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.133454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.133508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.133557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.134823] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.134877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.134925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.136134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.136190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.137504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.139947] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  336.141510] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.141600] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.141651] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.141719] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.158505] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.158585] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.158702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.159667] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.159723] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.159902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.159999] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.160075] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.160156] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.160235] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.160310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.160384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.160455] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.160524] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.160537] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.160604] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.160616] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.160685] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.160810] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.160877] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.160949] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.161010] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.161090] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.161159] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.161223] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.161294] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.161353] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.161419] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.161526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.161610] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.161685] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.175234] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.175305] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.175693] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.192818] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.192884] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.192992] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.195256] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.195321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.195382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.195437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.195487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.195535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.195581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.195629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.195673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.196176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.196224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.196273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.196319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.196365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.196416] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.196476] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.196531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.196584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.196660] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.196709] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.197276] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.197344] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.197407] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.197467] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.197525] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.197579] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.197628] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.197671] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.198447] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.199149] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.199207] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.199269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.199334] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.199386] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.199442] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.199497] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.199548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.199599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.199647] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.199693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.200259] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.200311] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.200318] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.200371] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.200420] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.200468] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.200514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.200561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.200617] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.200664] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.200713] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.201312] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.201360] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.201407] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.201481] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.201545] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.201598] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.202105] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.202148] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.202454] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.202517] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.202568] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.202667] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.203044] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.203110] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.203372] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.203429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.203484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.203534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.203582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.203628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.203673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.204199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.204245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.204289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.204333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.204375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.204417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.204457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.204505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.204557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.204607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.204656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.204715] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.205317] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.208910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.208967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.209019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.209072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.210283] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.210336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.210385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.211464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.211516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.211563] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.212630] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.212684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.214137] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.216524] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  336.218027] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.218109] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.218161] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.218228] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.234959] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.235034] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.235145] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.236017] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.236072] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.236133] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.236195] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.236244] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.236297] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.236350] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.236400] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.236449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.236495] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.236538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.236547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.236590] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.236598] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.236644] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.236687] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.237540] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.237585] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.237630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.237684] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.237992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.238043] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.238091] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.238136] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.238180] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.238249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.238308] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.238358] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.251691] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.251800] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.252167] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.268452] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.268516] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.268622] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.268979] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.269035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.269093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.269145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.269194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.269242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.269287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.269333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.269378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.269420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.269464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.269506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.269550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.269592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.269641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.269694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.270449] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.270500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.270569] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.270615] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.270659] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.271008] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.271070] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.271126] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.271182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.271233] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.271279] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.271318] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.272956] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.273550] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.273603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.273659] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.273720] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.274092] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.274146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.274201] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.274250] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.274298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.274341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.274385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.274393] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.274436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.274444] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.274488] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.274529] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.274572] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.274614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.274655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.274706] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.275488] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.275535] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.275579] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.275620] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.275661] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.276030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.276091] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.276142] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.276299] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.276338] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.276657] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.277048] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.277105] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.277201] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.277243] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.277307] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.277472] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.277528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.277582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.277633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.277680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.278227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.278275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.278326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.278371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.278416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.278460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.278505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.278547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.278589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.278638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.278693] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.279294] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.279346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.279407] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.279457] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.283131] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.283189] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.283239] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.283292] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.284177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.284227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.284273] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.285367] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.285417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.285465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.286628] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.286683] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.288221] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.290627] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  336.292140] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.292224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.292274] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.292343] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.309127] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.309207] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.309325] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.310263] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.310322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.310384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.310450] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.310502] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.310556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.310612] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.310664] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.310714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.311260] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.311310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.311319] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.311367] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.311374] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.311422] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.311469] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.311515] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.311560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.311605] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.311661] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.311708] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.312404] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.312455] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.312503] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.312549] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.312625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.312688] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.313095] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.325892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.325963] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.326354] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.342648] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.342718] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.343064] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.345370] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.345435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.345496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.345551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.345600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.345649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.345696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.346210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.346260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.346307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.346353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.346400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.346446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.346490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.346541] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.346600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.346654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.346708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.347347] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.347397] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.347446] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.347511] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.347573] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.347633] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.347691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.348129] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.348179] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.348223] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.348693] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.349933] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.349990] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.350054] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.350120] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.350172] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.350228] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.350284] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.350335] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.350495] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.350545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.350592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.350600] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.350646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.350653] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.350701] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.351513] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.351563] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.351611] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.351657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.351713] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.352078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.352128] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.352175] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.352219] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.352263] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.352336] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.352398] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.352452] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.352615] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.352657] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.353524] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.353990] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.354041] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.354143] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.354186] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.354251] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.354458] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.354515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.354568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.354620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.354668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.354714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.355310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.355359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.355404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.355447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.355490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.355531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.355572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.355613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.355661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.355714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.356316] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.356368] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.356429] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.356480] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.360024] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.360077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.360126] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.360177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.361379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.361431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.361479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.362615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.362665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.362713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.363857] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.363910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.365273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.367653] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  336.369134] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.369211] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.369261] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.369327] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.386114] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.386193] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.386309] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.387201] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.387260] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.387322] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.387390] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.387443] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.387499] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.387554] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.387605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.387656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.387703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.388338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.388347] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.388397] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.388404] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.388454] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.388502] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.388549] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.388595] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.388639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.388695] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.389348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.389519] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.389570] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.389617] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.389662] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.390074] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.390139] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.390194] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.402907] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.402979] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.403369] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.419645] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.419712] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.420062] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.420272] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.420330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.420386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.420438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.420486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.420531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.420576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.420623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.420666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.420708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.421367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.421414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.421458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.421502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.421551] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.421607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.421657] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.421706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.422209] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.422255] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.422301] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.422362] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.422421] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.422478] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.422532] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.422582] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.422627] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.422667] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.423943] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.424543] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.424598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.424654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.424715] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.425168] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.425224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.425277] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.425326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.425373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.425418] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.425460] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.425468] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.425511] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.425518] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.425562] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.425605] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.425647] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.425689] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.426665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.426720] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.427006] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.427083] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.427143] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.427189] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.427233] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.427305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.427364] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.427414] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.427572] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.427611] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.428692] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.429046] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.429102] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.429196] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.429239] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.429303] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.431509] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.431576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.431639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.431695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.432196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.432248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.432295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.432345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.432390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.432434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.432478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.432521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.432562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.432604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.432652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.432707] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.433606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.433662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.433726] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.434089] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.437683] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.437785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.437836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.437891] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.439240] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.439293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.439342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.440561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.440613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.440660] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.441903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.441958] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.443345] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.445821] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  336.447396] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.447485] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.447535] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.447602] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.464389] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.464468] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.464583] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.465351] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.465406] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.465465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.465526] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.465576] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.465627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.465680] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.465793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.465847] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.465895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.465938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.465950] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.465994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.466003] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.466048] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.466092] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.466136] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.466180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.466224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.466277] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.466323] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.466368] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.466412] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.466455] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.466495] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.466567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.466625] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.466677] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.481202] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.481277] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.481719] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.498893] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.498960] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.499071] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.499282] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.499339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.499396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.499448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.499496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.499541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.499584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.499630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.499673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.500534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.500587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.500635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.500680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.501012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.501088] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.501163] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.501217] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.501269] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.501347] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.501394] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.501440] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.501503] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.501563] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.501619] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.501673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.502311] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.502358] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.502399] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.503404] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.504257] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.504313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.504373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.504435] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.504484] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.504536] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.504588] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.504636] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.504684] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.505333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.505396] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.505408] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.505454] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.505463] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.505508] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.505553] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.505598] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.505643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.505687] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.506298] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.506349] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.506399] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.506445] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.506489] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.506532] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.506605] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.507223] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.507275] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.507443] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.507482] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.508112] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.508470] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.508517] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.508616] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.508658] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.508723] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.509338] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.509395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.509450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.509500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.509547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.509592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.509636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.509682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.510257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.510328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.510375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.510421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.510464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.510506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.510556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.510612] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.510663] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.510714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.511318] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.511371] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.515027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.515086] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.515136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.515187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.516436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.516489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.516538] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.517664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.517717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.518004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.518989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.519047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.520476] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.522853] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  336.524451] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.524540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.524592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.524660] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.541445] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.541524] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.541640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.542650] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.542705] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.542962] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.543055] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.543130] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.543190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.543246] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.543297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.543347] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.543394] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.543440] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.543450] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.543494] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.543502] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.543547] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.543591] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.543635] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.543679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.544561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.544617] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.544665] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.544715] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.545036] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.545106] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.545170] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.545245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.545305] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.545357] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.558172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.558244] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.558354] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.575602] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.575668] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.576079] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.576295] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.576353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.576410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.576463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.576510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.576557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.576601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.576647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.576689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.577332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.577381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.577427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.577473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.577516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.577566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.577622] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.577673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.578214] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.578289] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.578337] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.578383] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.578446] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.578507] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.578565] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.578620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.578672] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.579205] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.579246] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.579697] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.580898] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.580954] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.581012] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.581074] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.581123] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.581174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.581226] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.581274] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.581321] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.581365] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.581408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.581416] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.581458] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.581465] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.581508] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.581549] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.581590] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.581630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.581670] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.581720] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.582865] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.582920] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.582969] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.583015] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.583059] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.583132] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.583193] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.583244] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.583405] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.583444] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.584301] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.584642] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.584691] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.585211] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.585278] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.585350] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.587700] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.587816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.587878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.587933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.587984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.588033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.588080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.588129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.588174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.588219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.588263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.588308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.588352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.588395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.588445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.588503] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.588557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.588609] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.588672] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.588724] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.593292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.593350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.593402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.593455] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.594875] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.594928] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.594976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.596217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.596270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.596317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.597595] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.597650] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.599032] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.601419] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  336.602910] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.602989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.603039] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.603107] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.619894] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.619973] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.620089] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.620683] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.620822] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.620891] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.620965] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.621028] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.621107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.621188] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.621266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.621342] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.621412] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.621480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.621495] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.621560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.621570] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.621618] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.621663] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.621707] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.621797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.621845] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.621904] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.621953] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.622003] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.622049] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.622095] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.622141] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.622221] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.622303] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.622378] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.636629] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.636702] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.636877] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.654214] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.654283] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.654394] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.656724] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.656825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.656890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.656945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.656996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.657045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.657092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.657141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.657186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.657230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.657274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.657319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.657364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.657408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.657459] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.657517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.657572] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.657624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.657707] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.657823] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.657877] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.657957] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.658023] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.658083] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.658145] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.658204] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.658272] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.658336] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.658873] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.660172] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.660228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.660287] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.660350] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.660399] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.660452] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.660504] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.660554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.660601] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.660646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.660690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.660754] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.660799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.660818] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.660865] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.660916] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.660966] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.661015] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.661061] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.661121] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.661166] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.661217] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.661263] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.661310] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.661356] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.661435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.661520] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.661598] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.661905] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.661969] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.662295] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.662389] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.662457] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.662527] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.662570] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.662637] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.664822] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.664880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.664934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.664985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.665033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.665078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.665122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.665167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.665209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.665250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.665291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.665331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.665371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.665412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.665459] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.665511] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.665560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.665608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.665667] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.665717] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.669357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.669415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.669467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.669520] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.670466] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.670519] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.670567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.671817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.671870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.671919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.673128] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.673183] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.674505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.676905] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  336.678480] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.678675] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.678975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.679079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.714604] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.714684] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.715173] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.715623] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.715661] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.715702] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.716034] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.716071] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.716110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.716147] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.716182] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.716215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.716247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.716279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.716284] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.716315] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.716320] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.716352] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.716382] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.716411] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.716440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.716468] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.716504] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.716533] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.716563] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.716592] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.716620] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.716648] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.716697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.717743] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.717780] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.728890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.728939] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.729015] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.746087] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.746134] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.746213] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.748564] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.748611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.748655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.748694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.749077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.749113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.749147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.749181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.749211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.749241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.749271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.749300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.749330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.749359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.749393] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.749432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.749467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.749501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.749554] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.749586] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.749617] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.749661] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.749700] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.750521] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.750562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.750599] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.750632] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.750660] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.751657] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.752190] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.752228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.752269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.752312] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.752347] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.752384] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.752420] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.752454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.752487] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.752518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.752549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.752556] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.752586] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.752590] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.752621] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.752650] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.752679] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.753468] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.753501] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.753539] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.753571] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.753604] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.753634] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.753662] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.753692] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.754170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.754214] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.754249] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.754366] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.754393] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.754696] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.755342] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.755380] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.755451] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.755480] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.755525] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.756020] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.756060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.756099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.756135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.756167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.756200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.756230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.756262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.756291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.756321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.756350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.756378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.756407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.756435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.756468] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.756504] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.756539] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.756572] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.757512] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.757548] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.761048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.761088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.761123] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.761159] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.762267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.762308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.762343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.763217] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.763254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.763287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.764241] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.764279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.765372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.767781] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  336.768886] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.768977] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.769014] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.769062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.785815] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.785871] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.785953] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.786425] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.786464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.786506] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.786552] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.786589] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.786627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.786665] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.786700] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.787268] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.787303] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.787335] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.787342] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.787373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.787377] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.787409] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.787440] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.787470] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.787499] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.787527] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.787564] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.787593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.787624] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.787653] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.787681] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.788516] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.788568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.788612] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.788648] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.802595] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.802659] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.803047] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.820312] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.820380] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.820489] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.822823] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.822889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.822954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.823008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.823059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.823107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.823154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.823203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.823248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.823292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.823336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.823380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.823424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.823467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.823518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.823575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.823628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.823679] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.824896] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.824944] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.824990] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.825053] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.825114] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.825172] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.825229] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.825279] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.825325] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.825365] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.826711] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.827363] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.827417] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.827477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.827539] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.827588] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.827640] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.827693] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.828334] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.828386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.828433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.828478] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.828488] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.828530] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.828537] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.828583] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.828628] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.828670] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.828713] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.829591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.829648] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.829697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.830045] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.830110] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.830158] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.830202] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.830274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.830335] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.830386] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.830554] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.830593] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.831516] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.832026] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.832090] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.832192] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.832257] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.832328] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.832535] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.832592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.832647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.832698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.833319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.833369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.833417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.833465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.833509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.833553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.833595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.833639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.833681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.834306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.834359] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.834415] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.834467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.834516] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.834577] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.834627] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.838261] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.838320] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.838372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.838424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.839478] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.839533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.839583] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.840713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.840812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.840861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.841728] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.841896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.843220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.845607] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  336.847137] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.847222] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.847272] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.847339] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.864120] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.864199] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.864316] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.865228] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.865285] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.865343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.865406] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.865456] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.865509] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.865562] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.865611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.865659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.865704] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.866125] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.866140] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.866210] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.866223] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.866295] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.866366] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.866437] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.866507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.866569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.866647] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.866716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.867012] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.867083] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.867145] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.867213] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.867316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.867401] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.867479] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.880996] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.881071] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.881188] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.898633] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.898702] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.899105] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.899363] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.899420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.899477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.899529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.899577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.899624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.899669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.899716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.900034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.900103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.900166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.900233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.900295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.900360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.900434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.900517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.900595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.900672] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.900958] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.901031] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.901103] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.901202] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.901291] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.901374] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.901456] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.901538] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.901612] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.901676] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.902375] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.903257] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.903311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.903370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.903432] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.903482] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.903534] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.903585] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.903634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.903682] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.903999] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.904070] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.904083] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.904144] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.904157] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.904227] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.904298] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.904368] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.904436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.904503] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.904584] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.904652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.904717] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.905029] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.905095] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.905156] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.905259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.905346] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.905424] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.905671] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.905890] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.906233] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.906324] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.906390] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.906490] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.906558] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.906650] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.907027] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.907109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.907191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.907268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.907340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.907409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.907479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.907551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.907618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.907685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.907968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.908034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.908095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.908160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.908227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.908310] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.908387] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.908463] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.908551] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.908627] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.912276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.912334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.912385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.912438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.913725] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.913821] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.913871] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.914869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.914949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.915028] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.915921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.915976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.917309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.919812] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  336.921310] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.921403] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.921454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.921522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  336.938313] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.938393] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.938510] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.939467] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.939526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.939588] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.939654] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.939706] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.940115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.940171] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.940224] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.940275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.940323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.940369] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.940379] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.940425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.940432] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.940480] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.940526] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.940571] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.940615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.940659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.940714] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.941513] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.941566] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.941614] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.941661] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.941706] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.942159] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  336.942223] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.942276] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.955037] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  336.955109] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  336.955217] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  336.972510] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  336.972577] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  336.972686] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.973284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.973343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.973400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.973453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.973502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.973550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.973595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.973641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.973685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.974238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.974285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.974329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.974373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.974414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.974462] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.974518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.974569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.974617] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.974686] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  336.975243] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  336.975290] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  336.975353] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  336.975520] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  336.975576] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  336.975631] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.975681] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.976115] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.976156] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.976607] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.977430] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  336.977484] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.977542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  336.977603] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  336.977654] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  336.977706] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.978145] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  336.978194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  336.978241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  336.978284] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  336.978327] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.978335] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.978378] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.978385] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  336.978428] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  336.978470] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  336.978511] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  336.978552] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.978592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.978644] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.978687] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.979547] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  336.979595] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  336.979640] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  336.979685] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  336.980033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  336.980093] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  336.980142] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  336.980300] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.980339] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.980640] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.980698] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  336.981149] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  336.981251] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  336.981294] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  336.981358] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  336.983699] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  336.983795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  336.983859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  336.983915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  336.983966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  336.984014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  336.984062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  336.984113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  336.984160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  336.984206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  336.984251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  336.984296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  336.984340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  336.984384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  336.984435] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  336.984494] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  336.984547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  336.984600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  336.984663] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  336.984716] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  336.989298] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  336.989356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  336.989407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  336.989458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  336.990819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  336.990873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  336.990923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.992088] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  336.992139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  336.992188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  336.993340] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  336.993394] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  336.994588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  336.997028] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  336.998540] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  336.998620] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  336.998672] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  336.998984] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.015523] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.015603] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.015719] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.016607] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.016665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.016728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.017051] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.017106] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.017163] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.017219] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.017272] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.017322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.017370] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.017416] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.017425] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.017469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.017476] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.017522] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.017566] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.017610] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.017654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.017696] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.018543] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.018596] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.018649] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.018699] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.019021] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.019069] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.019144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.019205] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.019258] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.032259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.032331] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.032437] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.049651] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.049718] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.050082] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.050261] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.050318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.050373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.050425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.050471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.050516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.050561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.050607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.050649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.050690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.051319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.051365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.051409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.051452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.051501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.051556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.051606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.051654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.052159] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.052206] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.052251] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.052312] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.052370] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.052425] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.052478] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.052529] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.052575] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.052614] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.053970] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.054552] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.054605] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.054663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.054724] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.055115] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.055170] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.055222] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.055271] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.055319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.055364] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.055407] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.055416] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.055459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.055465] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.055511] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.055554] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.055596] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.055637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.055678] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.056538] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.056589] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.056639] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.056686] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.057008] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.057053] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.057125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.057185] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.057236] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.057399] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.057437] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.058164] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.058485] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.058540] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.058631] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.058673] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.059007] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.059269] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.059325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.059380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.059431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.059479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.059525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.059570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.059616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.059659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.059700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.060319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.060365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.060409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.060451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.060499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.060555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.060605] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.060654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.060714] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.061239] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.064877] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.064934] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.064984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.065036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.066242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.066295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.066344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.067472] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.067522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.067569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.068636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.068690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.070249] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.072681] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  337.074215] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.074294] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.074345] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.074412] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.091198] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.091279] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.091394] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.092301] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.092359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.092423] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.092489] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.092542] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.092597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.092652] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.092704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.093237] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.093288] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.093337] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.093345] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.093392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.093399] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.093447] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.093494] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.093539] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.093583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.093628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.093683] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.094362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.094414] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.094464] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.094510] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.094554] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.094627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.094689] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.095220] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.107942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.108014] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.108122] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.125405] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.125474] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.125582] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.128197] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.128265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.128330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.128385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.128434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.128480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.128527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.128575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.128621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.128666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.128709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.129427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.129476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.129524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.129577] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.129637] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.129691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.130099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.130178] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.130228] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.130276] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.130342] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.130403] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.130462] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.130518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.130572] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.130622] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.130664] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.132065] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.132697] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.132960] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.133025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.133095] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.133149] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.133208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.133264] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.133318] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.133369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.133420] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.133469] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.133480] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.133527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.133535] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.133584] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.133631] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.133677] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.134580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.134630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.134686] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.134964] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.135018] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.135068] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.135115] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.135162] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.135236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.135301] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.135353] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.135526] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.135568] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.136423] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.136868] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.136921] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.137024] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.137068] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.137137] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.137347] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.137404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.137458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.137507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.137554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.137599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.137643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.137689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.138388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.138435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.138480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.138524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.138567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.138609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.138658] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.138713] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.139187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.139237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.139297] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.139348] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.142937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.142995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.143045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.143098] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.144375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.144428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.144477] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.145708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.145803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.145851] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.146714] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.147065] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.148380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.150810] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  337.152271] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.152350] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.152400] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.152466] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.169250] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.169329] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.169445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.170388] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.170447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.170510] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.170575] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.170627] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.170683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.171212] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.171267] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.171320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.171369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.171415] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.171424] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.171470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.171477] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.171525] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.171571] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.171615] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.171659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.171702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.172408] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.172464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.172521] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.172573] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.172622] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.172670] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.173102] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.173166] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.173220] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.185987] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.186059] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.186166] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.203405] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.203471] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.203578] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.203968] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.204027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.204089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.204142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.204192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.204239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.204287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.204335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.204381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.204425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.204470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.204514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.204558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.204601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.204651] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.204705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.204949] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.205000] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.205073] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.205118] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.205166] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.205228] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.205284] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.205338] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.205392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.205442] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.205487] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.205526] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.206495] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.207209] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.207261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.207317] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.207379] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.207428] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.207480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.207534] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.207582] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.207629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.207674] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.207883] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.207895] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.207943] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.207952] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.207996] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.208040] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.208086] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.208127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.208170] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.208225] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.208270] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.208318] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.208362] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.208405] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.208446] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.208518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.208578] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.208629] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.208998] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.209039] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.209360] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.209420] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.209474] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.209568] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.209611] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.209677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.212391] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.212460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.212524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.212579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.212628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.212677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.212954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.213012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.213065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.213117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.213168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.213219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.213272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.213319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.213373] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.213433] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.213490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.213545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.213614] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.213670] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.217471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.217533] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.217584] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.217638] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.218641] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.218690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.218802] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.219676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.219787] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.219843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.220708] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.220818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.222083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.224465] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  337.225951] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.226040] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.226090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.226158] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.242944] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.243025] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.243141] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.243908] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.243970] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.244035] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.244104] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.244160] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.244219] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.244277] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.244331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.244384] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.244433] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.244483] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.244499] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.244546] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.244555] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.244604] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.244651] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.244699] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.244789] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.244842] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.244905] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.244955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.245010] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.245058] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.245109] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.245158] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.245239] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.245303] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.245363] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.259678] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.259797] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.259906] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.277223] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.277291] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.277402] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.277607] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.277663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.277719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.277993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.278048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.278097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.278146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.278195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.278243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.278287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.278331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.278376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.278419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.278463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.278512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.278570] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.278622] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.278673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.278894] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.278940] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.278987] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.279051] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.279111] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.279166] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.279221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.279273] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.279320] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.279362] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.280326] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.281040] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.281095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.281152] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.281218] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.281269] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.281320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.281371] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.281418] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.281464] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.281507] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.281549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.281559] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.281601] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.281608] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.281652] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.281694] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.281933] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.281979] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.282024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.282076] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.282121] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.282169] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.282214] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.282260] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.282302] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.282374] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.282435] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.282485] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.282657] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.282696] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.283177] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.283240] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.283288] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.283396] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.283441] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.283505] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.283714] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.283922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.283979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.284033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.284080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.284128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.284173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.284221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.284265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.284310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.284353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.284397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.284440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.284484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.284532] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.284587] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.284638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.284689] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.284920] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.284971] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.288547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.288606] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.288657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.288710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.289858] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.289909] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.289957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.290948] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.291001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.291053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.291939] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.291993] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.293187] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.295624] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  337.297026] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.297114] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.297164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.297232] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.314010] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.314089] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.314205] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.314900] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.314961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.315026] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.315093] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.315150] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.315208] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.315267] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.315321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.315375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.315427] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.315477] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.315488] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.315535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.315545] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.315593] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.315640] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.315688] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.315780] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.315835] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.315892] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.315947] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.316001] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.316050] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.316099] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.316149] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.316228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.316296] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.316352] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.330867] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.330941] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.331055] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.348512] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.348580] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.348690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.353250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.353316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.353381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.353437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.353487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.353536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.353583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.353633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.353678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.353968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.354020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.354070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.354123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.354171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.354230] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.354291] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.354349] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.354404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.354489] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.354541] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.354590] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.354656] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.354718] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.354946] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.355007] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.355063] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.355114] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.355160] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.355614] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.356376] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.356432] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.356493] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.356560] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.356612] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.356667] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.356722] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.356927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.356983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.357038] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.357086] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.357098] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.357149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.357157] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.357206] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.357256] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.357304] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.357352] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.357397] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.357454] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.357502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.357553] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.357599] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.357646] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.357689] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.357975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.358040] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.358099] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.358270] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.358313] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.358632] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.358695] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.358894] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.359001] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.359046] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.359112] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.361357] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.361424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.361487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.361542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.361592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.361640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.361687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.361932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.361984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.362032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.362079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.362128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.362175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.362223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.362275] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.362337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.362394] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.362448] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.362514] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.362569] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.366360] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.366417] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.366467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.366519] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.367567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.367618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.367665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.368705] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.368799] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.368845] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.369703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.369904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.371185] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.373567] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  337.375026] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.375110] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.375160] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.375227] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.391961] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.392032] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.392142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.392978] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.393033] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.393095] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.393161] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.393212] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.393268] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.393320] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.393372] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.393420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.393468] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.393513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.393525] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.393567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.393577] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.393622] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.393667] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.393712] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.393936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.393981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.394037] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.394082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.394131] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.394174] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.394217] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.394259] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.394328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.394388] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.394440] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.408806] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.408877] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.408987] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.426362] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.426431] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.426542] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.426928] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.426990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.427054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.427107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.427158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.427205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.427254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.427301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.427346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.427390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.427434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.427476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.427519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.427562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.427610] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.427667] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.427906] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.427959] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.428037] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.428085] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.428132] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.428195] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.428254] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.428311] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.428365] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.428418] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.428466] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.428615] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.429568] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.430238] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.430290] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.430347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.430409] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.430456] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.430506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.430557] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.430605] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.430651] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.430694] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.430903] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.430916] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.430963] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.430972] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.431018] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.431066] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.431110] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.431152] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.431196] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.431247] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.431291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.431339] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.431383] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.431426] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.431468] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.431540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.431600] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.431651] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.432023] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.432064] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.432376] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.432436] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.432491] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.432590] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.432633] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.432697] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.433053] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.433109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.433164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.433214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.433263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.433306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.433351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.433395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.433438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.433480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.433522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.433563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.433605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.433645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.433693] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.433985] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.434038] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.434090] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.434152] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.434204] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.437827] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.437885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.437937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.437990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.438969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.439023] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.439077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.439962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.440013] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.440060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.440932] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.440987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.442188] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.444597] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  337.445990] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.446070] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.446121] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.446190] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.462963] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.463043] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.463159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.463882] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.463941] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.464008] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.464079] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.464133] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.464193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.464252] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.464310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.464364] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.464415] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.464466] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.464477] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.464525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.464534] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.464583] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.464632] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.464680] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.464771] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.464825] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.464883] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.464935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.464989] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.465038] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.465089] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.465139] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.465218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.465287] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.465348] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.479680] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.479788] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.479899] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.497375] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.497442] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.497554] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.497831] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.497894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.497965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.498023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.498079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.498127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.498178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.498227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.498274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.498318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.498363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.498405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.498447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.498490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.498540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.498597] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.498650] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.498701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.498824] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.498877] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.498929] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.498995] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.499053] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.499107] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.499163] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.499218] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.499265] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.499309] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.499809] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.500882] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.500935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.500994] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.501058] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.501107] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.501161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.501214] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.501264] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.501313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.501361] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.501408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.501419] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.501463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.501471] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.501516] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.501559] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.501602] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.501644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.501686] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.501782] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.501837] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.501889] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.501938] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.501989] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.502033] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.502108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.502169] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.502222] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.502393] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.502434] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.502789] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.502850] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.502906] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.503009] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.503056] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.503118] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.505405] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.505475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.505539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.505593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.505643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.505692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.505809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.505874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.505930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.505984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.506037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.506091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.506139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.506195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.506252] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.506316] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.506373] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.506434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.506502] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.506558] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.510304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.510364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.510414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.510466] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.511423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.511474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.511521] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.512414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.512463] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.512509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.513518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.513568] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.514816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.517255] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  337.518724] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.518836] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.518887] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.518956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.535740] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.535875] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.535994] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.536670] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.536728] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.536953] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.537024] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.537083] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.537143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.537204] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.537259] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.537314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.537364] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.537413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.537425] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.537472] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.537481] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.537530] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.537578] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.537626] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.537671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.537995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.538054] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.538104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.538155] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.538205] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.538251] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.538298] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.538375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.538439] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.538493] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.552553] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.552629] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.552957] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.570348] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.570416] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.570526] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.575000] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.575067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.575131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.575185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.575236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.575283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.575330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.575381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.575428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.575473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.575517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.575562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.575606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.575650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.575701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.576611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.576669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.576935] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.577016] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.577068] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.577116] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.577183] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.577246] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.577307] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.577366] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.577420] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.577469] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.577512] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.578803] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.579404] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.579460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.579522] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.579587] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.579639] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.579694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.580185] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.580239] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.580293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.580341] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.580389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.580399] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.580446] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.580454] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.580503] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.580549] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.580595] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.580640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.580685] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.581404] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.581457] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.581510] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.581559] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.581606] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.581651] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.581724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.582269] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.582326] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.582497] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.582539] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.583118] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.583442] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.583496] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.583595] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.583636] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.583701] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.584290] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.584347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.584403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.584456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.584504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.584550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.584596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.584642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.584687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.585327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.585372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.585417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.585461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.585503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.585551] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.585605] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.585655] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.585703] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.586230] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.586281] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.589921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.589980] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.590034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.590087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.591084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.591137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.591188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.592123] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.592172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.592220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.593096] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.593146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.594334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.596711] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  337.598088] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.598167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.598217] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.598284] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.615065] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.615145] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.615262] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.615985] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.616151] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.616215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.616284] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.616337] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.616398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.616454] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.616511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.616562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.616614] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.616661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.616674] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.616766] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.616773] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.616826] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.616879] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.616926] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.616980] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.617026] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.617090] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.617139] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.617191] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.617242] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.617287] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.617337] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.617411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.617473] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.617535] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.631997] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.632071] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.632189] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.649649] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.649718] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.650128] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.652340] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.652408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.652471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.652526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.652574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.652622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.652669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.652718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.653341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.653391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.653439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.653485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.653531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.653576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.653628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.653687] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.654192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.654248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.654326] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.654376] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.654425] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.654490] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.654550] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.654609] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.654665] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.655189] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.655240] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.655283] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.656240] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.657031] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.657088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.657150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.657215] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.657266] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.657322] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.657377] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.657429] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.657480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.657528] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.657573] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.657583] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.657628] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.657635] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.657681] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.658502] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.658552] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.658599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.658646] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.658701] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.659072] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.659123] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.659170] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.659216] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.659261] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.659334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.659397] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.659451] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.659620] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.659662] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.660581] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.661063] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.661118] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.661219] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.661262] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.661327] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.663667] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.663733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.664050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.664109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.664160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.664208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.664254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.664303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.664349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.664394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.664438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.664482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.664525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.664568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.664618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.664676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.665410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.665466] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.665532] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.665586] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.669170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.669228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.669280] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.669333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.670556] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.670608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.670658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.671873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.671926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.671975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.673088] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.673141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.674424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.676812] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  337.678294] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.678379] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.678429] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.678600] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.714613] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.714693] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.715068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.715506] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.715546] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.715589] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.715634] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.715670] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.715708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.716051] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.716088] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.716124] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.716158] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.716190] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.716195] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.716227] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.716232] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.716264] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.716295] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.716326] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.716356] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.716386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.716425] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.716456] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.716488] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.716519] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.716549] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.716579] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.716629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.716670] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.716707] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.728597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.728647] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.728889] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.746101] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.746150] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.746230] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.746428] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.746467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.746506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.746542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.746574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.746607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.746640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.746674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.746775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.746814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.746850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.746882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.746916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.746948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.746984] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.747027] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.747066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.747104] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.747160] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.747195] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.747227] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.747271] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.747311] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.747348] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.747385] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.747421] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.747455] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.747483] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.747972] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.748403] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.748439] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.748477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.748520] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.748554] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.748590] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.748625] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.748658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.748690] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.748760] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.748790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.748805] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.748836] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.748845] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.748877] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.748910] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.748945] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.748976] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.749008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.749046] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.749081] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.749115] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.749149] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.749181] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.749212] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.749264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.749307] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.749345] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.749469] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.749497] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.749816] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.749860] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.749895] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.749947] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.749978] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.750020] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.750419] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.750459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.750496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.750532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.750564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.750596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.750627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.750658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.750687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.750762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.750794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.750826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.750860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.750891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.750925] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.750967] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.751006] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.751044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.751088] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.751126] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.754588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.754628] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.754664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.754701] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.755614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.755649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.755681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.756546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.756581] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.756755] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.757546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.757583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.758785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.761152] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  337.762263] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.762327] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.762363] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.762410] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.779181] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.779236] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.779319] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.779986] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.780029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.780074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.780122] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.780159] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.780198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.780238] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.780275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.780311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.780345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.780378] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.780386] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.780418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.780424] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.780457] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.780490] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.780522] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.780554] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.780585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.780625] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.780657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.780691] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.780823] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.780858] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.780896] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.780952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.780998] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.781038] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.795982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.796053] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.796161] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.813424] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.813493] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.813604] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.814015] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.814074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.814136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.814189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.814236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.814282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.814328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.814375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.814419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.814462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.814502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.814543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.814584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.814625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.814674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.815274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.815326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.815377] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.815453] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.815499] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.815545] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.815607] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.815662] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.815717] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.816160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.816213] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.816260] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.816302] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.817266] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.818016] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.818069] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.818127] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.818188] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.818237] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.818288] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.818339] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.818387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.818434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.818477] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.818520] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.818530] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.818573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.818580] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.818623] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.818666] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.818708] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.819501] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.819547] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.819602] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.819648] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.819695] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.819991] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.820035] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.820077] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.820149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.820208] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.820258] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.820421] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.820459] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.821120] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.821458] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.821508] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.821609] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.821650] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.821715] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.824250] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.824316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.824377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.824431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.824479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.824527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.824575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.824622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.824667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.824710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.825230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.825281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.825329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.825377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.825430] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.825490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.825546] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.825599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.825664] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.825719] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.829726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.829824] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.829876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.829930] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.831135] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.831187] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.831236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.832294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.832345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.832394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.833418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.833472] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.834932] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.837367] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  337.838874] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.838964] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.839015] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.839083] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.855868] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.855947] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.856062] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.856706] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.857045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.857111] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.857177] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.857233] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.857289] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.857347] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.857401] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.857452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.857501] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.857548] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.857559] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.857605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.857613] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.857661] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.857708] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.858337] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.858384] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.858429] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.858485] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.858531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.858579] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.858623] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.858666] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.858709] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.859174] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.859240] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.859295] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.872691] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.872826] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.872947] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.890373] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.890441] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.890552] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.893192] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.893258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.893323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.893378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.893427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.893476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.893523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.893573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.893619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.893664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.893708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.894290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.894341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.894389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.894443] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.894506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.894564] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.894620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.894703] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.895111] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.895161] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.895227] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.895288] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.895347] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.895405] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.895459] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.895508] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.895551] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.896646] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.897501] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.897559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.897620] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.897686] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.897972] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.898032] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.898089] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.898142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.898194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.898244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.898291] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.898303] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.898351] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.898360] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.898407] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.898454] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.898501] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.898546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.898590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.898647] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.898693] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.899366] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.899415] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.899461] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.899507] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.899582] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.899646] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.899701] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.900189] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.900232] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.900538] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.900601] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.900650] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.901044] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.901087] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.901153] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.901360] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.901418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.901471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.901522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.901568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.901612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.901654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.901699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.902219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.902266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.902311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.902356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.902399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.902442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.902492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.902548] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.902598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.902648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.902708] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.903184] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.906807] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.906866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.906917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.906970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.908167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.908221] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.908274] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.909386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.909437] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.909485] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.910623] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.910677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.912141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.914549] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  337.916064] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.916144] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.916195] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.916262] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  337.932993] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.933065] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.933177] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.934081] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.934137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.934196] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.934259] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.934308] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.934361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.934413] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.934461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.934508] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.934554] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.934598] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.934606] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.934648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.934655] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.934700] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.935580] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.935625] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.935670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.935712] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.936037] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.936084] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.936132] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.936177] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.936220] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.936262] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.936331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  337.936389] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.936439] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.949920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  337.949994] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  337.950112] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  337.967517] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  337.967585] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  337.967697] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.968385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.968443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.968501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.968554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.968602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.968647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.968693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.969166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.969212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.969256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.969301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.969344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.969387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.969428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.969477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.969531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.969582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.969632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.969705] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  337.970396] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  337.970443] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  337.970505] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  337.970564] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  337.970621] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  337.970675] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.971064] [drm:intel_power_well_disable [i915]] disabling DC off
>[  337.971111] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  337.971151] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  337.971602] [drm:intel_power_well_disable [i915]] disabling always-on
>[  337.972431] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  337.972486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  337.972544] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  337.972607] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  337.972657] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  337.972710] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  337.973143] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  337.973194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  337.973241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  337.973285] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  337.973328] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  337.973338] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.973381] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  337.973388] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  337.973432] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  337.973474] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  337.973515] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  337.973556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  337.973597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  337.973649] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  337.973691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  337.974497] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:69, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  337.974543] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  337.974587] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  337.974630] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  337.974701] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  337.975084] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  337.975137] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  337.975300] [drm:intel_power_well_enable [i915]] enabling always-on
>[  337.975338] [drm:intel_power_well_enable [i915]] enabling DC off
>[  337.976083] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  337.976404] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  337.976459] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  337.976551] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  337.976593] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  337.976657] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  337.977109] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  337.977165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  337.977221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  337.977271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  337.977317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  337.977361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  337.977404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  337.977450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  337.977493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  337.977536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  337.977577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  337.977619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  337.977659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  337.977700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  337.978420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  337.978475] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  337.978526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  337.978574] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  337.978634] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  337.978684] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  337.982581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.982639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.982689] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.983040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.983991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  337.984044] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  337.984092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.985085] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  337.985135] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  337.985183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  337.986120] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.986171] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  337.987358] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.989766] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  337.991221] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  337.991301] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  337.991351] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  337.991419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.008195] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  338.008275] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  338.008390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  338.009105] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  338.009164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.009225] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  338.009291] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  338.009343] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  338.009398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.009453] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  338.009506] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  338.009556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  338.009605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.009652] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.009660] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  338.009706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.009769] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  338.009818] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  338.009873] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  338.009925] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  338.009978] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.010029] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.010085] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  338.010137] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.010190] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] FB:110, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  338.010241] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  338.010289] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  338.010339] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  338.010416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  338.010480] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  338.010535] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  338.024943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  338.025015] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  338.025124] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  338.042490] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  338.042557] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  338.042667] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  338.042976] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  338.043034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  338.043092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  338.043144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  338.043192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  338.043237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  338.043282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  338.043328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  338.043372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  338.043415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  338.043457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  338.043499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  338.043540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  338.043581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  338.043631] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  338.043686] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  338.043797] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  338.043853] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  338.043935] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  338.043987] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  338.044037] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  338.044102] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  338.044160] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  338.044214] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  338.044271] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  338.044326] [drm:intel_power_well_disable [i915]] disabling DC off
>[  338.044374] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  338.044415] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  338.044908] [drm:intel_power_well_disable [i915]] disabling always-on
>[  338.045862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.045982] [drm:intel_power_well_enable [i915]] enabling always-on
>[  338.046022] [drm:intel_power_well_enable [i915]] enabling DC off
>[  338.046324] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  338.046399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  338.046452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  338.046503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  338.046548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  338.046591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  338.046634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  338.046679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  338.046775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  338.046821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  338.046868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  338.046917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  338.046962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  338.047006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  338.047059] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  338.047109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  338.047168] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  338.047221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  338.047276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  338.047347] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  338.047399] [drm:intel_power_well_disable [i915]] disabling DC off
>[  338.047447] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  338.047487] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  338.047980] [drm:intel_power_well_disable [i915]] disabling always-on
>[  338.055973] [IGT] kms_flip: exiting, ret=0
>[  338.090624] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  338.090658] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  338.090694] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  338.090758] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.090788] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  338.090822] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.090855] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  338.090886] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  338.090917] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  338.090947] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  338.090975] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.090981] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  338.091008] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.091013] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  338.091042] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  338.091069] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  338.091096] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  338.091123] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.091149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.091182] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  338.091209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.091236] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  338.091263] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  338.091289] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  338.091328] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  338.091359] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.091392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  338.091429] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  338.091459] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  338.091490] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.091521] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  338.091550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.091579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  338.091607] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  338.091633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.091638] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  338.091665] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.091669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  338.091697] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  338.091740] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  338.091766] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  338.091793] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.091819] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.091850] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  338.091877] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.091904] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  338.091930] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  338.091955] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  338.091987] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  338.092023] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  338.092054] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  338.092084] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  338.092113] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  338.092243] [drm:intel_power_well_enable [i915]] enabling always-on
>[  338.092268] [drm:intel_power_well_enable [i915]] enabling DC off
>[  338.092555] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  338.092602] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  338.092630] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  338.092799] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  338.092827] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  338.092862] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  338.092890] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  338.092931] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  338.094783] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  338.094809] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  338.094848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  338.094883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  338.094913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  338.094943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  338.094970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  338.094998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  338.095027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  338.095054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  338.095080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  338.095106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  338.095145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  338.095166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  338.095188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  338.095212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  338.095242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  338.095269] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  338.095296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  338.095328] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  338.095355] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  338.107260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.115768] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.124277] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.132788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.141298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.149807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.158315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.166822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.175331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.183840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.192349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.200965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.209480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.217990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.226501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.235009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.243518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.252027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  338.259902] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  338.274999] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  338.275045] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  338.275126] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  338.276471] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  338.279192] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  338.280817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.280857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.280893] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.280932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.286263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.286301] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  338.291630] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.294220] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  338.295462] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  338.295541] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  338.295580] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  338.295704] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  338.295766] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  338.299264] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.299306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.299343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.299383] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.300226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  338.300263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  338.300298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  338.301122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  338.301157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  338.301193] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  338.302018] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.302055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  338.303196] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.305549] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  338.306781] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.306846] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  338.306883] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  338.306936] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  338.323719] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  338.323822] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  338.323919] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  338.324023] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  338.324075] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  338.324164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  338.324510] Console: switching to colour frame buffer device 240x75
>[  338.790409] Console: switching to colour dummy device 80x25
>[  338.790512] [IGT] kms_flip: executing
>[  338.805509] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  338.805590] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  338.814136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.822594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.831051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.839507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.847962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.856415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.864870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.873324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.881779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.890232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.898686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.907153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.915607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.924073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.932527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.940982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.949436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.957890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.966344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.974798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.983251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  338.991705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.000158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.008612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.017068] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.025522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.033977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.042444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.050899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.059352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.067808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.076262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  339.076271] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  339.076275] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  339.076286] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  339.076302] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  339.077137] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  339.078656] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  339.078672] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  339.078687] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  339.078753] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  339.079551] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  339.080262] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  339.081047] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  339.081072] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  339.081077] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.081078] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  339.081080] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  339.081082] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  339.081083] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  339.081085] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  339.081087] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  339.081088] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  339.081089] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  339.081091] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  339.081092] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  339.081094] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  339.081109] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  339.081138] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  339.081156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  339.081163] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  339.081177] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  339.082877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  339.082892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  339.084949] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  339.084953] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  339.086876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  339.086892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  339.089156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  339.089162] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  339.089165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  339.089174] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  339.089192] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  339.089649] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  339.090019] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  339.090036] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  339.090052] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  339.090066] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  339.090471] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  339.090813] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  339.091309] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  339.091310] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  339.091389] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  339.091391] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  339.091394] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  339.091395] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  339.091397] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  339.091398] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  339.091404] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  339.091406] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  339.091407] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  339.091409] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  339.091410] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  339.091411] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  339.091413] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  339.091414] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  339.091415] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  339.091417] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  339.091418] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  339.091420] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  339.091421] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  339.091422] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  339.091424] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  339.091425] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  339.091426] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  339.091428] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  339.091429] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  339.091430] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  339.091432] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  339.091433] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  339.091434] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  339.091436] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  339.091437] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  339.091439] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  339.091440] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  339.091441] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  339.091443] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  339.091444] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  339.091445] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  339.091447] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  339.091448] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  339.091476] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  339.091490] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  339.092875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  339.092890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  339.094876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  339.094880] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  339.096878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  339.096894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  339.099158] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  339.099162] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  339.099164] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  339.099354] [IGT] kms_flip: starting subtest basic-flip-vs-modeset
>[  339.100146] [drm:drm_mode_addfb2] [FB:68]
>[  339.100164] [drm:drm_mode_addfb2] [FB:110]
>[  339.149398] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.149446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  339.149538] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  339.164740] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  339.164762] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  339.164781] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  339.164822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.164840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.164857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.164872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.164886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.164899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.164913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.164927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.164940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.164953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.164966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.164978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.164991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.165005] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  339.165022] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.165038] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.165054] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.165069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.173684] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  339.173724] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  339.173752] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  339.173772] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  339.173841] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  339.173888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.173951] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  339.173973] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  339.174011] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.190983] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  339.191007] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  339.191046] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  339.191266] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  339.191286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.191304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.191321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.191336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.191351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.191365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.191380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.191394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.191408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.191422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.191437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.191450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.191463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.191479] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  339.191497] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.191514] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.191529] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.191545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.191572] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  339.191587] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  339.191602] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  339.191624] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  339.191648] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  339.191665] [drm:intel_power_well_disable [i915]] disabling DC off
>[  339.191680] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  339.192173] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  339.192591] [drm:intel_power_well_disable [i915]] disabling always-on
>[  339.192654] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  339.193112] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.193121] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  339.193170] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  339.193187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  339.193206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  339.193226] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.193241] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.193258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.193274] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  339.193290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  339.193306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.193320] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  339.193334] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.193337] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.193350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.193352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.193366] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  339.193380] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.193393] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  339.193407] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.193419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.193436] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  339.193450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.193463] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  339.193475] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  339.193488] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  339.193504] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.193523] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  339.193539] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  339.194430] [drm:intel_power_well_enable [i915]] enabling always-on
>[  339.194445] [drm:intel_power_well_enable [i915]] enabling DC off
>[  339.194793] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  339.194817] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  339.194833] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  339.194890] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  339.194905] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  339.194929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.194950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.194968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.194986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.195003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.195019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.195036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.195051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.195067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.195082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.195097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.195113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.195127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.195144] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.195164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.195182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.195199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.195221] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  339.195238] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  339.207938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.216438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.224936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.233431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.241928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.250421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.258916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.267410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.275903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.284392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.292872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.301340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.309808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.318274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.326741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.335207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.343672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.352169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.360637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.361714] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  339.375606] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  339.375622] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  339.375736] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  339.376607] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  339.377323] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  339.379195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.379212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.379228] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.379244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.385138] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.385154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  339.390290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.392753] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  339.393214] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  339.393246] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  339.393259] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  339.410057] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  339.410077] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  339.410109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.426814] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.426826] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  339.443633] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.443698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.460181] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  339.477561] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  339.477611] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  339.477654] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  339.478042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.478084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.478123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.478157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.478190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.478221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.478254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.478284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.478314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.478343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.478373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.478402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.478430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.478463] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  339.478501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.478537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.478571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.478605] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.478655] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  339.478687] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  339.479327] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  339.479374] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  339.479429] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  339.479471] [drm:intel_power_well_disable [i915]] disabling DC off
>[  339.479503] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  339.479532] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  339.480472] [drm:intel_power_well_disable [i915]] disabling always-on
>[  339.480649] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.480667] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  339.480919] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  339.480956] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  339.481003] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  339.481046] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.481080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.481117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.481153] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  339.481188] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  339.481220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.481253] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  339.481282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.481289] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.481318] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.481322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.481354] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  339.481383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.481413] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  339.481442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.481471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.481507] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  339.481538] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.481567] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  339.481596] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  339.481624] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  339.481660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.481700] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  339.482825] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  339.482988] [drm:intel_power_well_enable [i915]] enabling always-on
>[  339.483024] [drm:intel_power_well_enable [i915]] enabling DC off
>[  339.483338] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  339.483393] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  339.483435] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  339.483526] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  339.483570] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  339.483630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.483680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.484192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.484239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.484280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.484323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.484366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.484406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.484444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.484482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.484522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.484560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.484598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.484641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.484689] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.485283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.485330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.485386] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  339.485430] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  339.498708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.507497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.516221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.524942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.533657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.542514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.551230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.559949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.568666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.577578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.586297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.595013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.603670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.612394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.620930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.629437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.637926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.646400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.650850] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  339.666008] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  339.666025] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  339.666060] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  339.666894] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  339.667595] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  339.669390] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.669407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.669422] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.669438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.675345] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.675361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  339.680544] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.683023] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  339.683500] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  339.683557] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  339.683572] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  339.714418] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  339.714441] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  339.714477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.715289] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.715331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.717046] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  339.734365] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  339.734387] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  339.734406] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  339.734444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.734461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.734479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.734493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.734508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.734521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.734536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.734549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.734561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.734574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.734587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.734600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.734612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.734627] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  339.734644] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.734659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.734674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.735202] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.735226] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  339.735241] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  339.735254] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  339.735275] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  339.735300] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  339.735317] [drm:intel_power_well_disable [i915]] disabling DC off
>[  339.735332] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  339.735344] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  339.736286] [drm:intel_power_well_disable [i915]] disabling always-on
>[  339.736379] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.736388] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  339.736436] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  339.736453] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  339.736471] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  339.736490] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.736504] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.736520] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.736536] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  339.736551] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  339.736565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.736579] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  339.736592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.736595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.736608] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.736610] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.736623] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  339.736636] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.736648] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  339.736661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.736673] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.736689] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  339.737229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.737244] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  339.737258] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  339.737272] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  339.737288] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.737307] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  339.737323] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  339.737380] [drm:intel_power_well_enable [i915]] enabling always-on
>[  339.737392] [drm:intel_power_well_enable [i915]] enabling DC off
>[  339.737665] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  339.737684] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  339.737987] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  339.738023] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  339.738037] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  339.738057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.738073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.738089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.738103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.738117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.738130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.738144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.738157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.738170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.738183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.738197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.738209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.738221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.738236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.738253] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.738268] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.738283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.738301] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  339.738316] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  339.751065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.759546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.768025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.776505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.784983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.793461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.801937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.810412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.818886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.827355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.835824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.844292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.852761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.861230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.869713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.878183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.886749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.895218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.903688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  339.904566] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  339.920026] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  339.920087] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  339.920227] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  339.921390] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  339.923633] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  339.925964] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  339.926026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  339.926082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  339.926140] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  339.931782] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  339.931835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  339.937253] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  339.939904] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  339.941276] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  339.941389] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  339.941441] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  339.958296] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  339.958374] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  339.958490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.959719] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.959854] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.975030] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  339.992732] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  339.992865] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  339.992927] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  339.993038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.993095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.993151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.993199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.993245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.993291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.993339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.993381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.993423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.993463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.993507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.993547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.993587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.993635] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  339.993691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.993808] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.993859] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.993913] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.993989] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  339.994034] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  339.994078] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  339.994141] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  339.994213] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  339.994270] [drm:intel_power_well_disable [i915]] disabling DC off
>[  339.994316] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  339.994355] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  339.994839] [drm:intel_power_well_disable [i915]] disabling always-on
>[  339.995112] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  339.995138] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  339.995289] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  339.995343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  339.995403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  339.995466] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  339.995514] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  339.995568] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.995621] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  339.995671] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  339.995719] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  339.995809] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  339.995853] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.995862] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.995905] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.995913] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  339.995958] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  339.996000] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  339.996043] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  339.996084] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.996126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.996177] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  339.996219] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.996260] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  339.996301] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  339.996342] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  339.996394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.996453] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  339.996501] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  339.998251] [drm:intel_power_well_enable [i915]] enabling always-on
>[  339.998297] [drm:intel_power_well_enable [i915]] enabling DC off
>[  339.998604] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  339.998671] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  339.998774] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  339.998877] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  339.998927] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  339.998998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  339.999059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  339.999112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  339.999162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  339.999212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  339.999257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  339.999307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  339.999353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  339.999399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  339.999444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  339.999491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  339.999533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  339.999577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  339.999626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  339.999684] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  339.999766] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  339.999820] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  339.999881] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  339.999932] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  340.013167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.021943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.030671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.039497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.048230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.057054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.065777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.074490] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.083206] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.091917] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.100590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.109163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.117772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.126275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.134776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.143247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.151715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.160183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.166129] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  340.181700] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  340.181717] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  340.181753] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  340.182576] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  340.184019] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  340.186251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.186266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.186281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.186295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.191568] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.191583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  340.196726] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.199201] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  340.199677] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  340.199839] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  340.199854] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  340.216642] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  340.216665] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  340.216801] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.217600] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  340.217638] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.233396] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  340.250548] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  340.250576] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  340.250602] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  340.250649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  340.250672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  340.250940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  340.250968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  340.250989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  340.251010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  340.251031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  340.251050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  340.251067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  340.251085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  340.251103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  340.251119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  340.251136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  340.251155] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  340.251177] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  340.251198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.251217] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  340.251236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  340.251266] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  340.251285] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  340.251302] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  340.251328] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  340.251357] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  340.251380] [drm:intel_power_well_disable [i915]] disabling DC off
>[  340.251398] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  340.251414] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  340.252817] [drm:intel_power_well_disable [i915]] disabling always-on
>[  340.252925] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  340.252936] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  340.252998] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  340.253019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  340.253042] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  340.253067] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.253086] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.253107] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.253127] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  340.253146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  340.253165] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.253183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  340.253200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.253203] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  340.253219] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.253222] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  340.253239] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  340.253255] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.253272] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  340.253288] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.253303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.253324] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  340.253340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.253355] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  340.253371] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  340.253387] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  340.253407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.253429] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  340.253448] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  340.253523] [drm:intel_power_well_enable [i915]] enabling always-on
>[  340.253538] [drm:intel_power_well_enable [i915]] enabling DC off
>[  340.254770] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  340.255069] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  340.255096] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  340.255172] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  340.255198] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  340.255235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  340.255267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  340.255296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  340.255324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  340.255352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  340.255379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  340.255406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  340.255433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  340.255459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  340.255484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  340.255511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  340.255537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  340.255562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  340.255591] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  340.255622] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.255652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  340.255682] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  340.255742] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  340.255772] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  340.268600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.277164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.285724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.294280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.302837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.311392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.319946] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.328534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.337095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.345651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.354320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.362846] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.371344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.379828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.388300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.396769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.405236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.413704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.422172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.423244] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  340.437475] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  340.437541] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  340.437709] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  340.438905] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  340.439925] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  340.440838] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.440904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.440963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.441022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.447056] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.447108] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  340.452520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.455086] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  340.456457] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  340.456550] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  340.456601] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  340.473409] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  340.473476] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  340.473584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.474779] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  340.474908] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.490180] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  340.507856] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  340.507926] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  340.507986] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  340.508095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  340.508152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  340.508207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  340.508256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  340.508303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  340.508348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  340.508395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  340.508437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  340.508479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  340.508519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  340.508561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  340.508602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  340.508641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  340.508689] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  340.508857] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  340.508913] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.508969] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  340.509021] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  340.509101] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  340.509148] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  340.509196] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  340.509260] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  340.509331] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  340.509391] [drm:intel_power_well_disable [i915]] disabling DC off
>[  340.509438] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  340.509479] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  340.509968] [drm:intel_power_well_disable [i915]] disabling always-on
>[  340.510245] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  340.510272] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  340.510422] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  340.510472] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  340.510528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  340.510588] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.510636] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.510686] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.510793] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  340.510845] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  340.510900] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.510951] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  340.510997] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.511008] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  340.511056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.511068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  340.511115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  340.511164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.511211] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  340.511259] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.511307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.511362] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  340.511409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.511457] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  340.511505] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  340.511549] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  340.511604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.511662] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  340.511715] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  340.511926] [drm:intel_power_well_enable [i915]] enabling always-on
>[  340.511966] [drm:intel_power_well_enable [i915]] enabling DC off
>[  340.512271] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  340.512332] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  340.512375] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  340.512443] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  340.512485] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  340.512547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  340.512600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  340.512649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  340.512694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  340.512777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  340.512822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  340.512877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  340.512923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  340.512968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  340.513012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  340.513059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  340.513102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  340.513150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  340.513202] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  340.513260] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.513314] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  340.513364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  340.513427] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  340.513479] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  340.526809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.535541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.544267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.552994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.561721] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.570493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.579213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.587931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.596648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.605481] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.614203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.622963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.631539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.640169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.648673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.657221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.665708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.674176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.678427] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  340.694024] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  340.694040] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  340.694166] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  340.714258] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  340.715011] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  340.716798] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.716814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.716828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.716843] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.723212] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.723228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  340.728385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.730848] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  340.731320] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  340.731395] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  340.731410] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  340.748263] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  340.748284] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  340.748320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.749133] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  340.749171] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.764997] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  340.782352] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  340.782382] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  340.782408] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  340.782457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  340.782480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  340.782503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  340.782523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  340.782542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  340.782560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  340.782579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  340.782597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  340.782614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  340.782631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  340.782648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  340.782665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  340.782681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  340.782759] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  340.782793] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  340.782829] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.782862] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  340.782894] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  340.782941] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  340.782970] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  340.783000] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  340.783042] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  340.783086] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  340.783124] [drm:intel_power_well_disable [i915]] disabling DC off
>[  340.783154] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  340.783180] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  340.783632] [drm:intel_power_well_disable [i915]] disabling always-on
>[  340.783829] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  340.783847] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  340.783947] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  340.783978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  340.784013] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  340.784050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  340.784080] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  340.784113] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.784144] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  340.784175] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  340.784205] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  340.784233] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  340.784261] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.784266] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  340.784293] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.784298] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  340.784325] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  340.784353] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  340.784377] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  340.784404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.784427] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.784460] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  340.784487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.784514] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  340.784541] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  340.784564] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  340.784596] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.784630] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  340.784661] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  340.784800] [drm:intel_power_well_enable [i915]] enabling always-on
>[  340.784826] [drm:intel_power_well_enable [i915]] enabling DC off
>[  340.785114] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  340.785154] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  340.785183] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  340.785225] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  340.785253] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  340.785290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  340.785323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  340.785352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  340.785383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  340.785411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  340.785440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  340.785470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  340.785498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  340.785525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  340.785552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  340.785580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  340.785606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  340.785633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  340.785662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  340.785696] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  340.785752] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  340.785784] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  340.785821] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  340.785853] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  340.798686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.807343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.815909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.824474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.833038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.841644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.850305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.858968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.867532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.876098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.884665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.893275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.901782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.910267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.918740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.927207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.935674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.944186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  340.952008] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  340.966215] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  340.966234] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  340.966272] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  340.967610] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  340.970208] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  340.971548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.971563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.971577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.971591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.976732] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.976748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  340.981886] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.984352] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  340.984921] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  340.984999] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  340.985014] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  341.001803] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.001825] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.001862] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.002661] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.002864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.018489] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  341.035532] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  341.035556] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  341.035578] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  341.035617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.035637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.035656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.035672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.035689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.035879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.035897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.035913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.035929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.035944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.035960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.035975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.035990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.036007] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.036027] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.036045] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.036063] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.036080] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.036104] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  341.036121] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  341.036137] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  341.036160] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  341.036184] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.036204] [drm:intel_power_well_disable [i915]] disabling DC off
>[  341.036221] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  341.036235] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  341.036654] [drm:intel_power_well_disable [i915]] disabling always-on
>[  341.037064] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.037073] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  341.037125] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  341.037143] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  341.037163] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  341.037184] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.037201] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.037219] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.037237] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  341.037254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  341.037270] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.037286] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  341.037301] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.037304] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.037318] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.037321] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.037336] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  341.037351] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.037365] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  341.037379] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.037393] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.037410] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  341.037425] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.037439] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  341.037453] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  341.037466] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  341.037483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.037503] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  341.037520] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  341.037580] [drm:intel_power_well_enable [i915]] enabling always-on
>[  341.037593] [drm:intel_power_well_enable [i915]] enabling DC off
>[  341.038420] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  341.038784] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  341.038800] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  341.038828] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  341.038849] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  341.038877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.038896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.038914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.038931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.038947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.038962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.038979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.038994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.039009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.039024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.039039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.039054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.039068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.039085] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.039104] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.039121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.039138] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.039173] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  341.039193] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  341.051959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.060523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.069080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.077739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.086291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.094851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.103434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.111988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.120545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.129126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.137682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.146235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.154734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.163214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.171687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.180247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.188716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.197184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.205652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.206729] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  341.220849] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  341.220870] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  341.220895] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  341.222188] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  341.223993] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  341.225874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.225890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.225904] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.225918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.231100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.231128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  341.236285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.238766] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  341.239234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  341.239293] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  341.239307] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  341.256165] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.256185] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.256218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.257096] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.257135] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.272816] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  341.289962] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  341.289983] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  341.290002] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  341.290038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.290056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.290073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.290088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.290102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.290116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.290130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.290143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.290157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.290170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.290183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.290195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.290208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.290223] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.290240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.290256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.290272] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.290287] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.290308] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  341.290323] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  341.290337] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  341.290357] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  341.290379] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.290396] [drm:intel_power_well_disable [i915]] disabling DC off
>[  341.290410] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  341.290423] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  341.290866] [drm:intel_power_well_disable [i915]] disabling always-on
>[  341.290946] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.290954] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  341.290999] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  341.291016] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  341.291034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  341.291053] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.291068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.291086] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.291101] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  341.291117] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  341.291147] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.291164] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  341.291179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.291184] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.291198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.291201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.291216] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  341.291232] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.291246] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  341.291262] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.291276] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.291294] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  341.291310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.291324] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  341.291339] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  341.291353] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  341.291371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.291391] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  341.291409] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  341.291472] [drm:intel_power_well_enable [i915]] enabling always-on
>[  341.291486] [drm:intel_power_well_enable [i915]] enabling DC off
>[  341.291773] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  341.291796] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  341.291812] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  341.291851] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  341.291871] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  341.291893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.291912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.291929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.291946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.291962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.291977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.291993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.292009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.292023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.292038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.292054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.292069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.292083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.292100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.292118] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.292137] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.292154] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.292176] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  341.292193] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  341.304956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.313498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.322024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.330552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.339080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.347607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.356133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.364662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.373263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.381808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.390334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.398859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.407362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.415847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.424315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.432783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.441248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.449715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.458181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.459315] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  341.473848] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  341.473866] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  341.473907] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  341.474934] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  341.477188] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  341.478595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.478610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.478624] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.478639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.483781] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.483798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  341.488935] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.491489] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  341.492018] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  341.492045] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  341.492060] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  341.508837] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.508859] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.508894] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.509772] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.509811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.525609] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  341.542742] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  341.542769] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  341.542790] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  341.542833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.542853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.542872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.542889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.542905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.542920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.542936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.542951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.542965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.542979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.542995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.543009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.543023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.543040] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.543059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.543078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.543095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.543112] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.543155] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  341.543173] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  341.543190] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  341.543216] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  341.543245] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.543268] [drm:intel_power_well_disable [i915]] disabling DC off
>[  341.543286] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  341.543301] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  341.544614] [drm:intel_power_well_disable [i915]] disabling always-on
>[  341.544819] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.544831] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  341.544893] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  341.544915] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  341.544938] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  341.544963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.544982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.545002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.545023] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  341.545042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  341.545061] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.545078] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  341.545095] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.545098] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.545114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.545116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.545133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  341.545150] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.545167] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  341.545183] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.545199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.545219] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  341.545235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.545251] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  341.545267] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  341.545283] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  341.545303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.545325] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  341.545345] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  341.545419] [drm:intel_power_well_enable [i915]] enabling always-on
>[  341.545434] [drm:intel_power_well_enable [i915]] enabling DC off
>[  341.546290] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  341.546576] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  341.546593] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  341.546626] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  341.546651] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  341.546678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.546834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.546854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.546873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.546891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.546909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.546927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.546945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.546961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.546978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.546996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.547013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.547029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.547048] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.547069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.547089] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.547108] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.547132] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  341.547152] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  341.559921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.568476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.577033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.585586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.594141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.602693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.611272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.619824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.628376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.636927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.645480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.654117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.662625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.671112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.679586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.688053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.715343] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  341.728880] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  341.728897] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  341.728943] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  341.729788] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  341.730521] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  341.733127] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.733144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.733160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.733177] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.738582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.738597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  341.743785] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.746259] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  341.746805] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  341.746845] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  341.746860] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  341.763651] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.763673] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.763817] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.764615] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.764655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.780406] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  341.797648] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  341.797676] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  341.797853] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  341.797902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.797925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.797948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.797967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.797985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.798002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.798021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.798038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.798054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.798070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.798087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.798103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.798119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.798138] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  341.798159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.798180] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.798199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.798218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.798247] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  341.798266] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  341.798283] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  341.798310] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  341.798339] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  341.798362] [drm:intel_power_well_disable [i915]] disabling DC off
>[  341.798380] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  341.798395] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  341.799617] [drm:intel_power_well_disable [i915]] disabling always-on
>[  341.799800] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  341.799812] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  341.799873] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  341.799894] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  341.799917] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  341.799942] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  341.799961] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  341.799981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  341.800002] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  341.800021] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  341.800039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  341.800056] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  341.800073] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  341.800077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.800093] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  341.800096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  341.800113] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  341.800130] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  341.800146] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  341.800162] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  341.800178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  341.800198] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  341.800215] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  341.800231] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  341.800247] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  341.800262] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  341.800282] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  341.800305] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  341.800325] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  341.800399] [drm:intel_power_well_enable [i915]] enabling always-on
>[  341.800414] [drm:intel_power_well_enable [i915]] enabling DC off
>[  341.801315] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  341.801611] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  341.801628] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  341.801676] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  341.801834] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  341.801860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  341.801882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  341.801902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  341.801920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  341.801939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  341.801956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  341.801974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  341.801991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  341.802008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  341.802024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  341.802041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  341.802057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  341.802073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  341.802091] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  341.802112] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  341.802131] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  341.802150] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  341.802174] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  341.802193] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  341.815001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.823564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.832124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.840683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.849265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.857820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.866374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.874931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.883484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.892039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.900593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.909125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.917628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.926113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.934585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.943056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.951523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.959989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  341.967812] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  341.982606] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  341.982622] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  341.982687] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  341.983538] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  341.984981] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  341.987212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.987227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.987241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.987256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.992393] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.992409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  341.997547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.000021] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  342.000497] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  342.000557] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  342.000572] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  342.017365] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.017387] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.017423] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.018221] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.018259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.034117] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  342.051276] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  342.051305] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  342.051329] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  342.051375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.051397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.051419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.051438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.051457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.051474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.051492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.051509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.051525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.051542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.051559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.051575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.051591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.051610] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.051632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.051653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.051672] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.051691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.052188] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  342.052207] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  342.052224] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  342.052250] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  342.052281] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.052304] [drm:intel_power_well_disable [i915]] disabling DC off
>[  342.052323] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  342.052338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  342.053263] [drm:intel_power_well_disable [i915]] disabling always-on
>[  342.053376] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.053387] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  342.053448] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  342.053572] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  342.053594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  342.053618] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.053638] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.053657] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.053677] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  342.053959] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  342.053979] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.053998] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  342.054015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.054018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.054035] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.054038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.054055] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  342.054072] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.054089] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  342.054105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.054121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.054141] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  342.054157] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.054173] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  342.054190] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  342.054205] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  342.054226] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.054249] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  342.054269] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  342.054342] [drm:intel_power_well_enable [i915]] enabling always-on
>[  342.054357] [drm:intel_power_well_enable [i915]] enabling DC off
>[  342.054633] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  342.054658] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  342.054676] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  342.055214] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  342.055232] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  342.055257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.055279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.055299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.055317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.055335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.055352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.055371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.055387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.055404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.055420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.055437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.055453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.055469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.055487] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.055508] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.055527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.055546] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.055570] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  342.055589] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  342.068398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.076961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.085520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.094079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.102638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.111195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.119758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.128314] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.136871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.145428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.153985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.162512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.171012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.179497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.187969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.196452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.204920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.213390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.221215] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  342.235925] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  342.235945] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  342.235997] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  342.236942] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  342.239196] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  342.240603] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.240619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.240633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.240648] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.245806] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.245822] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  342.250963] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.253426] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  342.253991] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  342.254024] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  342.254039] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  342.270832] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.270854] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.270890] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.271784] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.271840] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.287581] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  342.304836] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  342.304861] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  342.304882] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  342.304924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.304944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.304964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.304980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.304997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.305013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.305029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.305045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.305060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.305075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.305090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.305105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.305120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.305137] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.305157] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.305176] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.305193] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.305210] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.305239] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  342.305255] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  342.305271] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  342.305294] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  342.305320] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.305340] [drm:intel_power_well_disable [i915]] disabling DC off
>[  342.305357] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  342.305371] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  342.306544] [drm:intel_power_well_disable [i915]] disabling always-on
>[  342.306758] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.306773] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  342.306856] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  342.306884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  342.306907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  342.306929] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.306947] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.306965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.306983] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  342.307000] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  342.307017] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.307033] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  342.307048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.307051] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.307065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.307068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.307083] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  342.307098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.307113] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  342.307127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.307142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.307159] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  342.307174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.307188] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  342.307202] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  342.307216] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  342.307234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.307254] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  342.307272] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  342.307338] [drm:intel_power_well_enable [i915]] enabling always-on
>[  342.307352] [drm:intel_power_well_enable [i915]] enabling DC off
>[  342.307625] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  342.307647] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  342.307662] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  342.308673] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  342.308787] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  342.308825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.308855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.308875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.308893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.308911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.308929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.308947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.308964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.308981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.308997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.309014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.309030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.309046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.309065] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.309086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.309106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.309125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.309149] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  342.309168] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  342.321930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.330478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.339037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.347594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.356150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.364732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.373286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.381841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.390398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.399032] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.407576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.416097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.424599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.433081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.441550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.450019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.458488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.466956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.475433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.476509] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  342.490871] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  342.490932] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  342.491187] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  342.492365] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  342.493593] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  342.496866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.496926] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.496980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.497037] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.502567] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.502623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  342.508023] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.510663] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  342.512170] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  342.512310] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  342.512363] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  342.529206] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.529282] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.529399] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.530545] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.530680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.545999] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  342.563561] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  342.563631] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  342.563691] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  342.564400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.564460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.564517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.564565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.564611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.564655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.564701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.565255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.565300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.565345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.565392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.565435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.565477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.565526] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.565583] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.565635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.565686] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.566219] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.566289] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  342.566336] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  342.566380] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  342.566441] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  342.566515] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.566572] [drm:intel_power_well_disable [i915]] disabling DC off
>[  342.566617] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  342.566656] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  342.567854] [drm:intel_power_well_disable [i915]] disabling always-on
>[  342.568121] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.568146] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  342.568301] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  342.568353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  342.568412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  342.568474] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.568523] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.568576] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.568628] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  342.568677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  342.569462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.569510] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  342.569555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.569563] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.569607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.569613] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.569659] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  342.569703] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.570213] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  342.570257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.570300] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.570355] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  342.570402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.570446] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  342.570491] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  342.570533] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  342.570588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.570647] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  342.570698] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  342.571421] [drm:intel_power_well_enable [i915]] enabling always-on
>[  342.571460] [drm:intel_power_well_enable [i915]] enabling DC off
>[  342.571961] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  342.572300] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  342.572355] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  342.572445] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  342.572487] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  342.572552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.572608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.572658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.572705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.573201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.573249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.573299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.573343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.573389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.573433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.573479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.573520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.573563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.573610] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.573665] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.573717] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.574385] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.574447] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  342.574497] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  342.587779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.596507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.605229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.613946] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.622663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.631605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.640507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.649219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.657934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.666650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.675377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.683952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.692502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.721049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.729517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.737985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.742434] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  342.756363] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  342.756379] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  342.756433] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  342.757268] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  342.758053] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  342.760676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  342.760706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  342.760722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  342.760738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  342.766129] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  342.766145] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  342.771282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  342.773759] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  342.774234] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  342.774293] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  342.774308] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  342.791098] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.791120] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.791155] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.791953] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.791992] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.807853] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  342.824989] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  342.825019] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  342.825044] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  342.825091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.825114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.825136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.825155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.825173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.825191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.825209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.825226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.825242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.825259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.825276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.825292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.825308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.825326] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  342.825348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.825369] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.825389] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.825408] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.825439] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  342.825458] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  342.825475] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  342.825502] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  342.825530] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  342.825553] [drm:intel_power_well_disable [i915]] disabling DC off
>[  342.825571] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  342.825587] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  342.826826] [drm:intel_power_well_disable [i915]] disabling always-on
>[  342.827044] [drm:drm_mode_addfb2] [FB:68]
>[  342.827072] [drm:drm_mode_addfb2] [FB:110]
>[  342.889373] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  342.890030] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  342.890465] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  342.891104] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  342.891125] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  342.891257] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  342.891304] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  342.891353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  342.891403] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  342.891443] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  342.891486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  342.891530] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  342.891571] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  342.891611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  342.891649] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  342.891685] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  342.892121] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.892161] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  342.892168] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  342.892207] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  342.892244] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  342.892280] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  342.892316] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  342.892350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  342.892394] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  342.892430] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  342.892466] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  342.892500] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  342.892534] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  342.892576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.892623] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  342.892663] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  342.894120] [drm:intel_power_well_enable [i915]] enabling always-on
>[  342.894153] [drm:intel_power_well_enable [i915]] enabling DC off
>[  342.894461] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  342.894510] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  342.894553] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  342.894641] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  342.894675] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  342.894990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  342.895038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  342.895079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  342.895119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  342.895157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  342.895195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  342.895234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  342.895271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  342.895306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  342.895341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  342.895378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  342.895412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  342.895447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  342.895487] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  342.895531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  342.895573] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  342.895614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  342.895664] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  342.895705] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  342.909388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.918123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.926785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.935465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.944598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.965735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.974270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.982795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.991284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  342.999775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.008252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.016722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.025190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.033665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.042207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.050675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.059158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.063608] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  343.078003] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  343.078022] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  343.078065] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  343.079257] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  343.081048] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  343.082926] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.082941] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.082956] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.082970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.088109] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.088125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  343.093265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.095744] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  343.096220] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  343.113091] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.113114] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.113150] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.129834] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.129846] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  343.146656] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.146866] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.163192] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  343.180609] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  343.180656] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  343.181012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.181055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.181095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.181128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.181178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.181217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.181258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.181297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.181334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.181373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.181412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.181449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.181486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.181529] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.181579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.181626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.181671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.182402] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.182474] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  343.182518] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  343.182560] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  343.182618] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  343.182685] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.183058] [drm:intel_power_well_disable [i915]] disabling DC off
>[  343.183100] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  343.183135] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  343.183595] [drm:intel_power_well_disable [i915]] disabling always-on
>[  343.184067] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.184091] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  343.184230] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  343.184279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  343.184331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  343.184389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.184433] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.184482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.184530] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  343.184574] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  343.184618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.184659] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  343.184699] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.185339] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.185383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.185392] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.185437] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  343.185480] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.185522] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  343.185562] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.185601] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.185649] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  343.185691] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.186202] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  343.186243] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  343.186283] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  343.186332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.186384] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  343.186430] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  343.186592] [drm:intel_power_well_enable [i915]] enabling always-on
>[  343.186627] [drm:intel_power_well_enable [i915]] enabling DC off
>[  343.187314] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  343.187633] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  343.187681] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  343.187962] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  343.188000] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  343.188059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.188108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.188152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.188194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.188235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.188274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.188315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.188353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.188391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.188428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.188467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.188503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.188540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.188583] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.188631] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.188676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.189486] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.189542] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  343.189587] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  343.202965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.211690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.220504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.229223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.237942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.246655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.255483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.264202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.272922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.281635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.290538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.299225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.307848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.316390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.324907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.333403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.341883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.350430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.356567] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  343.371411] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  343.371427] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  343.371477] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  343.372303] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  343.374083] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  343.375974] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.375990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.376003] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.376030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.381196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.381211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  343.386455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.388939] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  343.389401] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  343.406271] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.406291] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.406323] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.407146] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.407196] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.422984] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  343.440205] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  343.440228] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  343.440268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.440287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.440305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.440320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.440335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.440349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.440365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.440379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.440392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.440405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.440419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.440432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.440445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.440461] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.440479] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.440496] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.440511] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.440527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.440554] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  343.440570] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  343.440584] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  343.440606] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  343.440630] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.440647] [drm:intel_power_well_disable [i915]] disabling DC off
>[  343.440662] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  343.440675] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  343.441144] [drm:intel_power_well_disable [i915]] disabling always-on
>[  343.441273] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.441286] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  343.441361] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  343.441386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  343.441413] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  343.441441] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.441465] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.441490] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.441515] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  343.441539] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  343.441562] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.441584] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  343.441606] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.441611] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.441632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.441636] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.441658] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  343.441679] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.441719] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  343.441741] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.441761] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.441787] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  343.441809] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.441832] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  343.441853] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  343.441875] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  343.441899] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.441928] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  343.441952] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  343.442046] [drm:intel_power_well_enable [i915]] enabling always-on
>[  343.442066] [drm:intel_power_well_enable [i915]] enabling DC off
>[  343.442364] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  343.442398] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  343.442422] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  343.442464] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  343.442489] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  343.442522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.442552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.442579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.442605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.442631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.442653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.442680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.442720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.442743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.442767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.442792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.442813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.442836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.442863] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.442892] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.442921] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.442949] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.442980] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  343.443007] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  343.455760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.464289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.472825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.481361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.489896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.498429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.506962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.515501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.524036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.532568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.541124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.549660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.558260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.566749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.575222] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.583691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.592171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.600637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.609104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.610193] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  343.624662] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  343.624683] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  343.624728] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  343.625970] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  343.628225] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  343.629632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.629648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.629662] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.629677] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.634919] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.634934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  343.640089] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.642551] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  343.643085] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  343.659955] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.659978] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.660014] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.660826] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.660867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.676735] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  343.694113] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  343.694152] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  343.694200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.694223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.694245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.694264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.694282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.694299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.694318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.694334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.694350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.694366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.694383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.694399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.694414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.694433] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.694454] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.694474] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.694493] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.694512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.694544] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  343.694562] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  343.694580] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  343.694606] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  343.694634] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.694654] [drm:intel_power_well_disable [i915]] disabling DC off
>[  343.694672] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  343.694688] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  343.695157] [drm:intel_power_well_disable [i915]] disabling always-on
>[  343.695319] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.695335] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  343.695424] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  343.695451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  343.695484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  343.695518] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.695544] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.695574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.695602] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  343.695630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  343.695656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.695682] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  343.695731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.695736] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.695761] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.695767] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.695794] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  343.695817] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.695843] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  343.695866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.695892] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.695921] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  343.695946] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.695969] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  343.695994] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  343.696016] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  343.696046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.696080] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  343.696107] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  343.696201] [drm:intel_power_well_enable [i915]] enabling always-on
>[  343.696223] [drm:intel_power_well_enable [i915]] enabling DC off
>[  343.696508] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  343.696543] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  343.696569] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  343.696613] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  343.696638] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  343.696673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.696725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.696752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.696780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.696805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.696832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.696858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.696884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.696908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.696933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.696957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.696982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.697005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.697032] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.697063] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.697092] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.697122] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.697156] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  343.697183] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  343.721044] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.729607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.738165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.746723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.755275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.763828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.772378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.780930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.789480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.798014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.806522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.815008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.823483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.831950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.840415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.848883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.857348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.863485] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  343.877540] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  343.877601] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  343.877709] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  343.878865] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  343.879988] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  343.883321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.883380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.883435] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.883492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.889022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.889077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  343.894465] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.897025] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  343.898534] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  343.915551] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.915629] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.915896] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.917015] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.917151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.932248] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  343.951209] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  343.951274] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  343.951382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.951440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.951494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.951541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.951586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.951631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.951678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.951889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.951933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.951976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.952021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.952064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.952105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.952154] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  343.952210] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.952263] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.952313] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.952363] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.952431] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  343.952477] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  343.952521] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  343.952582] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  343.952648] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  343.952699] [drm:intel_power_well_disable [i915]] disabling DC off
>[  343.952912] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  343.952952] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  343.953419] [drm:intel_power_well_disable [i915]] disabling always-on
>[  343.953663] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  343.953799] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  343.953949] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  343.954000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  343.954058] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  343.954119] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  343.954168] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  343.954223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.954274] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  343.954324] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  343.954373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  343.954421] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  343.954465] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.954475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.954518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.954525] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  343.954570] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  343.954613] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  343.954656] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  343.954696] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.954910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.954963] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  343.955007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.955050] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  343.955092] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  343.955134] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  343.955187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.955244] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  343.955292] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  343.955465] [drm:intel_power_well_enable [i915]] enabling always-on
>[  343.955504] [drm:intel_power_well_enable [i915]] enabling DC off
>[  343.955880] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  343.956327] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  343.956373] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  343.956474] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  343.956516] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  343.956575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  343.956626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  343.956672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  343.956716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  343.956805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  343.956847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  343.956897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  343.956940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  343.956983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  343.957025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  343.957070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  343.957111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  343.957152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  343.957200] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  343.957256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  343.957309] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  343.957360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  343.957421] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  343.957469] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  343.970450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.980715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.989504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  343.998230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.006952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.015673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.024414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.033140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.041855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.050573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.059246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.067833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.076369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.084875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.093363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.101837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.110305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.118774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.123224] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  344.137831] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  344.137850] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  344.137892] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  344.138926] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  344.141159] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  344.143208] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.143223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.143237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.143252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.148391] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.148406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  344.153549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.156023] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  344.156497] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  344.173364] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.173387] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.173423] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.174227] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.174265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.190050] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  344.207240] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  344.207267] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  344.207315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.207338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.207360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.207379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.207397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.207414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.207432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.207449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.207465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.207481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.207498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.207514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.207529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.207548] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.207569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.207590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.207609] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.207628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.207660] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  344.207678] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  344.207753] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  344.207794] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  344.207833] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.207865] [drm:intel_power_well_disable [i915]] disabling DC off
>[  344.207893] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  344.207918] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  344.208350] [drm:intel_power_well_disable [i915]] disabling always-on
>[  344.208500] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.208515] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  344.208582] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  344.208604] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  344.208627] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  344.208652] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.208672] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.208694] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.208956] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  344.208977] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  344.208997] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.209017] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  344.209035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.209038] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.209055] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.209059] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.209076] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  344.209094] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.209111] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  344.209129] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.209145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.209166] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  344.209183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.209200] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  344.209217] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  344.209233] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  344.209255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.209278] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  344.209299] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  344.209374] [drm:intel_power_well_enable [i915]] enabling always-on
>[  344.209390] [drm:intel_power_well_enable [i915]] enabling DC off
>[  344.209666] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  344.209834] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  344.209860] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  344.209912] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  344.209938] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  344.209975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.210002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.210022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.210041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.210059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.210076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.210094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.210112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.210128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.210145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.210162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.210178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.210194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.210213] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.210234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.210254] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.210274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.210298] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  344.210317] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  344.223135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.231690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.240275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.248833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.257390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.265947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.274530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.283087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.291646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.300301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.308856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.317418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.325960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.334467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.342943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.351411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.359879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.368347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.376172] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  344.390683] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  344.390702] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  344.390746] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  344.391826] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  344.394103] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  344.395531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.395547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.395562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.395576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.400718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.400734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  344.405873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.408342] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  344.408956] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  344.425796] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.425817] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.425850] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.426653] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.426855] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.442541] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  344.459838] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  344.459864] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  344.459908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.459929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.459950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.459967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.459984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.460001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.460018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.460034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.460049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.460065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.460080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.460095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.460110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.460127] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.460148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.460167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.460185] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.460202] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.460232] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  344.460249] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  344.460265] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  344.460290] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  344.460317] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.460336] [drm:intel_power_well_disable [i915]] disabling DC off
>[  344.460353] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  344.460367] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  344.461741] [drm:intel_power_well_disable [i915]] disabling always-on
>[  344.461847] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.461858] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  344.461916] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  344.461936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  344.461957] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  344.461980] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.461997] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.462017] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.462035] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  344.462053] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  344.462070] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.462086] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  344.462102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.462105] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.462121] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.462124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.462140] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  344.462155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.462170] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  344.462185] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.462199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.462218] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  344.462233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.462248] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  344.462263] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  344.462278] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  344.462296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.462317] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  344.462335] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  344.462403] [drm:intel_power_well_enable [i915]] enabling always-on
>[  344.462417] [drm:intel_power_well_enable [i915]] enabling DC off
>[  344.463364] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  344.463648] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  344.463664] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  344.463835] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  344.463854] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  344.463879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.463900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.463918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.463935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.463952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.463967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.463984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.463999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.464015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.464030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.464045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.464060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.464074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.464091] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.464110] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.464128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.464146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.464167] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  344.464185] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  344.476924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.485463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.494004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.502544] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.511083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.519621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.528158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.536696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.545256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.553817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.562357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.570880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.579378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.587859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.596329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.604798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.613266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.621734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.630201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.631338] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  344.645848] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  344.645865] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  344.645891] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  344.647004] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  344.648866] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  344.650741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.650756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.650770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.650784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.655925] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.655941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  344.661094] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.663487] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  344.664042] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  344.680910] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.680932] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.680968] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.681821] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.681862] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.714392] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  344.731699] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  344.731748] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  344.731791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.731812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.731831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.731847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.731862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.731877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.731892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.731907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.731921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.731936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.731951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.731965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.731979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.731995] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.732015] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.732033] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.732050] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.732067] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.732097] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  344.732113] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  344.732128] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  344.732152] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  344.732177] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.732195] [drm:intel_power_well_disable [i915]] disabling DC off
>[  344.732212] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  344.732225] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  344.732644] [drm:intel_power_well_disable [i915]] disabling always-on
>[  344.732807] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.732822] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  344.732901] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  344.732927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  344.732955] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  344.732985] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.733010] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.733036] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.733056] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  344.733073] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  344.733090] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.733106] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  344.733121] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.733124] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.733139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.733142] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.733157] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  344.733173] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.733188] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  344.733203] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.733217] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.733236] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  344.733251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.733266] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  344.733281] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  344.733295] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  344.733314] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.733335] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  344.733352] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  344.733420] [drm:intel_power_well_enable [i915]] enabling always-on
>[  344.733434] [drm:intel_power_well_enable [i915]] enabling DC off
>[  344.733734] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  344.733768] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  344.733790] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  344.733830] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  344.733853] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  344.733883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.733909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.733934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.733956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.733980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.734001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.734024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.734045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.734065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.734086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.734109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.734131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.734152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.734175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.734204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.734231] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.734257] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.734287] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  344.734312] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  344.747069] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.755584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.764096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.772606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.781118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.789630] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.798141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.806650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.815255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.823765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.832261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.840741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.849212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.857681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.866163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.874631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.883100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.891568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  344.899191] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  344.914740] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  344.914773] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  344.914820] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  344.915675] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  344.917172] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  344.919415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  344.919431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  344.919445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  344.919460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  344.924600] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  344.924615] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  344.929756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  344.932231] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  344.932798] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  344.949678] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.949715] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.949751] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.950552] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.950589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.966430] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  344.983616] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  344.983644] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  344.983692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.983910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.983945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.983973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.983999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.984017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.984036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.984053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.984070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.984086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.984103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.984120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.984136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.984155] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  344.984177] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.984198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.984217] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.984236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.984267] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  344.984285] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  344.984303] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  344.984329] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  344.984357] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  344.984377] [drm:intel_power_well_disable [i915]] disabling DC off
>[  344.984395] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  344.984411] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  344.985715] [drm:intel_power_well_disable [i915]] disabling always-on
>[  344.985823] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  344.985834] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  344.985896] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  344.985916] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  344.985939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  344.985963] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  344.985982] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  344.986002] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  344.986023] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  344.986042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  344.986060] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  344.986077] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  344.986094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  344.986097] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.986114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  344.986116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  344.986133] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  344.986149] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  344.986165] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  344.986181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  344.986197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  344.986217] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  344.986233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  344.986249] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  344.986265] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  344.986280] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  344.986300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  344.986323] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  344.986343] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  344.986417] [drm:intel_power_well_enable [i915]] enabling always-on
>[  344.986432] [drm:intel_power_well_enable [i915]] enabling DC off
>[  344.987266] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  344.987564] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  344.987591] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  344.987641] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  344.987667] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  344.987703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  344.987930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  344.987950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  344.987970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  344.987988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  344.988006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  344.988024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  344.988041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  344.988058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  344.988075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  344.988092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  344.988108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  344.988124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  344.988142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  344.988163] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  344.988183] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  344.988202] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  344.988226] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  344.988245] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  345.001043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.009607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.018166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.026728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.035283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.043839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.052394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.060948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.069518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.078074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.086625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.095157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.103662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.112226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.120700] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.129169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.137638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.146107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.153930] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  345.168582] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  345.168602] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  345.168648] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  345.169604] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  345.172208] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  345.173550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.173565] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.173579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.173594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.178737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.178753] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  345.183894] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.186355] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  345.186939] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  345.203813] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  345.203836] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  345.203872] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.204665] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  345.204891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.220565] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  345.237828] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  345.237853] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  345.237896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  345.237916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  345.237936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  345.237953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  345.237969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  345.237985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  345.238001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  345.238015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  345.238030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  345.238044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  345.238060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  345.238074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  345.238088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  345.238105] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  345.238124] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  345.238142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.238159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  345.238176] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  345.238205] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  345.238222] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  345.238237] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  345.238261] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  345.238287] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  345.238305] [drm:intel_power_well_disable [i915]] disabling DC off
>[  345.238321] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  345.238335] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  345.239856] [drm:intel_power_well_disable [i915]] disabling always-on
>[  345.240004] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  345.240019] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  345.240091] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  345.240110] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  345.240131] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  345.240153] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.240171] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.240190] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.240208] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  345.240225] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  345.240243] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.240259] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  345.240274] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.240277] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  345.240292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.240294] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  345.240310] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  345.240325] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.240339] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  345.240353] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.240367] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.240385] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  345.240400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.240415] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  345.240429] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  345.240443] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  345.240460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.240481] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  345.240498] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  345.240564] [drm:intel_power_well_enable [i915]] enabling always-on
>[  345.240577] [drm:intel_power_well_enable [i915]] enabling DC off
>[  345.241818] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  345.242112] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  345.242128] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  345.242168] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  345.242200] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  345.242226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  345.242248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  345.242268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  345.242287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  345.242305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  345.242322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  345.242340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  345.242356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  345.242372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  345.242388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  345.242405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  345.242421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  345.242437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  345.242455] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  345.242476] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.242496] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  345.242515] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  345.242538] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  345.242557] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  345.255388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.263924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.272456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.280987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.289618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.298154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.306685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.315238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.323768] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.332298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.340827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.349335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.357823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.366295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.374765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.383235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.391705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.400175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.408001] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  345.422968] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  345.422985] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  345.423025] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  345.423853] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  345.426101] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  345.427532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.427547] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.427561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.427577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.432737] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.432755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  345.437896] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.440366] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  345.440902] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  345.457769] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  345.457791] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  345.457827] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.458637] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  345.458678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.474436] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  345.491624] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  345.491649] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  345.491692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  345.491891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  345.491922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  345.491948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  345.491971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  345.491987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  345.492004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  345.492019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  345.492034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  345.492049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  345.492064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  345.492078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  345.492092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  345.492109] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  345.492129] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  345.492148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.492165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  345.492182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  345.492209] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  345.492226] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  345.492241] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  345.492264] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  345.492290] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  345.492308] [drm:intel_power_well_disable [i915]] disabling DC off
>[  345.492324] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  345.492338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  345.493554] [drm:intel_power_well_disable [i915]] disabling always-on
>[  345.493656] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  345.493667] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  345.493840] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  345.493859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  345.493880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  345.493901] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.493919] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.493937] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.493955] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  345.493972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  345.493989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.494005] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  345.494020] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.494023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  345.494038] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.494040] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  345.494056] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  345.494070] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.494085] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  345.494099] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.494113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.494131] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  345.494160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.494176] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  345.494191] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  345.494207] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  345.494227] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.494250] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  345.494269] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  345.494343] [drm:intel_power_well_enable [i915]] enabling always-on
>[  345.494358] [drm:intel_power_well_enable [i915]] enabling DC off
>[  345.494634] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  345.494657] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  345.494676] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  345.494885] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  345.494912] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  345.494948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  345.494980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  345.495009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  345.495038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  345.495066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  345.495090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  345.495118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  345.495144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  345.495171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  345.495194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  345.495221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  345.495246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  345.495270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  345.495298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  345.495330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.495361] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  345.495391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  345.495425] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  345.495455] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  345.508274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.516821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.525377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.533934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.542487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.551041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.559594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.568147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.576705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.585283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.594030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.602668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.611282] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.619780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.628263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.636732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.645198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.653668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.661554] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  345.675827] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  345.675846] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  345.675939] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  345.677219] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  345.678997] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  345.681170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.681186] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.681202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.681218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.686639] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.686654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  345.691853] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.714331] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  345.714860] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  345.731762] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  345.731785] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  345.731824] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.732783] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  345.732838] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.748444] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  345.766981] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  345.767006] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  345.767049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  345.767069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  345.767089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  345.767106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  345.767122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  345.767137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  345.767153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  345.767168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  345.767182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  345.767197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  345.767212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  345.767226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  345.767240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  345.767257] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  345.767277] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  345.767295] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.767313] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  345.767330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  345.767359] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  345.767376] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  345.767391] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  345.767415] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  345.767441] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  345.767459] [drm:intel_power_well_disable [i915]] disabling DC off
>[  345.767476] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  345.767490] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  345.768667] [drm:intel_power_well_disable [i915]] disabling always-on
>[  345.768807] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  345.768818] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  345.768873] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  345.768891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  345.768912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  345.768934] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.768951] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  345.768969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.768988] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  345.769005] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  345.769022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  345.769037] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  345.769052] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.769055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  345.769070] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.769072] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  345.769087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  345.769102] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  345.769116] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  345.769131] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.769145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.769162] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  345.769177] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.769191] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  345.769205] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  345.769218] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  345.769236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.769256] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  345.769274] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  345.769340] [drm:intel_power_well_enable [i915]] enabling always-on
>[  345.769353] [drm:intel_power_well_enable [i915]] enabling DC off
>[  345.769627] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  345.769648] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  345.769663] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  345.770250] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  345.770266] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  345.770288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  345.770307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  345.770325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  345.770342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  345.770358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  345.770373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  345.770389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  345.770403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  345.770418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  345.770432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  345.770448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  345.770462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  345.770477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  345.770494] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  345.770512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.770530] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  345.770548] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  345.770568] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  345.770585] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  345.783388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.791919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.800447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.808974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.817500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.826027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.834556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.843082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.851609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.860133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.868660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.877298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.885790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.894264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.902732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.911198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.919673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.928209] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  345.936032] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  345.951013] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  345.951029] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  345.951080] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  345.951913] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  345.953088] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  345.955671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.955687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.955782] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.955798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.960938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.960954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  345.966104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.968579] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  345.969124] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  345.985975] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  345.985997] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  345.986033] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  345.986844] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  345.986884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.002699] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  346.021648] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  346.021675] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  346.021899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.021924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.021946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.021966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.021984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.022002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.022020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.022037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.022054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.022070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.022087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.022103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.022119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.022137] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  346.022160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.022181] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.022304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.022323] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.022353] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  346.022372] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  346.022389] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  346.022415] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  346.022444] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  346.022464] [drm:intel_power_well_disable [i915]] disabling DC off
>[  346.022482] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  346.022498] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  346.023944] [drm:intel_power_well_disable [i915]] disabling always-on
>[  346.024073] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  346.024085] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  346.024146] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  346.024167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  346.024190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  346.024215] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.024235] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.024255] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.024275] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  346.024294] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  346.024313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.024330] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  346.024347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.024351] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.024367] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.024370] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.024388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  346.024405] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.024421] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  346.024437] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.024453] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.024473] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  346.024489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.024506] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  346.024522] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  346.024537] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  346.024558] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.024580] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  346.024600] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  346.024675] [drm:intel_power_well_enable [i915]] enabling always-on
>[  346.025693] [drm:intel_power_well_enable [i915]] enabling DC off
>[  346.026071] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  346.026112] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  346.026144] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  346.026192] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  346.026219] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  346.026261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.026295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.026328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.026358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.026389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.026417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.026448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.026474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.026503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.026530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.026560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.026586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.026614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.026643] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.026679] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.027258] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.027282] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.027311] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  346.027333] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  346.040150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.048743] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.057344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.065944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.074571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.083169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.091765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.100463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.109059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.117655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.126448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.135125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.143662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.152383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.160869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.169341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.177810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.186277] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.194179] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  346.209063] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  346.209079] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  346.209221] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  346.210049] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  346.212336] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  346.213759] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.213774] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.213800] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.213814] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.218952] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.218967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  346.224104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.226578] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  346.227085] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  346.243922] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  346.243945] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  346.243981] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.244827] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  346.244868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.260674] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  346.277948] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  346.277975] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  346.278023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.278046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.278068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.278086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.278103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.278120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.278138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.278155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.278171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.278187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.278204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.278220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.278235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.278254] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  346.278276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.278296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.278315] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.278334] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.278366] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  346.278385] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  346.278402] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  346.278428] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  346.278457] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  346.278477] [drm:intel_power_well_disable [i915]] disabling DC off
>[  346.278496] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  346.278511] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  346.278975] [drm:intel_power_well_disable [i915]] disabling always-on
>[  346.279095] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  346.279108] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  346.279168] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  346.279187] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  346.279210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  346.279234] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.279254] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.279275] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.279296] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  346.279315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  346.279335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.279353] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  346.279371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.279375] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.279392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.279395] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.279412] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  346.279430] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.279447] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  346.279465] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.279481] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.279503] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  346.279520] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.279538] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  346.279555] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  346.279572] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  346.279592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.279616] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  346.279635] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  346.279715] [drm:intel_power_well_enable [i915]] enabling always-on
>[  346.279731] [drm:intel_power_well_enable [i915]] enabling DC off
>[  346.280023] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  346.280047] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  346.280065] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  346.280094] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  346.280111] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  346.280135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.280156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.280176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.280194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.280212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.280230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.280249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.280266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.280283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.280300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.280318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.280334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.280351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.280370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.280392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.280412] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.280432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.280455] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  346.280475] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  346.293300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.301851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.310436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.319006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.327669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.336360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.344916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.353470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.362023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.370611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.379170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.387731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.396241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.404731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.413204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.421673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.430233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.438702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.446524] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  346.460900] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  346.460965] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  346.461109] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  346.462171] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  346.463417] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  346.465714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.465831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.465887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.465944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.472218] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.472273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  346.477787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.480358] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  346.481884] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  346.498942] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  346.499020] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  346.499136] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.500340] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  346.500476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.515558] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  346.533307] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  346.533375] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  346.533488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.533545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.533601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.533649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.533694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.534426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.534480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.534529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.534575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.534621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.534667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.534711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.535362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.535415] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  346.535474] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.535529] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.535579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.535629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.535702] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  346.536345] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  346.536390] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  346.536452] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  346.536529] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  346.536581] [drm:intel_power_well_disable [i915]] disabling DC off
>[  346.536626] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  346.536665] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  346.538008] [drm:intel_power_well_disable [i915]] disabling always-on
>[  346.539130] [drm:drm_mode_addfb2] [FB:68]
>[  346.539202] [drm:drm_mode_addfb2] [FB:110]
>[  346.620624] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  346.621207] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  346.621751] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  346.622218] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  346.622245] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  346.622406] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  346.622464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  346.622527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  346.622593] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.622646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.622704] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.622815] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  346.622880] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.622937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.622987] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  346.623042] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.623055] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.623106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.623116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.623165] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  346.623220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.623267] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  346.623318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.623366] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.623428] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  346.623477] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.623530] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  346.623575] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  346.623625] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  346.623682] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.623774] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  346.623830] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  346.624998] [drm:intel_power_well_enable [i915]] enabling always-on
>[  346.625044] [drm:intel_power_well_enable [i915]] enabling DC off
>[  346.625351] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  346.625417] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  346.625472] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  346.625577] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  346.625623] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  346.625688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.625785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.625835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.625891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.625939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.625991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.626039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.626091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.626136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.626188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.626234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.626281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.626324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.626378] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.626436] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.626491] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.626543] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.626606] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  346.626656] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  346.639964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.648696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.657515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.666233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.674990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.683692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.692260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.719352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.727820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.736287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.744766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.753234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.761730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.770198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.778666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.787165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.793115] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  346.808522] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  346.808538] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  346.808596] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  346.809426] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  346.810867] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  346.813096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.813111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.813125] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.813151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.818288] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.818303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  346.823518] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.825998] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  346.826473] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  346.843337] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  346.843358] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  346.843391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.860084] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  346.860097] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  346.876921] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  346.876983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.893490] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  346.910971] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  346.911027] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  346.911120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.911167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.911212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.911251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.911288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.911324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.911361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.911396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.911431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.911464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.911500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.911534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.911567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.911606] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  346.911652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.911695] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.912620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.912665] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.913031] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  346.913071] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  346.913107] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  346.913159] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  346.913222] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  346.913263] [drm:intel_power_well_disable [i915]] disabling DC off
>[  346.913300] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  346.913332] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  346.914449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  346.914670] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  346.914873] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  346.915001] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  346.915046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  346.915093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  346.915143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  346.915182] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  346.915227] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  346.915269] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  346.915310] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  346.915349] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  346.915386] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  346.915422] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  346.915428] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.915463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  346.915469] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  346.915505] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  346.915540] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  346.915574] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  346.915607] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  346.915640] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  346.915682] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  346.916882] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  346.916933] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  346.916981] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  346.917026] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  346.917080] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  346.917140] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  346.917190] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  346.917370] [drm:intel_power_well_enable [i915]] enabling always-on
>[  346.917410] [drm:intel_power_well_enable [i915]] enabling DC off
>[  346.917710] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  346.918656] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  346.918703] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  346.919020] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  346.919063] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  346.919129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  346.919187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  346.919237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  346.919287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  346.919334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  346.919379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  346.919426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  346.919469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  346.919511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  346.919555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  346.919599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  346.919640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  346.919681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  346.920611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  346.920669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  346.920962] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  346.921016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  346.921078] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  346.921128] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  346.934421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.943151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.951881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.960597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.969324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.978049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.986769] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  346.995486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.004205] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.012922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.021642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.030506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.039152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.047723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.056251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.064753] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.073239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.081710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.085957] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  347.101625] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  347.101642] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  347.101706] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  347.102553] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  347.104023] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  347.106256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.106271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.106285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.106299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.111482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.111497] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  347.116634] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.119092] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  347.119578] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.136453] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.136476] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.136512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.137315] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.137353] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.153198] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.172101] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  347.172128] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  347.172176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.172199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.172221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.172240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.172258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.172276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.172294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.172310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.172327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.172344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.172361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.172377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.172393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.172411] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.172433] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.172454] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.172473] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.172492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.172525] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  347.172543] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  347.172561] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  347.172587] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  347.172616] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.172636] [drm:intel_power_well_disable [i915]] disabling DC off
>[  347.172654] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  347.172669] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  347.173611] [drm:intel_power_well_disable [i915]] disabling always-on
>[  347.173765] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.173779] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  347.173839] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  347.173859] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  347.173884] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  347.173908] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.173927] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.173949] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.173969] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  347.173990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.174009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.174027] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  347.174044] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.174048] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.174065] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.174069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.174087] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  347.174103] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.174121] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  347.174138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.174155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.174176] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  347.174194] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.174211] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  347.174228] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  347.174244] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  347.174265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.174289] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  347.174309] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  347.174384] [drm:intel_power_well_enable [i915]] enabling always-on
>[  347.174399] [drm:intel_power_well_enable [i915]] enabling DC off
>[  347.174685] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  347.175206] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  347.175223] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  347.175259] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  347.175284] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  347.175309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.175330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.175348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.175366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.175383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.175400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.175418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.175435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.175451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.175467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.175484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.175500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.175515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.175533] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.175554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.175574] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.175593] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.175616] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  347.175636] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  347.188496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.197071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.205665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.214359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.222954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.231546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.240139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.248733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.257321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.265909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.274497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.283047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.291566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.300061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.308607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.317075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.325541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.334007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.341842] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  347.356016] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  347.356035] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  347.356079] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  347.357562] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  347.360160] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  347.361498] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.361513] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.361526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.361541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.366767] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.366782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  347.371919] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.374383] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  347.374911] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.391793] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.391816] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.391852] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.392658] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.392745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.408535] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.425678] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  347.425727] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  347.425770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.425791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.425811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.425828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.425844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.425860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.425876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.425891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.425905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.425920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.425935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.425949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.425963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.425980] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.426000] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.426018] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.426036] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.426052] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.426082] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  347.426099] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  347.426114] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  347.426138] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  347.426163] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.426181] [drm:intel_power_well_disable [i915]] disabling DC off
>[  347.426197] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  347.426211] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  347.426630] [drm:intel_power_well_disable [i915]] disabling always-on
>[  347.426840] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.426852] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  347.426906] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  347.426924] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  347.426945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  347.426967] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.426984] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.427004] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.427021] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  347.427039] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.427057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.427073] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  347.427089] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.427093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.427109] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.427111] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.427126] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  347.427142] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.427157] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  347.427173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.427186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.427205] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  347.427221] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.427237] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  347.427252] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  347.427266] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  347.427284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.427306] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  347.427323] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  347.427390] [drm:intel_power_well_enable [i915]] enabling always-on
>[  347.427404] [drm:intel_power_well_enable [i915]] enabling DC off
>[  347.427679] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  347.428191] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  347.428206] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  347.428247] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  347.428267] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  347.428290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.428310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.428327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.428344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.428359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.428375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.428391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.428406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.428421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.428537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.428553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.428568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.428582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.428599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.428618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.428637] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.428653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.428675] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  347.428765] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  347.441533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.450075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.458629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.467180] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.475733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.484284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.492834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.501384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.509935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.518486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.527037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.535589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.544112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.552612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.561093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.569561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.578028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.586494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.594316] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  347.609101] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  347.609120] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  347.609151] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  347.609996] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  347.612305] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  347.613713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.613728] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.613742] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.613757] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.618897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.618912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  347.624050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.626476] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  347.626999] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.643871] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.643894] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.643930] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.644761] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.644802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.660617] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.677895] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  347.677919] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  347.677962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.677982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.678001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.678018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.678035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.678050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.678066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.678081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.678096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.678111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.678126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.678140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.678155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.678171] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.678191] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.678209] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.678226] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.678242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.678272] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  347.678288] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  347.678304] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  347.678327] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  347.678353] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.678370] [drm:intel_power_well_disable [i915]] disabling DC off
>[  347.678387] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  347.678401] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  347.679341] [drm:intel_power_well_disable [i915]] disabling always-on
>[  347.679446] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.679457] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  347.679510] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  347.679527] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  347.679546] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  347.679568] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.679585] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.679602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.679620] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  347.679636] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.679652] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.679668] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  347.679682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.679749] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.679765] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.679770] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.679785] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  347.679800] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.679816] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  347.679830] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.679845] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.679863] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  347.679879] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.679893] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  347.679909] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  347.679923] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  347.679941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.679963] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  347.679980] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  347.680047] [drm:intel_power_well_enable [i915]] enabling always-on
>[  347.680061] [drm:intel_power_well_enable [i915]] enabling DC off
>[  347.680336] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  347.680357] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  347.680372] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  347.680411] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  347.680430] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  347.680452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.680470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.680487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.680503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.680518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.680533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.680548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.680563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.680577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.680591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.680606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.680620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.680634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.680650] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.680668] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.680685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.680798] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.680847] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  347.680866] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  347.693632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.721121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.729676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.738255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.746829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.755379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.763928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.772479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.781031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.789631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.798161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.806654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.815201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.823669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.832214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.840681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.848516] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  347.862531] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  347.862548] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  347.862573] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  347.863408] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  347.864211] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  347.866813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  347.866843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  347.866873] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  347.866889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  347.872266] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  347.872281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  347.877516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  347.879996] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  347.880475] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  347.897415] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.897436] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.897470] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.898269] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.898312] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.914070] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  347.931161] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  347.931184] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  347.931225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.931244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.931262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.931277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.931292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.931306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.931321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.931335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.931348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.931362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.931375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.931388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.931401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.931416] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  347.931434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.931451] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.931467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.931483] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.931510] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  347.931526] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  347.931540] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  347.931562] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  347.931586] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  347.931603] [drm:intel_power_well_disable [i915]] disabling DC off
>[  347.931618] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  347.931630] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  347.932783] [drm:intel_power_well_disable [i915]] disabling always-on
>[  347.932881] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  347.932891] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  347.932942] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  347.932959] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  347.932977] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  347.932997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  347.933013] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  347.933030] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.933046] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  347.933062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  347.933078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  347.933093] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  347.933107] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.933109] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.933123] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.933125] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  347.933139] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  347.933167] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  347.933182] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  347.933196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.933211] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.933229] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  347.933244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.933259] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  347.933274] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  347.933289] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  347.933307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.933328] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  347.933345] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  347.933414] [drm:intel_power_well_enable [i915]] enabling always-on
>[  347.933428] [drm:intel_power_well_enable [i915]] enabling DC off
>[  347.934116] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  347.934400] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  347.934415] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  347.934461] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  347.934484] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  347.934508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  347.934528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  347.934546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  347.934564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  347.934581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  347.934597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  347.934613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  347.934629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  347.934644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  347.934659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  347.934675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  347.934910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  347.934926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  347.934944] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  347.934963] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  347.934981] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  347.934998] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  347.935020] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  347.935038] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  347.947809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.956340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.964899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.973435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.981972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.990508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  347.999042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.007577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.016110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.024644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.033180] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.041722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.050221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.058706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.067177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.075646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.084113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.092581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.100423] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  348.115439] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  348.115454] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  348.115513] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  348.116339] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  348.118174] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  348.120068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.120084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.120098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.120113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.125250] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.125279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  348.130454] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.132934] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  348.133409] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.150271] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.150293] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.150327] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.151199] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.151250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.167023] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.184261] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  348.184284] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  348.184325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.184344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.184362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.184378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.184393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.184408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.184423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.184437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.184451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.184465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.184479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.184492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.184505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.184521] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.184540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.184557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.184574] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.184590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.184618] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  348.184633] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  348.184648] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  348.184670] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  348.185131] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.185152] [drm:intel_power_well_disable [i915]] disabling DC off
>[  348.185170] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  348.185185] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  348.185606] [drm:intel_power_well_disable [i915]] disabling always-on
>[  348.185802] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.185813] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  348.185871] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  348.185891] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  348.185912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  348.185935] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.185953] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.185971] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.185990] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  348.186007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.186025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.186041] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  348.186057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.186060] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.186075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.186077] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.186093] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  348.186109] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.186124] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  348.186139] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.186153] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.186172] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  348.186188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.186203] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  348.186217] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  348.186232] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  348.186250] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.186272] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  348.186289] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  348.186357] [drm:intel_power_well_enable [i915]] enabling always-on
>[  348.186371] [drm:intel_power_well_enable [i915]] enabling DC off
>[  348.186646] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  348.186668] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  348.186683] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  348.187171] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  348.187187] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  348.187210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.187230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.187248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.187266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.187282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.187299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.187315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.187331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.187346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.187361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.187377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.187392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.187407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.187424] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.187443] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.187462] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.187480] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.187502] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  348.187520] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  348.200343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.208875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.217412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.225951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.234510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.243045] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.251580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.260113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.268650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.277267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.285804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.294329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.302829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.311309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.319780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.328247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.336715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.345182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.353650] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.354729] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  348.369228] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  348.369247] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  348.369285] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  348.370341] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  348.372200] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  348.374087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.374102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.374116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.374144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.379312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.379327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  348.384544] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.387023] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  348.387512] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.404366] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.404389] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.404425] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.405238] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.405279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.421113] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.438366] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  348.438393] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  348.438441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.438464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.438486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.438505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.438523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.438541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.438559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.438576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.438592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.438608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.438625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.438641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.438657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.438676] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.438912] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.438936] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.438959] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.438980] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.439014] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  348.439034] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  348.439053] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  348.439080] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  348.439110] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.439130] [drm:intel_power_well_disable [i915]] disabling DC off
>[  348.439149] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  348.439166] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  348.439588] [drm:intel_power_well_disable [i915]] disabling always-on
>[  348.439889] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.439902] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  348.439963] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  348.439984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  348.440007] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  348.440031] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.440050] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.440071] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.440091] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  348.440110] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.440129] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.440146] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  348.440163] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.440166] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.440183] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.440185] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.440202] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  348.440219] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.440235] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  348.440252] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.440268] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.440289] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  348.440305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.440321] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  348.440337] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  348.440353] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  348.440372] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.440396] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  348.440415] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  348.440488] [drm:intel_power_well_enable [i915]] enabling always-on
>[  348.440503] [drm:intel_power_well_enable [i915]] enabling DC off
>[  348.441017] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  348.441321] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  348.441340] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  348.441389] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  348.441408] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  348.441434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.441456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.441475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.441493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.441511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.441528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.441547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.441564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.441581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.441597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.441615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.441631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.441647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.441666] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.441687] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.441845] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.441865] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.441889] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  348.441909] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  348.454785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.463339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.471930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.480570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.489166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.497861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.506453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.515049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.523642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.532331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.540927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.549520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.558086] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.566611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.575113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.583595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.592078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.600543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.608365] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  348.622350] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  348.622368] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  348.622396] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  348.623233] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  348.623973] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  348.626578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.626595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.626611] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.626627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.632063] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.632079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  348.637216] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.639690] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  348.640189] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.657034] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.657057] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.657094] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.657899] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.657937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.673736] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.690912] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  348.690940] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  348.690988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.691011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.691033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.691051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.691069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.691086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.691104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.691121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.691137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.691154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.691171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.691187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.691203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.691222] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.691244] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.691265] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.691284] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.691303] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.691335] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  348.691354] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  348.691371] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  348.691397] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  348.691426] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.691445] [drm:intel_power_well_disable [i915]] disabling DC off
>[  348.691463] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  348.691479] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  348.692449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  348.692563] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.692575] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  348.692636] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  348.692656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  348.692678] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  348.692813] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.692833] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.692856] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.692877] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  348.692898] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.692918] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.692937] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  348.692955] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.692959] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.692976] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.692979] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.692997] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  348.693014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.693032] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  348.693049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.693066] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.693087] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  348.693105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.693122] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  348.693139] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  348.693156] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  348.693177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.693201] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  348.693221] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  348.693296] [drm:intel_power_well_enable [i915]] enabling always-on
>[  348.693312] [drm:intel_power_well_enable [i915]] enabling DC off
>[  348.693589] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  348.693613] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  348.693631] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  348.693679] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  348.693926] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  348.693953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.693974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.693994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.694011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.694029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.694046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.714446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.714472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.714496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.714519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.714543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.714565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.714588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.714613] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.714642] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.714669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.714695] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.714932] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  348.714960] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  348.727828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.736386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.744943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.753525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.762080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.770634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.779185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.787738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.796290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.804814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.813311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.821794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.830265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.838734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.847201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.855667] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.864197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.872665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.881189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  348.882360] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  348.896686] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  348.896751] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  348.896876] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  348.898020] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  348.899112] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  348.901331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.901393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.901450] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.901508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.907721] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.907811] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  348.913278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.915926] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  348.917465] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  348.934458] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.934535] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.934649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.936124] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.936260] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.951138] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  348.968917] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  348.968986] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  348.969100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.969158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.969215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.969263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.969308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.969352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.969398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.969441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.969481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.969522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.969565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.969604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.969644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.969692] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  348.970624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.970680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.970919] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.970971] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.971046] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  348.971092] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  348.971137] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  348.971200] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  348.971275] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  348.971324] [drm:intel_power_well_disable [i915]] disabling DC off
>[  348.971370] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  348.971409] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  348.972624] [drm:intel_power_well_disable [i915]] disabling always-on
>[  348.972996] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  348.973023] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  348.973176] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  348.973229] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  348.973286] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  348.973347] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  348.973396] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  348.973449] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  348.973501] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  348.973548] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  348.973596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  348.973641] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  348.973684] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  348.974403] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.974451] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  348.974459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  348.974507] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  348.974551] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  348.974595] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  348.974637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  348.974679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  348.975186] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  348.975235] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  348.975283] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  348.975336] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  348.975386] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  348.975450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  348.975508] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  348.975558] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  348.976175] [drm:intel_power_well_enable [i915]] enabling always-on
>[  348.976214] [drm:intel_power_well_enable [i915]] enabling DC off
>[  348.976529] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  348.976588] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  348.976629] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  348.977041] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  348.977083] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  348.977147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  348.977201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  348.977249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  348.977296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  348.977341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  348.977386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  348.977431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  348.977472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  348.977513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  348.977554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  348.977597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  348.977638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  348.977678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  348.978419] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  348.978475] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  348.978525] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  348.978575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  348.978636] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  348.978685] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  348.992340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.001076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.009805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.018524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.027248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.035985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.044887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.053656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.062487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.071208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.079876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.088459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.097004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.105517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.114006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.122484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.130954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.139423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.145561] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  349.159533] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  349.159550] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  349.159598] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  349.160438] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  349.161225] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  349.163825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.163842] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.163857] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.163873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.169282] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.169298] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  349.174536] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.177011] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  349.177499] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.194294] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.194316] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.194352] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.195224] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.195263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.211089] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.228281] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  349.228306] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  349.228348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.228369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.228388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.228405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.228421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.228437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.228453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.228468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.228482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.228497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.228512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.228526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.228540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.228557] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.228576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.228595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.228612] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.228629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.228659] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  349.228675] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  349.229351] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  349.229384] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  349.229418] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.229438] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.229456] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  349.229472] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  349.230404] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.230518] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.230530] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  349.230592] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  349.230613] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  349.230637] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  349.230661] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.230681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.230978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.231007] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  349.231036] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.231062] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.231089] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  349.231113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.231118] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.231142] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.231147] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.231173] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  349.231196] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.231222] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  349.231245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.231269] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.231297] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  349.231322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.231346] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  349.231370] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  349.231393] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  349.231422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.231455] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  349.231482] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  349.231589] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.231610] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.232463] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  349.232834] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  349.232861] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  349.232907] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  349.232924] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  349.232950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.232972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.232991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.233010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.233028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.233046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.233064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.233081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.233098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.233114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.233131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.233147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.233163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.233182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.233202] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.233222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.233240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.233264] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  349.233283] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  349.246145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.254703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.263291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.271852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.280431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.288987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.297545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.306127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.314687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.323266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.331822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.340362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.348875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.357362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.365839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.374307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.382776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.391245] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.399070] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  349.413615] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  349.413634] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  349.413665] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  349.414656] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  349.417255] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  349.418594] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.418610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.418625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.418639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.423780] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.423795] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  349.428936] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.431363] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  349.431897] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.448757] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.448780] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.448816] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.449614] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.449651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.465508] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.482817] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  349.482844] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  349.482893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.482916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.482939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.482958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.482976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.482993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.483012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.483029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.483046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.483062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.483079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.483095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.483111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.483130] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.483152] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.483172] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.483192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.483211] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.483244] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  349.483262] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  349.483280] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  349.483306] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  349.483335] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.483354] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.483373] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  349.483389] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  349.484321] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.484483] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.484500] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  349.484590] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  349.484618] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  349.484651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  349.484685] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.484794] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.484824] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.484855] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  349.484882] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.484910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.484934] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  349.484959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.484964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.484989] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.484994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.485019] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  349.485043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.485068] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  349.485091] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.485116] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.485144] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  349.485169] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.485192] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  349.485216] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  349.485239] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  349.485270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.485303] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  349.485330] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  349.485438] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.485462] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.485880] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  349.486262] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  349.486290] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  349.486334] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  349.486360] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  349.486395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.486425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.486452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.486478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.486504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.486527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.486554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.486576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.486601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.486623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.486649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.486671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.486696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.486835] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.486866] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.486896] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.486925] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.486959] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  349.486986] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  349.499759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.508392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.516950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.525531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.534085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.542638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.551192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.559748] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.568303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.576857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.585434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.593968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.602474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.610960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.619430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.627898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.636365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.644832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.652652] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  349.667413] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  349.667430] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  349.667471] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  349.668299] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  349.670084] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  349.671958] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.671973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.671987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.672001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.677141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.677156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  349.682294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.684770] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  349.685258] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.714396] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.714419] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.714455] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.715269] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.715309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.718795] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.735969] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  349.735991] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  349.736029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.736047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.736064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.736079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.736092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.736106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.736120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.736133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.736146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.736159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.736172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.736184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.736196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.736211] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.736228] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.736243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.736258] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.736273] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.736299] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  349.736314] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  349.736327] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  349.736348] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  349.736370] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.736386] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.736400] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  349.736412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  349.737338] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.737458] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.737471] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  349.737541] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  349.737562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  349.737586] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  349.737612] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.737632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.737655] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.737676] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  349.737765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.737786] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.737806] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  349.737825] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.737829] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.737848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.737852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.737872] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  349.737891] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.737911] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  349.737929] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.737948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.737970] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  349.737990] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.738008] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  349.738027] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  349.738045] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  349.738069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.738094] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  349.738115] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  349.738199] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.738218] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.738497] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  349.738525] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  349.738545] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  349.738581] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  349.738601] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  349.738628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.738650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.738672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.738690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.738828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.738848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.738870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.738888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.738908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.738927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.738947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.738965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.738984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.739004] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.739028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.739051] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.739074] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.739099] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  349.739120] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  349.751780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.760262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.768738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.777213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.785687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.794177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.802651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.811124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.819598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.828084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.836552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.845019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.853487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.861956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.870423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.878891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.887357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.895825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.904291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  349.905365] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  349.919388] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  349.919404] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  349.919431] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  349.920265] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  349.921056] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  349.923667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  349.923684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  349.923756] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  349.923778] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  349.929125] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  349.929141] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  349.934280] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  349.936756] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  349.937245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  349.954104] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.954127] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.954164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.954972] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.955013] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.970788] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  349.987929] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  349.987956] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  349.988005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.988027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.988049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.988068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.988085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.988103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.988120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.988137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.988153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.988169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.988186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.988202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.988217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.988236] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  349.988258] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.988279] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.988298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.988317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.988350] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  349.988368] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  349.988386] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  349.988412] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  349.988441] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  349.988461] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.988480] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  349.988495] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  349.989428] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.989591] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  349.989608] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  349.989699] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  349.989801] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  349.989833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  349.989868] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  349.989895] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  349.989926] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.989954] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  349.989983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  349.990010] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  349.990037] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  349.990061] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.990067] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.990091] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.990096] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  349.990122] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  349.990146] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  349.990172] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  349.990195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.990220] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.990249] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  349.990274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.990297] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  349.990323] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  349.990345] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  349.990376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.990408] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  349.990436] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  349.990544] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.990569] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.991113] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  349.991409] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  349.991435] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  349.991479] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  349.991505] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  349.991541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  349.991570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  349.991599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  349.991625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  349.991651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  349.991675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  349.991792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  349.991817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  349.991843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  349.991866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  349.991893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  349.991916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  349.991941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  349.991967] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  349.991998] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  349.992028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  349.992058] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  349.992091] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  349.992119] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.004997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.013558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.022117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.030672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.039336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.047889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.056441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.064995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.073551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.082132] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.090685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.099240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.107743] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.116227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.124700] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.133166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.141635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.150102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  350.157924] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  350.172495] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  350.172515] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  350.172567] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  350.173450] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  350.174891] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  350.177144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.177160] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.177174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.177188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.182327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.182342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.187497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.189974] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  350.190462] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  350.207317] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  350.207341] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  350.207377] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.208191] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  350.208232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.224052] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  350.241416] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  350.241444] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.241492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.241515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.241537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.241556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.241575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.241592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.241611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.241628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.241644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.241660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.241677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.241849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.241875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.241906] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  350.241941] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.241973] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.242004] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.242034] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.242079] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  350.242107] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  350.242135] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.242175] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.242217] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  350.242247] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.242275] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.242298] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.243233] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.243803] [drm:drm_mode_addfb2] [FB:68]
>[  350.243831] [drm:drm_mode_addfb2] [FB:110]
>[  350.393003] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.393344] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  350.393393] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  350.393443] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.393452] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.393505] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.393520] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.393537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.393555] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.393568] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.393583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.393598] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.393611] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.393625] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.393637] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.393649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.393651] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.393663] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.393665] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.393677] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.393747] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.393772] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.393786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.393814] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.393831] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.393845] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.393858] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.393872] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.393886] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.393909] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.393929] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.393945] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.395033] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.395044] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.395332] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.395350] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.395362] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.395383] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.395401] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.395424] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.395581] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.395596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.395610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.395623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.395635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.395647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.395658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.395670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.395681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.395751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.395763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.395791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.395805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.395817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.395832] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.395848] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.395863] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.395878] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.395897] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.395912] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.399163] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.399180] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.399195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.399210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.399861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.399876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.399889] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.400524] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.400538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.400551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.401201] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.401215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.402181] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.404454] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  350.405012] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.405037] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.405050] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.405069] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.405124] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.405137] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.421901] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.421921] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.421953] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.438558] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.438569] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.455350] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.455414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.471957] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  350.472000] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  350.472067] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  350.489388] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  350.489457] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  350.489517] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.489624] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.490033] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.490114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.490197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.490269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.490341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.490403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.490470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.490534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.490599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.490658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.490723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.491137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.491205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.491265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.491337] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.491420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.491498] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.491574] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.491642] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.491948] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  350.492021] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  350.492093] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.492191] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.492297] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.492385] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.492456] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.492513] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.493484] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.493907] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.493936] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.494091] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.494144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.494201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.494263] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.494313] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.494366] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.494418] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.494466] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.494515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.494559] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.494602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.494611] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.494653] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.494660] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.494704] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.495042] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.495106] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.495173] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.495232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.495311] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.495370] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.495435] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.495493] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.495557] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.495657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.495742] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.496037] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.496278] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.496334] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.496659] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.496914] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.496982] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.497076] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.497135] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.497225] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.499470] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.499538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.499603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.499658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.499709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.500040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.500109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.500185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.500249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.500318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.500379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.500445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.500505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.500565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.500638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.500720] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.501024] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.501096] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.501185] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.501253] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.504895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.504953] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.505004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.505059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.506084] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.506154] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.506227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.507188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.507240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.507287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.508189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.508242] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.509439] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.511879] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  350.513295] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.513382] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.513434] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.513504] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.513627] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.513680] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.530286] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.530363] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.530477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.531149] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.531299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.547025] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  350.547101] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  350.547215] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  350.564684] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  350.564817] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  350.564880] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.564989] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.567201] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.567267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.567329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.567384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.567434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.567482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.567528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.567576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.567622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.567666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.567711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.567857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.567929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.567993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.568065] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.568151] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.568237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.568315] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.568392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.568499] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  350.568573] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  350.568645] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.568806] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.568916] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.569006] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.569078] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.569253] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.569795] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.570492] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.570533] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.570834] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.570918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.570998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.571090] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.571157] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.571236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.571308] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.571382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.571451] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.571521] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.571584] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.571599] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.571662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.571674] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.571765] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.571831] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.571900] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.571961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.572028] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.572103] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.572170] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.572234] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.572302] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.572362] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.572464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.572548] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.572620] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.572928] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.572985] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.573321] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.573413] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.573473] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.573569] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.573633] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.573726] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.574031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.574108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.574188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.574259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.574330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.574394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.574461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.574526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.574591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.574651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.574716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.574852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.574922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.574984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.575060] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.575144] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.575221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.575298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.575387] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.575456] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.579103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.579162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.579213] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.579265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.580290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.580343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.580392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.581439] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.581490] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.581539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.582555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.582607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.583884] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.586326] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  350.587865] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.587946] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.587998] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.588066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.588188] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.588242] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.604889] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.604966] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.605081] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.605518] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.605667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.621523] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  350.621595] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  350.621702] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  350.639081] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  350.639148] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  350.639209] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.639315] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.641576] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.641641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.641703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.641993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.642062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.642135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.642199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.642274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.642336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.642402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.642462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.642537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.642596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.642662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.642728] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.643041] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.643121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.643198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.643266] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.643364] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  350.643434] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  350.643505] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.643599] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.643701] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.644006] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.644079] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.644137] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.644616] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.645107] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.645134] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.645286] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.645341] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.645399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.645461] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.645511] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.645564] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.645617] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.645666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.645714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.646013] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.646076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.646092] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.646156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.646168] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.646237] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.646299] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.646366] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.646427] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.646492] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.646564] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.646630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.646690] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.646988] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.647048] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.647152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.647341] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.647411] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.647650] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.647707] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.648226] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.648317] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.648382] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.648476] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.648535] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.648626] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.648980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.649062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.649136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.649212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.649276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.649345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.649406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.649476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.649534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.649599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.649659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.649723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.650013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.650071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.650143] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.650224] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.650301] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.650375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.650463] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.650530] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.654167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.654227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.654278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.654330] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.655450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.655503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.655551] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.656558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.656609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.656656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.657649] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.657702] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.659070] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.661454] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  350.662977] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.663054] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.663104] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.663171] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.663286] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.663339] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.679957] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.680035] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.680149] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.680594] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.680860] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.714700] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  350.714834] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  350.714955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  350.730172] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  350.730240] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  350.730301] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.730408] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.730612] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.730669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.730822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.730905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.730976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.731044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.731109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.731184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.731247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.731316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.731377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.731453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.731513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.731580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.731648] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.731734] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.731885] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.731963] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.732039] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.732145] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  350.732217] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  350.732288] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.732385] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.732487] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.732575] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.732646] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.732704] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.733259] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.733648] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.733751] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.733981] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.734053] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.734136] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.734224] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.734292] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.734369] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.734440] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.734512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.734578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.734646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.734707] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.734767] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.734830] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.734849] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.734920] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.734984] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.735052] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.735115] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.735182] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.735255] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.735325] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.735386] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.735451] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.735510] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.735611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.735694] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.735803] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.736051] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.736107] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.736448] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.736541] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.736602] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.736698] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.736829] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.736930] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.737269] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.737345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.737422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.737493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.737563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.737625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.737690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.737834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.737902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.737970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.738034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.738102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.738164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.738230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.738299] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.738382] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.738458] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.738534] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.738620] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.738688] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.742438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.742497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.742549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.742602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.743536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.743589] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.743638] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.744547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.744599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.744649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.745611] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.745665] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.746934] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.749316] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  350.750710] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.750817] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.750866] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.750934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.751060] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.751111] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.767715] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.767846] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.767962] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.768426] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.768576] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.784462] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  350.784538] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  350.784654] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  350.801926] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  350.801996] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  350.802057] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.802165] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.802335] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.802391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.802448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.802499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.802545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.802589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.802632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.802677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.802805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.802872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.802940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.803016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.803078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.803148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.803217] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.803304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.803379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.803457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.803641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.803805] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  350.803877] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  350.803949] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.804048] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.804153] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.804242] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.804314] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.804372] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.804901] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.805617] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.805657] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.805951] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.806025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.806108] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.806197] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.806266] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.806344] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.806416] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.806490] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.806556] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.806626] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.806688] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.806753] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.806814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.806833] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.806904] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.806967] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.807035] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.807097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.807162] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.807238] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.807305] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.807368] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.807436] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.807495] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.807598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.807682] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.807790] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.808034] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.808091] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.808415] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.808505] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.808565] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.808660] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.808725] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.808882] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.811260] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.811328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.811392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.811447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.811497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.811545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.811593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.811643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.811688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.811823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.811890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.811957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.812022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.812083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.812159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.812244] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.812323] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.812399] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.812487] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.812560] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.816236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.816295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.816345] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.816398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.817330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.817382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.817431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.818330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.818381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.818430] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.819318] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.819371] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.820562] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.823028] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  350.824529] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.824613] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.824663] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.824934] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.825114] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.825185] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.841518] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.841594] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.841710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.842451] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.842599] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.858255] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  350.858330] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  350.858444] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  350.875837] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  350.875908] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  350.875969] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.876077] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.876282] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.876339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.876396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.876446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.876492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.876537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.876580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.876626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.876668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.876709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.877105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.877181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.877243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.877308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.877375] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.877459] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.877537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.877608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.877681] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.877994] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  350.878066] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  350.878138] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.878234] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.878339] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.878428] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.878498] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.878555] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.879536] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.880066] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.880106] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.880310] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.880364] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.880422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.880485] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.880535] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.880588] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.880639] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.880687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.880980] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.881046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.881115] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.881129] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.881194] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.881207] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.881274] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.881335] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.881402] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.881462] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.881526] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.881598] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.881999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.882062] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.882129] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.882188] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.882291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.882376] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.882446] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.882690] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.882945] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.883277] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.883370] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.883430] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.883528] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.883591] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.883682] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.886239] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.886304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.886367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.886421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.886471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.886518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.886564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.886613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.886659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.886704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.887027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.887090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.887157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.887218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.887293] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.887374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.887454] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.887531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.887619] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.887688] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.891499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.891557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.891609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.891662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.892815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.892869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.892919] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.893981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.894053] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.894127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.895115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.895168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.896375] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.898803] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  350.900259] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.900344] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.900395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.900463] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.900584] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.900636] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.917240] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.917318] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.917433] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.918146] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.918294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  350.933928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  350.934001] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  350.934109] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  350.951520] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  350.951590] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  350.951651] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  350.952060] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.954408] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.954474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.954538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.954594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.954645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.954693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.955002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.955074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.955145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.955210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.955280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.955356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.955417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.955483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.955551] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.955634] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.955713] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.956019] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.956095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.956201] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  350.956271] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  350.956341] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  350.956437] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  350.956539] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.956627] [drm:intel_power_well_disable [i915]] disabling DC off
>[  350.956698] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  350.956980] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  350.957457] [drm:intel_power_well_disable [i915]] disabling always-on
>[  350.957940] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.957969] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  350.958123] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  350.958177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  350.958235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  350.958297] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  350.958346] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  350.958400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  350.958453] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  350.958503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  350.958551] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  350.958597] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  350.958641] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  350.958649] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.958693] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  350.958967] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  350.959035] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  350.959100] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  350.959168] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  350.959230] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  350.959297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  350.959370] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  350.959437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  350.959497] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  350.959563] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  350.959620] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  350.959721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  350.960144] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  350.960211] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  350.960454] [drm:intel_power_well_enable [i915]] enabling always-on
>[  350.960518] [drm:intel_power_well_enable [i915]] enabling DC off
>[  350.961014] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  350.961373] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  350.961438] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  350.961533] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  350.961593] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  350.961684] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  350.962109] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  350.962186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  350.962266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  350.962336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  350.962407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  350.962470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  350.962538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  350.962602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  350.962669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  350.962731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  350.963025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  350.963091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  350.963151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  350.963215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  350.963281] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  350.963359] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.963428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  350.963501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  350.963586] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  350.963654] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  350.967471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.967529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.967579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.967631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.968568] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  350.968622] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  350.968670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.969650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  350.969702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  350.969846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  350.970747] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.970892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  350.972144] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.974537] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  350.976094] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.976174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  350.976224] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  350.976293] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  350.976415] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.976466] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.993068] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  350.993144] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  350.993260] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  350.993816] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  350.994006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.009861] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.009937] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.010050] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.027480] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.027549] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.027611] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.027720] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.028062] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.028125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.028189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.028243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.028294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.028341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.028388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.028437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.028483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.028527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.028570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.028619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.028662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.028704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.028841] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.028927] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.029004] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.029080] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.029152] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.029260] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.029329] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.029400] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.029467] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.029540] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.029599] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.029645] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.029686] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.030213] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.030518] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.030546] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.030698] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.030828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.030915] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.031006] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.031061] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.031118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.031172] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.031223] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.031273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.031322] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.031368] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.031380] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.031422] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.031431] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.031476] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.031520] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.031563] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.031605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.031648] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.031701] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.031807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.031871] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.031935] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.031998] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.032100] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.032182] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.032254] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.032492] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.032533] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.032909] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.033384] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.033440] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.033524] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.033565] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.033628] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.038110] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.038180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.038244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.038298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.038347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.038395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.038442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.038491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.038536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.038580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.038624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.038667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.038710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.038850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.038925] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.039011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.039090] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.039165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.039253] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.039326] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.043003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.043061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.043111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.043164] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.044121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.044172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.044219] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.045279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.045329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.045374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.046347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.046398] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.047597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.050039] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  351.051500] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.051588] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.051639] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.051707] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.051970] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.052025] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.068476] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.068553] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.068669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.069416] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.069571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.085168] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.085240] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.085348] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.102674] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.102807] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.102869] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.102977] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.105235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.105302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.105365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.105421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.105471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.105519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.105567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.105616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.105660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.105704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.105973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.106037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.106087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.106138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.106194] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.106256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.106314] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.106369] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.106423] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.106503] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.106555] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.106606] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.106675] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.106920] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.106985] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.107036] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.107083] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.107536] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.107936] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.107965] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.108123] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.108178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.108237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.108302] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.108354] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.108407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.108461] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.108510] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.108558] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.108605] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.108650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.108658] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.108702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.108907] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.108958] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.109005] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.109052] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.109101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.109144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.109201] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.109250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.109293] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.109339] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.109386] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.109459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.109521] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.109575] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.109910] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.109954] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.110277] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.110343] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.110393] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.110493] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.110538] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.110604] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.110887] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.110945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.111003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.111053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.111103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.111150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.111198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.111243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.111288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.111331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.111375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.111418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.111462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.111504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.111554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.111608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.111659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.111709] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.111952] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.112002] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.115587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.115645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.115697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.115920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.116935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.116987] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.117035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.117940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.117996] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.118047] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.118931] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.118985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.120175] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.122611] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  351.123987] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.124074] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.124126] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.124195] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.124318] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.124370] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.140964] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.141041] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.141156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.141605] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.141835] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.157639] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.157712] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.157893] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.175213] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.175284] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.175344] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.175452] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.179991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.180061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.180127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.180183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.180234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.180282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.180328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.180376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.180421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.180464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.180509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.180558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.180602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.180645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.180696] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.181448] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.181507] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.181563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.181616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.181696] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.182020] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.182071] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.182139] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.182221] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.182283] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.182333] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.182378] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.183411] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.183678] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.183864] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.184027] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.184085] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.184148] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.184218] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.184272] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.184328] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.184385] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.184437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.184489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.184538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.184586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.184596] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.184642] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.184651] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.184698] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.185374] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.185423] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.185470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.185515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.185571] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.185618] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.185664] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.185709] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.186100] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.186179] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.186243] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.186297] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.186469] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.186512] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.187115] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.187457] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.187508] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.187608] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.187650] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.187715] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.188297] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.188354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.188408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.188460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.188507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.188552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.188595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.188640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.188682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.189129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.189176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.189222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.189266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.189309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.189358] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.189414] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.189465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.189516] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.189577] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.189628] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.193255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.193313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.193364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.193417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.194315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.194366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.194413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.195290] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.195338] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.195384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.196276] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.196326] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.197512] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.199896] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  351.201336] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.201420] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.201469] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.201535] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.201660] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.201711] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.218320] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.218396] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.218512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.219220] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.219371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.234988] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.235059] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.235167] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.252405] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.252473] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.252534] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.252639] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.253006] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.253065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.253121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.253174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.253222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.253268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.253314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.253361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.253405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.253447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.253489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.253536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.253577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.253618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.253666] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.254305] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.254360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.254409] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.254458] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.254527] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.254572] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.254617] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.254678] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.255123] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.255182] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.255228] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.255270] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.256224] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.256474] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.256498] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.256950] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.257005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.257065] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.257126] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.257177] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.257230] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.257283] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.257333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.257381] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.257425] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.257470] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.257479] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.257522] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.257530] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.257574] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.257619] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.257661] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.257704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.258444] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.258498] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.258546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.258592] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.258636] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.258679] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.259030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.259090] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.259142] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.259302] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.259341] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.259642] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.259702] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.260093] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.260192] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.260235] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.260303] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.260470] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.260525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.260578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.260629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.260676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.261118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.261166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.261214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.261259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.261302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.261346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.261389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.261431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.261472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.261521] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.261574] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.261623] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.261673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.262210] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.262260] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.265901] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.265959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.266010] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.266064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.267124] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.267176] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.267223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.268293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.268345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.268393] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.269416] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.269469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.270861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.273311] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  351.274806] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.274894] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.274945] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.275013] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.275130] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.275183] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.291872] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.291952] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.292069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.292545] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.292702] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.308463] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.308538] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.308650] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.326069] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.326138] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.326199] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.326307] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.330664] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.330731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.331002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.331064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.331120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.331172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.331224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.331280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.331335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.331386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.331434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.331491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.331537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.331586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.331640] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.331701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.331934] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.331990] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.332044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.332120] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.332171] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.332220] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.332285] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.332358] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.332420] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.332470] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.332512] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.333472] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.333837] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.333866] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.334023] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.334078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.334139] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.334204] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.334256] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.334311] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.334365] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.334416] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.334466] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.334512] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.334558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.334566] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.334611] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.334619] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.334665] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.335022] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.335072] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.335119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.335165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.335222] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.335271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.335317] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.335363] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.335407] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.335483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.335546] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.335601] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.335911] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.335955] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.336263] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.336329] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.336382] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.336482] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.336532] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.336596] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.337324] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.337381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.337435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.337485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.337531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.337576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.337620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.337666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.337708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.337808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.337861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.337904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.337945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.337988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.338038] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.338093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.338146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.338198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.338262] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.338315] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.341942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.342002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.342054] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.342107] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.343326] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.343379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.343428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.344436] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.344489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.344537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.345593] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.345647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.346951] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.349335] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  351.350870] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.350956] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.351008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.351075] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.351201] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.351252] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.367859] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.367935] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.368050] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.368548] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.368700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.384521] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.384594] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.384703] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.401926] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.401994] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.402054] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.402159] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.402364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.402418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.402473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.402523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.402569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.402611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.402654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.402698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.402826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.402895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.402963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.403034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.403102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.403162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.403238] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.403325] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.403406] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.403483] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.403557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.403663] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.403792] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.403868] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.403965] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.404069] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.404157] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.404228] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.404286] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.404832] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.405562] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.405600] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.405890] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.405964] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.406049] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.406137] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.406206] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.406285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.406357] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.406432] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.406501] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.406571] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.406632] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.406647] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.406712] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.406777] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.406841] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.406917] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.406981] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.407048] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.407111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.407192] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.407256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.407326] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.407388] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.407459] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.407564] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.407642] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.407724] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.408002] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.408059] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.408385] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.408477] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.408537] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.408633] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.408696] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.408848] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.409205] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.409284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.409364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.409434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.409505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.409568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.409635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.409699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.409830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.409895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.409962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.410022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.410089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.410148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.410222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.410304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.410381] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.410458] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.410546] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.410615] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.414362] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.414420] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.414472] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.414525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.415460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.415512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.415561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.416465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.416515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.416563] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.417465] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.417517] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.418777] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.421163] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  351.422553] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.422642] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.422693] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.422854] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.423032] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.423104] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.439539] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.439617] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.439853] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.440433] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.440583] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.456231] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.456303] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.456411] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.473591] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.473658] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.473719] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.473975] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.474217] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.474273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.474329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.474381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.474430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.474476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.474520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.474567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.474609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.474652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.474693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.474844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.474922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.474983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.475058] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.475145] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.475225] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.475304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.475484] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.475588] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.475660] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.475790] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.475891] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.475994] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.476082] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.476153] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.476211] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.476686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.477476] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.477515] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.477743] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.477877] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.477970] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.478059] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.478129] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.478206] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.478278] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.478351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.478418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.478487] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.478549] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.478564] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.478624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.478636] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.478704] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.478819] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.478884] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.478951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.479011] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.479090] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.479154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.479223] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.479284] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.479350] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.479454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.479539] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.479608] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.479903] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.479961] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.480302] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.480393] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.480457] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.480551] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.480609] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.480699] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.481063] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.481145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.481227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.481301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.481372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.481439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.481505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.481573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.481636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.481699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.481835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.481902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.481966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.482030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.482104] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.482188] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.482266] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.482342] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.482431] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.482508] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.486252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.486333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.486407] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.486486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.487674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.487790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.487861] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.488743] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.488949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.489001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.489917] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.489968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.491311] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.493784] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  351.495236] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.495328] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.495378] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.495446] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.495562] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.495612] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.512219] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.512296] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.512410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.513021] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.513178] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.528895] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.528966] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.529073] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.546368] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.546440] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.546501] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.546611] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.548896] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.548961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.549025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.549080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.549130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.549179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.549227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.549276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.549321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.549365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.549409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.549458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.549502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.549545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.549596] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.549654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.549709] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.550038] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.550093] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.550172] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.550224] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.550274] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.550340] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.550417] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.550480] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.550531] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.550575] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.551537] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.551891] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.551919] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.552076] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.552131] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.552194] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.552259] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.552310] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.552364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.552419] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.552470] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.552519] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.552567] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.552614] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.552622] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.552668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.552674] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.552889] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.552940] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.552990] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.553035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.553081] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.553139] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.553188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.553237] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.553283] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.553331] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.553406] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.553578] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.553633] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.553964] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.554011] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.554315] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.554380] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.554437] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.554531] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.554574] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.554641] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.554895] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.554952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.555008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.555061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.555110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.555157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.555202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.555251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.555294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.555337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.555381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.555423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.555467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.555509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.555558] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.555611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.555662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.555712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.555951] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.556002] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.559581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.559639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.559690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.559913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.560933] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.560985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.561033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.561940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.561995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.562044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.562936] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.562989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.564189] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.566625] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  351.568001] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.568086] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.568138] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.568205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.568327] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.568380] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.585050] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.585127] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.585242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.585778] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.585935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.601682] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.601793] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.601903] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.619153] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.619221] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.619281] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.619387] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.619551] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.619606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.619661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.619712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.619832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.619888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.619941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.619992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.620045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.620089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.620138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.620188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.620239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.620282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.620336] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.620394] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.620453] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.620508] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.620556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.620631] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.620682] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.620765] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.620836] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.620905] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.620963] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.621011] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.621054] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.621506] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.621795] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.621821] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.621967] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.622019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.622079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.622143] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.622194] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.622250] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.622302] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.622352] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.622401] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.622450] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.622495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.622507] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.622550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.622557] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.622603] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.622647] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.622693] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.622777] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.622823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.622885] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.622936] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.622983] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.623032] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.623077] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.623153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.623216] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.623274] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.623436] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.623478] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.623822] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.623885] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.623933] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.624035] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.624080] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.624144] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.624349] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.624406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.624460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.624511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.624557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.624603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.624648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.624696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.624790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.624837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.624882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.624927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.624971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.625016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.625070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.625129] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.625182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.625234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.625300] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.625355] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.628925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.628983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.629035] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.629088] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.630056] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.630109] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.630161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.631096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.631144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.631190] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.632165] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.632215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.633399] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.635838] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  351.637191] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.637280] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.637331] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.637397] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.637511] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.637562] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.654169] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.654246] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.654360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.654883] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.655036] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.670883] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.670955] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.671062] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.688278] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.688346] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.688405] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.688510] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.688715] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.688848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.688919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.688978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.689026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.689077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.689126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.689179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.689225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.689276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.689322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.689374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.689418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.689465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.689515] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.689576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.689629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.689680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.689763] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.689837] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.689883] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.689933] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.689996] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.690067] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.690126] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.690174] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.690216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.690667] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.690957] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.690983] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.691131] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.691184] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.691244] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.691306] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.691358] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.691412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.691464] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.691515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.691564] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.691612] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.691656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.691666] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.691710] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.691759] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.691805] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.691852] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.691903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.691948] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.691994] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.692050] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.692097] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.692142] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.692186] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.692231] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.692305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.692370] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.692428] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.692592] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.692633] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.692997] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.693061] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.693114] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.693210] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.693252] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.693317] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.693480] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.693537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.693592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.693643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.693689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.693784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.693834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.693885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.693933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.693976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.694026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.714343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.714387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.714429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.714478] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.714533] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.714582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.714631] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.714689] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.714787] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.718369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.718428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.718479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.718532] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.719696] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.719792] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.719840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.720701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.720994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.721045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.721986] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.722039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.723387] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.725772] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  351.726702] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.726900] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.726938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.726985] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.727068] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.727105] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.743840] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.743893] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.743974] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.744281] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.744384] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.760484] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.760556] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.760665] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.778164] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.778232] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.778293] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.778399] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.778646] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.778702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.779113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.779168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.779217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.779263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.779307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.779354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.779398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.779442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.779484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.779533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.779575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.779616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.779664] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.780234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.780290] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.780342] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.780391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.780461] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.780507] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.780551] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.780611] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.780682] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.781111] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.781158] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.781199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.781648] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.782101] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.782127] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.782275] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.782327] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.782384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.782445] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.782495] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.782545] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.782596] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.782645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.782691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.783204] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.783251] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.783260] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.783305] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.783314] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.783359] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.783403] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.783447] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.783489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.783531] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.783582] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.783627] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.783670] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.783712] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.784296] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.784371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.784430] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.784481] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.784639] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.784677] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.785265] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.785327] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.785373] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.785469] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.785511] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.785575] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.786102] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.786160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.786218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.786269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.786317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.786364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.786410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.786457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.786501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.786544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.786586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.786630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.786671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.786713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.787302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.787358] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.787408] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.787456] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.787516] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.787566] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.791145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.791202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.791253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.791306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.792528] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.792579] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.792629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.793651] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.793705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.793933] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.794942] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.794995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.796279] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.798667] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  351.800123] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.800205] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.800255] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.800322] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.800440] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.800491] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.817097] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.817173] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.817289] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.817943] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.818101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.833821] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.833894] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.834001] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.851196] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.851263] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.851322] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.851429] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.851596] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.851652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.851707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.852131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.852182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.852230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.852275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.852323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.852367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.852410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.852453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.852501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.852544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.852586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.852635] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.852691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.853254] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.853306] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.853355] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.853425] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.853471] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.853516] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.853577] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.853648] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.853704] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.854128] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.854170] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.854621] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.855068] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.855094] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.855245] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.855299] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.855356] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.855417] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.855467] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.855518] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.855569] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.855618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.855665] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.855710] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.856248] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.856259] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.856304] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.856312] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.856358] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.856402] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.856446] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.856489] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.856532] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.856584] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.856628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.856672] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.857191] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.857236] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.857309] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.857369] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.857420] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.857578] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.857618] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.858251] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.858574] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.858620] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.858718] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.858990] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.859056] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.859302] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.859359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.859412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.859463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.859509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.859553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.859598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.859645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.859687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.860176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.860221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.860265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.860309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.860351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.860400] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.860455] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.860506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.860555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.860615] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.860665] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.864685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.864785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.864836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.864888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.866191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.866243] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.866292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.867340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.867393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.867441] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.868552] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.868605] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.869863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.872297] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  351.873793] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.873880] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.873932] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.874000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.874116] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.874167] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.890823] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.890900] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.891015] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.891463] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.891612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.907448] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.907520] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.907629] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.924859] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.924927] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.924987] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.925093] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.925304] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.925360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.925416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.925467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.925514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.925559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.925603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.925649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.925692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.926328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.926377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.926431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.926477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.926522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.926572] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.926628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.926683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.927100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.927152] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.927222] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  351.927268] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  351.927313] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  351.927373] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  351.927445] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.927502] [drm:intel_power_well_disable [i915]] disabling DC off
>[  351.927547] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  351.927587] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  351.928867] [drm:intel_power_well_disable [i915]] disabling always-on
>[  351.929115] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.929140] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  351.929289] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  351.929340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.929399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  351.929460] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  351.929509] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  351.929560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.929611] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  351.929660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  351.929708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  351.930251] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  351.930299] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.930309] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.930354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.930362] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  351.930408] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  351.930453] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  351.930497] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.930539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.930581] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.930634] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.930677] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.931206] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  351.931250] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  351.931293] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  351.931367] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  351.931426] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  351.931478] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  351.931637] [drm:intel_power_well_enable [i915]] enabling always-on
>[  351.931676] [drm:intel_power_well_enable [i915]] enabling DC off
>[  351.932350] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  351.932412] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.932459] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  351.932555] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  351.932597] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  351.932661] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  351.933054] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  351.933112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  351.933168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  351.933218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  351.933263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  351.933309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  351.933353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  351.933398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  351.933441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  351.933484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  351.933526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  351.933567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  351.933609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  351.933650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  351.933699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  351.934325] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.934378] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  351.934427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  351.934490] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  351.934540] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.938155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.938215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.938267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.938320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.939474] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  351.939527] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  351.939574] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.940587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  351.940638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  351.940687] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  351.941862] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.941915] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.943230] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.945613] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  351.947056] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  351.947139] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  351.947188] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  351.947254] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  351.947369] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  351.947420] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  351.964036] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  351.964113] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  351.964227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  351.964674] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  351.965161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.980753] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  351.980881] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  351.980993] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  351.998207] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  351.998274] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  351.998333] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  351.998439] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.000721] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.000842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.000907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.000962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.001012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.001060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.001108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.001156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.001202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.001246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.001290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.001342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.001387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.001431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.001482] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.001540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.001596] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.001648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.001699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.002576] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.002628] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.002678] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.002937] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.003020] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.003084] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.003134] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.003178] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.003631] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.004172] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.004200] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.004358] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.004413] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.004472] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.004537] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.004589] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.004642] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.004695] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.005142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.005196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.005245] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.005293] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.005303] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.005349] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.005358] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.005405] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.005452] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.005499] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.005545] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.005591] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.005647] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.005694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.006284] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.006331] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.006376] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.006452] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.006515] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.006569] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.007141] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.007184] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.007488] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.007551] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.007606] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.007697] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.008027] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.008095] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.008315] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.008372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.008425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.008476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.008523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.008569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.008613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.008658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.008701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.009219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.009265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.009310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.009354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.009397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.009446] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.009501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.009553] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.009603] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.009664] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.009716] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.013737] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.013833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.013885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.013940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.015093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.015147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.015197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.016284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.016335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.016384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.017442] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.017496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.018860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.021246] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  352.022813] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.022892] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.022942] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.023008] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.023130] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.023181] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.039842] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.039919] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.040034] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.040478] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.040626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.056460] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.056532] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.056640] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.073823] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.073889] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.073950] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.074055] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.074301] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.074358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.074414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.074465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.074513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.074559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.074603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.074648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.074692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.075320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.075370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.075425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.075471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.075515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.075566] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.075623] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.075678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.076087] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.076141] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.076211] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.076257] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.076302] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.076363] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.076433] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.076490] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.076535] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.076575] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.077711] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.077983] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.078008] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.078159] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.078212] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.078269] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.078331] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.078380] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.078432] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.078482] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.078531] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.078579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.078624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.078666] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.078674] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.079283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.079292] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.079339] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.079384] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.079428] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.079472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.079515] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.079568] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.079612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.079654] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.079696] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.080175] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.080251] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.080310] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.080361] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.080520] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.080560] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.081177] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.081515] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.081563] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.081660] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.081702] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.082014] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.082262] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.082318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.082371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.082421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.082467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.082512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.082556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.082601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.082644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.082685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.083198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.083244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.083287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.083330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.083380] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.083435] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.083487] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.083536] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.083597] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.083648] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.087153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.087206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.087254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.087305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.088481] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.088531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.088578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.089585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.089634] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.089681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.090842] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.090894] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.092232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.094613] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  352.096054] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.096141] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.096190] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.096257] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.096373] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.096423] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.113032] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.113107] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.113222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.113669] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.114115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.129706] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.129828] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.129936] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.147175] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.147348] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.147407] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.147513] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.147717] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.148075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.148134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.148187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.148237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.148286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.148332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.148379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.148422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.148465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.148507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.148556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.148598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.148638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.148687] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.149286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.149340] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.149390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.149438] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.149508] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.149553] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.149598] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.149659] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.150087] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.150148] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.150195] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.150236] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.150687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.151446] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.151471] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.151622] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.151674] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.151944] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.152008] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.152059] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.152114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.152167] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.152217] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.152266] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.152313] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.152358] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.152368] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.152411] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.152419] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.152464] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.152508] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.152552] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.152596] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.152639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.152692] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.153406] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.153453] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.153496] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.153538] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.153609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.153667] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.153718] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.154198] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.154238] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.154541] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.154600] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.154649] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.154993] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.155035] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.155101] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.157446] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.157513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.157577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.157631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.157679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.158051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.158102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.158154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.158202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.158249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.158295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.158341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.158386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.158430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.158481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.158539] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.158593] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.158646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.158710] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.159301] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.162984] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.163043] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.163095] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.163147] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.164366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.164419] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.164468] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.165593] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.165645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.165694] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.166860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.166914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.168127] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.170508] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  352.171952] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.172036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.172086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.172153] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.172269] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.172321] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.188939] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.189017] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.189132] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.189581] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.189730] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.205685] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.205819] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.205933] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.223260] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.223330] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.223391] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.223499] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.225840] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.225900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.225959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.226012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.226059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.226105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.226149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.226196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.226238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.226281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.226323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.226371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.226411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.226453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.226500] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.226555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.226607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.226656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.226704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.227553] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.227600] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.227647] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.227710] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.228008] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.228067] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.228114] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.228154] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.228605] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.229130] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.229158] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.229311] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.229363] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.229420] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.229482] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.229532] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.229583] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.229635] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.229682] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.230181] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.230230] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.230276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.230286] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.230330] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.230338] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.230382] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.230425] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.230469] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.230510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.230552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.230606] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.230649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.230692] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.231292] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.231338] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.231411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.231472] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.231522] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.231688] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.232036] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.232348] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.232409] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.232456] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.232555] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.232597] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.232662] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.234942] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.235012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.235076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.235130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.235179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.235227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.235273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.235321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.235366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.235410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.235454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.235497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.235540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.235583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.235633] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.235690] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.236473] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.236531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.236598] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.236654] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.238355] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.238409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.238457] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.238509] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.239655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.239705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.239928] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.240937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.241095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.241142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.242258] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.242311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.243506] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.245891] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  352.247323] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.247402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.247452] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.247518] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.247642] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.247693] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.264307] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.264385] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.264500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.265217] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.265370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.280969] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.281041] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.281149] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.298542] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.298611] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.298671] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.299096] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.299365] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.299422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.299478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.299529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.299577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.299623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.299666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.299713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.300184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.300229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.300273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.300324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.300367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.300410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.300460] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.300517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.300569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.300619] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.300669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.301200] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.301247] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.301293] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.301355] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.301429] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.301487] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.301532] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.301572] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.302625] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.303011] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.303038] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.303190] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.303243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.303300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.303360] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.303409] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.303571] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.303621] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.303669] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.303715] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.304231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.304279] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.304289] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.304333] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.304341] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.304385] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.304429] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.304472] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.304515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.304556] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.304609] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.304653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.304697] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.305265] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.305310] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.305385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.305446] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.305498] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.305662] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.305701] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.306349] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.306410] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.306457] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.306557] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.306598] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.306663] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.307053] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.307110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.307165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.307218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.307266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.307312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.307358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.307405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.307449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.307492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.307535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.307578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.307621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.307663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.307712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.308326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.308379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.308428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.308489] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.308538] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.312247] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.312304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.312355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.312408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.313523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.313574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.313621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.314606] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.314658] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.314707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.315860] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.315914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.317270] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.319611] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  352.321072] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.321151] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.321201] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.321268] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.321391] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.321443] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.338047] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.338123] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.338239] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.338969] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.339126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.354720] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.354843] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.354953] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.372175] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.372242] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.372303] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.372408] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.372616] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.372671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.373068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.373125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.373176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.373224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.373270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.373318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.373363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.373408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.373452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.373501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.373544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.373586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.373634] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.373689] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.374296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.374348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.374397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.374467] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.374514] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.374559] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.374622] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.374694] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.375112] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.375159] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.375200] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.375651] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.376116] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.376142] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.376293] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.376347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.376404] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.376466] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.376516] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.376567] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.376619] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.376668] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.376714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.377236] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.377282] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.377291] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.377334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.377342] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.377386] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.377429] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.377471] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.377511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.377551] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.377603] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.377646] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.377686] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.380217] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.380275] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.380364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.380431] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.380486] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.380631] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.380674] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.381021] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.381087] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.381133] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.381202] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.381246] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.381315] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.382320] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.382388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.382453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.382511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.382566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.382620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.382671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.382759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.382814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.382864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.382912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.382966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.383014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.383064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.383117] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.383179] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.383240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.383294] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.383359] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.383420] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.387025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.387083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.387134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.387186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.388110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.388159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.388206] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.389093] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.389139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.389183] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.390071] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.390121] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.391218] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.393480] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  352.393994] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.394029] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.394042] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.394061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.394092] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.394106] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.410884] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.410904] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.410937] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.411032] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.411071] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.427509] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.427530] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.427562] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.444504] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.444536] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.444565] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.444617] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.446859] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.446891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.446921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.446947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.446971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.446994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.447016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.447039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.447060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.447081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.447102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.447126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.447147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.447167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.447191] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.447219] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.447246] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.447271] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.447295] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.447337] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.447361] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.447384] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.447417] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.447452] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.447482] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.447506] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.447527] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.448021] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.448162] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.448178] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.448252] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.448279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.448308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.448340] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.448365] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.448392] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.448418] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.448444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.448469] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.448494] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.448517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.448522] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.448544] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.448548] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.448572] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.448594] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.448617] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.448638] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.448660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.448687] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.448731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.448753] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.448779] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.448801] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.448839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.448871] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.448898] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.448970] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.448990] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.449290] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.449336] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.449362] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.449404] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.449430] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.449468] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.449623] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.449656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.449688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.449750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.449783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.449813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.449843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.449873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.449902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.449930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.449958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.449986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.450013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.450040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.450072] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.450106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.450137] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.450167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.450206] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.450237] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.453638] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.453671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.453700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.453774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.454549] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.454583] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.454615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.455414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.455448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.455479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.456311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.456345] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.457438] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.459894] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  352.461116] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.461188] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.461232] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.461293] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.461404] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.461450] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.478108] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.478184] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.478298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.478669] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.478911] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.494790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.494862] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.494971] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.512207] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.512273] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.512333] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.512440] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.512605] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.512660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.512715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.512848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.512907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.512959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.513007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.513061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.513110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.513160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.513209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.513262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.513304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.513352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.513404] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.513465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.513519] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.513570] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.513620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.513693] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.513798] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.513850] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.513921] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.513992] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.514054] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.514101] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.514141] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.514594] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.514884] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.514910] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.515059] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.515108] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.515166] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.515228] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.515276] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.515327] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.515378] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.515425] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.515473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.515517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.515560] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.515568] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.515610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.515618] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.515662] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.515705] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.515800] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.515846] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.515893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.515951] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.516003] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.516050] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.516097] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.516142] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.516218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.516280] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.516332] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.516498] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.516539] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.516882] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.516943] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.516985] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.517050] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.517092] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.517154] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.517399] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.517456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.517509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.517560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.517607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.517654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.517700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.517799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.517854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.517899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.517947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.517991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.518038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.518082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.518135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.518194] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.518242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.518293] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.518355] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.518410] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.522020] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.522077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.522128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.522180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.523177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.523235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.523285] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.524203] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.524256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.524305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.525207] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.525262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.526459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.528896] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  352.530319] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.530402] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.530454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.530523] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.530641] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.530692] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.547291] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.547368] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.547482] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.548130] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.548277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.563972] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.564044] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.564150] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.581354] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.581421] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.581482] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.581588] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.581972] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.582057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.582132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.582210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.582276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.582346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.582408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.582478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.582539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.582604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.582663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.582968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.583028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.583092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.583158] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.583242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.583320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.583397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.583472] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.583570] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.583639] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.583710] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.584044] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.584148] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.584238] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.584309] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.584367] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.585367] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.585672] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.585768] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.585978] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.586034] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.586092] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.586154] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.586206] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.586258] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.586311] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.586360] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.586408] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.586454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.586498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.586508] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.586550] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.586558] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.586602] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.586645] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.586689] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.586812] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.586871] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.586948] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.587008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.587068] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.587135] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.587192] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.587295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.587373] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.587448] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.587682] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.587795] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.588120] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.588215] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.588282] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.588378] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.588445] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.588536] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.588819] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.588902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.588976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.589053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.589117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.589179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.589247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.589310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.589376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.589434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.589492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.589555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.589613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.589676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.589799] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.589879] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.589956] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.590026] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.590114] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.590180] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.593881] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.593939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.593989] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.594040] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.595036] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.595108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.595182] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.596226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.596279] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.596327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.597404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.597458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.598851] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.601296] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  352.602826] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.602914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.602965] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.603034] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.603158] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.603211] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.619860] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.619936] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.620051] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.620544] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.620694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.636483] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.636555] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.636664] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.654065] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.654134] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.654195] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.654301] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.654506] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.654562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.654617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.654666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.654713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.655031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.655095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.655169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.655229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.655297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.655357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.655431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.655489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.655554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.655624] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.655708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.656008] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.656087] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.656164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.656264] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.656336] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.656407] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.656504] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.656605] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.656692] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.656966] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.657029] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.657523] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.658062] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.658101] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.658325] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.658397] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.658479] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.658566] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.658633] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.658709] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.658985] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.659037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.659087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.659133] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.659176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.659186] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.659228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.659236] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.659280] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.659324] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.659366] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.659408] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.659449] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.659501] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.659543] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.659586] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.659627] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.659668] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.660033] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.660117] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.660186] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.660419] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.660483] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.661005] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.661358] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.661418] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.661516] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.661579] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.661671] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.661952] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.662034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.662108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.662184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.662248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.662317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.662376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.662445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.662504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.662569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.662627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.662692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.663086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.663146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.663217] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.663296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.663372] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.663440] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.663526] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.663593] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.667188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.667246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.667298] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.667350] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.668455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.668509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.668558] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.669550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.669600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.669648] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.670641] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.670694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.672068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.674453] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  352.675875] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.675963] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.676013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.676080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.676196] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.676247] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.692856] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.692932] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.693045] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.693495] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.693642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.714447] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.714494] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.714566] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.727484] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.727531] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.727574] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.727651] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.728030] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.728089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.728147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.728187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.728220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.728251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.728282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.728314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.728344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.728374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.728402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.728435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.728463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.728490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.728523] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.728562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.728598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.728632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.728666] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.729406] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.729439] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.729470] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.729514] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.729568] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.729608] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.729639] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.729667] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.730739] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.730919] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.730939] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.731044] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.731081] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.731122] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.731165] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.731199] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.731236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.731271] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.731305] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.731339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.731370] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.731400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.731406] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.731436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.731441] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.731472] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.731502] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.731532] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.731561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.731589] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.731625] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.731655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.731684] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.732612] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.732647] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.732700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.732899] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.732952] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.733090] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.733117] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.733404] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.733447] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.733483] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.733551] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.733580] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.733624] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.734143] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.734183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.734222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.734258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.734290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.734321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.734352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.734383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.734413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.734442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.734470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.734498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.734525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.734552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.734584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.734622] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.734656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.734690] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.735411] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.735447] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.738874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.738914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.738949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.738986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.740026] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.740064] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.740098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.741075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.741112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.741145] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.742007] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.742045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.743277] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.745610] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  352.746715] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.746802] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.746837] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.746884] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.746972] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.747008] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.763651] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.763704] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.764056] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.764365] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.764465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.780372] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.780437] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.780534] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.797727] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.797849] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.797911] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.798017] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.800397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.800462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.800525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.800581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.800632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.800682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.801215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.801273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.801321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.801368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.801414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.801466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.801511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.801555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.801604] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.801662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.801716] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.802427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.802481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.802551] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.802597] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.802642] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.802701] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.803206] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.803266] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.803314] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.803355] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.804332] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.804745] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.804770] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.804966] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.805041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.805100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.805164] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.805214] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.805269] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.805322] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.805373] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.805421] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.805467] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.805512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.805521] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.805564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.805571] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.805617] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.805659] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.805701] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.805784] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.805825] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.805883] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.805927] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.805972] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.806015] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.806059] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.806131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.806193] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.806244] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.806448] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.806510] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.806907] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.807397] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.807464] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.807561] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.807628] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.807721] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.810146] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.810212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.810274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.810329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.810380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.810428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.810475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.810524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.810569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.810613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.810656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.810700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.811470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.811521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.811572] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.811629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.811681] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.812078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.812168] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.812223] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.815917] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.815975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.816026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.816079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.817475] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.817530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.817580] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.818687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.818786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.818835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.820092] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.820149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.821457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.823851] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  352.825411] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.825492] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.825544] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.825611] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.826147] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.826203] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.842387] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.842465] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.842581] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.843430] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.843586] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.859056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.859129] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.859237] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.876437] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.876504] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.876564] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.876670] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.877139] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.877201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.877257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.877309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.877357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.877402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.877447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.877494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.877535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.877577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.877618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.877666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.877707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.878547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.878601] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.878660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.878715] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.879063] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.879140] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.879220] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.879267] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.879312] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.879373] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.879445] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.879500] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.879546] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.879585] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.880932] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.881184] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.881210] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.881361] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.881415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.881474] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.881536] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.881694] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.882285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.882340] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.882389] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.882437] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.882482] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.882526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.882535] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.882578] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.882585] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.882630] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.882672] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.882714] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.883500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.883550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.883605] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.883653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.883701] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.884110] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.884159] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.884234] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.884293] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.884344] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.884502] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.884540] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.885307] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.885649] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.885702] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.885888] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.885951] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.886044] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.888422] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.888489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.888551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.888607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.888657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.888705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.889107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.889161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.889210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.889257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.889305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.889350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.889397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.889442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.889493] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.889552] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.889607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.889661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.889725] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.890346] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.893935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.893994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.894045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.894097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.895351] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.895404] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.895454] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.896592] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.896644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.896691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.897855] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.897911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.899129] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.901509] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  352.902882] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.902964] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.903013] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.903080] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.903196] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.903247] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.919857] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.919934] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.920048] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.920499] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.920646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.936529] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  352.936602] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  352.936710] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.954043] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.954110] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  352.954170] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.954274] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.954477] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.954533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.954588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.954638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.954683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.955174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.955220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.955268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.955313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.955355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.955398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.955447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.955488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.955530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.955578] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.955635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.955688] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.956233] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.956284] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.956354] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  352.956399] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  352.956444] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.956505] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  352.956577] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.956633] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.956678] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.957117] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.957569] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.957950] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.957976] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  352.958128] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  352.958180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.958238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  352.958299] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  352.958348] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  352.958400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.958452] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  352.958499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  352.958546] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  352.958590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  352.958633] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.958641] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.958683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.959295] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  352.959343] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  352.959391] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  352.959437] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.959482] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.959526] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.959581] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.959626] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.959670] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  352.960207] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  352.960251] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  352.960324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  352.960381] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  352.960432] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  352.960588] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.960627] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.961264] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.961586] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  352.961638] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  352.961817] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  352.961882] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  352.961979] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  352.964238] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  352.964305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  352.964367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  352.964422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  352.964473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  352.964522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  352.964569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  352.964617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  352.964662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  352.964706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  352.965240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  352.965290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  352.965339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  352.965386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  352.965439] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  352.965499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.965555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  352.965608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  352.965672] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  352.965727] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  352.969809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  352.969868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  352.969918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  352.969970] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  352.971151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  352.971202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  352.971250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.972292] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  352.972343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  352.972392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  352.973426] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  352.973478] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  352.974861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  352.977297] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  352.978795] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  352.978877] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  352.978929] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  352.978996] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  352.979122] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  352.979174] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  352.995832] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  352.995910] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  352.996025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  352.996500] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  352.996649] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.012446] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.012517] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.012627] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.029868] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.029936] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.029995] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.030100] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.030346] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.030401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.030456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.030508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.030555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.030600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.030644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.030691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.031345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.031395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.031442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.031495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.031539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.031582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.031632] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.031688] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.032121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.032173] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.032222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.032293] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.032338] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.032384] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.032446] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.032518] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.032574] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.032620] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.032660] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.033870] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.034121] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.034147] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.034295] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.034347] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.034405] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.034467] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.034516] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.034566] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.034617] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.034665] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.034713] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.035267] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.035315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.035325] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.035370] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.035378] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.035423] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.035468] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.035512] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.035555] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.035596] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.035649] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.035694] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.036227] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.036271] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.036313] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.036385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.036443] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.036492] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.036650] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.036688] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.037362] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.037424] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.037477] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.037569] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.037611] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.037675] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.040464] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.040530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.040592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.040647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.040698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.041058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.041110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.041164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.041212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.041260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.041308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.041355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.041400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.041446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.041498] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.041556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.041610] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.041663] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.041727] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.042359] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.045939] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.045997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.046048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.046100] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.047327] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.047379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.047428] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.048314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.048365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.048411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.049295] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.049347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.050533] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.052914] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  353.054356] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.054441] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.054490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.054557] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.054673] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.054725] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.071341] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.071420] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.071536] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.072056] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.072204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.088059] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.088134] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.088249] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.105545] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.105613] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.105674] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.105827] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.106045] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.106105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.106168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.106223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.106275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.106322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.106369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.106416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.106460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.106503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.106547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.106596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.106638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.106681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.106790] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.106852] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.106910] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.106964] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.107017] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.107094] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.107141] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.107186] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.107249] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.107319] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.107377] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.107423] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.107462] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.107981] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.108651] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.108730] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.108880] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.108932] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.108992] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.109056] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.109107] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.109159] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.109212] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.109262] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.109311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.109360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.109404] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.109415] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.109457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.109466] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.109512] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.109555] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.109600] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.109643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.109687] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.109778] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.109822] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.109874] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.109917] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.109962] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.110035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.110097] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.110153] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.110325] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.110365] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.110683] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.110792] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.110843] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.110906] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.110949] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.111015] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.111282] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.111336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.111388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.111438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.111483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.111528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.111570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.111615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.111656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.111696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.111800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.111845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.111897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.111939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.111989] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.112052] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.112109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.112163] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.112224] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.112275] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.115908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.116074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.116127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.116181] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.117113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.117163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.117210] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.118099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.118147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.118194] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.119093] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.119144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.120330] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.122710] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  353.124076] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.124163] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.124213] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.124280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.124404] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.124457] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.141044] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.141121] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.141236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.141967] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.142121] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.157731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.157854] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.157963] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.175166] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.175234] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.175294] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.175400] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.179808] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.179874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.179938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.179993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.180044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.180091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.180139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.180188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.180234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.180278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.180324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.180374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.180419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.180464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.180515] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.180573] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.180628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.180681] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.181527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.181611] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.181663] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.181713] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.182005] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.182088] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.182150] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.182200] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.182244] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.182712] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.183517] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.183545] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.183703] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.183962] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.184027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.184094] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.184148] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.184205] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.184262] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.184315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.184367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.184416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.184464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.184473] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.184518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.184527] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.184573] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.184618] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.184663] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.184708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.185410] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.185466] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.185516] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.185562] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.185608] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.185652] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.185727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.186130] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.186186] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.186360] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.186403] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.186944] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.187270] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.187323] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.187421] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.187464] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.187529] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.187697] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.188112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.188169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.188220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.188266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.188310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.188355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.188400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.188443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.188486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.188529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.188571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.188612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.188653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.188701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.189302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.189354] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.189402] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.189463] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.189513] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.193137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.193196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.193247] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.193300] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.194449] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.194504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.194554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.195470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.195522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.195571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.196474] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.196528] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.197787] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.200171] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  353.201564] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.201652] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.201704] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.201864] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.202044] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.202117] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.218544] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.218622] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.218961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.219393] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.219540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.235222] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.235293] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.235401] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.252591] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.252658] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.252718] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.253098] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.255406] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.255472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.255536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.255593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.255643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.255693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.256102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.256157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.256206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.256254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.256299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.256351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.256397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.256441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.256493] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.256554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.256717] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.257240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.257294] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.257368] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.257418] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.257466] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.257530] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.257605] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.257665] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.257713] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.258154] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.258610] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.259012] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.259037] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.259191] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.259246] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.259308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.259373] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.259426] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.259483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.259537] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.259588] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.259638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.259687] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.260246] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.260256] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.260305] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.260314] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.260362] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.260410] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.260458] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.260505] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.260550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.260608] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.260655] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.260701] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.261235] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.261283] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.261359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.261421] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.261473] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.261635] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.261677] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.262323] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.262388] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.262437] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.262535] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.262577] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.262641] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.263064] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.263121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.263176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.263227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.263274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.263318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.263362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.263408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.263452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.263494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.263537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.263579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.263622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.263662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.263711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.264338] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.264391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.264441] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.264501] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.264551] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.268166] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.268223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.268275] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.268327] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.269521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.269573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.269620] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.270632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.270682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.270909] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.271921] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.271973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.273386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.275827] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  353.277301] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.277388] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.277439] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.277507] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.277624] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.277676] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.294279] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.294358] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.294473] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.295215] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.295366] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.310952] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.311023] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.311131] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.328489] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.328558] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.328619] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.328728] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.331471] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.331537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.331600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.331655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.331705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.332074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.332127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.332179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.332229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.332275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.332322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.332374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.332419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.332464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.332516] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.332576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.332633] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.332686] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.333274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.333353] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.333403] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.333452] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.333517] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.333596] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.333657] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.333705] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.334123] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.334595] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.335128] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.335157] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.335314] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.335370] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.335432] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.335499] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.335551] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.335607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.335662] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.335713] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.336189] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.336240] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.336289] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.336299] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.336346] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.336354] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.336401] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.336448] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.336494] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.336539] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.336583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.336639] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.336686] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.337277] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.337327] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.337373] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.337451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.337515] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.337570] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.338013] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.338055] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.338368] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.338431] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.338481] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.338579] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.338621] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.338685] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.341355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.341422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.341483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.341538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.341587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.341635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.341681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.342203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.342253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.342302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.342348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.342396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.342442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.342488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.342540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.342600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.342655] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.342710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.343375] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.343429] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.347048] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.347106] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.347158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.347211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.348239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.348292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.348342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.349365] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.349415] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.349462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.350508] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.350561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.351807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.354187] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  353.355611] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.355690] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.355857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.355930] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.356055] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.356108] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.372581] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.372656] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.372945] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.373400] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.373548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.389255] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.389327] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.389435] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.406624] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.406691] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.406913] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.407023] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.409373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.409439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.409501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.409556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.409605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.409653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.409701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.409943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.409991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.410037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.410084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.410140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.410186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.410232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.410285] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.410346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.410404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.410460] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.410512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.410586] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.410637] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.410687] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.410931] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.411007] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.411070] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.411119] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.411163] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.411627] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.412009] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.412035] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.412186] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.412240] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.412300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.412363] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.412416] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.412470] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.412523] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.412573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.412622] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.412668] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.412713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.413001] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.413050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.413059] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.413108] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.413155] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.413204] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.413249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.413295] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.413351] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.413402] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.413448] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.413496] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.413540] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.413616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.413679] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.413900] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.414066] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.414109] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.414429] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.414495] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.414548] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.414645] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.414687] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.414891] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.415054] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.415109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.415163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.415213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.415260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.415304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.415348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.415392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.415434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.415476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.415517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.415557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.415598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.415638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.415685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.415939] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.415994] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.416045] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.416106] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.416158] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.419825] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.419884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.419934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.419987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.420993] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.421047] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.421099] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.422092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.422143] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.422191] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.423149] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.423202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.424392] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.426806] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  353.428191] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.428270] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.428319] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.428386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.428617] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.428669] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.445167] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.445244] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.445360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.445961] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.446194] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.461891] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.461965] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.462073] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.479481] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.479551] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.479612] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.479722] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.480260] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.480321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.480379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.480432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.480480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.480527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.480572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.480619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.480662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.480706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.481025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.481104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.481171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.481232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.481308] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.481396] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.481477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.481554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.481628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.481943] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.482015] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.482088] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.482185] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.482291] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.482381] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.482452] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.482516] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.483496] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.483987] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.484015] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.484171] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.484225] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.484282] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.484343] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.484393] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.484446] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.484498] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.484547] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.484594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.484639] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.484683] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.484955] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.485022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.485035] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.485107] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.485177] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.485241] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.485310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.485370] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.485450] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.485519] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.485585] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.485653] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.485717] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.486057] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.486141] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.486216] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.486462] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.486525] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.486925] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.487396] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.487462] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.487558] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.487623] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.487719] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.490049] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.490116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.490178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.490232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.490282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.490331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.490377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.490426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.490471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.490515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.490560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.490604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.490648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.490693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.491181] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.491263] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.491342] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.491417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.491507] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.491583] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.495269] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.495327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.495377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.495429] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.496600] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.496654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.496703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.497884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.497938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.497987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.498900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.498974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.500289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.502726] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  353.504254] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.504337] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.504389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.504457] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.504581] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.504633] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.521236] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.521313] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.521427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.522301] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.522451] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.538009] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.538081] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.538189] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.555574] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.555642] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.555703] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.556148] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.560636] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.560703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.561067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.561128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.561181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.561232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.561280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.561329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.561375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.561421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.561466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.561517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.561561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.561604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.561655] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.561713] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.562454] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.562511] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.562563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.562640] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.562689] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.563045] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.563114] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.563193] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.563255] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.563304] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.563347] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.564492] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.564891] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.564919] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.565077] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.565134] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.565197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.565263] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.565315] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.565370] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.565426] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.565478] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.565529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.565576] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.565622] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.565631] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.565678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.566448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.566503] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.566553] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.566601] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.566648] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.566694] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.567132] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.567182] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.567233] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.567280] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.567328] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.567404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.567467] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.567521] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.567692] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.568225] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.568545] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.568609] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.568663] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.568849] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.568919] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.569014] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.571441] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.571508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.571570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.571624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.571674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.571722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.572331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.572409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.572479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.572548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.572616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.572683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.573123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.573169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.573220] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.573276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.573327] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.573376] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.573438] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.573489] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.577115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.577172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.577223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.577277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.578468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.578522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.578571] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.579690] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.579793] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.579841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.580702] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.581149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.582423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.584900] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  353.586412] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.586501] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.586551] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.586619] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.587127] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.587183] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.603394] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.603470] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.603586] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.604318] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.604463] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.620074] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.620145] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.620254] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.637503] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.637571] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.637632] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.638047] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.638394] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.638452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.638508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.638559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.638606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.638651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.638695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.639282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.639329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.639375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.639419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.639468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.639510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.639552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.639601] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.639656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.639708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.640275] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.640329] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.640397] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.640443] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.640489] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.640550] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.640620] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.640676] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.641156] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.641197] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.641647] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.642115] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.642140] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.642289] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.642342] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.642399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.642460] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.642509] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.642560] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.642610] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.642657] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.642703] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.643340] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.643387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.643397] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.643441] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.643448] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.643495] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.643539] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.643584] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.643627] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.643669] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.643722] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.644350] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.644397] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.644442] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.644485] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.644555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.644613] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.644663] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.645279] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.645318] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.645635] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.645695] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.646016] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.646114] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.646157] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.646223] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.646472] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.646530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.646583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.646635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.646682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.647341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.647390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.647439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.647485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.647529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.647572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.647615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.647656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.647697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.648223] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.648279] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.648331] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.648380] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.648442] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.648493] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.652047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.652101] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.652151] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.652202] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.653404] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.653456] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.653505] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.654658] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.654709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.654979] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.655974] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.656028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.657435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.659825] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  353.661290] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.661374] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.661423] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.661488] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.661603] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.661655] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.678268] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.678345] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.678566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.679270] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.679418] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.714658] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.714986] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.715439] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.729612] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.729683] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.730009] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.730121] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.730337] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.730394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.730451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.730501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.730548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.730593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.730637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.730682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.731268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.731313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.731359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.731408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.731449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.731493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.731541] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.731598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.731651] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.731702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.732271] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.732343] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.732389] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.732433] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.732495] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.732568] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.732624] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.732670] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.732709] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.733658] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.734343] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.734370] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.734522] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.734576] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.734634] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.734696] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.735121] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.735178] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.735232] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  353.735282] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  353.735330] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.735378] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.735423] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.735433] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.735475] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.735482] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.735529] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.735572] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.735615] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.735656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.735697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.736553] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.736604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.736651] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  353.736697] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  353.737008] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  353.737081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.737141] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  353.737192] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  353.737357] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.737395] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.737707] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.738444] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.738500] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.738593] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.738636] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.738701] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.739230] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.739288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.739344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.739394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.739442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.739489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.739534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.739580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.739622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.739663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.739704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.740310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.740355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.740399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.740448] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.740504] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.740558] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.740608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.740669] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  353.740719] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.744915] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.744973] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.745024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.745077] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.746252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.746306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.746355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.747470] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.747522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.747569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.748644] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.748698] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.750044] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.752372] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  353.753419] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.753478] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.753512] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  353.753559] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.754060] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  353.754098] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  353.770262] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.770298] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.770358] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.770595] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.770671] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.786959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  353.787001] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.787240] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.805530] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  353.805595] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  353.805654] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  353.806122] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.808335] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.808393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.808449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.808501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.808548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.808592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.808637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.808682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.809243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.809288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.809333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.809383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.809426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.809468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.809515] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.809571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.809624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.809675] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.810283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.810351] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  353.810396] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  353.810441] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  353.810502] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  353.810573] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  353.810629] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.810674] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.811199] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.811649] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.812386] [drm:drm_mode_addfb2] [FB:68]
>[  353.812457] [drm:drm_mode_addfb2] [FB:110]
>[  353.905860] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  353.906206] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  353.906259] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  353.906821] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  353.906831] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.906882] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  353.906898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.906917] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  353.906948] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  353.906962] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  353.906978] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.906993] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  353.907008] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  353.907022] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  353.907035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  353.907048] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.907051] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.907063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.907065] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  353.907078] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  353.907090] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  353.907102] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.907114] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.907126] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.907141] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.907153] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.907166] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  353.907178] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  353.907189] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  353.907209] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  353.907226] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  353.907240] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  353.908348] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.908359] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.908640] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.908658] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  353.908670] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  353.908758] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  353.908771] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  353.908803] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  353.910978] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  353.910993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  353.911008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  353.911021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  353.911034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  353.911046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  353.911058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  353.911070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  353.911081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  353.911092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  353.911102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  353.911113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  353.911124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  353.911135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  353.911147] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  353.911161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.911174] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  353.911187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  353.911203] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  353.911216] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  353.914408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.914424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.914438] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.914453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.915104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  353.915118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  353.915144] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.915786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  353.915814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  353.915844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  353.916476] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.916491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  353.917463] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.919790] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  353.920814] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  353.920882] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  353.920921] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  353.920974] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  353.937833] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  353.937912] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  353.938028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  353.954476] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  353.954505] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  353.971374] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  353.971529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.987839] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  353.987912] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  353.988307] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.004851] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.004920] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.005029] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.005277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.005333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.005389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.005440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.005487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.005532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.005577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.005623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.005666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.005709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.006525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.006688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.006954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.007001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.007053] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.007112] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.007167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.007218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.007268] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.007341] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.007389] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.007436] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.007499] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.007570] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.007622] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.007669] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.007709] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.008337] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.008583] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.008610] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.008886] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.008939] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.008997] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.009059] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.009108] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.009161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.009212] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.009261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.009310] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.009357] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.009400] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.009410] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.009452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.009459] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.009503] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.009546] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.009589] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.009630] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.009671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.009723] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.009955] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.009998] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.010041] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.010081] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.010152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.010211] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.010261] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.010397] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.010436] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.010908] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.011284] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.011331] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.011436] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.011479] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.011543] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.011710] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.011922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.011976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.012027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.012072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.012117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.012160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.012207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.012249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.012293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.012335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.012377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.012417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.012458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.012506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.012561] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.012611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.012660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.012720] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.012946] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.016535] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.016592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.016643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.016695] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.017951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.018004] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.018053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.019248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.019302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.019350] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.020500] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.020555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.022028] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.024461] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  354.026076] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.026167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.026219] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.026285] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.043064] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.043143] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.043260] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.044041] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.044192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.059752] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.059880] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.060272] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.076634] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.076700] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.077132] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.077354] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.077412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.077466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.077516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.077563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.077607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.077651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.077698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.078096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.078143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.078190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.078242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.078286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.078330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.078380] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.078437] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.078490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.078540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.078590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.078661] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.078708] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.079194] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.079258] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.079330] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.079382] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.079427] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.079467] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.080477] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.080928] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.080953] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.081103] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.081157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.081215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.081276] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.081325] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.081377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.081429] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.081478] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.081525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.081570] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.081612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.081620] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.081662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.081668] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.081712] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.082160] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.082207] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.082253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.082297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.082354] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.082398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.082445] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.082487] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.082532] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.082603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.082663] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.082716] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.083303] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.083345] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.083656] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.083989] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.084037] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.084141] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.084188] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.084254] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.086545] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.086612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.086674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.087033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.087089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.087138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.087187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.087237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.087284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.087330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.087375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.087420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.087463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.087505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.087556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.087615] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.087669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.087721] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.088288] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.088345] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.091925] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.091983] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.092034] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.092086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.093207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.093259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.093309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.094407] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.094460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.094509] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.095518] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.095572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.096952] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.099393] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  354.101048] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.101135] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.101187] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.101255] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.118033] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.118112] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.118230] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.118671] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.118897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.134704] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.134830] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.135222] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.151626] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.151693] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.152025] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.156535] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.156602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.156666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.156721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.157106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.157161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.157212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.157263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.157314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.157364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.157410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.157463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.157508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.157553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.157605] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.157664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.157721] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.158314] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.158369] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.158451] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.158500] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.158548] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.158614] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.158693] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.159086] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.159138] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.159183] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.159636] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.160136] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.160163] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.160319] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.160374] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.160435] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.160501] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.160555] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.160609] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.160664] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.160715] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.161216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.161268] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.161316] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.161326] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.161372] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.161380] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.161427] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.161474] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.161520] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.161564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.161608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.161664] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.161710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.162286] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.162333] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.162379] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.162455] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.162517] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.162572] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.163137] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.163181] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.163496] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.163557] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.163607] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.163709] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.164068] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.164135] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.168550] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.168617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.168679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.168988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.169042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.169093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.169141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.169190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.169236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.169283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.169329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.169374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.169419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.169462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.169512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.169569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.169624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.169677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.170334] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.170389] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.174065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.174123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.174173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.174226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.175395] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.175447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.175496] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.176633] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.176682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.176930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.177939] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.177991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.179278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.181663] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  354.183123] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.183204] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.183254] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.183321] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.200106] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.200183] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.200301] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.201056] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.201211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.216906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.216981] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.217430] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.233790] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.233859] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.233969] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.236299] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.236366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.236430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.236485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.236535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.236584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.236631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.236680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.237224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.237274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.237320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.237374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.237422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.237468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.237521] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.237582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.237640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.237694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.238171] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.238253] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.238302] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.238350] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.238416] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.238493] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.238548] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.238597] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.238640] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.239832] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.240081] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.240108] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.240263] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.240319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.240379] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.240445] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.240498] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.240552] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.240607] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.240658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.240708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.241391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.241442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.241452] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.241499] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.241508] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.241556] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.241604] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.241651] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.241697] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.242143] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.242200] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.242250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.242297] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.242342] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.242387] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.242462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.242525] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.242577] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.243119] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.243164] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.243481] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.243542] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.243594] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.243694] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.244047] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.244115] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.244297] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.244355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.244410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.244461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.244509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.244555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.244600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.244646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.244689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.245222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.245270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.245315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.245361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.245404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.245455] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.245512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.245564] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.245615] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.245676] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.246147] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.249731] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.249833] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.249885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.249938] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.251119] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.251172] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.251220] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.252293] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.252345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.252392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.253433] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.253486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.254861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.257244] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  354.258660] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.258865] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.258918] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.258987] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.275638] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.275717] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.276037] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.276483] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.276633] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.292309] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.292381] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.292990] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.309597] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.309664] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.309974] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.312311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.312377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.312437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.312493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.312542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.312591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.312638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.312686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.313160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.313208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.313255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.313309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.313355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.313400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.313452] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.313512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.313569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.313624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.313677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.314203] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.314253] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.314301] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.314366] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.314441] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.314495] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.314543] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.314585] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.315678] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.315946] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.315971] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.316126] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.316180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.316241] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.316305] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.316358] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.316412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.316465] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.316515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.316565] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.316613] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.316659] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.316667] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.316713] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.317355] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.317410] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.317462] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.317512] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.317561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.317609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.317665] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.317713] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.318104] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.318154] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.318202] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.318280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.318345] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.318401] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.318565] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.318608] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.319397] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.319855] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.319912] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.320017] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.320059] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.320123] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.320290] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.320347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.320401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.320451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.320498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.320542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.320585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.320632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.320675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.321261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.321308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.321352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.321397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.321440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.321489] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.321545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.321596] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.321647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.321708] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.322173] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.325809] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.325866] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.325917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.325971] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.327141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.327194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.327242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.328312] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.328363] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.328411] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.329447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.329500] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.330859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.333268] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  354.334699] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.334924] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.334975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.335041] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.351853] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.351932] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.352047] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.352490] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.352637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.368489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.368560] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.369028] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.385684] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.385801] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.385908] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.388156] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.388222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.388284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.388338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.388387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.388434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.388482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.388531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.388576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.388621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.388666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.388717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.388825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.388872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.388932] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.388995] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.389056] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.389111] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.389164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.389244] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.389293] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.389344] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.389409] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.389481] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.389535] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.389584] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.389627] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.390118] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.390818] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.390844] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.390995] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.391050] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.391110] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.391175] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.391229] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.391285] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.391340] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.391392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.391443] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.391491] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.391538] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.391547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.391593] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.391601] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.391648] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.391694] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.391793] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.391842] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.391890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.391948] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.391998] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.392045] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.392093] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.392138] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.392215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.392280] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.392334] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.392501] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.392543] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.392907] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.392973] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.393026] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.393125] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.393173] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.393236] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.395149] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.395204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.395259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.395310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.395356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.395401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.395443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.395488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.395529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.395570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.395611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.395652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.395692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.396416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.396467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.396523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.396573] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.396622] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.396682] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.397085] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.400657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.400714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.400998] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.401053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.402037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.402090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.402141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.403315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.403367] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.403416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.404479] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.404533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.405917] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.408303] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  354.409769] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.409857] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.409907] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.409973] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.426793] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.426872] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.426989] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.427435] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.427581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.443428] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.443500] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.444250] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.460565] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.460632] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.460985] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.461237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.461294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.461350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.461401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.461448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.461495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.461541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.461588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.461633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.461675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.462313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.462367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.462412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.462456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.462506] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.462561] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.462614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.462664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.462711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.463304] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.463350] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.463395] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.463456] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.463528] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.463578] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.463622] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.463661] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.464860] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.465082] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.465107] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.465256] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.465308] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.465365] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.465425] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.465475] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.465525] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.465576] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.465624] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.465670] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.465714] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.466437] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.466446] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.466492] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.466500] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.466546] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.466592] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.466635] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.466679] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.467179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.467233] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.467280] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.467323] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.467365] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.467405] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.467474] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.467532] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.467582] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.468225] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.468265] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.468579] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.468637] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.468682] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.469208] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.469251] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.469318] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.469531] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.469590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.469645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.469696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.470253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.470302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.470349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.470398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.470442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.470485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.470528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.470570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.470612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.470653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.470700] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.471395] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.471449] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.471499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.471561] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.471611] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.475151] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.475206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.475256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.475308] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.476586] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.476640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.476690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.477873] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.477925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.477973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.479094] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.479149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.480467] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.482858] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  354.484330] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.484408] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.484457] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.484525] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.501307] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.501385] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.501500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.502133] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.502297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.518049] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.518124] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.518553] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.534846] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.534914] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.535024] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.535274] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.535331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.535387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.535439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.535485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.535529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.535572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.535618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.535661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.535704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.536808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.536894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.536960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.537030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.537104] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.537189] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.537269] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.537346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.537421] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.537529] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.537601] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.537673] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.538412] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.538491] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.538544] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.538589] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.538629] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.539852] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.540499] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.540526] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.540681] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.541121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.541207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.541298] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.541374] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.541453] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.541531] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.541606] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.541680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.542179] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.542226] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.542235] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.542280] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.542287] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.542332] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.542375] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.542416] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.542457] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.542498] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.542550] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.542594] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.542636] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.542676] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.543698] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.543978] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.544065] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.544142] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.544385] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.544448] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.545079] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.545415] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.545466] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.545561] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.545603] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.545668] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.548355] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.548421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.548483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.548538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.548587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.548635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.548680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.549346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.549417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.549489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.549560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.549629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.549696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.550130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.550182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.550239] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.550292] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.550341] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.550402] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.550451] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.554091] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.554147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.554198] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.554250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.555562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.555616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.555665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.557037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.557092] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.557141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.558226] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.558282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.559480] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.561917] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  354.563406] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.563497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.563549] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.563616] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.580395] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.580473] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.580590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.581246] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.581393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.597063] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.597134] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.597528] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.613830] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.613898] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.614009] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.616329] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.616396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.616460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.616515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.616566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.616614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.616661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.616710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.617466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.617541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.617613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.617693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.618050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.618098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.618151] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.618211] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.618266] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.618317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.618367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.618441] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.618487] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.618531] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.618593] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.618665] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.619580] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.619655] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.619719] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.620436] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.620896] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.620927] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.621083] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.621137] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.621196] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.621259] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.621309] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.621361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.621413] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.621461] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.621509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.621552] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.621594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.621603] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.621644] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.621651] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.621695] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.622966] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.623039] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.623113] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.623176] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.623257] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.623329] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.623401] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.623469] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.623528] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.623630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.623715] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.624454] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.624621] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.624660] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.625299] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.625622] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.625671] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.626051] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.626094] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.626161] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.626369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.626426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.626481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.626533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.626580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.626625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.626670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.626717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.627598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.627671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.627739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.628051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.628097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.628142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.628192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.628248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.628299] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.628348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.628408] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.628459] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.632160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.632218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.632268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.632321] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.633629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.633682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.633994] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.634975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.635027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.635076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.636099] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.636154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.637494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.639885] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  354.641413] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.641493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.641543] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.641609] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.658389] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.658467] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.658584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.659381] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.659529] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.675066] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.675136] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.675528] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.693822] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.693887] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.693995] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.714714] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.714823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.714883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.714936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.714985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.715031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.715076] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.715121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.715163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.715203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.715245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.715293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.715333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.715374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.715421] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.715477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.715528] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.715579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.715627] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.715695] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.715840] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.715910] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.716008] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.716111] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.716190] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.716262] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.716326] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.716865] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.717579] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.717616] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.717890] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.717967] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.718052] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.718142] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.718218] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.718296] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.718375] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.718449] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.718524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.718593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.718661] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.718674] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.718783] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.718796] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.718864] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.718932] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.718999] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.719065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.719136] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.719186] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.719232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.719274] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.719320] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.719360] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.719430] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.719487] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.719540] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.719711] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.719786] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.720091] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.720154] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.720200] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.720323] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.720370] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.720433] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.720602] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.720657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.720713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.720797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.720846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.720895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.720943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.720991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.721037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.721082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.721128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.721173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.721218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.721262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.721311] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.721367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.721421] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.721472] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.721533] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.721585] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.724074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.724125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.724189] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.724227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.725226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.725264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.725303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.726320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.726348] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.726374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.727306] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.727336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.728372] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.730652] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  354.731369] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.731409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.731430] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.731460] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.748204] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.748232] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.748276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.748431] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.748484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.764879] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.764909] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.765069] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.783604] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.783652] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.783983] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.786378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.786438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.786495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.786544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.786588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.786632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.786675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.787407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.787455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.787499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.787540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.787588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.787627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.787665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.787709] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.788478] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.788531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.788579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.788624] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.788686] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.789195] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.789243] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.789305] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.789380] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.789431] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.789476] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.789515] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.790926] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.791591] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.791617] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.792134] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.792192] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.792252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.792315] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.792365] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.792417] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.792470] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.792520] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.792569] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.792615] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.792658] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.792666] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.792709] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.793866] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.793933] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.793985] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.794033] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.794079] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.794124] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.794178] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.794223] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.794268] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.794311] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.794352] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.794424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.794482] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.794532] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.794667] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.794706] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.795113] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.795208] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.795275] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.795418] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.795485] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.795577] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.796897] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.796983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.797065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.797141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.797215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.797286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.797354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.797425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.797493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.797560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.797626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.797691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.797812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.797878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.797950] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.798030] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.798106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.798180] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.798268] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.798343] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.802061] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.802121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.802172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.802224] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.803537] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.803595] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.803645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.804621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.804671] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.804719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.805666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.805719] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.807068] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.809453] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  354.810855] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.810937] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.810988] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.811056] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.827875] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.827950] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.828063] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.828490] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.828665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.844465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.844541] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.844678] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.861901] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.861968] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.862074] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.864373] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.864437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.864498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.864552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.864602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.864650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.864697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.864843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.864909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.864976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.865037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.865112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.865176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.865241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.865314] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.865399] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.865477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.865555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.865608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.865681] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.865806] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.865879] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.865997] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.866095] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.866150] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.866196] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.866240] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.866690] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.867432] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.867459] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.867610] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.867662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.867719] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.867876] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.867954] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.868035] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.868095] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.868144] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.868195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.868241] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.868288] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.868299] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.868342] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.868353] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.868400] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.868444] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.868489] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.868534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.868577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.868630] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.868679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.868787] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.868854] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.868918] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.869020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.869107] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.869181] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.869400] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.869443] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.869825] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.870306] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.870350] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.870474] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.870515] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.870583] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.872828] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.872897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.872962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.873017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.873067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.873115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.873163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.873212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.873257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.873301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.873344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.873387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.873431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.873475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.873525] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.873582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.873635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.873686] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.873854] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.873931] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.877548] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.877607] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.877658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.877710] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.878878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.878930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.878978] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.879935] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.879986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.880038] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.880945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.880998] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.882332] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.884825] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  354.886239] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.886322] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.886373] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.886442] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.903208] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.903288] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.903404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.904046] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.904204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.919965] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.920041] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.920473] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  354.936832] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  354.936901] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  354.937011] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.937260] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.937318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.937374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.937425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.937472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.937516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.937561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.937607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.937650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.937692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.937977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.938029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.938074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.938119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.938168] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.938227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.938280] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.938334] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.938382] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.938459] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  354.938508] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  354.938552] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  354.938619] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  354.938691] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.938908] [drm:intel_power_well_disable [i915]] disabling DC off
>[  354.938957] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  354.938998] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  354.939459] [drm:intel_power_well_disable [i915]] disabling always-on
>[  354.939847] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.939876] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  354.940026] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  354.940079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  354.940137] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  354.940202] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  354.940253] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  354.940306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  354.940361] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  354.940411] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  354.940460] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  354.940511] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  354.940555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  354.940566] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.940613] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  354.940619] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  354.940667] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  354.940713] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  354.940944] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  354.940988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  354.941034] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  354.941087] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  354.941134] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  354.941179] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  354.941223] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  354.941265] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  354.941337] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  354.941399] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  354.941456] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  354.941619] [drm:intel_power_well_enable [i915]] enabling always-on
>[  354.941663] [drm:intel_power_well_enable [i915]] enabling DC off
>[  354.942124] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  354.942500] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  354.942553] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  354.942653] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  354.942699] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  354.942883] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  354.943101] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  354.943160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  354.943217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  354.943267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  354.943316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  354.943359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  354.943405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  354.943451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  354.943496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  354.943540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  354.943584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  354.943625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  354.943669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  354.943708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  354.943935] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  354.943991] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.944041] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  354.944199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  354.944259] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  354.944312] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  354.947937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.947995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.948044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.948096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.949209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  354.949260] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  354.949307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.950196] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  354.950245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  354.950291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  354.951211] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.951264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  354.952457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.954845] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  354.956248] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  354.956338] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  354.956389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  354.956456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  354.973233] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  354.973312] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  354.973428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  354.974070] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  354.974223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  354.989910] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  354.989983] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  354.990376] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.006833] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.006902] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.007012] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.009352] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.009419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.009482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.009537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.009588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.009636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.009683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.009945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.010002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.010052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.010104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.010163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.010215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.010268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.010324] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.010387] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.010449] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.010503] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.010559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.010637] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.010690] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.010915] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.010983] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.011061] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.011119] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.011168] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.011216] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.011684] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.012379] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.012406] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.012561] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.012615] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.012675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.012881] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.012936] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.012996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.013052] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.013108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.013159] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.013214] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.013261] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.013275] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.013321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.013329] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.013376] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.013427] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.013472] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.013519] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.013565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.013622] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.013670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.013718] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.013952] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.013997] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.014075] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.014140] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.014195] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.014367] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.014412] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.014852] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.015249] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.015306] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.015405] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.015450] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.015514] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.015679] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.015880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.015937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.015988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.016036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.016080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.016128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.016173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.016218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.016262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.016305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.016347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.016391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.016432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.016482] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.016537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.016590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.016640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.016702] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.016928] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.020505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.020564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.020616] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.020669] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.021802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.021855] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.021903] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.022943] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.022998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.023048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.023936] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.023990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.025182] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.027619] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  355.028973] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.029064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.029115] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.029183] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.045952] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.046030] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.046146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.046594] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.046819] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.062703] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.062817] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.063264] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.079808] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.079876] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.079986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.080273] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.080329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.080384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.080435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.080482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.080526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.080569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.080614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.080656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.080698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.080813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.080873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.080919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.080962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.081011] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.081071] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.081125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.081181] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.081232] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.081315] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.081364] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.081412] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.081479] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.081552] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.081605] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.081651] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.081695] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.082184] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.082454] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.082483] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.082634] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.082684] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.082784] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.082850] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.082906] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.082960] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.083016] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.083070] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.083120] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.083169] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.083214] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.083224] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.083271] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.083285] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.083332] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.083376] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.083423] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.083467] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.083509] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.083560] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.083605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.083646] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.083689] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.083766] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.083839] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.083900] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.083956] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.084122] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.084165] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.084475] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.084534] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.084580] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.084683] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.084881] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.084944] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.087188] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.087255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.087318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.087373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.087422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.087472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.087520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.087570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.087615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.087661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.087705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.087810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.087862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.087915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.087968] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.088034] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.088095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.088151] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.088216] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.088275] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.091893] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.091951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.092002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.092054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.093099] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.093150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.093197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.094297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.094349] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.094397] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.095423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.095476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.096843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.099231] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  355.100730] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.100844] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.100894] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.100962] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.117743] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.117864] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.117980] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.118432] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.118579] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.134491] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.134567] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.135127] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.151913] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.151980] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.152089] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.154433] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.154500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.154564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.154618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.154668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.154716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.154829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.154887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.154939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.154991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.155038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.155095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.155143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.155191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.155245] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.155308] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.155368] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.155422] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.155476] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.155559] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.155610] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.155660] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.155764] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.155839] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.155896] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.155947] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.155993] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.156449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.156775] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.156803] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.156956] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.157011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.157072] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.157140] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.157193] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.157248] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.157303] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.157355] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.157406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.157456] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.157504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.157514] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.157560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.157569] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.157616] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.157663] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.157708] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.157803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.157850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.157910] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.157957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.158003] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.158051] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.158096] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.158170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.158234] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.158289] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.158462] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.158507] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.158866] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.158930] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.158983] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.159087] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.159148] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.159240] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.161528] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.161597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.161662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.161718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.161863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.161941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.162010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.162087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.162157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.162229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.162294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.162360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.162423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.162486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.162556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.162638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.162702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.162824] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.162999] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.163050] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.166680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.166766] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.166818] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.166871] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.167841] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.167911] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.167983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.168879] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.168930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.168976] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.169866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.169921] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.171145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.173527] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  355.174916] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.174996] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.175047] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.175114] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.191876] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.191954] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.192070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.192536] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.192685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.208649] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.208726] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.209301] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.225855] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.225924] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.226033] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.228452] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.228519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.228582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.228637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.228687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.229131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.229183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.229234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.229281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.229325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.229368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.229419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.229461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.229502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.229551] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.229607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.229660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.229710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.230399] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.230475] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.230522] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.230569] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.230631] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.230708] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.231127] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.231174] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.231214] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.231664] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.232474] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.232502] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.232654] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.232707] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.233066] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.233130] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.233181] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.233236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.233290] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.233340] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.233390] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.233437] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.233482] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.233492] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.233535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.233544] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.233589] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.233634] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.233678] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.234424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.234471] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.234526] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.234575] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.234622] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.234667] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.234711] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.235172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.235236] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.235289] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.235455] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.235495] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.236155] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.236492] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.236540] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.236641] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.236684] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.237078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.239456] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.239523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.239586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.239642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.239691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.240127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.240177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.240228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.240275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.240319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.240364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.240407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.240450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.240493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.240542] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.240597] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.240649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.240700] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.241464] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.241516] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.245143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.245200] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.245251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.245303] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.246338] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.246391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.246440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.247424] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.247475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.247523] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.248662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.248717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.250153] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.252561] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  355.254059] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.254140] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.254191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.254259] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.271035] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.271113] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.271229] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.271677] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.272166] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.287709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.287937] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.288330] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.304828] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.304896] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.305006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.307256] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.307323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.307388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.307444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.307494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.307543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.307592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.307642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.307687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.308277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.308326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.308380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.308425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.308469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.308519] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.308576] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.308631] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.308682] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.309218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.309294] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.309341] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.309387] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.309448] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.309523] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.309575] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.309621] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.309661] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.310891] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.311156] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.311183] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.311334] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.311386] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.311443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.311505] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.311553] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.311605] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.311656] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.311704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.312328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.312379] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.312425] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.312435] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.312479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.312487] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.312533] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.312577] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.312620] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.312664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.312705] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.313298] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.313347] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.313394] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.313440] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.313482] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.313555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.313614] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.313663] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.314268] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.314308] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.314621] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.314679] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.315021] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.315121] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.315164] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.315236] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.317584] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.317650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.317713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.318079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.318131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.318181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.318228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.318278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.318321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.318363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.318405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.318447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.318488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.318529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.318578] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.318632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.318683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.319511] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.319575] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.319627] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.323275] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.323334] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.323385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.323437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.324712] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.324813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.324863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.325732] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.326088] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.326139] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.327134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.327188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.328384] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.330810] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  355.332238] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.332326] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.332377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.332444] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.349224] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.349303] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.349420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.350132] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.350296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.365892] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.366065] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.366457] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.382708] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.382824] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.382932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.383178] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.383233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.383288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.383339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.383386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.383430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.383474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.383519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.383561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.383603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.383644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.383691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.384067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.384136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.384207] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.384293] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.384374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.384452] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.384528] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.384632] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.384706] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.384995] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.385092] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.385197] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.385276] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.385348] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.385412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.386411] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.386933] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.386972] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.387205] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.387283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.387370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.387460] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.387535] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.387614] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.387693] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.387979] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.388031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.388080] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.388124] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.388134] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.388179] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.388186] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.388232] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.388276] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.388320] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.388363] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.388405] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.388457] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.388502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.388545] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.388588] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.388629] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.388700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.389060] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.389135] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.389373] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.389437] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.389946] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.390305] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.390370] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.390470] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.390536] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.390630] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.390969] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.391054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.391136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.391216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.391289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.391361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.391429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.391502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.391569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.391636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.391701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.391984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.392052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.392112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.392184] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.392267] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.392344] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.392420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.392510] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.392585] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.396175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.396233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.396283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.396335] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.397581] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.397635] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.397684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.398868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.398922] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.398971] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.399903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.399976] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.401285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.403673] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  355.405110] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.405195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.405246] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.405313] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.422090] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.422167] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.422283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.422836] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.423046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.438828] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.438900] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.439291] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.455638] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.455707] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.456117] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.456327] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.456385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.456441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.456492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.456540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.456586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.456632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.456679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.457297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.457344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.457388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.457439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.457483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.457525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.457573] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.457629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.457682] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.458285] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.458337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.458406] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.458452] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.458497] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.458559] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.458631] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.458681] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.459291] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.459332] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.460310] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.460607] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.460633] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.460906] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.460987] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.461074] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.461164] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.461239] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.461320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.461399] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.461475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.461550] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.461624] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.461687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.461743] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.461811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.461823] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.461889] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.461959] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.462030] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.462090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.462158] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.462238] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.462310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.462371] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.462439] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.462497] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.462600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.462687] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.462804] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.463043] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.463107] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.463446] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.463539] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.463606] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.463706] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.463833] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.463926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.464498] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.464556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.464612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.464664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.464712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.464965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.465035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.465108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.465176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.465245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.465311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.465377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.465443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.465509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.465582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.465667] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.465968] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.466046] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.466136] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.466210] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.469826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.469883] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.469934] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.469986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.471027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.471105] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.471178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.472221] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.472273] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.472320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.473334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.473388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.474581] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.477019] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  355.478433] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.478524] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.478574] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.478642] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.495418] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.495497] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.495614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.496251] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.496396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.512172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.512247] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.512680] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.529721] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.529846] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.529956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.530245] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.530302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.530359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.530411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.530457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.530503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.530546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.530592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.530635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.530677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.530829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.530909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.530984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.531053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.531134] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.531221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.531304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.531381] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.531457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.531567] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.531638] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.531708] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.531858] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.531968] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.532045] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.532115] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.532171] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.532650] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.533463] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.533504] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.533739] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.533884] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.533975] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.534071] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.534146] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.534225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.534302] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.534379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.534453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.534524] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.534592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.534608] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.534673] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.534706] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.534776] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.534842] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.534913] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.534985] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.535053] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.535137] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.535209] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.535281] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.535343] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.535411] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.535514] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.535599] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.535677] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.535962] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.536025] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.536360] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.536451] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.536520] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.536623] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.536691] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.536838] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.538980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.539039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.539095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.539147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.539194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.539241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.539286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.539332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.539375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.539418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.539459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.539501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.539542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.539582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.539630] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.539682] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.540913] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.540993] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.541083] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.541158] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.544781] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.544839] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.544890] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.544942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.546198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.546251] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.546299] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.547393] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.547448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.547497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.548697] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.548798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.550254] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.552643] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  355.554253] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.554334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.554387] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.554454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.571226] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.571305] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.571422] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.572070] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.572217] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.587903] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.587975] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.588369] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.604715] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.604830] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.604939] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.605224] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.605279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.605336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.605387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.605433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.605476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.605520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.605565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.605607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.605648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.605689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.606067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.606135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.606197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.606270] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.606356] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.606436] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.606512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.606586] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.606690] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.606972] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.607046] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.607143] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.607246] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.607326] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.607399] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.607463] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.608444] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.608956] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.608993] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.609224] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.609303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.609388] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.609477] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.609554] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.609635] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.609712] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.609997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.610047] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.610094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.610138] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.610148] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.610192] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.610199] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.610246] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.610289] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.610332] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.610374] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.610415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.610469] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.610511] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.610555] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.610597] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.610637] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.610708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.611064] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.611139] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.611379] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.611442] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.611968] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.612337] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.612400] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.612499] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.612565] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.612658] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.614903] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.614971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.615036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.615091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.615141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.615188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.615236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.615284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.615329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.615374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.615417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.615461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.615504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.615548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.615598] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.615656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.615709] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.616271] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.616365] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.616442] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.620130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.620188] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.620238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.620291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.621223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.621276] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.621327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.622331] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.622384] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.622434] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.623351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.623406] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.624597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.627037] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  355.628450] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.628540] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.628592] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.628662] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.645439] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.645517] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.645634] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.646306] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.646457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.662106] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.662178] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.662572] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.680813] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.680880] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.680988] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.681234] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.681291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.681345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.681397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.681444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.681489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.681534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.681580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.681623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.681665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.681707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.681876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.681943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.682018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.682096] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.682189] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.682272] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.682351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.682428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.682535] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.682606] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.682678] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.682840] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.682944] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.683024] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.683097] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.683161] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.683658] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.684425] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.684462] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.684694] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.684839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.684929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.685026] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.685100] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.685180] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.685258] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.685333] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.685406] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.685478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.685544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.685556] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.685624] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.685634] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.685706] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.685830] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.685895] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.685967] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.686036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.686117] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.686186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.686258] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.686317] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.686385] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.686489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.686574] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.686652] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.686931] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.686994] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.687329] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.687421] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.687490] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.687591] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.687658] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.687748] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.688014] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.688094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.688172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.688247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.688317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.688386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.688453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.688522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.688589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.688654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.688718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.688860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.688932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.689006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.689081] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.689167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.689247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.689325] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.689414] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.689489] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.693092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.693152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.693203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.693254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.714358] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.714386] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.714412] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.715145] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.715173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.715199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.715959] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.715987] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.717034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.719313] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  355.719978] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.720024] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.720046] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.720076] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.736829] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.736864] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.736915] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.737099] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.737163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.753512] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.753548] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.753913] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.770575] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.770644] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.771156] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.775510] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.775577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.775642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.775698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.776246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.776300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.776349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.776400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.776446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.776491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.776536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.776585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.776628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.776669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.776718] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.777616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.777704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.778019] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.778098] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.778207] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.778280] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.778353] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.778450] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.778557] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.778635] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.778707] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.779213] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.779672] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.780463] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.780492] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.780645] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.780700] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.781150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.781214] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.781265] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.781320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.781373] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.781423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.781472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.781518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.781564] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.781572] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.781617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.781624] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.781669] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.781713] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.782749] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.782996] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.783067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.783143] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.783216] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.783288] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.783357] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.783426] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.783530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.783617] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.783693] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.784366] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.784407] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.784709] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.785350] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.785399] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.785495] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.785537] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.785603] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.786187] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.786272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.786353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.786432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.786505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.786575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.786643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.786715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.787191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.787238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.787282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.787327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.787371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.787413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.787462] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.787517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.787568] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.787618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.787679] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.788633] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.792258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.792316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.792365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.792417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.793645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.793699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.794019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.794995] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.795049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.795097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.796086] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.796139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.797350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.799740] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  355.801150] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.801230] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.801281] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.801349] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.818126] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.818207] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.818323] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.818907] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.819206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.834934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.835005] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.835399] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.851638] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.851705] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.851966] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.852248] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.852307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.852362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.852414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.852460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.852506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.852549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.852595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.852639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.852680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.852831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.852906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.852977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.853047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.853125] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.853212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.853295] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.853375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.853452] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.853557] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.853628] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.853698] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.853863] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.853968] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.854049] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.854121] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.854186] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.854674] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.855474] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.855511] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.855743] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.855888] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.855979] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.856071] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.856145] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.856225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.856303] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.856380] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.856455] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.856529] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.856599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.856614] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.856679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.856741] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.856809] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.856886] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.856958] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.857029] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.857099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.857175] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.857247] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.857319] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.857380] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.857449] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.857551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.857636] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.857712] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.857993] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.858054] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.858388] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.858478] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.858546] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.858646] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.858714] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.858866] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.861117] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.861184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.861246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.861301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.861352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.861400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.861448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.861497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.861543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.861588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.861633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.861677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.861812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.861882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.861961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.862048] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.862130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.862208] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.862298] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.862373] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.866100] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.866159] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.866209] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.866262] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.867200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.867254] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.867304] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.868207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.868259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.868306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.869257] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.869331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.870547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.872996] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  355.874481] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.874564] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.874613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.874681] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.891459] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.891537] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.891652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.892459] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.892604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.908133] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.908204] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.908595] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.926818] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.926885] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.926992] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.927236] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.927292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.927346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.927397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.927444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.927488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.927531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.927576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.927618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.927660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.927702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.928975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.929028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.929077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.929128] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.929186] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.929239] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.929288] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.929337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.929405] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  355.929450] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  355.929495] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  355.929556] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  355.929626] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.929676] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.929829] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.929892] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.930374] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.930762] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.930802] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  355.931027] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  355.931099] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.931183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  355.931271] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  355.931339] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  355.931418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.931491] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  355.931563] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  355.931629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  355.931699] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  355.931809] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.931823] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.931888] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.931900] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  355.931969] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  355.932031] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  355.932097] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.932158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.932222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.932294] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.932361] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.932421] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  355.932485] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  355.932542] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  355.932645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  355.932722] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  355.932835] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  355.933072] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.933134] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.933475] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.933565] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  355.933633] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  355.933771] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  355.933843] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  355.933937] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  355.934231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  355.934308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  355.934391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  355.934472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  355.934539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  355.934612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  355.934672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  355.934775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  355.934838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  355.934907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  355.934971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  355.935041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  355.935104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  355.935170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  355.935239] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  355.935319] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.935395] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  355.935471] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  355.935559] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  355.935627] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  355.939256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  355.939314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  355.939366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  355.939418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  355.940450] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  355.940503] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  355.940552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.941502] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  355.941554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  355.941603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  355.942535] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  355.942591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  355.943850] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  355.946293] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  355.947697] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  355.947805] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  355.947857] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  355.947925] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  355.964691] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  355.964803] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  355.964915] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  355.965243] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  355.965439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.981338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  355.981408] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  355.981545] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  355.998170] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  355.998237] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  355.998344] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.000718] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.000821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.000886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.000941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.000991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.001040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.001088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.001137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.001182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.001226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.001271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.001321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.001366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.001409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.001460] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.001518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.001573] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.001627] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.001679] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.002132] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.002204] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.002277] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.002373] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.002479] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.002557] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.002630] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.002687] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.003386] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.004316] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.004356] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.004584] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.004656] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.004741] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.005019] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.005091] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.005171] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.005245] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.005321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.005390] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.005460] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.005523] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.005539] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.005601] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.005613] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.005682] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.005967] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.006029] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.006095] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.006153] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.006231] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.006291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.006357] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.006418] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.006483] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.006572] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.006642] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.006711] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.007176] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.007232] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.007572] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.007661] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.007727] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.008082] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.008150] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.008242] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.008457] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.008530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.008607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.008674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.008907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.008970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.009037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.009101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.009166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.009225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.009289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.009348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.009412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.009469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.009539] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.009618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.009695] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.009998] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.010085] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.010154] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.013811] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.013870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.013921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.013974] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.015002] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.015079] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.015146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.016110] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.016163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.016212] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.017164] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.017217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.018413] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.020806] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  356.022173] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.022369] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.022420] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.022487] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.039265] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.039343] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.039459] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.040056] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.040202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.055938] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.056009] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.056401] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.072701] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.072818] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.072926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.075128] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.075194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.075256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.075311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.075360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.075408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.075455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.075505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.075550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.075595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.075638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.075689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.075823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.075895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.075968] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.076049] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.076128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.076204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.076275] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.076385] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.076445] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.076493] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.076556] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.076629] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.076681] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.076801] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.076861] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.077343] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.077597] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.077622] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.077870] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.077926] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.077987] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.078050] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.078101] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.078157] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.078211] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.078263] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.078313] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.078360] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.078405] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.078416] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.078459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.078468] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.078513] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.078557] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.078600] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.078643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.078686] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.078805] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.078873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.078938] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.079003] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.079066] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.079170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.079253] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.079327] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.079569] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.079615] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.080006] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.080494] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.080542] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.080635] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.080677] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.080835] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.083089] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.083156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.083218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.083274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.083324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.083372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.083419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.083468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.083514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.083558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.083603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.083646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.083691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.083827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.083902] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.083986] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.084061] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.084136] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.084221] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.084295] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.087940] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.087998] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.088049] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.088101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.089074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.089124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.089173] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.090144] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.090195] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.090242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.091148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.091200] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.092391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.094805] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  356.096169] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.096256] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.096306] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.096375] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.113156] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.113235] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.113352] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.113960] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.114122] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.129919] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.129994] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.130427] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.146732] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.146859] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.146971] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.147325] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.147382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.147437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.147488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.147535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.147580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.147625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.147671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.147715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.147862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.147930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.148005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.148072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.148137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.148209] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.148292] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.148366] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.148444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.148518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.148627] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.148675] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.148796] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.148888] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.148965] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.149018] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.149065] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.149106] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.149558] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.149910] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.149938] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.150089] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.150141] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.150197] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.150257] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.150307] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.150359] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.150409] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.150457] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.150505] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.150550] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.150594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.150602] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.150646] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.150653] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.150697] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.150828] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.150895] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.150960] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.151025] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.151103] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.151168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.151234] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.151297] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.151359] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.151458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.151539] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.151611] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.151883] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.151924] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.152236] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.152297] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.152353] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.152443] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.152487] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.152551] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.152715] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.152858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.152939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.153011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.153082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.153151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.153214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.153281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.153346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.153414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.153477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.153540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.153599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.153663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.153735] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.153847] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.153899] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.153950] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.154011] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.154062] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.157647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.157705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.157849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.157935] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.158868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.158920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.158969] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.159869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.159920] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.159972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.160859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.160911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.162333] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.164721] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  356.166223] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.166304] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.166353] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.166419] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.183200] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.183278] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.183393] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.183952] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.184170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.199889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.199961] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.200351] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.216652] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.216719] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.217129] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.219463] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.219528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.219590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.219644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.219693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.220194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.220244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.220295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.220341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.220386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.220429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.220479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.220522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.220563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.220611] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.220667] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.221369] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.221426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.221478] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.221546] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.221592] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.221636] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.221697] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.222243] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.222296] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.222342] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.222382] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.223507] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.223926] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.223951] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.224104] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.224158] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.224215] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.224277] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.224328] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.224381] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.224434] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.224483] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.224530] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.224574] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.224618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.224626] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.224668] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.224675] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.225763] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.225812] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.225859] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.225904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.225946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.225999] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.226042] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.226085] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.226127] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.226168] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.226237] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.226294] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.226343] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.226502] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.226541] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.227689] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.228042] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.228095] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.228196] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.228239] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.228305] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.228513] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.228571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.228626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.228677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.229355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.229405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.229452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.229500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.229546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.229589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.229631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.229672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.229712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.230359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.230411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.230467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.230518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.230567] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.230626] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.230677] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.234721] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.234823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.234874] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.234927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.236205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.236258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.236306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.237315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.237366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.237413] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.238305] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.238358] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.239550] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.242024] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  356.243410] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.243491] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.243543] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.243610] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.260386] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.260464] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.260579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.261155] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.261300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.277059] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.277131] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.277523] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.295876] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.295943] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.296053] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.298390] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.298456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.298521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.298577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.298629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.298679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.299388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.299455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.299503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.299549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.299594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.299645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.299687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.300464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.300519] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.300580] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.300636] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.300687] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.301239] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.301316] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.301364] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.301409] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.301472] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.301548] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.301600] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.301645] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.301685] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.303408] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.304340] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.304369] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.304523] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.304578] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.304636] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.304699] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.305324] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.305390] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.305444] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.305493] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.305543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.305589] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.305634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.305642] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.305687] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.306486] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.306549] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.306599] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.306645] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.306690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.307283] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.307339] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.307390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.307439] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.307485] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.307529] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.307602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.307662] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.307712] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.308657] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.308697] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.309386] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.309447] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.309502] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.309591] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.309633] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.309701] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.312590] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.312657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.312719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.313211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.313265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.313314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.313360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.313408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.313452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.313496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.313539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.313581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.313623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.313664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.313712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.314744] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.315051] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.315108] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.315173] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.315225] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.318818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.318876] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.318926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.318978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.320272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.320325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.320375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.321619] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.321672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.321720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.323115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.323172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.324527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.327015] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  356.328575] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.328666] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.328717] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.329179] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.345559] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.345637] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.346091] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.346540] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.346684] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.362241] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.362312] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.362704] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.379812] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.379880] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.379988] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.382383] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.382448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.382509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.382563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.382612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.382660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.382708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.383461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.383513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.383562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.383609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.383663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.383707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.384334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.384388] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.384449] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.384505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.384557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.384607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.384676] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.385360] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.385414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.385476] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.385552] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.385603] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.385648] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.385687] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.387283] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.387533] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.387558] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.387709] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.388198] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.388258] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.388322] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.388371] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.388424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.388477] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.388525] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.388573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.388617] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.388660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.388668] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.388711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.389778] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.389837] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.389888] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.389936] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.389983] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.390027] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.390080] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.390125] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.390169] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.390212] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.390255] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.390326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.390384] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.390434] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.390593] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.390632] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.392329] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.392698] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.392849] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.392990] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.393051] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.393144] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.395597] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.395666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.395858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.395934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.396003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.396073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.396136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.396207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.396267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.396333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.396393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.396457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.396516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.396579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.396645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.396726] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.396853] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.396930] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.397018] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.397087] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.400692] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.400790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.400841] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.400895] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.402249] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.402304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.402354] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.403490] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.403545] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.403594] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.404810] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.404865] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.406314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.408815] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  356.410282] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.410365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.410417] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.410485] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.427249] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.427326] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.427439] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.427930] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.428145] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.443896] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.443967] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.444088] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.461330] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.461399] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.461506] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.463749] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.463857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.463920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.463975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.464025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.464074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.464121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.464170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.464215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.464259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.464303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.464352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.464396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.464439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.464490] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.464549] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.464605] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.464658] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.464709] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.466184] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.466258] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.466331] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.466430] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.466539] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.466618] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.466690] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.467291] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.468286] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.468573] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.468601] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.469100] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.469156] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.469214] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.469276] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.469326] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.469378] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.469431] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.469479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.469525] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.469569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.469612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.469620] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.469662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.469669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.469713] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.470854] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.470929] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.471001] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.471072] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.471147] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.471218] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.471290] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.471352] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.471421] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.471525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.471611] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.471689] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.472826] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.472867] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.473182] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.473241] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.473283] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.473407] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.473448] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.473515] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.474376] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.474459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.474542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.474621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.474693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.475179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.475229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.475284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.475336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.475390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.475437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.475480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.475522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.475564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.475613] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.475667] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.475718] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.476635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.476728] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.477043] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.480651] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.480711] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.481070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.481151] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.482301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.482355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.482405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.483583] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.483637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.483686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.484911] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.484967] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.486220] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.488611] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  356.490097] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.490178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.490229] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.490296] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.507026] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.507100] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.507212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.507600] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.508038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.523712] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.523845] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.523982] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.541223] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.541290] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.541397] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.541601] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.541657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.541713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.542040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.542117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.542185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.542257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.542334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.542403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.542473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.542541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.542617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.542683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.542961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.543033] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.543118] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.543199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.543276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.543351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.543454] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.543526] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.543600] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.543700] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.544025] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.544104] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.544176] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.544240] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.544730] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.545459] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.545485] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.545638] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.545693] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.545956] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.546047] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.546127] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.546211] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.546294] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.546370] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.546446] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.546517] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.546588] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.546602] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.546670] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.546683] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.546992] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.547062] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.547131] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.547193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.547261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.547333] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.547401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.547462] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.547529] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.547588] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.547691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.547997] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.548073] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.548316] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.548381] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.548721] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.549260] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.549328] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.549428] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.549494] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.549589] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.551834] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.551903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.551968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.552023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.552071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.552118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.552165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.552212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.552257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.552301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.552346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.552390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.552433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.552476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.552526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.552584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.552637] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.552689] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.553258] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.553336] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.557059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.557117] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.557167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.557221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.558160] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.558213] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.558262] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.559168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.559220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.559267] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.560190] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.560244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.561474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.563916] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  356.565381] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.565464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.565516] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.565584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.582365] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.582445] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.582563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.583271] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.583424] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.599035] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.599107] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.599499] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.617829] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.617896] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.618003] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.620245] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.620310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.620372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.620428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.620479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.620528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.620575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.620624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.620669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.620715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.621056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.621136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.621207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.621274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.621351] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.621437] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.621519] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.621595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.621671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.621989] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.622065] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.622138] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.622236] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.622340] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.622421] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.622493] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.622558] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.623538] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.624043] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.624070] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.624222] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.624276] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.624334] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.624396] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.624446] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.624497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.624548] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.624597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.624645] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.624689] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.625007] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.625095] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.625165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.625176] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.625243] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.625311] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.625371] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.625439] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.625496] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.625576] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.625644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.625713] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.626003] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.626070] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.626177] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.626260] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.626339] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.626579] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.626643] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.627161] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.627530] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.627595] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.627700] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.627940] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.628035] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.628275] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.628357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.628439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.628516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.628589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.628662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.628732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.629033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.629101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.629169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.629235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.629302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.629367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.629431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.629503] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.629584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.629661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.629739] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.630052] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.630127] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.633749] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.633845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.633895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.633948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.635045] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.635123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.635199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.636220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.636272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.636320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.637334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.637388] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.638582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.641021] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  356.642441] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.642524] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.642575] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.642644] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.659423] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.659502] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.659619] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.660292] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.660442] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.676090] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.676163] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.676555] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.714687] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.714803] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.714910] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.715116] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.715173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.715229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.715281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.715330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.715377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.715422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.715469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.715512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.715554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.715595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.715643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.715684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.716550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.716601] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.716660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.716714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.717032] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.717082] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.717153] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.717198] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.717244] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.717306] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.717377] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.717427] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.717472] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.717513] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.718760] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.718989] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.719014] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.719162] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.719215] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.719272] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.719335] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.719385] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.719437] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.719489] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.719538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.719586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.719632] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.719676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.720447] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.720497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.720505] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.720555] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.720601] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.720646] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.720690] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.721145] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.721197] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.721241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.721285] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.721327] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.721369] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.721437] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.721495] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.721546] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.721703] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.722290] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.722608] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.722668] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.722720] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.723083] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.723126] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.723193] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.727651] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.727697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.727916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.727956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.727993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.728027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.728061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.728095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.728128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.728160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.728192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.728223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.728254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.728284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.728319] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.728359] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.728397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.728434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.728478] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.728514] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.731968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.732008] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.732043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.732080] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.733063] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.733100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.733134] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.733950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.733986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.734019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.734877] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.734905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.736063] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.738387] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  356.739226] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.739273] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.739301] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.739338] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.756095] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.756137] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.756200] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.756434] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.756511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.772813] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.772859] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.773109] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.789693] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.789861] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.789967] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.792353] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.792418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.792480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.792535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.792585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.792633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.792681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.793210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.793260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.793309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.793356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.793411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.793458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.793504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.793556] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.793617] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.793675] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.794249] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.794304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.794377] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.794426] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.794474] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.794538] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.794613] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.794666] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.794714] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.795270] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.796239] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.796480] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.796505] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.796657] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.796714] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.797091] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.797160] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.797213] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.797273] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.797329] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.797383] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.797434] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.797484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.797533] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.797543] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.797589] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.797597] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.797646] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.797692] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.798471] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.798521] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.798569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.798625] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.798673] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.798720] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.799114] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.799160] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.799238] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.799300] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.799355] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.799516] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.799558] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.800275] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.800609] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.800664] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.800843] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.800912] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.801008] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.803218] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.803286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.803347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.803403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.803561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.803610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.803657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.803706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.803845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.803914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.803990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.804060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.804130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.804198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.804276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.804362] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.804442] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.804521] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.804610] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.804685] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.808379] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.808438] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.808490] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.808545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.809622] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.809677] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.809925] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.810927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.810979] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.811026] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.811969] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.812047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.813369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.815811] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  356.817297] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.817391] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.817443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.817511] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.834283] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.834362] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.834480] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.835266] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.835415] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.850954] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.851026] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.851421] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.867713] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.867821] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.867930] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.870226] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.870291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.870354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.870410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.870460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.870508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.870555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.870605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.870651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.870696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.871567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.871648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.871722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.872050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.872103] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.872164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.872219] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.872271] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.872320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.872392] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.872438] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.872482] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.872544] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.872615] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.872665] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.872711] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.873679] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.874338] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.874590] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.874615] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.875091] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.875147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.875207] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.875269] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.875318] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.875372] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.875424] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.875474] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.875522] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.875568] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.875611] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.875620] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.875662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.875669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.875713] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.876860] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.876934] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.876999] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.877069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.877142] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.877211] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.877273] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.877341] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.877399] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.877503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.877586] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.877662] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.878597] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.878637] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.879222] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.879544] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.879598] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.879690] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.880097] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.880165] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.880371] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.880429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.880484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.880535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.880583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.880629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.880673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.881436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.881508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.881579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.881956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.882002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.882046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.882090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.882139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.882196] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.882247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.882298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.882359] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.882410] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.886037] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.886096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.886146] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.886199] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.887458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.887511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.887559] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.888681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.888770] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.888819] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.889679] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.890117] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.891367] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.893792] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  356.895264] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.895354] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.895405] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.895471] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.912247] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.912325] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.912440] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.913155] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.913305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  356.928927] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  356.928999] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  356.929389] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  356.945724] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  356.945831] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  356.945939] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.946144] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.946199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.946254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.946305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.946351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.946397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.946441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.946486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.946529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.946571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.946613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.946660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.946701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.947539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.947589] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.947649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.947706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.948049] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.948100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.948170] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  356.948216] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  356.948262] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  356.948324] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  356.948395] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.948445] [drm:intel_power_well_disable [i915]] disabling DC off
>[  356.948491] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  356.948530] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  356.949780] [drm:intel_power_well_disable [i915]] disabling always-on
>[  356.950002] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.950027] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  356.950175] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  356.950228] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  356.950285] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  356.950346] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  356.950395] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  356.950446] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  356.950497] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  356.950546] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  356.950594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  356.950638] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  356.950682] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  356.951378] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.951426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  356.951433] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  356.951481] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  356.951526] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  356.951574] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  356.951619] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  356.951664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  356.951719] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  356.952323] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  356.952370] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  356.952414] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  356.952458] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  356.952528] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  356.952587] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  356.952638] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  356.953185] [drm:intel_power_well_enable [i915]] enabling always-on
>[  356.953225] [drm:intel_power_well_enable [i915]] enabling DC off
>[  356.953540] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  356.953599] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  356.953646] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  356.953838] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  356.953906] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  356.953999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  356.958554] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  356.958622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  356.958686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  356.959162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  356.959216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  356.959265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  356.959312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  356.959360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  356.959404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  356.959447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  356.959490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  356.959532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  356.959575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  356.959616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  356.959664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  356.960727] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.960967] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  356.961022] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  356.961088] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  356.961139] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  356.964722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.964825] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.964876] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.964929] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.966220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  356.966275] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  356.966324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.967578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  356.967630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  356.967679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  356.968889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.968944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  356.970354] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.972822] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  356.974308] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  356.974392] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  356.974443] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  356.974511] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  356.991296] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  356.991374] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  356.991489] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  356.992164] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  356.992317] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.007953] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  357.008024] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.008416] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  357.024812] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  357.024878] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.024986] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.025231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.025286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.025343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.025393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.025439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.025484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.025528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.025574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.025617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.025660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.025703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.026470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.026519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.026564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.026618] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.026680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.027049] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.027101] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.027153] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.027223] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.027270] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.027315] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.027377] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.027450] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.027501] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.027547] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.027587] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.028851] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.029099] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.029125] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.029275] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.029328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.029387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.029448] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.029497] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.029549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.029600] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  357.029649] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  357.029696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.030410] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.030457] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.030468] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.030516] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.030526] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.030573] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.030621] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.030667] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.030712] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.031238] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.031291] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.031337] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.031381] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  357.031424] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  357.031465] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  357.031536] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.031593] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  357.031644] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  357.032267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.032307] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.032617] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.032676] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.032989] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.033097] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.033142] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.033208] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.035551] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.035617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.035679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.036031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.036086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.036138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.036187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.036238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.036286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.036331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.036377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.036423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.036468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.036513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.036563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.036620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.036674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.037432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.037500] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  357.037559] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.041252] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.041311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.041363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.041416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.042610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.042663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.042713] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.043883] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.043936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.043984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.044858] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.044911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.046114] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.048494] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  357.049833] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  357.049919] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.049970] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  357.050038] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.066863] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.066942] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.067059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.067548] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.067696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.083489] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  357.083560] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.084033] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  357.100843] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  357.100911] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.101021] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.103364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.103430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.103494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.103551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.103601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.103649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.103696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.103825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.103879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.103931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.103981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.104040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.104087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.104136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.104191] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.104256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.104315] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.104371] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.104425] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.104507] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.104559] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.104609] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.104677] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.104793] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.104848] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.104898] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.104944] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.105399] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.105673] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.105759] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.105919] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.105976] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.106038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.106106] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.106160] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.106219] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.106275] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  357.106329] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  357.106381] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.106432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.106480] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.106492] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.106538] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.106547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.106595] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.106642] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.106690] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.106769] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.106816] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.106874] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.106922] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.106970] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  357.107016] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  357.107062] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  357.107136] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.107201] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  357.107256] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  357.107433] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.107476] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.107836] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.107900] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.107955] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.108055] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.108097] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.108162] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.110364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.110430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.110492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.110547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.110598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.110645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.110693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.111192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.111242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.111290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.111336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.111383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.111429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.111475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.111526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.111585] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.111640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.111693] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.112297] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  357.112352] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.116117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.116174] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.116224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.116277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.117448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.117502] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.117552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.118662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.118714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.118983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.119973] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.120028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.121426] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.123816] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  357.125259] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  357.125340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.125389] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  357.125456] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.142235] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.142313] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.142430] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.142992] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.143144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.158917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  357.158990] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.159382] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  357.175727] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  357.175834] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.175941] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.176107] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.176163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.176218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.176269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.176315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.176360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.176403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.176449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.176490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.176532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.176574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.176621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.176662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.176703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.177658] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.177717] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.177957] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.178009] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.178059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.178127] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.178173] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.178217] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.178279] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.178349] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.178399] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.178551] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.178591] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.179912] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.180140] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.180166] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.180314] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.180367] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.180425] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.180487] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.180537] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.180587] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.180638] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  357.180687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  357.181328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.181376] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.181424] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.181433] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.181479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.181487] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.181534] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.181577] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.181622] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.181664] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.181706] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.182414] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.182464] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.182512] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  357.182557] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  357.182601] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  357.182670] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.183097] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  357.183150] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  357.183310] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.183349] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.183666] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.184039] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.184091] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.184190] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.184232] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.184297] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.184503] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.184559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.184615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.184666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.184712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.185306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.185355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.185405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.185452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.185496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.185540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.185583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.185627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.185670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.185719] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.186286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.186339] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.186390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.186452] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  357.186502] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.190059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.190114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.190165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.190217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.191388] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.191439] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.191487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.192644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.192694] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.192957] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.193873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.193926] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.195142] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.197526] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  357.198996] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  357.199081] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.199131] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  357.199196] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.216004] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.216084] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.216201] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.216680] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.217215] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.232655] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  357.232730] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.233415] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  357.249937] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  357.250006] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.250114] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.250276] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.250334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.250390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.250441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.250489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.250534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.250578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.250624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.250666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.250707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.251477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.251533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.251581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.251628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.251678] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.252043] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.252097] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.252149] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.252199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.252272] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.252318] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.252363] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.252425] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.252497] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.252547] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.252593] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.252632] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.253969] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.254233] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.254260] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.254412] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.254465] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.254522] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.254583] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.254632] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.254682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.255300] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  357.255351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  357.255398] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.255445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.255487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.255497] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.255539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.255546] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.255592] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.255635] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.255678] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.256305] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.256349] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.256402] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.256448] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.256492] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  357.256536] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  357.256686] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  357.257152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.257213] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  357.257265] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  357.257431] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.257470] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.258110] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.258440] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.258491] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.258589] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.258631] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.258696] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.259253] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.259311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.259367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.259419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.259467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.259513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.259559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.259605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.259647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.259689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.260281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.260329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.260375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.260421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.260470] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.260527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.260578] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.260627] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.260690] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  357.261264] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.264906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.264964] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.265014] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.265066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.266188] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.266242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.266292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.267175] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.267225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.267272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.268150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.268201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.269388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.271805] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  357.273231] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  357.273315] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.273364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  357.273430] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.290209] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.290286] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.290402] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.290930] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.291081] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.306882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  357.306953] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.307346] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  357.323729] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  357.323837] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.323945] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.324191] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.324247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.324303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.324354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.324401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.324446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.324490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.324535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.324578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.324619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.324660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.324707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.325552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.325599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.325652] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.325711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.326032] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.326083] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.326135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.326203] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.326249] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.326293] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.326355] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.326424] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  357.326475] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.326520] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.326560] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.327954] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.328475] [drm:drm_mode_addfb2] [FB:68]
>[  357.328545] [drm:drm_mode_addfb2] [FB:110]
>[  357.421093] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  357.421445] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  357.421498] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.422042] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.422056] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.422132] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.422148] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.422167] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.422186] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.422200] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.422216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.422231] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.422245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.422259] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.422272] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.422284] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.422286] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.422299] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.422302] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.422314] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.422326] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.422339] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.422351] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.422363] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.422377] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.422390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.422402] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.422414] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.422425] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.422445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.422463] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.422477] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.423541] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.423551] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.423896] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.423923] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.423951] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.423977] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.423988] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.424006] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.424366] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.424381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.424395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.424408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.424420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.424432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.424443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.424456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.424467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.424477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.424488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.424499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.424509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.424520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.424532] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.424546] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.424559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.424571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.424587] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.424599] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.427814] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.427829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.427843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.427858] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.428522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.428535] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.428548] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.429297] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.429311] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.429324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.430014] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.430029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.431004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.433289] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  357.433823] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.433859] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.433872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.433891] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.450720] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.450741] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.450774] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.467336] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.467343] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.484095] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.484173] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.500709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  357.500786] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.500859] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  357.518247] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  357.518315] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.518424] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.518635] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.518691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.518836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.518900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.518958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.519007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.519057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.519108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.519157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.519202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.519245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.519295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.519346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.519388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.519443] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.519499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.519551] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.519606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.519660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.519776] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.519825] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.519871] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.519936] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.520008] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.520060] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.520106] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.520148] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.520609] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.520921] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.520949] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.521098] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.521147] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.521203] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.521266] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.521316] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.521367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.521417] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.521464] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.521509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.521552] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.521594] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.521603] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.521645] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.521652] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.521695] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.521792] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.521838] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.521885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.521932] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.521992] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.522039] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.522087] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.522134] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.522288] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.522358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.522416] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.522468] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.522614] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.522654] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.523014] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.523078] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.523127] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.523238] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.523286] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.523352] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.523565] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.523621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.523677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.523779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.523831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.523879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.523933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.523982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.524030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.524075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.524120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.524165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.524212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.524256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.524307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.524364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.524418] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.524473] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.524535] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.524590] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.528245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.528306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.528358] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.528412] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.529304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.529354] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.529400] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.530273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.530321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.530366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.531248] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.531297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.532482] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.534921] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  357.536281] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.536363] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.536414] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.536483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.553265] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.553345] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.553568] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.554105] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.554256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.569934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  357.570005] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.570395] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  357.586708] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  357.586814] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.586922] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.587210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.587266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.587323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.587374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.587423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.587468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.587512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.587559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.587602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.587647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.587689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.587965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.588011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.588058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.588107] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.588164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.588221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.588274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.588326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.588399] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.588446] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.588493] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.588557] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.588627] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.588678] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.588901] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.588942] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.589411] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.589663] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.589820] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.589970] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.590021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.590077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.590138] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.590187] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.590238] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.590289] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.590337] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.590383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.590429] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.590472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.590480] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.590523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.590530] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.590574] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.590616] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.590657] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.590698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.590953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.591011] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.591056] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.591101] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.591142] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.591185] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.591257] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.591316] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.591370] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.591530] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.591571] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.592029] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.592395] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.592448] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.592548] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.592591] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.592653] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.592891] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.592948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.593004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.593057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.593106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.593153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.593199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.593246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.593290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.593334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.593378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.593420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.593463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.593504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.593554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.593608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.593659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.593710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.593952] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.594001] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.597578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.597637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.597688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.597912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.598936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.598990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.599039] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.599941] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.599997] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.600048] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.601115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.601168] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.602364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.604842] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  357.606290] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.606380] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.606432] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.606499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.623274] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.623354] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.623468] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.623991] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.624141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.640021] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  357.640096] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.640531] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  357.656828] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  357.656895] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.657005] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.657249] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.657305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.657361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.657412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.657459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.657503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.657546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.657591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.657633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.657674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.658423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.658477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.658524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.658568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.658618] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.658677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.659083] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.659136] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.659190] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.659264] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.659312] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.659357] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.659420] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.659491] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.659541] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.659586] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.659625] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.660992] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.661262] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.661290] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.661441] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.661492] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.661549] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.661611] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.661660] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.661711] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.662275] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.662327] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.662378] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.662424] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.662470] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.662478] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.662524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.662531] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.662577] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.662622] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.662666] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.662708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.663499] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.663553] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.663604] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.663653] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.663698] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.664058] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.664134] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.664195] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.664248] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.664414] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.664453] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.665134] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.665463] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.665516] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.665610] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.665651] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.665715] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.668308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.668375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.668438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.668493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.668543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.668593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.668640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.668689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.669323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.669374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.669424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.669471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.669518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.669565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.669618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.669678] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.670170] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.670226] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.670292] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.670347] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.673927] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.673985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.674036] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.674089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.675128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.675206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.675283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.676183] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.676236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.676283] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.677187] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.677240] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.678437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.680928] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  357.682351] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.682438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.682490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.682557] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.714478] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.714534] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.714616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.715054] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.715160] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.715959] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  357.716010] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.716091] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  357.733184] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  357.733230] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.733305] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.735509] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.735555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.735601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.735639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.735674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.735707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.735807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.735849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.735889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.735926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.735962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.736004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.736040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.736078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.736120] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.736167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.736212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.736254] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.736297] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.736361] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.736399] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.736437] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.736487] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.736542] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.736580] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.736615] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.736647] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.737125] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.737316] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.737336] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.737442] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.737478] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.737520] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.737564] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.737600] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.737638] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.737676] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.737749] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.737785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.737830] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.737864] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.737876] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.737914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.737922] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.737961] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.737996] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.738032] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.738066] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.738102] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.738148] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.738185] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.738223] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.738256] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.738292] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.738346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.738390] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.738434] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.738558] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.738588] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.738911] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.738956] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.738992] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.739092] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.739123] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.739170] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.739645] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.739685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.739769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.739812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.739851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.739888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.739924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.739961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.739995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.740030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.740064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.740099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.740132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.740165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.740204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.740245] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.740283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.740321] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.740365] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.740404] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.743888] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.743929] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.743965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.744001] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.744818] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.744858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.744896] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.745669] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.745702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.745780] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.746553] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.746587] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.747682] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.750027] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  357.750992] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.751058] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.751092] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.751139] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.768000] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.768078] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.768194] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.768577] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.768727] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.784627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  357.784698] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.784918] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  357.802270] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  357.802337] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.802448] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.802614] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.802671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.802819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.802883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.802939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.802987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.803040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.803089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.803140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.803187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.803232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.803537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.803582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.803626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.803677] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.803777] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.803835] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.803887] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.803941] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.804019] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.804247] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.804294] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.804356] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.804429] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.804479] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.804524] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.804564] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.805070] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.805775] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.805802] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.805952] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.806003] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.806061] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.806123] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.806171] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.806224] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.806275] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.806325] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.806372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.806419] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.806462] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.806472] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.806515] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.806522] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.806566] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.806607] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.806650] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.806692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.806779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.806831] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.806885] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.806932] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.806978] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.807023] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.807093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.807154] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.807208] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.807375] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.807416] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.807795] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.808295] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.808341] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.808410] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.808452] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.808514] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.810906] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.810975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.811038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.811093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.811144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.811192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.811240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.811290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.811335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.811378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.811423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.811465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.811509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.811553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.811604] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.811661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.811714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.811862] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.811938] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.811998] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.815617] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.815674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.815770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.815853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.816850] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.816901] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.816949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.817870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.817937] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.818009] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.818910] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.818963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.820173] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.822614] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  357.824076] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.824160] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.824212] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.824280] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.841061] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.841139] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.841256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.841832] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.842051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.857728] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  357.857837] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.857946] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  357.875109] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  357.875176] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.875284] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.875488] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.875544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.875599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.875650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.875698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.875831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.875905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.875979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.876044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.876113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.876175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.876249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.876310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.876378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.876447] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.876533] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.876611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.876682] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.876811] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.876922] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.876994] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.877067] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.877165] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.877268] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.877343] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.877414] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.877472] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.878036] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.878817] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.878855] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.879083] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.879157] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.879242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.879331] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.879401] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.879480] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.879551] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.879625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.879693] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.879815] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.879882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.879901] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.879964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.879980] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.880053] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.880117] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.880186] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.880247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.880315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.880391] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.880462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.880525] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.880597] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.880659] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.880805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.880884] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.880959] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.881193] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.881248] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.881681] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.882116] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.882182] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.882281] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.882341] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.882432] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.882663] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.882736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.882873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.882956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.883022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.883095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.883160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.883233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.883295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.883366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.883429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.883495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.883558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.883626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.883692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.883818] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.883899] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.883977] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.884064] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.884132] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.887803] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.887862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.887913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.887965] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.888876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.888946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.889015] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.889930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.889982] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.890030] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.890928] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.891000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.892285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.894668] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  357.896108] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.896195] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.896245] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.896311] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.913135] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.913212] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.913325] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.914153] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.914302] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.929808] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  357.929880] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  357.929988] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  357.947275] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  357.947342] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  357.947450] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.947614] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.947670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.947725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.948388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.948441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.948489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.948537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.948587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.948632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.948676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.949323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.949380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.949427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.949473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.949523] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.949579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.949632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.949683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.950447] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.950518] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  357.950564] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  357.950609] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  357.950671] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  357.951215] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.951267] [drm:intel_power_well_disable [i915]] disabling DC off
>[  357.951314] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  357.951354] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  357.952476] [drm:intel_power_well_disable [i915]] disabling always-on
>[  357.952786] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.952822] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  357.953037] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  357.953092] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.953150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  357.953211] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  357.953260] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  357.953313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.953365] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  357.953415] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  357.953463] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  357.953509] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  357.953553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.953561] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.953605] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.953612] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  357.953657] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  357.953699] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  357.953822] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  357.953889] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.953955] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.954030] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.954098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.954162] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  357.954231] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  357.954292] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  357.954394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  357.954475] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  357.954554] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  357.954830] [drm:intel_power_well_enable [i915]] enabling always-on
>[  357.954887] [drm:intel_power_well_enable [i915]] enabling DC off
>[  357.955228] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  357.955318] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.955386] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  357.955486] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  357.955554] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  357.955644] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  357.956004] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  357.956081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  357.956159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  357.956230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  357.956302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  357.956366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  357.956433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  357.956499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  357.956565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  357.956625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  357.956692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  357.956977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  357.957035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  357.957099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  357.957164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  357.957243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.957313] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  357.957386] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  357.957472] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  357.957540] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.961253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.961312] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.961363] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.961415] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.962459] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  357.962512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  357.962561] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.963563] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  357.963615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  357.963664] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  357.964800] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.964855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.966238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.968623] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  357.970115] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  357.970193] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  357.970243] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  357.970309] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  357.987097] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  357.987178] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  357.987294] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  357.987952] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  357.988153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.003830] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.003905] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.004015] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.021408] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.021477] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.021587] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.023844] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.023909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.023973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.024027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.024077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.024125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.024172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.024221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.024266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.024310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.024353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.024402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.024446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.024489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.024539] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.024597] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.024652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.024704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.025825] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.025903] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.025951] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.025997] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.026060] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.026135] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.026185] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.026230] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.026270] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.027538] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.027994] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.028022] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.028177] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.028232] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.028290] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.028352] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.028401] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.028454] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.028506] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.028554] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.028603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.028649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.028693] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.029461] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.029511] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.029518] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.029567] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.029613] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.029658] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.029701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.030302] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.030358] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.030407] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.030455] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.030499] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.030542] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.030613] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.030673] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.030723] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.031447] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.031487] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.032041] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.032378] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.032430] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.032530] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.032572] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.032638] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.033144] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.033202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.033257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.033309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.033356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.033401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.033447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.033493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.033536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.033578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.033620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.033662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.033703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.034470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.034521] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.034577] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.034628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.034677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.035116] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.035168] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.038746] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.038829] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.038880] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.038934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.040198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.040253] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.040303] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.041213] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.041265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.041312] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.042265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.042319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.043513] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.045995] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  358.047540] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.047623] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.047675] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.048052] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.064525] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.064606] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.064722] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.065531] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.065677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.081271] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.081351] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.081467] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.098833] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.098901] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.099012] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.101364] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.101431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.101496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.101550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.101601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.101649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.101696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.102287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.102336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.102381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.102425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.102475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.102517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.102559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.102607] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.102663] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.102716] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.103364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.103416] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.103491] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.103538] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.103583] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.103645] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.103719] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.104240] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.104287] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.104327] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.105353] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.105620] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.105646] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.106063] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.106116] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.106175] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.106237] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.106287] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.106340] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.106393] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.106442] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.106489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.106534] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.106577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.106586] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.106629] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.106636] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.106681] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.107640] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.107688] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.107984] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.108031] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.108085] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.108132] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.108178] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.108221] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.108263] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.108335] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.108395] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.108446] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.108610] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.108649] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.109656] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.110186] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.110238] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.110335] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.110377] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.110443] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.110611] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.110668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.110724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.111280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.111330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.111378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.111424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.111471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.111515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.111557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.111598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.111639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.111680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.112308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.112360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.112416] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.112467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.112515] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.112576] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.112626] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.116374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.116433] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.116484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.116537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.117815] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.117867] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.117914] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.119141] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.119194] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.119243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.120375] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.120430] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.121748] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.124175] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  358.125684] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.125803] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.125853] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.125921] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.142711] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.142845] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.142963] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.143456] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.143608] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.159454] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.159530] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.159644] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.177085] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.177152] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.177263] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.179514] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.179581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.179645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.179700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.180178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.180230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.180278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.180327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.180371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.180415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.180459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.180508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.180550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.180591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.180640] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.180696] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.181446] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.181500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.181552] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.181626] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.181672] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.182162] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.182226] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.182301] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.182351] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.182397] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.182437] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.183585] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.184002] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.184029] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.184184] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.184237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.184296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.184357] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.184406] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.184457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.184509] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.184557] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.184605] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.184649] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.184692] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.185447] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.185495] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.185503] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.185551] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.185598] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.185644] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.185687] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.186235] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.186291] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.186340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.186387] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.186432] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.186476] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.186548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.186608] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.186658] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.187371] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.187411] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.187964] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.188286] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.188335] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.188433] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.188475] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.188542] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.188705] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.189308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.189365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.189417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.189464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.189510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.189554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.189600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.189644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.189686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.190274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.190321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.190366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.190410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.190459] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.190514] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.190564] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.190613] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.190673] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.190724] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.194943] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.195001] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.195053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.195106] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.196132] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.196183] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.196230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.197411] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.197464] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.197514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.198689] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.198792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.200278] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.202678] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  358.204219] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.204310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.204360] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.204427] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.221217] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.221297] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.221413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.222252] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.222410] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.237882] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.237953] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.238061] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.255530] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.255598] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.255709] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.256279] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.256338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.256396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.256448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.256497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.256543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.256696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.257313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.257362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.257408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.257454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.257503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.257546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.257587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.257636] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.257692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.258298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.258352] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.258403] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.258478] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.258523] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.258568] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.258630] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.258705] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.259255] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.259302] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.259343] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.260351] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.260617] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.260644] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.261065] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.261120] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.261178] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.261240] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.261289] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.261343] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.261396] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.261444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.261493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.261538] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.261583] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.261591] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.261634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.261641] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.261685] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.262603] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.262650] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.262695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.263040] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.263095] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.263141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.263186] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.263230] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.263273] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.263344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.263404] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.263455] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.263617] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.263656] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.264679] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.265045] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.265097] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.265197] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.265240] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.265304] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.265514] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.265570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.265623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.265674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.266312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.266361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.266407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.266454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.266497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.266539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.266581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.266623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.266664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.266704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.267348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.267406] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.267458] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.267508] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.267570] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.267620] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.271276] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.271333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.271385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.271438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.272804] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.272859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.272908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.274116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.274168] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.274216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.275367] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.275423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.276715] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.279129] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  358.280542] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.280622] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.280672] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.280866] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.297533] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.297612] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.297729] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.298390] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.298542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.314200] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.314272] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.314380] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.331604] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.331671] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.331956] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.334310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.334375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.334437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.334491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.334542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.334591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.334638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.335347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.335397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.335445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.335492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.335545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.335590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.335634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.335686] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.336227] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.336286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.336340] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.336391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.336465] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.336513] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.336562] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.336627] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.336702] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.337301] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.337352] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.337395] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.338388] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.338638] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.338664] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.339083] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.339140] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.339202] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.339267] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.339320] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.339375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.339430] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.339482] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.339533] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.339580] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.339626] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.339634] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.339679] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.340392] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.340447] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.340500] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.340550] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.340600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.340647] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.340705] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.341182] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.341232] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.341278] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.341324] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.341397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.341459] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.341512] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.341675] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.342164] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.342488] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.342550] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.342607] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.342700] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.343045] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.343113] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.343319] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.343375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.343430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.343482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.343529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.343575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.343620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.343667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.343711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.344326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.344373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.344420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.344466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.344510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.344560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.344616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.344668] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.344718] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.345247] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.345297] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.348918] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.348976] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.349027] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.349079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.350267] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.350428] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.350476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.351634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.351685] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.351947] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.352968] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.353023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.354428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.356820] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  358.358287] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.358365] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.358415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.358481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.375247] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.375327] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.375444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.376189] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.376340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.391937] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.392008] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.392115] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.409353] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.409421] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.409529] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.409692] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.410093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.410150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.410206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.410253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.410300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.410346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.410394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.410437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.410482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.410524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.410572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.410615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.410657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.410705] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.411434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.411490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.411541] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.411591] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.411660] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.411706] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.412093] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.412155] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.412229] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.412281] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.412327] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.412366] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.413598] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.413951] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.413976] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.414128] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.414181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.414238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.414299] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.414349] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.414401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.414453] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.414502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.414549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.414593] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.414637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.414645] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.414688] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.415437] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.415487] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.415532] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.415577] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.415620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.415662] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.415715] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.416171] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.416219] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.416265] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.416308] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.416381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.416442] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.416492] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.416649] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.416689] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.417478] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.417538] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.417587] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.417688] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.418010] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.418076] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.420389] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.420455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.420517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.420572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.420622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.420671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.420718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.421281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.421331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.421378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.421424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.421470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.421514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.421558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.421609] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.421666] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.421719] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.422297] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.422364] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.422419] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.426028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.426087] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.426140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.426194] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.427425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.427479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.427528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.428632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.428683] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.428932] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.429958] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.430012] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.431410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.433801] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  358.435256] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.435334] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.435384] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.435451] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.452229] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.452308] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.452424] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.453136] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.453289] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.468887] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.468958] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.469066] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.486391] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.486457] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.486566] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.486982] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.487039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.487098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.487150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.487198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.487244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.487289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.487337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.487380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.487424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.487466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.487514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.487555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.487595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.487642] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.487699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.488428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.488480] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.488530] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.488601] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.488647] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.488692] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.489093] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.489174] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.489224] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.489271] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.489311] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.490282] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.490525] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.490550] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.490700] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.490889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.491055] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.491117] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.491171] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.491225] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.491279] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.491331] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.491380] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.491428] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.491473] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.491485] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.491527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.491536] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.491582] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.491627] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.491673] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.491864] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.491908] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.491964] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.492010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.492057] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.492101] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.492143] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.492214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.492275] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.492327] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.492487] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.492527] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.492983] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.493367] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.493414] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.493516] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.493557] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.493620] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.493896] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.493956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.494014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.494065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.494113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.494158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.494204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.494251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.494296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.494338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.494381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.494424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.494468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.494511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.494560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.494615] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.494666] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.494715] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.494943] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.494995] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.498577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.498635] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.498686] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.499076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.500150] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.500202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.500250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.501178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.501230] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.501278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.502189] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.502243] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.503457] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.505856] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  358.507436] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.507520] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.507572] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.507641] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.524376] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.524449] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.524560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.525198] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.525344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.541091] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.541167] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.541275] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.558683] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.558813] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.558926] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.561131] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.561198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.561260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.561314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.561364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.561411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.561459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.561509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.561554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.561599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.561643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.561694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.562000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.562066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.562139] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.562223] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.562291] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.562344] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.562394] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.562472] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.562520] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.562567] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.562631] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.562704] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.562963] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.563035] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.563098] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.563582] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.564061] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.564090] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.564243] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.564296] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.564353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.564415] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.564464] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.564516] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.564569] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.564618] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.564667] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.564713] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.564977] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.564992] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.565060] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.565072] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.565145] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.565216] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.565286] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.565354] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.565419] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.565483] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.565531] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.565575] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.565620] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.565663] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.565986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.566072] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.566145] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.566353] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.566394] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.566888] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.567289] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.567352] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.567444] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.567486] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.567553] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.569866] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.569935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.570000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.570056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.570105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.570153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.570199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.570247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.570293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.570336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.570381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.570424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.570469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.570512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.570563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.570619] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.570673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.571026] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.571203] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.571279] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.574932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.574991] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.575043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.575095] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.576251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.576304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.576355] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.577399] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.577452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.577500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.578542] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.578596] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.579843] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.582284] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  358.583874] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.583957] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.584007] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.584074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.600887] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.600967] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.601085] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.601578] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.601737] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.617597] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.617672] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.618050] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.635485] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.635553] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.635664] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.638151] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.638218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.638282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.638337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.638387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.638435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.638482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.638531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.638577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.638621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.638665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.638716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.639047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.639116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.639190] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.639274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.639343] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.639395] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.639444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.639525] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.639574] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.639620] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.639685] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.639971] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.640048] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.640121] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.640183] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.640664] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.641401] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.641429] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.641583] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.641636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.641694] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.641940] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.642018] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.642095] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.642158] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.642207] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.642258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.642305] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.642351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.642361] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.642406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.642415] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.642460] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.642505] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.642551] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.642592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.642636] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.642689] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.642961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.643030] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.643096] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.643162] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.643265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.643329] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.643381] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.643550] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.643590] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.644101] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.644481] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.644544] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.644646] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.644710] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.644999] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.645242] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.645302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.645359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.645412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.645461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.645507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.645551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.645598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.645641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.645683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.645941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.646007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.646070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.646131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.646180] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.646235] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.646286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.646337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.646396] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.646446] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.650090] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.650148] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.650199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.650250] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.651279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.651333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.651383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.652428] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.652480] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.652528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.653546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.653600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.654864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.657311] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  358.658903] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.658989] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.659041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.659109] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.675890] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.675970] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.676086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.676518] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.676665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.692561] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.692633] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.692928] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.714620] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.714687] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.715164] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.717482] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.717545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.717606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.717659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.717707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.718232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.718283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.718334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.718380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.718424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.718467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.718517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.718559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.718601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.718650] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.718705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.719499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.719554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.719607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.719678] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.720136] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.720182] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.720244] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.720320] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.720370] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.720415] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.720454] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.721684] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.721959] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.721984] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.722136] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.722191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.722249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.722312] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.722361] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.722413] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.722465] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.722512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.722561] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.722606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.722649] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.722657] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.722700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.723589] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.723666] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.723725] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.723880] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.723934] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.723987] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.724044] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.724093] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.724159] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.724191] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.724224] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.724279] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.724323] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.724361] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.724456] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.724485] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.724829] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.724875] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.724908] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.724963] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.724996] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.725046] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.725523] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.725566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.725607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.725645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.725680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.725764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.725802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.725839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.725874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.725906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.725942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.725974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.726009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.726041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.726080] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.726277] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.726315] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.726355] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.726400] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.726440] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.729834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.729865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.729891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.729918] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.730652] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.730678] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.730735] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.731504] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.731531] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.731556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.732289] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.732317] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.733359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.735662] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  358.736390] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.736425] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.736447] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.736476] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.753289] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.753324] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.753375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.753526] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.753589] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.769917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.769952] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.770008] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.787154] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.787221] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.787329] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.787533] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.787590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.787645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.787697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.787824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.787875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.787920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.787977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.788026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.788071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.788118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.788169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.788212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.788261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.788311] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.788372] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.788432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.788486] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.788537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.788616] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.789120] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.789172] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.789234] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.789309] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.789361] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.789407] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.789450] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.789946] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.790594] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.790619] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.790820] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.791126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.791183] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.791245] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.791295] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.791347] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.791399] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.791447] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.791494] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.791539] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.791582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.791591] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.791634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.791641] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.791686] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.791784] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.791832] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.791879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.791923] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.791984] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.792028] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.792075] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.792118] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.792165] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.792241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.792302] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.792359] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.792976] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.793017] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.793340] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.793400] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.793454] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.793559] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.793605] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.793670] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.795956] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.796022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.796083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.796138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.796187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.796236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.796284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.796333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.796377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.796422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.796466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.796511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.796555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.796599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.796650] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.796706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.797334] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.797392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.797461] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.797518] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.801153] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.801212] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.801263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.801316] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.802582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.802635] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.802683] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.803905] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.803958] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.804007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.805099] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.805153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.806666] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.807268] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  358.808861] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.808940] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.808992] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.809061] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.825883] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.825962] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.826077] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.826424] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.826571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.842455] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.842524] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.842632] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.859904] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.859971] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.860079] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.860325] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.860381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.860438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.860489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.860536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.860581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.860624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.860669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.860712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.861688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.862068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.862124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.862171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.862217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.862267] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.862323] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.862377] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.862427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.862475] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.862544] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.862589] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.862634] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.862695] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.863634] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.863685] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.863978] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.864019] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.864485] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.865038] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.865065] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.865221] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.865277] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.865337] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.865400] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.865450] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.865506] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.865558] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.865608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.865656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.865703] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.866434] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.866442] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.866490] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.866497] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.866543] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.866587] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.866630] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.866672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.866713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.867263] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.867313] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.867363] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.867408] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.867454] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.867525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.867585] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.867634] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.868239] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.868279] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.868598] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.868657] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.868698] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.869074] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.869117] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.869180] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.871579] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.871646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.871708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.872067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.872122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.872176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.872226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.872278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.872325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.872371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.872416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.872463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.872507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.872552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.872603] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.872662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.872717] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.873432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.873499] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.873555] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.877287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.877346] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.877398] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.877450] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.878824] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.878877] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.878926] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.880066] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.880118] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.880171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.881324] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.881378] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.882895] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.885266] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  358.886726] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.886838] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.886888] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.886956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.903812] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.903891] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.904008] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.904382] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.904533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.920453] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.920528] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.920653] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  358.938141] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  358.938209] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  358.938319] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.938524] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.938581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.938637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.938686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.939244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.939294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.939340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.939389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.939433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.939477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.939521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.939569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.939610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.939650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.939699] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.940309] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.940364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.940416] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.940465] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.940540] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  358.940587] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  358.940633] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  358.940694] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  358.941265] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.941316] [drm:intel_power_well_disable [i915]] disabling DC off
>[  358.941362] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  358.941402] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  358.942391] [drm:intel_power_well_disable [i915]] disabling always-on
>[  358.942652] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.942845] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  358.943006] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  358.943061] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  358.943118] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  358.943181] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  358.943230] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  358.943283] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  358.943335] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  358.943386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  358.943435] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  358.943482] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  358.943528] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  358.943536] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.943581] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  358.943588] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  358.943633] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  358.943677] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  358.944561] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  358.944609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  358.944652] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  358.944705] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  358.945022] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  358.945069] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  358.945114] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  358.945156] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  358.945228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  358.945288] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  358.945337] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  358.945499] [drm:intel_power_well_enable [i915]] enabling always-on
>[  358.945536] [drm:intel_power_well_enable [i915]] enabling DC off
>[  358.946353] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  358.946675] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  358.946847] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  358.946915] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  358.946956] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  358.947021] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  358.947310] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  358.947366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  358.947421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  358.947472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  358.947518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  358.947563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  358.947606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  358.947651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  358.947695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  358.948447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  358.948494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  358.948538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  358.948581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  358.948625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  358.948672] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  358.949075] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.949130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  358.949180] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  358.949243] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  358.949293] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  358.952912] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  358.952970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  358.953021] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  358.953074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  358.954309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  358.954366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  358.954416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.955453] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  358.955506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  358.955556] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  358.956659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  358.956713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  358.958092] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  358.960479] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  358.961848] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  358.961927] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  358.961977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  358.962044] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  358.978877] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  358.978958] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  358.979074] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  358.979538] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  358.979687] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  358.995504] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  358.995579] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  358.995688] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.013087] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.013153] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.013261] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.015476] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.015534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.015590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.015641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.015688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.016059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.016108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.016158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.016203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.016248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.016291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.016340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.016382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.016424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.016473] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.016529] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.016582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.016632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.016681] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.017191] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.017238] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.017284] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.017345] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.017417] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.017467] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.017513] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.017552] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.018521] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.018884] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.018909] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.019060] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.019113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.019169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.019231] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.019280] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.019330] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.019382] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.019431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.019478] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.019522] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.019564] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.019572] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.019614] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.019621] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.019665] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.019708] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.019958] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.020004] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.020047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.020102] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.020149] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.020195] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.020238] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.020281] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.020352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.020411] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.020462] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.020622] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.020662] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.021123] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.021516] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.021563] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.021661] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.021703] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.021909] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.022127] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.022183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.022346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.022396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.022443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.022488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.022532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.022577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.022619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.022661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.022703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.022932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.022977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.023021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.023070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.023126] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.023176] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.023228] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.023289] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.023340] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.027033] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.027090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.027141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.027195] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.028476] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.028529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.028578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.029668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.029721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.030001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.031227] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.031282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.032555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.035040] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  359.036662] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.036901] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.036955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.037028] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.053820] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.053899] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.054016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.054517] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.054668] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.070333] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.070403] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.070510] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.087838] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.087905] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.088013] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.088260] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.088316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.088371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.088422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.088468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.088513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.088557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.088604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.088647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.088689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.089443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.089497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.089543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.089587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.089635] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.089692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.090094] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.090146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.090199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.090269] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.090317] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.090362] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.090424] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.090495] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.090543] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.090588] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.090628] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.091921] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.092175] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.092201] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.092350] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.092401] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.092458] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.092519] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.092568] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.092619] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.092669] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.092716] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.093353] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.093401] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.093448] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.093456] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.093501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.093508] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.093554] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.093597] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.093640] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.093682] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.094315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.094369] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.094418] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.094465] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.094510] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.094553] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.094623] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.094682] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.095177] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.095335] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.095374] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.095675] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.096273] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.096326] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.096423] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.096465] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.096530] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.098869] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.098936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.098999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.099053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.099103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.099151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.099197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.099245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.099289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.099333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.099377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.099420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.099464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.099507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.099557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.099614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.099669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.099721] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.100798] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.100854] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.104423] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.104481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.104532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.104585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.105805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.105858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.105907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.107170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.107223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.107272] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.108347] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.108401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.109597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.112037] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  359.113547] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.113626] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.113677] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.113986] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.130530] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.130609] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.130726] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.131429] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.131685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.147303] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.147376] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.147484] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.164922] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.164990] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.165100] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.165306] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.165362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.165419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.165471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.165518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.165564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.165608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.165654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.165696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.166435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.166483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.166537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.166581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.166626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.166674] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.167040] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.167096] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.167148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.167198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.167273] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.167320] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.167365] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.167428] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.167500] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.167550] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.167596] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.167636] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.168979] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.169227] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.169254] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.169406] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.169460] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.169519] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.169581] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.169631] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.169683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.170300] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.170351] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.170400] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.170446] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.170490] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.170498] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.170541] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.170547] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.170591] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.170634] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.170676] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.171302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.171347] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.171403] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.171451] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.171498] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.171541] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.171584] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.171654] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.171714] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.172243] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.172408] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.172447] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.172984] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.173315] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.173366] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.173467] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.173508] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.173573] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.175921] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.175988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.176051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.176107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.176157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.176205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.176253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.176301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.176346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.176390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.176434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.176477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.176521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.176564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.176613] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.176671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.177593] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.177651] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.177718] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.178006] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.181585] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.181642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.181691] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.182028] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.182988] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.183042] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.183090] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.184095] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.184147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.184195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.185332] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.185385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.186583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.189028] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  359.190534] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.190615] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.190666] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.190976] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.207513] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.207592] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.207709] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.208443] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.208594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.224192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.224264] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.224374] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.241720] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.241850] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.241963] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.244174] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.244240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.244302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.244357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.244406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.244453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.244499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.244548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.244592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.244636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.244679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.245365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.245416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.245463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.245515] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.245575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.245631] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.245683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.246197] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.246276] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.246326] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.246375] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.246440] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.246517] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.246570] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.246618] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.246661] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.247884] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.248148] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.248175] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.248333] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.248390] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.248450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.248514] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.248567] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.248623] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.248678] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.249270] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.249322] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.249374] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.249421] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.249431] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.249478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.249485] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.249533] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.249580] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.249627] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.249672] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.249717] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.250397] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.250450] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.250501] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.250550] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.250597] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.250672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.251089] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.251145] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.251316] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.251358] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.251676] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.252384] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.252442] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.252536] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.252578] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.252644] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.253064] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.253123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.253177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.253228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.253272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.253317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.253359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.253404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.253446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.253489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.253529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.253570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.253609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.253649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.253696] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.254445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.254496] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.254546] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.254606] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.254657] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.256415] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.256470] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.256520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.256679] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.257878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.257930] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.257977] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.259065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.259115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.259163] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.260335] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.260389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.261583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.264028] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  359.265530] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.265617] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.265668] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.265980] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.282512] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.282593] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.282710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.283447] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.283597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.299261] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.299338] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.299452] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.316813] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.316881] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.316990] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.319308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.319376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.319439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.319493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.319542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.319590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.319636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.319684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.320250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.320297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.320345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.320399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.320445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.320490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.320543] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.320603] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.320660] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.320714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.321286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.321366] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.321416] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.321464] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.321529] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.321607] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.321659] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.321707] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.322182] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.322645] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.323096] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.323124] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.323283] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.323338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.323399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.323464] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.323517] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.323572] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.323628] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.323679] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.324273] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.324325] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.324374] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.324382] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.324430] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.324437] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.324485] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.324531] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.324576] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.324622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.324665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.324721] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.325474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.325526] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.325573] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.325619] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.325692] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.326069] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.326124] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.326294] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.326336] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.326657] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.327021] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.327076] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.327177] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.327219] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.327283] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.331738] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.331853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.331916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.331972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.332023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.332071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.332119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.332168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.332213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.332258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.332302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.332345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.332388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.332432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.332483] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.332540] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.332594] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.332645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.332709] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.333670] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.337392] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.337451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.337502] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.337557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.338799] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.338852] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.338900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.340081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.340133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.340180] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.341337] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.341391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.342586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.345031] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  359.346532] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.346618] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.346670] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.346982] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.363520] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.363600] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.363717] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.364454] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.364604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.380269] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.380344] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.380458] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.397704] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.397834] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.397946] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.398115] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.398171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.398228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.398280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.398327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.398371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.398415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.398460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.398502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.398542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.398583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.398629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.398670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.398709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.399642] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.399702] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.399944] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.399999] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.400050] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.400125] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.400171] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.400217] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.400280] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.400352] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.400401] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.400446] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.400486] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.401791] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.402038] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.402064] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.402219] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.402273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.402331] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.402393] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.402441] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.402493] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.402545] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.402594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.402643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.402688] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.403463] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.403472] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.403518] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.403525] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.403572] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.403617] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.403661] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.403704] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.404213] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.404267] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.404314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.404360] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.404404] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.404447] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.404518] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.404578] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.404629] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.405270] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.405310] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.405627] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.405685] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.406003] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.406104] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.406148] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.406213] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.406461] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.406517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.406572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.406622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.406672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.406717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.407305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.407355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.407400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.407444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.407485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.407527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.407568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.407608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.407655] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.407708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.408260] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.408312] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.408375] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.408425] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.412049] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.412107] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.412158] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.412211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.413278] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.413329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.413378] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.414281] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.414331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.414377] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.415273] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.415323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.416510] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.418900] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  359.420245] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.420328] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.420377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.420443] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.437227] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.437308] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.437425] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.438106] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.438256] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.453900] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.453972] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.454081] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.471290] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.471356] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.471464] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.471669] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.471725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.472103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.472160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.472210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.472258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.472306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.472354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.472398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.472442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.472484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.472533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.472575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.472617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.472665] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.473202] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.473259] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.473310] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.473359] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.473431] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.473477] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.473522] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.473583] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.473654] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.473703] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.474145] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.474187] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.474652] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.475073] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.475099] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.475249] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.475301] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.475465] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.475526] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.475574] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.475625] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.475677] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.476109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.476160] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.476205] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.476250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.476259] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.476302] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.476311] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.476355] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.476398] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.476441] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.476483] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.476523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.476576] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.476619] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.476661] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.476702] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.477310] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.477383] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.477442] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.477492] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.477647] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.477686] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.478271] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.478330] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.478378] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.478474] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.478515] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.478581] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.479044] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.479102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.479158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.479208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.479256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.479302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.479348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.479395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.479440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.479482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.479526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.479568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.479610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.479652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.479699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.480282] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.480336] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.480385] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.480446] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.480496] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.484121] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.484179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.484231] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.484284] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.485274] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.485325] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.485372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.486406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.486458] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.486506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.487705] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.487807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.489304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.491740] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  359.493372] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.493459] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.493511] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.493579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.510357] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.510437] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.510554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.511393] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.511545] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.527022] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.527094] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.527201] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.544742] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.544872] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.544984] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.545231] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.545287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.545344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.545393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.545439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.545484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.545527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.545573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.545615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.545659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.545701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.546704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.546919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.546991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.547069] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.547141] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.547196] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.547248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.547299] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.547374] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.547421] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.547467] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.547529] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.547601] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.547650] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.547695] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.548580] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.549589] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.550116] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.550144] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.550299] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.550353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.550411] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.550472] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.550522] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.550574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.550625] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.550673] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.550721] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.551489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.551536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.551545] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.551591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.551598] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.551645] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.551689] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.552267] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.552314] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.552359] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.552413] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.552459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.552503] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.552545] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.552588] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.552657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.552717] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.553634] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.553989] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.554052] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.554382] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.554442] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.554494] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.554585] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.554627] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.554693] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.555461] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.555520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.555577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.555630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.555677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.556163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.556213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.556264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.556308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.556352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.556395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.556437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.556478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.556518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.556566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.556620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.556672] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.557426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.557490] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.557542] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.561178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.561236] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.561287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.561339] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.562688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.562785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.562834] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.563699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.564149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.564201] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.565350] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.565405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.566608] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.569048] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  359.570796] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.570887] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.570938] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.571007] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.587843] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.587922] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.588039] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.588531] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.588681] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.604433] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.604505] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.604614] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.621897] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.621964] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.622073] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.624419] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.624483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.624547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.624602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.624653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.624701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.625166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.625241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.625311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.625380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.625448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.625524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.625583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.625625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.625674] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.626164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.626225] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.626299] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.626375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.626483] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.626556] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.626616] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.626680] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.627191] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.627269] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.627341] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.627404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.628398] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.628830] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.628856] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.629019] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.629097] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.629176] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.629240] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.629291] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.629345] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.629397] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.629446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.629496] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.629542] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.629587] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.629595] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.629640] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.629647] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.629692] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.630735] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.631031] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.631104] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.631173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.631242] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.631291] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.631336] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.631379] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.631420] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.631490] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.631549] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.631708] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.632465] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.632525] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.633031] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.633410] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.633475] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.633577] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.633642] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.633717] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.634311] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.634367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.634424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.634476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.634524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.634570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.634613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.634657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.634700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.635233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.635303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.635373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.635441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.635506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.635579] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.635647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.635699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.636174] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.636262] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.636337] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.639934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.639993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.640044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.640097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.641350] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.641424] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.641476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.642601] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.642653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.642702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.643893] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.643948] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.645350] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.647720] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  359.649352] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.649444] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.649497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.649566] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.666338] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.666416] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.666533] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.667337] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.667484] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.683096] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.683170] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.683285] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.714671] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.715039] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.715191] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.715360] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.715418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.715475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.715527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.715574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.715622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.715667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.715714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.716430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.716478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.716523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.716575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.716619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.716661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.716710] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.717278] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.717334] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.717386] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.717435] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.717508] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.717554] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.717598] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.717660] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.718279] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.718331] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.718378] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.718417] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.719537] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.719835] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.719864] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.719993] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.720032] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.720073] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.720118] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.720153] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.720191] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.720227] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.720261] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.720293] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.720324] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.720354] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.720360] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.720389] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.720394] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.720425] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.720455] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.720483] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.720511] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.720538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.720574] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.720603] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.720632] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.720660] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.720688] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.721789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.721833] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.721870] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.721985] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.722012] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.722318] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.722359] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.722393] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.722467] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.722497] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.722542] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.722704] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.723307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.723346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.723382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.723414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.723446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.723476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.723508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.723538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.723567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.723596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.723624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.723653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.723680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.724252] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.724283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.724311] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.724337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.724369] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.724396] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.727763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.727794] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.727820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.727848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.728570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.728597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.728621] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.729531] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.729554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.729575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.730351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.730375] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.731375] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.733676] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  359.734343] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.734377] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.734395] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.734421] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.751180] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.751209] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.751253] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.751419] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.751472] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.767920] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.767952] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.768002] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.785259] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.785322] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.785422] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.787812] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.787981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.788040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.788089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.788133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.788176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.788218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.788262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.788304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.788344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.788384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.788429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.788468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.788507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.788553] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.788606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.788656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.788704] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.789866] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.789944] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.789991] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.790036] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.790098] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.790175] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.790224] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.790270] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.790309] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.791696] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.791994] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.792022] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.792178] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.792233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.792296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.792359] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.792408] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.792461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.792513] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.792562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.792611] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.792657] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.792702] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.793540] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.793592] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.793599] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.793649] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.793697] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.794191] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.794240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.794286] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.794340] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.794388] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.794433] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.794476] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.794517] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.794588] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.794648] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.794698] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.795670] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.795710] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.796252] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.796346] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.796408] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.796500] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.796541] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.796607] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.799379] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.799449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.799515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.799570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.799620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.799668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.799715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.800378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.800427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.800473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.800517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.800561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.800604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.800646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.800694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.801301] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.801358] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.801410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.801474] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.801526] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.805113] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.805173] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.805224] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.805277] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.806519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.806573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.806622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.807826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.807880] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.807930] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.809140] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.809196] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.810491] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.812881] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  359.814445] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.814528] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.814579] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.814647] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.831426] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.831505] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.831622] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.832515] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.832663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.848105] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.848177] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.848284] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.865615] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.865680] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.866232] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.866484] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.866542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.866597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.866649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.866697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.867256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.867307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.867358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.867403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.867448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.867492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.867541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.867584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.867627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.867676] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.868434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.868491] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.868544] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.868596] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.868665] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.868712] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.869104] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.869167] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.869246] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.869302] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.869372] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.869435] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.870686] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.870946] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.870971] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.871122] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.871175] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.871235] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.871297] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.871347] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.871399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.871451] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.871499] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.871545] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.871590] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.871634] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.871642] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.871684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.872610] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.872662] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.872711] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.873176] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.873247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.873316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.873373] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.873420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.873466] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.873511] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.873554] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.873626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.873684] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.874398] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.874557] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.874596] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.875214] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.875577] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.875626] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.875730] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.876110] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.876179] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.876389] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.876446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.876501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.876552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.876600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.876648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.876693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.877357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.877406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.877451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.877495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.877538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.877581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.877623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.877672] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.878280] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.878338] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.878389] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.878451] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.878502] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.882143] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.882202] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.882254] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.882306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.883339] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.883391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.883440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.884440] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.884491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.884539] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.885818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.885873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.887346] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.889792] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  359.891348] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.891438] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.891488] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.891556] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.908342] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.908420] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.908537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.909346] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.909493] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.924987] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.925060] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.925171] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  359.942413] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  359.942479] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  359.942587] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.943025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.943084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.943141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.943194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.943242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.943288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.943333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.943379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.943421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.943464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.943506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.943554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.943594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.943634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.943682] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.943800] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.943859] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.943914] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.943963] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.944038] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  359.944085] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  359.944141] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  359.944212] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  359.944287] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.944336] [drm:intel_power_well_disable [i915]] disabling DC off
>[  359.944383] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  359.944422] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  359.944935] [drm:intel_power_well_disable [i915]] disabling always-on
>[  359.945583] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.945610] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  359.945814] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  359.945865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  359.945928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  359.945992] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  359.946044] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  359.946096] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  359.946150] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  359.946200] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  359.946248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  359.946295] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  359.946339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  359.946351] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.946392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  359.946402] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  359.946447] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  359.946491] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  359.946536] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  359.946578] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  359.946619] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  359.946673] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  359.946732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  359.946773] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  359.946813] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  359.946857] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  359.946926] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  359.946984] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  359.947035] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  359.947198] [drm:intel_power_well_enable [i915]] enabling always-on
>[  359.947239] [drm:intel_power_well_enable [i915]] enabling DC off
>[  359.947543] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  359.947605] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  359.947650] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  359.947767] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  359.947809] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  359.947871] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  359.948090] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  359.948147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  359.948201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  359.948252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  359.948298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  359.948344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  359.948388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  359.948435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  359.948478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  359.948521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  359.948564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  359.948606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  359.948648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  359.948690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  359.948804] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  359.948860] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.948915] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  359.948965] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  359.949027] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  359.949078] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  359.952671] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  359.952730] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  359.953032] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  359.953087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  359.954255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  359.954308] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  359.954357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.955479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  359.955530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  359.955577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  359.956636] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  359.956689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  359.958126] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  359.960542] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  359.962049] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  359.962129] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  359.962180] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  359.962246] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  359.979045] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  359.979124] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  359.979240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  359.979591] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  359.980062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  359.995742] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  359.995880] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  359.996000] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.013401] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.013470] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.013580] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.014091] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.014150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.014207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.014258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.014304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.014349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.014393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.014439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.014481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.014522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.014563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.014610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.014650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.014690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.015419] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.015477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.015530] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.015581] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.015629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.015703] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.016177] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.016223] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.016285] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.016362] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.016412] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.016457] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.016497] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.017613] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.018008] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.018036] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.018191] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.018246] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.018304] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.018366] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.018415] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.018468] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.018521] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.018568] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.018614] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.018659] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.018703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.019387] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.019434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.019441] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.019490] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.019536] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.019580] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.019623] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.019664] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.019717] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.020266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.020313] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.020357] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.020398] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.020468] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.020528] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.020578] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.021135] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.021174] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.021483] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.021542] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.021591] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.021689] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.022137] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.022203] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.022427] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.022485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.022539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.022591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.022637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.022683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.023201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.023251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.023295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.023339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.023382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.023425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.023466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.023507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.023554] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.023608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.023658] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.023707] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.024350] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.024401] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.028054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.028114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.028165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.028218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.029435] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.029486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.029535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.030703] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.030812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.030864] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.031741] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.031857] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.033150] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.035568] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  360.037177] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.037258] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.037310] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.037377] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.054164] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.054243] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.054360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.055195] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.055344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.070905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.070979] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.071094] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.088504] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.088572] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.088683] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.089388] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.089449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.089506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.089557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.089605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.089650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.089695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.090284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.090334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.090382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.090428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.090480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.090524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.090567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.090617] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.090674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.091315] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.091370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.091421] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.091495] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.091541] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.091586] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.091648] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.091722] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.092361] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.092410] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.092450] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.093466] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.093916] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.093957] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.094133] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.094188] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.094246] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.094309] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.094357] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.094411] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.094462] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.094511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.094560] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.094606] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.094650] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.094658] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.094702] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.095640] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.095693] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.095989] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.096062] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.096119] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.096166] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.096220] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.096266] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.096310] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.096353] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.096394] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.096465] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.096524] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.096574] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.097616] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.097655] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.098192] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.098562] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.098626] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.098722] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.099093] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.099162] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.101485] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.101551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.101612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.101667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.101716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.102265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.102316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.102371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.102419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.102464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.102508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.102552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.102594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.102636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.102684] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.103379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.103434] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.103488] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.103551] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.103603] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.107170] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.107227] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.107278] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.107331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.108680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.108778] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.108829] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.109695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.110147] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.110199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.111351] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.111405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.112605] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.115043] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  360.116794] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.116881] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.116933] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.117000] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.133839] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.133918] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.134034] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.134468] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.134617] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.150456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.150528] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.150637] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.167901] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.167969] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.168078] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.168282] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.168337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.168394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.168445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.168492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.168536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.168580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.168625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.168667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.168708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.169656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.169714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.169989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.170061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.170134] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.170195] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.170250] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.170302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.170351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.170422] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.170469] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.170514] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.170575] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.170644] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.170694] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.171481] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.171523] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.172527] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.173000] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.173029] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.173181] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.173237] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.173294] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.173356] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.173405] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.173459] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.173511] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.173561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.173609] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.173653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.173696] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.174548] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.174600] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.174608] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.174657] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.174703] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.175212] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.175281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.175336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.175390] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.175435] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.175480] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.175522] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.175564] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.175634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.175692] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.176402] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.176560] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.176600] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.177205] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.177568] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.177624] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.177729] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.178101] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.178171] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.178380] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.178544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.178600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.178652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.178700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.179281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.179330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.179380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.179426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.179471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.179516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.179560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.179603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.179645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.179695] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.180431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.180486] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.180537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.180599] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.180650] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.184256] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.184314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.184365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.184417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.185355] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.185407] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.185456] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.186434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.186487] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.186537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.187451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.187505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.188720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.191189] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  360.192661] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.192802] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.192864] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.192953] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.209654] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.209893] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.210010] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.210451] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.210601] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.226399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.226473] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.226587] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.243825] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.243892] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.244000] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.244289] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.244346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.244402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.244454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.244501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.244546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.244591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.244636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.244679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.244805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.244861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.244916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.244959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.245006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.245060] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.245121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.245176] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.245234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.245286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.245401] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.245478] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.245550] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.245646] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.245810] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.245896] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.245969] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.246035] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.246533] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.246854] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.246895] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.247123] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.247178] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.247237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.247304] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.247357] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.247412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.247467] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.247517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.247569] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.247618] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.247663] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.247672] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.247715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.247766] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.247812] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.247860] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.247906] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.247952] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.247996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.248054] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.248098] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.248148] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.248191] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.248237] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.248310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.248376] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.248426] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.248645] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.248709] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.249106] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.249203] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.249271] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.249372] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.249443] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.249538] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.249726] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.249836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.249905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.249960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.250017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.250066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.250118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.250167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.250217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.250261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.250312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.250355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.250403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.250446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.250500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.250563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.250643] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.250723] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.250864] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.250944] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.254541] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.254600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.254651] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.254705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.255686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.255789] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.255843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.256819] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.256873] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.256921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.257844] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.257919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.259145] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.261529] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  360.263004] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.263087] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.263137] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.263205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.279991] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.280070] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.280187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.280634] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.280867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.296730] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.296845] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.296959] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.314350] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.314419] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.314530] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.314826] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.314894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.314957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.315012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.315067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.315131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.315202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.315279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.315345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.315414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.315481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.315546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.315589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.315632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.315683] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.315785] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.315838] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.315889] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.315945] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.316029] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.316104] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.316178] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.316278] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.316383] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.316447] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.316493] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.316535] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.317031] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.317901] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.317941] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.318101] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.318154] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.318212] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.318275] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.318324] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.318375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.318426] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.318476] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.318524] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.318569] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.318612] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.318620] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.318662] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.318669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.318713] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.318813] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.318856] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.318911] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.318959] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.319013] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.319186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.319252] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.319316] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.319382] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.319485] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.319569] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.319623] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.319832] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.319876] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.320218] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.320312] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.320378] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.320481] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.320549] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.320639] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.320875] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.320956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.321037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.321111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.321161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.321206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.321252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.321299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.321340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.321383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.321427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.321469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.321512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.321555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.321606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.321661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.321711] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.321813] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.321882] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.321937] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.325520] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.325577] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.325628] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.325680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.326657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.326708] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.326810] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.327704] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.327805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.327858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.328834] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.328888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.330109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.332506] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  360.333981] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.334066] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.334116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.334183] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.350958] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.351037] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.351153] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.351580] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.351728] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.367718] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.367831] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.367946] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.385401] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.385471] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.385582] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.385837] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.385904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.385965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.386029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.386099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.386172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.386246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.386316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.386386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.386452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.386503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.386551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.386595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.386638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.386688] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.386792] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.386853] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.386905] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.386961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.387049] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.387123] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.387195] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.387296] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.387402] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.387481] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.387533] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.387574] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.388072] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.388886] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.388913] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.389067] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.389121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.389179] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.389240] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.389289] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.389341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.389392] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.389441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.389490] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.389536] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.389580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.389588] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.389631] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.389638] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.389681] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.389780] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.389826] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.389877] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.389924] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.389977] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.390027] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.390073] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.390118] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.390164] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.390235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.390296] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.390350] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.390558] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.390620] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.391018] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.391512] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.391579] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.391679] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.391797] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.391896] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.394145] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.394211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.394271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.394327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.394377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.394426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.394473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.394522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.394567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.394611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.394656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.394700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.394805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.394863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.394923] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.394984] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.395044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.395102] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.395170] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.395229] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.398826] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.398884] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.398936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.398989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.399895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.399974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.400050] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.400989] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.401055] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.401103] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.402074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.402130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.403347] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.405779] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  360.407229] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.407318] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.407369] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.407436] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.424225] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.424305] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.424421] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.424986] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.425198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.440890] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.440963] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.441072] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.458513] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.458581] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.458693] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.459031] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.459117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.459203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.459259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.459309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.459357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.459405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.459454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.459500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.459544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.459588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.459639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.459844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.459894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.459948] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.460013] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.460069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.460127] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.460179] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.460282] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.460357] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.460432] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.460533] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.460639] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.460717] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.460846] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.460917] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.461402] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.461756] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.461785] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.461986] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.462064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.462139] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.462206] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.462257] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.462314] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.462366] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.462417] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.462467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.462513] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.462558] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.462569] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.462614] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.462621] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.462665] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.462712] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.462797] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.462839] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.462893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.462950] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.462999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.463045] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.463091] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.463134] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.463211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.463278] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.463330] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.463555] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.463617] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.464000] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.464491] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.464559] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.464667] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.464799] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.464871] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.465083] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.465148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.465208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.465259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.465309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.465352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.465397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.465443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.465489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.465529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.465573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.465616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.465658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.465698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.465800] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.465860] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.465915] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.465969] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.466031] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.466086] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.469674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.469744] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.469796] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.469848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.470732] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.470834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.470891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.471843] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.471893] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.471939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.472854] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.472928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.474228] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.476660] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  360.478256] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.478339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.478390] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.478458] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.495232] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.495312] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.495429] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.496096] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.496295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.511908] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.511980] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.512089] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.529512] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.529579] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.529689] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.530152] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.530235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.530303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.530355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.530403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.530450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.530495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.530541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.530584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.530626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.530668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.530716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.530995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.531061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.531136] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.531218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.531274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.531326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.531377] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.531454] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.531503] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.531550] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.531614] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.531687] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.531936] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.532008] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.532071] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.532556] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.533025] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.533061] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.533215] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.533268] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.533327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.533390] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.533441] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.533495] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.533547] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.533596] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.533644] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.533690] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.533955] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.533970] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.534037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.534051] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.534120] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.534187] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.534255] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.534321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.534386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.534451] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.534497] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.534541] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.534582] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.534623] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.534696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.534976] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.535052] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.535291] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.535331] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.535653] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.535813] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.535868] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.535970] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.536013] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.536081] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.536259] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.536314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.536369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.536420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.536468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.536513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.536559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.536604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.536647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.536689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.536792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.536839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.536882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.536924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.536975] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.537032] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.537086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.537139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.537201] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.537253] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.540891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.540950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.541001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.541055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.542006] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.542061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.542110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.543074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.543125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.543172] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.544107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.544157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.545347] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.547737] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  360.549106] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.549197] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.549247] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.549315] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.566106] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.566186] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.566302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.567063] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.567218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.582901] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.582976] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.583092] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.600515] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.600583] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.600694] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.601325] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.601382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.601438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.601491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.601539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.601587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.601631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.601678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.602188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.602233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.602278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.602330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.602372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.602416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.602465] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.602522] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.602575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.602626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.602676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.603290] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.603337] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.603382] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.603444] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.603519] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.603568] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.603613] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.603651] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.604832] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.605078] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.605105] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.605257] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.605310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.605368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.605431] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.605480] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.605532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.605583] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.605631] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.605676] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.606348] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.606395] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.606404] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.606449] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.606457] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.606504] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.606547] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.606591] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.606632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.606674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.607274] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.607324] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.607372] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.607416] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.607460] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.607531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.607590] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.607639] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.608247] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.608287] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.608605] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.608663] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.608710] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.609121] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.609162] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.609226] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.611611] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.611677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.611989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.612047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.612099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.612148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.612195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.612244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.612290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.612335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.612379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.612423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.612466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.612509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.612559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.612616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.612669] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.612720] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.613546] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.613600] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.617257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.617315] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.617365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.617416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.618320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.618370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.618417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.619291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.619339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.619385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.620265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.620314] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.621502] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.623948] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  360.625304] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.625384] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.625434] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.625502] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.642129] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.642178] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.642254] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.642567] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.642666] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.658842] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.658881] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.658939] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.675805] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.675848] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.675918] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.678327] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.678370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.678412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.678555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.678587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.678617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.678647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.678678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.678754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.678787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.678823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.678864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.678900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.678933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.678973] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.679017] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.679059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.679103] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.679142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.679225] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.679270] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.679313] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.679368] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.679430] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.679474] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.679516] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.679554] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.680038] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.680266] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.680289] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.680416] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.680459] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.680507] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.680559] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.680601] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.680645] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.680689] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.680777] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.680823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.680870] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.680914] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.680926] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.680968] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.680978] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.681021] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.681064] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.681106] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.681148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.681189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.681236] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.681278] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.681316] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.681359] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.681397] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.681458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.681511] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.681557] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.681701] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.681770] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.682080] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.682134] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.682181] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.682265] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.682301] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.682354] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.686719] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.686806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.686859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.686905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.686946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.686987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.687025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.687066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.687104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.687141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.687177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.687213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.687249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.687285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.687327] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.687374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.687419] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.687461] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.687513] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.687556] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.691098] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.691146] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.691188] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.691232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.692354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.692397] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.692437] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.693386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.693426] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.693465] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.714693] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.714750] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.715887] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.718196] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  360.719127] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.719182] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.719206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.719240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.735988] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.736026] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.736084] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.736324] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.736396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.752778] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.752822] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.752889] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.770237] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.770304] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.770415] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.772832] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.772898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.772962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.773018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.773069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.773117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.773164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.773213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.773258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.773302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.773345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.773395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.773439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.773482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.773534] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.773592] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.773648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.773701] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.774673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.774925] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.774976] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.775027] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.775092] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.775173] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.775227] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.775276] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.775319] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.776491] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.776907] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.776935] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  360.777095] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.777152] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.777214] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.777281] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.777333] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.777389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.777443] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  360.777496] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  360.777548] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.777598] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.777646] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.777654] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.777700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.778467] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.778522] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.778572] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.778623] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  360.778670] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.778717] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.779137] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.779186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.779235] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  360.779280] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  360.779326] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  360.779399] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.779463] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  360.779516] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  360.779682] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.780222] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.780539] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.780602] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.780653] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.780831] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.780899] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.781000] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.781267] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.781349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.781430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.781507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.781579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.781650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.781720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.781846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.781919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.781986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.782055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.782122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.782191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.782257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.782334] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.782417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.782497] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.782575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.782664] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  360.782743] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.786381] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  360.786441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  360.786492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  360.786546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  360.787486] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  360.787540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  360.787588] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.788597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  360.788648] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  360.788697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  360.789663] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  360.789717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  360.791087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  360.793479] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  360.794920] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  360.795000] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  360.795051] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  360.795119] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  360.811897] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.811978] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.812094] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.812545] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  360.812693] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  360.828578] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  360.828651] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  360.828864] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  360.846128] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  360.846194] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  360.846303] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.850666] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.850734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.851132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.851192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.851242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.851290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.851336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.851383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.851425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.851467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.851508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.851555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.851595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.851636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.851683] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  360.852635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.852721] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.853041] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.853119] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.853232] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  360.853304] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  360.853375] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  360.853473] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  360.853579] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  360.853656] [drm:intel_power_well_disable [i915]] disabling DC off
>[  360.853728] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  360.854198] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  360.854648] [drm:intel_power_well_disable [i915]] disabling always-on
>[  360.862471] [IGT] kms_flip: exiting, ret=0
>[  360.885616] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  360.885657] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  360.885701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  360.885798] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  360.885837] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  360.885874] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.885910] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  360.885945] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  360.885978] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  360.886009] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  360.886039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.886046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  360.886075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.886080] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  360.886111] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  360.886140] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  360.886168] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.886196] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.886224] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.886260] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.886289] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.886317] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  360.886345] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  360.886372] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  360.886415] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  360.886447] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  360.886484] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  360.886524] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  360.886557] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  360.886591] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  360.886623] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  360.886653] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  360.886683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  360.886732] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  360.886760] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  360.886765] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.886793] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  360.886797] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  360.886827] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  360.886855] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  360.886884] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  360.886912] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  360.886939] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  360.886974] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  360.887001] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  360.887029] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  360.887056] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  360.887084] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  360.887119] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  360.887160] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  360.887194] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  360.887228] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  360.887260] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  360.887398] [drm:intel_power_well_enable [i915]] enabling always-on
>[  360.887425] [drm:intel_power_well_enable [i915]] enabling DC off
>[  360.887777] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  360.887825] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  360.887855] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  360.887905] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  360.887933] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  360.887970] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  360.887998] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  360.888042] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  360.889816] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  360.889840] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  360.889877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  360.889909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  360.889936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  360.889961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  360.889986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  360.890010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  360.890036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  360.890059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  360.890082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  360.890104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  360.890127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  360.890149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  360.890171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  360.890198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  360.890229] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  360.890257] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  360.890285] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  360.890319] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  360.890346] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  360.902368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.910879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.919399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.927907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.936417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.944926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.953436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.961952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.970463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.978974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.987485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  360.996101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.004616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.013126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.021635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.030144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.038652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.047161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.055035] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  361.070075] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  361.070091] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  361.070150] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  361.070982] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  361.073258] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  361.075320] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  361.075336] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.075349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.075364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.080513] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.080527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  361.085675] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.088164] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  361.088690] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  361.088746] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  361.088761] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  361.088812] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  361.088825] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  361.092068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  361.092084] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  361.092098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  361.092113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  361.092772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  361.092786] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  361.092799] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  361.093446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  361.093460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  361.093473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  361.094121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  361.094135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  361.095093] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  361.097351] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  361.097886] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  361.097921] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  361.097934] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  361.097956] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  361.114744] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  361.114766] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  361.114805] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  361.114846] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  361.114866] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  361.114901] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  361.115043] Console: switching to colour frame buffer device 240x75
>[  361.557579] Console: switching to colour dummy device 80x25
>[  361.557701] [IGT] kms_flip: executing
>[  361.569033] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  361.569059] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  361.577532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.585991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.594447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.602903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.611364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.619820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.628275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.636729] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.645184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.653638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.662094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.670549] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.679004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.687459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.714148] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.722615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.731091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.739550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.748006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.756463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.764919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.773374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.781829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.790282] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.798737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.807190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.815646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.824184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.832639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.841095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.849550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.858004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  361.858013] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  361.858017] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  361.858029] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  361.858045] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  361.858898] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  361.860419] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  361.860435] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  361.860450] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  361.860476] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  361.861307] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  361.862020] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  361.862820] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  361.862858] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  361.862862] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  361.862864] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  361.862865] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  361.862867] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  361.862868] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  361.862869] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  361.862871] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  361.862872] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  361.862874] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  361.862875] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  361.862876] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  361.862878] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  361.862891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  361.862906] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  361.862923] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  361.862930] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  361.862944] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  361.864865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  361.864879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  361.866871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  361.866874] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  361.868870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  361.868886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  361.870844] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  361.870848] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  361.870851] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  361.870861] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  361.870878] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  361.871327] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  361.871656] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  361.871671] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  361.871685] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  361.871881] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  361.872290] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  361.872604] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  361.873152] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  361.873154] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  361.873230] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  361.873231] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  361.873234] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  361.873235] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  361.873238] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  361.873239] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  361.873245] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  361.873248] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  361.873249] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  361.873251] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  361.873252] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  361.873253] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  361.873255] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  361.873256] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  361.873258] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  361.873259] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  361.873260] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  361.873262] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  361.873263] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  361.873265] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  361.873266] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  361.873267] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  361.873269] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  361.873270] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  361.873271] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  361.873273] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  361.873274] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  361.873276] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  361.873277] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  361.873278] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  361.873280] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  361.873281] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  361.873282] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  361.873284] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  361.873285] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  361.873286] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  361.873288] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  361.873289] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  361.873290] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  361.873316] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  361.873332] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  361.874858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  361.874872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  361.876871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  361.876876] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  361.878871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  361.878887] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  361.880883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  361.880886] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  361.880889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  361.881077] [IGT] kms_flip: starting subtest basic-flip-vs-wf_vblank
>[  361.881885] [drm:drm_mode_addfb2] [FB:70]
>[  361.881904] [drm:drm_mode_addfb2] [FB:110]
>[  361.931733] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  361.931783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  361.931872] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  361.940665] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  361.940686] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  361.940787] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  361.940821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  361.940837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  361.940852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  361.940866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  361.940879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  361.940892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  361.940905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  361.940930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  361.940941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  361.940952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  361.940963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  361.940974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  361.940985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  361.940998] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  361.941013] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  361.941027] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  361.941040] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  361.941054] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  361.948077] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  361.948092] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  361.948115] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  361.948132] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  361.948183] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  361.948223] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.948265] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  361.948284] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  361.948315] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  361.965425] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  361.965448] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  361.965486] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  361.965626] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  361.965645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  361.965663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  361.965680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  361.965731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  361.965746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  361.965763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  361.965781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  361.965797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  361.965813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  361.965827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  361.965843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  361.965857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  361.965871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  361.965886] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  361.965905] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  361.965922] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  361.965939] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  361.965955] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  361.965984] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  361.966000] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  361.966016] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  361.966038] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  361.966063] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  361.966080] [drm:intel_power_well_disable [i915]] disabling DC off
>[  361.966096] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  361.966109] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  361.966542] [drm:intel_power_well_disable [i915]] disabling always-on
>[  361.966607] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  361.967061] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  361.967071] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  361.967123] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  361.967142] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  361.967163] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  361.967185] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  361.967203] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  361.967222] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  361.967240] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  361.967258] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  361.967277] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  361.967293] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  361.967308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  361.967312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  361.967327] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  361.967330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  361.967346] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  361.967361] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  361.967376] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  361.967391] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  361.967406] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  361.967425] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  361.967440] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  361.967456] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  361.967470] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  361.967485] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  361.967503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  361.967525] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  361.967543] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  361.967948] [drm:intel_power_well_enable [i915]] enabling always-on
>[  361.967962] [drm:intel_power_well_enable [i915]] enabling DC off
>[  361.968237] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  361.968259] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  361.968276] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  361.968316] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  361.968337] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  361.968361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  361.968380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  361.968398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  361.968414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  361.968431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  361.968446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  361.968463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  361.968478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  361.968493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  361.968508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  361.968523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  361.968538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  361.968553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  361.968570] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  361.968590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  361.968608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  361.968626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  361.968647] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  361.968664] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  361.981457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.989976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  361.998491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.007003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.015515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.024027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.032539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.041050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.049561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.058073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.066581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.075066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.083537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.092005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.100471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.108939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.117405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.125873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  362.133495] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  362.149054] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  362.149071] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  362.149118] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  362.149950] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  362.151064] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  362.153655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  362.153670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  362.153685] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  362.153816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  362.158961] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  362.158977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  362.164115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  362.166591] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  362.167140] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  362.167177] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  362.167192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  362.183985] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  362.184007] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  362.184043] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  364.152698] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.153148] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  364.171346] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  364.171479] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  364.171574] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  364.171717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  364.171873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  364.171960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  364.172034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  364.172100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  364.172167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  364.172236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  364.172298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  364.172359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  364.172422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  364.172487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  364.172549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  364.172609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  364.172680] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  364.172811] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  364.172896] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  364.172963] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  364.173015] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  364.173121] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  364.173170] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  364.173216] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  364.173374] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  364.173450] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  364.173512] [drm:intel_power_well_disable [i915]] disabling DC off
>[  364.173560] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  364.173602] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  364.174161] [drm:intel_power_well_disable [i915]] disabling always-on
>[  364.175137] [drm:drm_mode_addfb2] [FB:70]
>[  364.175180] [drm:drm_mode_addfb2] [FB:110]
>[  364.207354] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  364.207780] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  364.208224] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  364.208289] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  364.208299] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  364.208350] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  364.208368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  364.208387] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  364.208407] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  364.208423] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  364.208439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.208456] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  364.208471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  364.208486] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  364.208500] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  364.208513] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.208515] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  364.208529] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.208531] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  364.208544] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  364.208557] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  364.208570] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.208583] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.208595] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.208611] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.208623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.208636] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  364.208648] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  364.208660] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  364.208677] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.208998] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  364.209014] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  364.209337] [drm:intel_power_well_enable [i915]] enabling always-on
>[  364.209349] [drm:intel_power_well_enable [i915]] enabling DC off
>[  364.209636] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  364.209656] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  364.209682] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  364.209802] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  364.209816] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  364.209836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  364.209853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  364.209869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  364.209884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  364.209899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  364.209913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  364.209928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  364.209941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  364.209954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  364.209967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  364.209981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  364.209994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  364.210006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  364.210021] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  364.210038] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  364.210054] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  364.210069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  364.210088] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  364.210104] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  364.222820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.231290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.239772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.248240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.256708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.265174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.274536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.283005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.291472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.299940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.308407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.316875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.325341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.333818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.342292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.350761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.359228] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.367707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.376178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  364.377234] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  364.391827] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  364.391843] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  364.391889] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  364.392756] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  364.393463] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  364.396081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.396098] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.396113] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.396130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.401541] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.401557] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  364.406709] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.409192] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  364.409656] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  364.426525] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  364.426545] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  364.426578] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  366.395214] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.395415] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  366.412957] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  366.413026] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  366.413141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  366.413198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  366.413254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  366.413302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  366.413348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  366.413393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  366.413440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  366.413483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  366.413525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  366.413567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  366.413612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  366.413653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  366.413693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  366.413828] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  366.413892] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  366.413955] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  366.414008] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  366.414059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  366.414137] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  366.414184] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  366.414231] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  366.414295] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  366.414365] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  366.414417] [drm:intel_power_well_disable [i915]] disabling DC off
>[  366.414464] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  366.414503] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  366.415014] [drm:intel_power_well_disable [i915]] disabling always-on
>[  366.415968] [drm:drm_mode_addfb2] [FB:70]
>[  366.416038] [drm:drm_mode_addfb2] [FB:110]
>[  366.446793] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  366.447144] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  366.447213] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  366.447659] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  366.447667] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  366.447736] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  366.447754] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  366.447773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  366.447795] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  366.447810] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  366.447826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.447842] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  366.447857] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  366.447872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  366.447885] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  366.447898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.447900] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  366.447914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.447917] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  366.447930] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  366.447943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  366.447956] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  366.447968] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.447981] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.447997] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.448011] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.448024] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  366.448037] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  366.448049] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  366.448065] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.448083] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  366.448098] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  366.448408] [drm:intel_power_well_enable [i915]] enabling always-on
>[  366.448419] [drm:intel_power_well_enable [i915]] enabling DC off
>[  366.448717] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  366.448736] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  366.448750] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  366.448778] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  366.448791] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  366.448810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  366.448827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  366.448842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  366.448856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  366.448870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  366.448883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  366.448897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  366.448910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  366.448923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  366.448936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  366.448949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  366.448961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  366.448974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  366.448988] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  366.449004] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  366.449019] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  366.449034] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  366.449052] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  366.449067] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  366.461784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.470254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.478743] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.487211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.495680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.504163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.512631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.521099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.529567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.538035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.546503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.554971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.563438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.571908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.580400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.588873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.597342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.605810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.614278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  366.615355] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  366.629446] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  366.629493] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  366.629584] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  366.630559] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  366.631776] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  366.635068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  366.635111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  366.635149] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  366.635189] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  366.640494] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  366.640535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  366.645852] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  366.648422] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  366.649699] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  366.666724] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  366.666858] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  366.666976] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  368.635275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  368.635477] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  368.653144] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  368.653213] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  368.653330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  368.653388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  368.653443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  368.653489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  368.653534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  368.653576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  368.653622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  368.653664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  368.653706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  368.653843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  368.653893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  368.653935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  368.653977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  368.654026] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  368.654083] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  368.654138] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  368.654190] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  368.654241] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  368.654335] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  368.654397] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  368.654468] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  368.654572] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  368.654680] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  368.654812] [drm:intel_power_well_disable [i915]] disabling DC off
>[  368.654881] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  368.654946] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  368.655438] [drm:intel_power_well_disable [i915]] disabling always-on
>[  368.657269] [drm:drm_mode_addfb2] [FB:70]
>[  368.657339] [drm:drm_mode_addfb2] [FB:110]
>[  368.735528] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  368.736000] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  368.736403] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  368.736468] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  368.736476] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  368.736523] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  368.736538] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  368.736555] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  368.736573] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  368.736587] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  368.736602] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  368.736616] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  368.736629] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  368.736642] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  368.736655] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  368.736667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  368.736669] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  368.736681] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  368.736924] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  368.736952] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  368.736965] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  368.736978] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  368.736991] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  368.737003] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  368.737018] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  368.737031] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  368.737043] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  368.737055] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  368.737067] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  368.737088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  368.737105] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  368.737120] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  368.738282] [drm:intel_power_well_enable [i915]] enabling always-on
>[  368.738293] [drm:intel_power_well_enable [i915]] enabling DC off
>[  368.738579] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  368.738597] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  368.738610] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  368.738645] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  368.738660] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  368.738677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  368.745378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  368.745430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  368.745481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  368.745524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  368.745563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  368.745600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  368.745636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  368.745673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  368.745708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  368.746220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  368.746258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  368.746294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  368.746328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  368.746362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  368.746400] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  368.746444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  368.746484] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  368.746523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  368.746572] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  368.746612] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  368.750054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  368.750095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  368.750131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  368.750169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  368.751272] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  368.751310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  368.751346] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  368.752300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  368.752337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  368.752371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  368.753245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  368.753274] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  368.754323] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  368.756658] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  368.757639] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  368.757686] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  368.757858] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  368.757899] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  368.757972] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  368.758002] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  368.774547] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  368.774582] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  368.774635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  370.741365] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  370.741433] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  370.741496] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  370.741826] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  370.759068] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  370.759117] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  370.759159] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  370.759239] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  370.760405] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  370.760448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  370.760490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  370.760526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  370.760560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  370.760593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  370.760625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  370.760658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  370.760689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  370.760765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  370.760797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  370.760830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  370.760859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  370.760889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  370.760923] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  370.760963] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  370.761000] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  370.761035] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  370.761070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  370.761124] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  370.761157] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  370.761190] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  370.761235] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  370.761285] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  370.761326] [drm:intel_power_well_disable [i915]] disabling DC off
>[  370.761358] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  370.761386] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  370.761868] [drm:intel_power_well_disable [i915]] disabling always-on
>[  370.762298] [drm:drm_mode_addfb2] [FB:70]
>[  370.762348] [drm:drm_mode_addfb2] [FB:110]
>[  370.840309] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  370.840658] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  370.841214] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  370.841267] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  370.841275] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  370.841321] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  370.841336] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  370.841352] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  370.841368] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  370.841381] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  370.841394] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  370.841408] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  370.841421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  370.841433] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  370.841445] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  370.841456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  370.841458] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  370.841469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  370.841471] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  370.841482] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  370.841493] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  370.841504] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  370.841515] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  370.841525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  370.841539] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  370.841550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  370.841560] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  370.841571] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  370.841582] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  370.841600] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  370.841615] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  370.841628] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  370.843015] [drm:intel_power_well_enable [i915]] enabling always-on
>[  370.843026] [drm:intel_power_well_enable [i915]] enabling DC off
>[  370.843309] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  370.843326] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  370.843337] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  370.843359] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  370.843379] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  370.843403] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  370.843559] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  370.843574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  370.843589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  370.843602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  370.843614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  370.843626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  370.843637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  370.843649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  370.843660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  370.843671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  370.843681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  370.844032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  370.844045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  370.844057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  370.844071] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  370.844086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  370.844100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  370.844113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  370.844141] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  370.844154] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  370.847385] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  370.847402] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  370.847417] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  370.847432] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  370.848195] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  370.848210] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  370.848237] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  370.848876] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  370.848892] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  370.848917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  370.849576] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  370.849590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  370.850689] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  370.852996] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  370.853436] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  370.853466] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  370.853479] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  370.853498] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  370.870299] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  370.870320] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  370.870353] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  372.837458] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  372.837633] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  372.837704] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  372.838026] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  372.855520] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  372.855588] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  372.855703] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  372.856279] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  372.856341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  372.856400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  372.856453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  372.856501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  372.856546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  372.856590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  372.856636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  372.856679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  372.856814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  372.856879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  372.856958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  372.857019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  372.857084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  372.857152] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  372.857235] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  372.857312] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  372.857390] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  372.857462] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  372.857579] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  372.857653] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  372.857729] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  372.857902] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  372.858012] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  372.858096] [drm:intel_power_well_disable [i915]] disabling DC off
>[  372.858171] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  372.858233] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  372.858809] [drm:intel_power_well_disable [i915]] disabling always-on
>[  372.860010] [drm:drm_mode_addfb2] [FB:70]
>[  372.860125] [drm:drm_mode_addfb2] [FB:110]
>[  372.944385] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  372.944811] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  372.945256] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  372.945301] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  372.945309] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  372.945354] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  372.945368] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  372.945384] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  372.945401] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  372.945414] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  372.945428] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  372.945441] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  372.945454] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  372.945467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  372.945479] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  372.945490] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  372.945493] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  372.945504] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  372.945505] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  372.945517] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  372.945529] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  372.945540] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  372.945551] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  372.945561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  372.945575] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  372.945586] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  372.945597] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  372.945608] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  372.945619] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  372.945637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  372.945653] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  372.945665] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  372.946752] [drm:intel_power_well_enable [i915]] enabling always-on
>[  372.946762] [drm:intel_power_well_enable [i915]] enabling DC off
>[  372.947045] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  372.947062] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  372.947073] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  372.947096] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  372.947111] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  372.947135] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  372.951505] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  372.951524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  372.951542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  372.951557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  372.951570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  372.951583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  372.951596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  372.951609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  372.951621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  372.951633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  372.951645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  372.951657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  372.951668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  372.951680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  372.951802] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  372.951836] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  372.951855] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  372.951872] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  372.951893] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  372.951911] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  372.955155] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  372.955171] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  372.955186] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  372.955213] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  372.955874] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  372.955888] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  372.955902] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  372.956540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  372.956554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  372.956586] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  372.957299] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  372.957315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  372.958282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  372.960562] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  372.961131] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  372.961155] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  372.961168] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  372.961188] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  372.978011] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  372.978033] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  372.978067] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  374.945144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  374.945319] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  374.945391] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  374.945511] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  374.962423] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  374.962514] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  374.962645] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  374.963159] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  374.963217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  374.963278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  374.963332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  374.963382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  374.963429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  374.963476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  374.963523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  374.963568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  374.963610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  374.963653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  374.963701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  374.964345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  374.964392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  374.964443] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  374.964502] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  374.964557] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  374.964609] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  374.964658] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  374.965122] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  374.965169] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  374.965215] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  374.965283] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  374.965360] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  374.965410] [drm:intel_power_well_disable [i915]] disabling DC off
>[  374.965456] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  374.965495] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  374.966743] [drm:intel_power_well_disable [i915]] disabling always-on
>[  374.974297] [IGT] kms_flip: exiting, ret=0
>[  375.029185] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  375.029201] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  375.029219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  375.029237] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  375.029252] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  375.029267] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.029283] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  375.029297] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  375.029312] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  375.029325] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  375.029338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.029341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  375.029354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.029356] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  375.029369] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  375.029381] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  375.029394] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  375.029406] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.029418] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.029433] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.029445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.029458] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  375.029470] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  375.029482] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  375.029499] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  375.029513] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  375.029528] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  375.029545] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  375.029559] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  375.029573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  375.029587] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  375.029600] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  375.029613] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  375.029625] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  375.029637] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  375.029639] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  375.029650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  375.029652] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  375.029664] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  375.029675] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  375.029687] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  375.029710] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  375.029722] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  375.029736] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  375.029748] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  375.029760] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  375.029772] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  375.029783] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  375.029798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  375.029816] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  375.029830] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  375.029844] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  375.029857] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  375.029907] [drm:intel_power_well_enable [i915]] enabling always-on
>[  375.029918] [drm:intel_power_well_enable [i915]] enabling DC off
>[  375.030203] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  375.030222] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  375.030234] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  375.030257] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  375.030278] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  375.030300] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  375.030312] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  375.030330] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  375.031871] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  375.031883] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  375.031904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  375.031922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  375.031936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  375.031951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  375.031964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  375.031977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  375.031991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  375.032003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  375.032016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  375.032028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  375.032040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  375.032052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  375.032064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  375.032078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  375.032094] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  375.032109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  375.032123] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  375.032142] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  375.032156] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  375.044293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.052808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.061320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.069830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.078340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.086848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.095357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.103866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.112376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.120885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.129411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.137920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.146428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.154936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.163446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.171956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.180465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.188973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  375.196648] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  375.212048] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  375.212091] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  375.212189] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  375.213159] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  375.216378] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  375.217865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.217904] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.217939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.217977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.223309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.223348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  375.228677] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.231303] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  375.232543] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  375.232619] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  375.232658] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  375.232806] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  375.232843] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  375.236330] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  375.236372] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  375.236409] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  375.236449] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  375.237374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  375.237411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  375.237447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  375.238318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  375.238355] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  375.238391] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  375.239214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  375.239252] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  375.240385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  375.242771] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  375.243975] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  375.244036] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  375.244073] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  375.244126] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  375.260907] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  375.260965] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  375.261062] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  375.261167] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  375.261219] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  375.261309] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  375.261776] Console: switching to colour frame buffer device 240x75
>[  375.725146] Console: switching to colour dummy device 80x25
>[  375.725245] [IGT] kms_flip: executing
>[  375.737528] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  375.737606] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  375.746172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.754636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.763094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.771554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.780010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.788467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.796924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.805395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.813851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.822307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.830764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.839220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.847677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.856147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.864604] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.873059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.881593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.890051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.898506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.906963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.915419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.923875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.932330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.940786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.949241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.957709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.966166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.974622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.983077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.991533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  375.999990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  376.008446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  376.008456] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  376.008459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  376.008472] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  376.008494] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  376.009328] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  376.010873] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  376.010890] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  376.010905] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  376.010919] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  376.011738] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  376.012448] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  376.013230] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  376.013259] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  376.013261] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  376.013263] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  376.013264] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  376.013266] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  376.013267] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  376.013269] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  376.013270] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  376.013272] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  376.013273] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  376.013275] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  376.013277] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  376.013278] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  376.013305] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  376.013320] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  376.013336] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  376.013343] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  376.013358] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  376.014810] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  376.014824] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  376.016874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  376.016878] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  376.018874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  376.018890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  376.020873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  376.020877] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  376.020880] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  376.020889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  376.020906] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  376.021356] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  376.021668] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  376.021684] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  376.021721] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  376.021766] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  376.022226] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  376.022538] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  376.023054] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  376.023056] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  376.023134] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  376.023135] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  376.023138] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  376.023139] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  376.023142] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  376.023143] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  376.023149] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  376.023151] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  376.023152] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  376.023154] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  376.023155] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  376.023156] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  376.023158] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  376.023159] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  376.023160] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  376.023162] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  376.023163] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  376.023165] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  376.023166] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  376.023167] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  376.023169] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  376.023170] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  376.023171] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  376.023173] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  376.023174] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  376.023175] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  376.023177] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  376.023178] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  376.023180] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  376.023181] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  376.023182] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  376.023184] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  376.023185] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  376.023186] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  376.023188] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  376.023189] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  376.023190] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  376.023192] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  376.023193] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  376.023221] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  376.023236] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  376.024788] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  376.024802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  376.026936] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  376.026940] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  376.028872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  376.028888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  376.030916] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  376.030919] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  376.030922] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  376.031108] [IGT] kms_flip: starting subtest basic-plain-flip
>[  376.031867] [drm:drm_mode_addfb2] [FB:69]
>[  376.031900] [drm:drm_mode_addfb2] [FB:110]
>[  376.081887] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  376.081942] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  376.082022] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  376.084518] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  376.084568] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  376.084585] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  376.084789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  376.084838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  376.084860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  376.084879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  376.084898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  376.084915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  376.084935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  376.084965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  376.084982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  376.084998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  376.085015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  376.085030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  376.085047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  376.085064] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  376.085086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  376.085107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  376.085127] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  376.085148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  376.094207] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  376.094222] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  376.094247] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  376.094265] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  376.094328] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  376.094370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.094426] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  376.094446] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  376.094499] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  376.111494] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  376.111517] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  376.111556] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  376.111802] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  376.111831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  376.111858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  376.111884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  376.111907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  376.111930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  376.111951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  376.111974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  376.111994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  376.112015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  376.112035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  376.112058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  376.112077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  376.112099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  376.112121] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  376.112148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  376.112173] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  376.112197] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  376.112222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  376.112258] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  376.112282] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  376.112306] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  376.112338] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  376.112373] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  376.112398] [drm:intel_power_well_disable [i915]] disabling DC off
>[  376.112421] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  376.112440] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  376.113380] [drm:intel_power_well_disable [i915]] disabling always-on
>[  376.113472] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  376.113942] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  376.113952] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  376.114001] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  376.114019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  376.114038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  376.114059] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  376.114075] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  376.114092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  376.114109] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  376.114126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  376.114141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  376.114156] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  376.114170] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  376.114173] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  376.114187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  376.114189] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  376.114203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  376.114218] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  376.114232] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  376.114245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  376.114258] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  376.114276] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  376.114290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  376.114303] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  376.114316] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  376.114329] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  376.114346] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  376.114366] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  376.114382] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  376.114887] [drm:intel_power_well_enable [i915]] enabling always-on
>[  376.114905] [drm:intel_power_well_enable [i915]] enabling DC off
>[  376.115195] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  376.115226] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  376.115247] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  376.115284] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  376.115303] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  376.115331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  376.115355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  376.115379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  376.115400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  376.115421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  376.115441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  376.115464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  376.115483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  376.115504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  376.115522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  376.115544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  376.115562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  376.115581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  376.115602] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  376.115627] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  376.115650] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  376.115673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  376.115811] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  376.115833] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  376.128660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.137214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.145714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.154196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.162677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.171176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.179658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.188202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.196684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.205168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.213636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.222105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.230573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.239041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.247509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.255977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.264458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.272925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.281392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  376.282316] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  376.297663] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  376.297679] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  376.297771] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  376.298603] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  376.300048] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  376.302280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  376.302295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  376.302309] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  376.302324] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  376.307578] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  376.307594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  376.313835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  376.316304] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  376.316852] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  376.316909] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  376.316935] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  376.333767] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  376.333787] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  376.333820] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  378.018888] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.019087] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  378.036732] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  378.036854] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  378.036917] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  378.037030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  378.037086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  378.037142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  378.037189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  378.037236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  378.037279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  378.037325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  378.037367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  378.037409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  378.037450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  378.037493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  378.037533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  378.037573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  378.037621] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  378.037677] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  378.037799] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  378.037855] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  378.037912] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  378.037990] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  378.038040] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  378.038086] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  378.038150] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  378.038221] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  378.038284] [drm:intel_power_well_disable [i915]] disabling DC off
>[  378.038330] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  378.038375] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  378.038887] [drm:intel_power_well_disable [i915]] disabling always-on
>[  378.039872] [drm:drm_mode_addfb2] [FB:69]
>[  378.039944] [drm:drm_mode_addfb2] [FB:110]
>[  378.081345] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  378.081720] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  378.081782] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  378.082209] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  378.082218] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  378.082267] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  378.082283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  378.082301] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  378.082320] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  378.082334] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  378.082349] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  378.082364] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  378.082379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  378.082393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  378.082406] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  378.082419] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  378.082421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  378.082434] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  378.082436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  378.082448] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  378.082461] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  378.082473] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  378.082485] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  378.082497] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  378.082512] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  378.082525] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  378.082537] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  378.082549] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  378.082560] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  378.082575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  378.082593] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  378.082607] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  378.082945] [drm:intel_power_well_enable [i915]] enabling always-on
>[  378.082957] [drm:intel_power_well_enable [i915]] enabling DC off
>[  378.083243] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  378.083262] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  378.083275] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  378.083327] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  378.083344] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  378.083363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  378.083378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  378.083392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  378.083405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  378.083417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  378.083430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  378.083443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  378.083454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  378.083466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  378.083478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  378.083490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  378.083501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  378.083512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  378.083526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  378.083541] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  378.083555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  378.083569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  378.083586] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  378.083600] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  378.096359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.104832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.113301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.121770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.130239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.138707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.147212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.155680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.164163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.172635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.181103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.189571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.198038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.206506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.214974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.223454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.231923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.240391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.248859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  378.249928] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  378.264008] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  378.264054] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  378.264310] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  378.265421] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  378.266481] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  378.268500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  378.268541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  378.268578] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  378.268616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  378.274881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  378.274923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  378.280231] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  378.282819] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  378.284034] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  378.301009] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  378.301069] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  378.301159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  379.986130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  379.986327] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  380.003977] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  380.004047] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  380.004163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  380.004220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  380.004275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  380.004322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  380.004367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  380.004410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  380.004455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  380.004496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  380.004537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  380.004578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  380.004620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  380.004660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  380.004700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  380.004871] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  380.004962] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  380.005044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  380.005121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  380.005196] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  380.005308] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  380.005379] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  380.005451] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  380.005548] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  380.005655] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  380.005803] [drm:intel_power_well_disable [i915]] disabling DC off
>[  380.005874] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  380.005933] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  380.006425] [drm:intel_power_well_disable [i915]] disabling always-on
>[  380.007593] [drm:drm_mode_addfb2] [FB:69]
>[  380.007665] [drm:drm_mode_addfb2] [FB:110]
>[  380.038386] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  380.038814] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  380.039252] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  380.039310] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  380.039319] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  380.039375] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  380.039393] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  380.039412] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  380.039432] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  380.039448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  380.039465] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  380.039481] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  380.039497] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  380.039512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  380.039527] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  380.039540] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  380.039543] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  380.039556] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  380.039559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  380.039573] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  380.039587] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  380.039600] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  380.039613] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  380.039626] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  380.039643] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  380.039656] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  380.039669] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  380.039682] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  380.040074] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  380.040092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  380.040111] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  380.040127] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  380.040461] [drm:intel_power_well_enable [i915]] enabling always-on
>[  380.040474] [drm:intel_power_well_enable [i915]] enabling DC off
>[  380.040887] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  380.041280] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  380.041294] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  380.041332] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  380.041350] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  380.041371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  380.041388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  380.041403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  380.041417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  380.041431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  380.041444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  380.041458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  380.041472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  380.041484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  380.041497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  380.041510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  380.041522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  380.041534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  380.041549] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  380.041565] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  380.041580] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  380.041594] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  380.041613] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  380.041627] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  380.054348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.062819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.071286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.079765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.088233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.096713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.105179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.113647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.122114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.130581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.139047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.147514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.155990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.164519] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.172992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.181464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.189933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.198403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.206872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  380.207943] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  380.222036] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  380.222052] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  380.222130] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  380.222960] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  380.225210] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  380.226650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  380.226665] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  380.226679] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  380.226829] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  380.231970] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  380.231985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  380.237124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  380.239585] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  380.240143] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  380.256998] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  380.257021] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  380.257058] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  381.942164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  381.942361] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  381.959928] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  381.959998] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  381.960115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  381.960172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  381.960227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  381.960273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  381.960318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  381.960361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  381.960407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  381.960450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  381.960492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  381.960533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  381.960576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  381.960617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  381.960657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  381.960704] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  381.960910] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  381.960988] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  381.961066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  381.961144] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  381.961258] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  381.961331] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  381.961402] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  381.961503] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  381.961610] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  381.961687] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.961808] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  381.961872] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  381.962363] [drm:intel_power_well_disable [i915]] disabling always-on
>[  381.964523] [drm:drm_mode_addfb2] [FB:69]
>[  381.964600] [drm:drm_mode_addfb2] [FB:110]
>[  382.041911] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  382.042261] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  382.042314] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  382.042930] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  382.042940] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  382.043001] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  382.043015] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  382.043031] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  382.043048] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  382.043061] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  382.043075] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  382.043088] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  382.043101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  382.043114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  382.043126] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  382.043137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  382.043139] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  382.043150] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  382.043152] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  382.043164] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  382.043175] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  382.043186] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  382.043197] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  382.043207] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  382.043221] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  382.043232] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  382.043242] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  382.043253] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  382.043263] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  382.043281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  382.043297] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  382.043309] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  382.044839] [drm:intel_power_well_enable [i915]] enabling always-on
>[  382.044850] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.045133] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  382.045150] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  382.045162] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  382.045204] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  382.045215] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  382.045232] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  382.045441] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  382.045455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  382.045470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  382.045483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  382.045495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  382.045507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  382.045518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  382.045530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  382.045541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  382.045552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  382.045563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  382.045573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  382.045584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  382.045594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  382.045606] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  382.045620] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  382.045632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  382.045645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  382.045660] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  382.045673] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  382.049662] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  382.049705] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  382.049984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  382.050027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  382.050991] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  382.051035] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  382.051072] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  382.052021] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  382.052061] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  382.052098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  382.053067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  382.053109] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  382.054285] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  382.056622] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  382.057491] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  382.057544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  382.057572] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  382.057611] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  382.057683] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  382.057757] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  382.074335] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  382.074364] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  382.074411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  383.757929] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  383.758012] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  383.758046] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  383.758115] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  383.775498] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  383.775567] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  383.775629] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  383.775844] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  383.778366] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  383.778433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  383.778499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  383.778554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  383.778604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  383.778653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  383.778700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  383.778856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  383.778906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  383.778957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  383.779005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  383.779062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  383.779112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  383.779162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  383.779217] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  383.779281] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  383.779341] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  383.779398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  383.779452] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  383.779535] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  383.779587] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  383.779638] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.779708] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  383.779821] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  383.779884] [drm:intel_power_well_disable [i915]] disabling DC off
>[  383.779938] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  383.779983] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  383.780451] [drm:intel_power_well_disable [i915]] disabling always-on
>[  383.781073] [drm:drm_mode_addfb2] [FB:69]
>[  383.781146] [drm:drm_mode_addfb2] [FB:110]
>[  383.859635] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  383.860120] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  383.860188] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  383.860615] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  383.860623] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  383.860671] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  383.860686] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  383.860868] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  383.860887] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  383.860902] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  383.860931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  383.860946] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  383.860961] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  383.860975] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  383.860988] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  383.861001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  383.861004] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  383.861016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  383.861018] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  383.861031] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  383.861044] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  383.861056] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  383.861068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  383.861080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  383.861095] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  383.861107] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  383.861119] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  383.861131] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  383.861143] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  383.861164] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  383.861181] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  383.861195] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  383.862501] [drm:intel_power_well_enable [i915]] enabling always-on
>[  383.862512] [drm:intel_power_well_enable [i915]] enabling DC off
>[  383.862895] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  383.863344] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.863356] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  383.863388] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  383.863403] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  383.863421] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  383.863550] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  383.863565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  383.863580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  383.863593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  383.863605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  383.863617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  383.863629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  383.863641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  383.863651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  383.863662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  383.863672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  383.863683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  383.864018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  383.864043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  383.864056] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  383.864070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  383.864083] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  383.864096] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  383.864112] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  383.864125] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  383.867389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  383.867406] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  383.867420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  383.867448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  383.868222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  383.868266] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  383.868279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  383.869001] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  383.869015] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  383.869029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  383.869659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  383.869673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  383.870761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  383.873027] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  383.873490] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  383.873513] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  383.873526] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  383.873545] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  383.890315] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  383.890336] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  383.890369] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  385.574210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  385.574377] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  385.574449] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  385.574571] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  385.591901] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  385.591969] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  385.592083] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  385.592284] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  385.592341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  385.592397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  385.592448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  385.592494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  385.592538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  385.592581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  385.592627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  385.592670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  385.592711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  385.592855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  385.592911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  385.592954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  385.592996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  385.593045] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  385.593103] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  385.593159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  385.593210] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  385.593261] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  385.593340] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  385.593385] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  385.593432] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  385.593498] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  385.593571] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  385.593626] [drm:intel_power_well_disable [i915]] disabling DC off
>[  385.593673] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  385.593736] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  385.594200] [drm:intel_power_well_disable [i915]] disabling always-on
>[  385.594855] [drm:drm_mode_addfb2] [FB:69]
>[  385.594934] [drm:drm_mode_addfb2] [FB:110]
>[  385.671511] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  385.672002] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  385.672370] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  385.672430] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  385.672437] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  385.672482] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  385.672497] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  385.672513] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  385.672530] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  385.672543] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  385.672556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  385.672570] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  385.672583] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  385.672596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  385.672608] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  385.672619] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  385.672621] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  385.672632] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  385.672634] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  385.672646] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  385.672657] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  385.672668] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  385.672678] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  385.672818] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  385.672834] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  385.672850] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  385.672863] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  385.672877] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  385.672889] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  385.672910] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  385.672941] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  385.672955] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  385.674031] [drm:intel_power_well_enable [i915]] enabling always-on
>[  385.674041] [drm:intel_power_well_enable [i915]] enabling DC off
>[  385.674324] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  385.674341] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  385.674351] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  385.674383] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  385.674398] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  385.674417] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  385.676636] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  385.676655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  385.676672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  385.676687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  385.676828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  385.676846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  385.676863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  385.676879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  385.676895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  385.676911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  385.676927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  385.676941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  385.676956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  385.676969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  385.676985] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  385.677004] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  385.677019] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  385.677035] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  385.677056] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  385.677073] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  385.681212] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  385.681229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  385.681243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  385.681258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  385.682035] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  385.682050] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  385.682064] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  385.682787] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  385.682801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  385.682816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  385.683455] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  385.683469] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  385.684424] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  385.686687] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  385.687155] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  385.687190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  385.687203] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  385.687222] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  385.714283] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  385.714305] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  385.714339] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  387.387867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  387.388045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  387.388118] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  387.388241] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  387.404508] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  387.404576] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  387.404689] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  387.405736] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  387.405869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  387.405936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  387.405994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  387.406043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  387.406092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  387.406139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  387.406189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  387.406234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  387.406279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  387.406321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  387.406370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  387.406412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  387.406454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  387.406503] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  387.406560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  387.406614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  387.406665] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  387.406721] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  387.406873] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  387.406923] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  387.406972] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  387.407039] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  387.407113] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  387.407166] [drm:intel_power_well_disable [i915]] disabling DC off
>[  387.407212] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  387.407252] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  387.407771] [drm:intel_power_well_disable [i915]] disabling always-on
>[  387.415746] [IGT] kms_flip: exiting, ret=0
>[  387.443526] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  387.443558] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  387.443592] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  387.443627] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  387.443655] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  387.443684] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.443738] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  387.443766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  387.443793] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  387.443819] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  387.443843] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.443849] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  387.443873] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.443877] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  387.443902] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  387.443926] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  387.443950] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  387.443974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.443996] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.444025] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  387.444048] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.444071] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  387.444094] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  387.444116] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  387.444150] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  387.444177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  387.444206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  387.444239] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  387.444267] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  387.444294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  387.444320] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  387.444345] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  387.444369] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  387.444391] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  387.444413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  387.444417] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  387.444439] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  387.444442] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  387.444466] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  387.444489] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  387.444511] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  387.444533] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  387.444555] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  387.444583] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  387.444606] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  387.444628] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  387.444649] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  387.444671] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  387.444700] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  387.444748] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  387.444776] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  387.444805] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  387.444832] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  387.444938] [drm:intel_power_well_enable [i915]] enabling always-on
>[  387.444960] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.445255] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  387.445293] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  387.445317] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  387.445359] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  387.445382] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  387.445411] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  387.445434] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  387.445470] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  387.445646] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  387.445668] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  387.445702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  387.445775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  387.445802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  387.445828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  387.445854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  387.445879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  387.445905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  387.445928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  387.445951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  387.445975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  387.445998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  387.446021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  387.446044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  387.446070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  387.446101] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  387.446129] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  387.446157] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  387.446190] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  387.446218] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  387.458238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.466746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.475312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.483821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.492330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.500840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.509348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.517857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.526365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.534872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.543382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.551891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.560399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.568907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.578154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.586663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.595187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.603715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  387.611590] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  387.625974] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  387.625993] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  387.626024] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  387.627168] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  387.629424] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  387.630847] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.630862] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.630875] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.630890] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.636060] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.636074] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  387.641242] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.643726] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  387.644246] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  387.644305] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  387.644320] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  387.644368] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  387.644381] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  387.647628] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  387.647644] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  387.647658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  387.647673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  387.648346] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  387.648360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  387.648373] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  387.649027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  387.649040] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  387.649053] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  387.649716] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  387.649730] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  387.650688] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  387.652957] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  387.653476] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  387.653509] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  387.653523] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  387.653544] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  387.670371] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  387.670393] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  387.670431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  387.670473] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  387.670493] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  387.670528] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  387.670666] Console: switching to colour frame buffer device 240x75
>[  387.862986] Console: switching to colour dummy device 80x25
>[  387.863076] [IGT] kms_force_connector_basic: executing
>[  387.876000] [IGT] kms_force_connector_basic: exiting, ret=77
>[  387.903929] Console: switching to colour frame buffer device 240x75
>[  388.130236] Console: switching to colour dummy device 80x25
>[  388.130321] [IGT] kms_force_connector_basic: executing
>[  388.142573] [IGT] kms_force_connector_basic: exiting, ret=77
>[  388.178875] Console: switching to colour frame buffer device 240x75
>[  388.377956] Console: switching to colour dummy device 80x25
>[  388.378051] [IGT] kms_force_connector_basic: executing
>[  388.390133] [IGT] kms_force_connector_basic: exiting, ret=77
>[  388.420860] Console: switching to colour frame buffer device 240x75
>[  388.640161] Console: switching to colour dummy device 80x25
>[  388.640250] [IGT] kms_force_connector_basic: executing
>[  388.651941] [IGT] kms_force_connector_basic: exiting, ret=77
>[  388.687447] Console: switching to colour frame buffer device 240x75
>[  388.907480] Console: switching to colour dummy device 80x25
>[  388.907577] [IGT] kms_frontbuffer_tracking: executing
>[  388.921090] [drm:drm_mode_addfb2] [FB:69]
>[  388.921185] [drm:drm_mode_addfb2] [FB:110]
>[  388.921277] [drm:drm_mode_addfb2] [FB:115]
>[  388.923466] [drm:drm_mode_addfb2] [FB:116]
>[  388.959499] [drm:drm_mode_addfb2] [FB:117]
>[  388.972831] [drm:drm_mode_addfb2] [FB:123]
>[  388.972910] [drm:drm_mode_addfb2] [FB:125]
>[  388.972988] [drm:drm_mode_addfb2] [FB:126]
>[  388.973402] [IGT] kms_frontbuffer_tracking: starting subtest basic
>[  388.977452] [drm:drm_mode_addfb2] [FB:69]
>[  388.977537] [drm:drm_mode_addfb2] [FB:110]
>[  388.977617] [drm:drm_mode_addfb2] [FB:115]
>[  388.979485] [drm:drm_mode_addfb2] [FB:116]
>[  389.016241] [drm:drm_mode_addfb2] [FB:117]
>[  389.030295] [drm:drm_mode_addfb2] [FB:123]
>[  389.030375] [drm:drm_mode_addfb2] [FB:125]
>[  389.030457] [drm:drm_mode_addfb2] [FB:126]
>[  389.030480] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.030530] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  389.030608] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  389.047747] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  389.047769] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  389.047788] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  389.047829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  389.047846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  389.047863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  389.047877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  389.047891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  389.047904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  389.047917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  389.047930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  389.047943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  389.047955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  389.047967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  389.047979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  389.047991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  389.048005] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  389.048022] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  389.048037] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.048051] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  389.048066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  389.053777] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  389.053794] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  389.053822] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  389.053843] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  389.053917] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  389.053965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.054029] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  389.054051] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  389.054089] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  389.071211] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  389.071237] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  389.071280] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  389.071369] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  389.071389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  389.071410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  389.071428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  389.071446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  389.071462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  389.071478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  389.071494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  389.071510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  389.071525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  389.071540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  389.071557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  389.071572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  389.071587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  389.071604] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  389.071625] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  389.071644] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.071662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  389.071679] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  389.071749] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  389.071769] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  389.071790] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.071818] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.071846] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  389.071870] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.071889] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  389.071906] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  389.072330] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.072410] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  389.079096] [drm:drm_mode_addfb2] [FB:113]
>[  389.082896] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.082907] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  389.082977] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  389.083000] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  389.083024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  389.083050] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.083070] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.083092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.083114] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  389.083134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  389.083153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.083172] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  389.083189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.083193] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  389.083210] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.083213] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  389.083230] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  389.083248] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.083264] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  389.083281] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.083297] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.083318] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  389.083335] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.083353] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  389.083369] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  389.083386] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  389.083407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.083431] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  389.083451] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  389.083938] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.083956] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.084248] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  389.084275] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.084293] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.084338] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  389.084366] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  389.084395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  389.084418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  389.084440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  389.084460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  389.084480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  389.084498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  389.084519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  389.084536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  389.084556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  389.084573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  389.084593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  389.084610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  389.084629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  389.084649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  389.084680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.084719] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  389.084743] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  389.084770] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  389.084793] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  389.097542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.106015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.114484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.122951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.131418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.139901] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.148368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.156836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.165302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.173768] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.182234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.190702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.199179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.207653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.216125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.224595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.233065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.241535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.250003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.251077] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  389.265154] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  389.265173] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  389.265204] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  389.266719] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  389.269305] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  389.270645] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.270661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.270675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.270689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.275907] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.275922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  389.281060] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.283523] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  389.284062] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  389.284122] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  389.284137] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  389.300939] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  389.300961] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  389.300997] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.334736] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.334798] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.334879] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  389.351819] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  389.351852] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  389.351881] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  389.351934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  389.351961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  389.351986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  389.352008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  389.352028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  389.352048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  389.352070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  389.352089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  389.352107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  389.352126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  389.352145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  389.352163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  389.352182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  389.352204] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  389.352229] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  389.352252] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.352274] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  389.352296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  389.352332] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  389.352353] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  389.352373] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.352403] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.352435] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  389.352461] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.352482] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  389.352500] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  389.353893] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.353990] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  389.354413] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  389.362773] [drm:drm_mode_addfb2] [FB:113]
>[  389.377944] [drm:drm_mode_addfb2] [FB:114]
>[  389.389148] [drm:drm_mode_addfb2] [FB:127]
>[  389.400428] [drm:drm_mode_addfb2] [FB:128]
>[  389.534028] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.534037] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  389.534089] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  389.534105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  389.534121] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  389.534139] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.534152] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.534167] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.534182] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  389.534196] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  389.534209] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.534222] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  389.534234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.534236] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  389.534248] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.534250] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  389.534262] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  389.534273] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.534285] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  389.534296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.534307] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.534321] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  389.534333] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.534345] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  389.534356] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  389.534367] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  389.534381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.534398] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  389.534411] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  389.534786] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.534812] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.535096] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  389.535116] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.535130] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.535158] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  389.535171] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  389.535190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  389.535207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  389.535221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  389.535236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  389.535250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  389.535264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  389.535278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  389.535291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  389.535304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  389.535317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  389.535330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  389.535343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  389.535356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  389.535370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  389.535386] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.535402] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  389.535416] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  389.535434] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  389.535449] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  389.548221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.556844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.565315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.573784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.582253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.590722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.599190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.607659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.616176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.624645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.633113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.641581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.650051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.658520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.666989] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.675459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.683929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.692397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  389.715218] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  389.719607] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  389.719624] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  389.719681] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  389.720518] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  389.721971] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  389.724210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  389.724239] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  389.724251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  389.724265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  389.729404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  389.729420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  389.734590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  389.737078] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  389.737545] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  389.737600] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  389.737614] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  389.754436] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  389.754457] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  389.754490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.787928] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.787939] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  389.837961] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.837986] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  389.888058] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.888089] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  389.938157] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.938316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.938557] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  389.954998] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  389.955071] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  389.955132] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  389.955240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  389.955296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  389.955351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  389.955399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  389.955444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  389.955488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  389.955534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  389.955577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  389.955619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  389.955661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  389.955705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  389.956889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  389.956941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  389.956993] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  389.957054] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  389.957108] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.957160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  389.957208] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  389.957279] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  389.957324] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  389.957368] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  389.957430] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  389.957501] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  389.957558] [drm:intel_power_well_disable [i915]] disabling DC off
>[  389.957603] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  389.957643] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  389.959092] [drm:intel_power_well_disable [i915]] disabling always-on
>[  389.959297] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  389.959849] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  389.964312] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  389.964341] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  389.964503] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  389.964562] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  389.964624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  389.964690] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  389.964804] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  389.964869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  389.964932] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  389.964988] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  389.965044] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  389.965096] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  389.965145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  389.965161] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  389.965209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  389.965220] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  389.965273] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  389.965322] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  389.965374] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  389.965421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  389.965472] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  389.965530] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  389.965582] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  389.965628] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  389.965678] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  389.965752] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  389.965807] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  389.965874] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  389.965931] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  389.967848] [drm:intel_power_well_enable [i915]] enabling always-on
>[  389.967892] [drm:intel_power_well_enable [i915]] enabling DC off
>[  389.968015] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  389.968080] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  389.968125] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  389.968196] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  389.968241] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  389.968310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  389.968371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  389.968424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  389.968476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  389.968525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  389.968573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  389.968624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  389.968671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  389.968717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  389.968815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  389.968869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  389.968918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  389.968964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  389.969018] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  389.969080] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  389.969139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  389.969196] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  389.969263] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  389.969318] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  389.995261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.004004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.012733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.021522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.030244] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.038978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.047707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.056522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.065252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.073979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.082708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.091467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.100059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.108606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.117121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.125616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.134098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.142583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.147035] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  390.162028] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  390.162045] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  390.162097] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  390.162928] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  390.164085] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  390.166685] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  390.166713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  390.166727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  390.166755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  390.171895] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  390.171911] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  390.177050] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  390.179531] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  390.180123] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  390.180160] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  390.180174] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  390.196991] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  390.197011] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  390.197044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  390.272258] [drm:drm_mode_addfb2] [FB:113]
>[  390.814574] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  390.814954] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  390.831971] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  390.832044] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  390.832108] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  390.832222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  390.832279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  390.832335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  390.832383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  390.832429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  390.832474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  390.832520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  390.832563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  390.832604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  390.832645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  390.832689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  390.832830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  390.832875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  390.832923] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  390.832980] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  390.833034] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  390.833085] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  390.833135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  390.833212] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  390.833259] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  390.833304] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  390.833368] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  390.833440] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  390.833498] [drm:intel_power_well_disable [i915]] disabling DC off
>[  390.833545] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  390.833586] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  390.834087] [drm:intel_power_well_disable [i915]] disabling always-on
>[  390.835180] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  390.859980] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  390.860002] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  390.860025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  390.860049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  390.860068] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  390.860088] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.860108] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  390.860126] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  390.860145] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  390.860161] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  390.860178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.860182] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  390.860198] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.860201] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  390.860218] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  390.860234] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  390.860250] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  390.860265] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.860281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.860300] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  390.860316] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.860331] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  390.860346] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  390.860362] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  390.860384] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  390.860402] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  390.860422] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  390.860444] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  390.860463] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  390.860481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  390.860499] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  390.860515] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  390.860531] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  390.860547] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  390.860562] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  390.860565] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  390.860580] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  390.860582] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  390.860598] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  390.860613] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  390.860628] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  390.860643] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  390.860658] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  390.860677] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  390.860728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  390.860746] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  390.860762] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  390.860782] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  390.860805] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  390.860830] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  390.860851] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  390.860874] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  390.860894] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  390.860988] [drm:intel_power_well_enable [i915]] enabling always-on
>[  390.861004] [drm:intel_power_well_enable [i915]] enabling DC off
>[  390.861311] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  390.861337] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  390.861354] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  390.861420] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  390.861437] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  390.861458] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  390.861474] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  390.861499] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  390.862103] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  390.862119] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  390.862145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  390.862168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  390.862187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  390.862206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  390.862224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  390.862242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  390.862260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  390.862278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  390.862294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  390.862311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  390.862327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  390.862342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  390.862358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  390.862376] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  390.862396] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  390.862416] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  390.862435] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  390.862465] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  390.862485] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  390.874234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.882749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.891253] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.899757] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.908262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.916767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.925273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.933791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.942306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.950832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.959342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.967851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.976359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.984868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  390.993376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.001885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.010408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.018916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.027422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  391.028508] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  391.043411] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  391.043428] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  391.043500] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  391.044332] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  391.046225] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  391.048148] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.048164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.048178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.048193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.053432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.053447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  391.058591] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.061056] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  391.061533] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  391.061626] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  391.061641] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  391.061692] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  391.061723] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  391.064954] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  391.064970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  391.064985] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  391.065000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  391.065647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  391.065661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  391.065674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  391.066375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  391.066391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  391.066404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  391.067083] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  391.067099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  391.068080] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  391.070358] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  391.070918] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  391.070953] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  391.070968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  391.070998] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  391.087754] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  391.087776] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  391.087813] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  391.087851] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  391.087871] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  391.087903] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  391.104610] Console: switching to colour frame buffer device 240x75
>[  391.559875] Console: switching to colour dummy device 80x25
>[  391.560177] [IGT] kms_pipe_crc_basic: executing
>[  391.579474] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  391.579560] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  391.588127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.596586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.605048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.613507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.621965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.630421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.638878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.647334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.655791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.664249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.672706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.681164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.689622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.717538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.725998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.734457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.742915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.751371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.759920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.768378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.776836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.785294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.793765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.802223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.810681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.819152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.827612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.836071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.844529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.852987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.861445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.869904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.869913] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  391.869916] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  391.869955] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  391.869987] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  391.870922] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  391.872444] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  391.872461] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  391.872487] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  391.872500] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  391.873330] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  391.874110] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  391.874891] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  391.874916] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  391.874931] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  391.874932] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  391.874934] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  391.874935] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  391.874937] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.874938] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  391.874940] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  391.874941] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  391.874942] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  391.874944] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  391.874945] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  391.874947] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.874960] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  391.874975] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  391.874992] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  391.874999] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  391.875013] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  391.876884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  391.876899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  391.878873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  391.878876] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  391.880852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  391.880868] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  391.883128] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  391.883135] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  391.883137] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  391.883147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  391.883164] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  391.883625] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  391.883952] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  391.883969] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  391.883983] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  391.884009] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  391.884412] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  391.884758] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  391.885259] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  391.885260] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  391.885335] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  391.885337] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  391.885340] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  391.885341] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  391.885343] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  391.885344] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  391.885350] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  391.885352] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  391.885353] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  391.885355] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  391.885356] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  391.885357] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.885359] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  391.885360] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  391.885362] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  391.885363] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  391.885364] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  391.885366] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  391.885367] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  391.885368] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  391.885370] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  391.885371] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.885372] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  391.885374] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  391.885375] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  391.885377] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.885378] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  391.885379] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  391.885381] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  391.885382] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  391.885383] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  391.885385] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  391.885386] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  391.885388] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.885389] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  391.885390] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  391.885392] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.885393] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  391.885394] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  391.885420] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  391.885435] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  391.886874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  391.886889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  391.888934] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  391.888938] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  391.890875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  391.890891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  391.892900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  391.892904] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  391.892906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  391.901481] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  391.901497] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  391.909952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.918410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.926868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.935324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.943780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.952237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.960708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.969166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.977622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.986078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  391.994533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.002992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.011448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.019904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.028360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.036816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.045272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.053728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.062184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.070733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.079189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.087647] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.096104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.104564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.113021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.121479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.129936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.138391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.146848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.155304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.163762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.172218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.172227] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  392.172230] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  392.172429] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  392.172445] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  392.173299] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  392.174822] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  392.174869] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  392.174882] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  392.174894] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  392.175685] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  392.176538] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.177320] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  392.177356] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  392.177358] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  392.177359] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  392.177361] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  392.177362] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  392.177363] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.177365] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  392.177366] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  392.177368] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  392.177369] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.177370] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.177372] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  392.177373] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.177532] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  392.177546] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  392.177563] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  392.178120] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  392.178136] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  392.179881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.179896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.181885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.181889] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  392.184152] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.184168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.186427] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.186431] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.186433] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  392.186617] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  392.186634] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  392.187175] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  392.187488] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  392.187504] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  392.187518] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  392.187532] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  392.188079] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  392.188391] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.188924] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  392.188925] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  392.189001] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  392.189002] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  392.189005] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.189006] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.189009] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.189010] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.189016] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  392.189017] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  392.189019] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  392.189020] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  392.189022] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  392.189023] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.189024] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.189026] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.189027] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.189029] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.189030] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  392.189031] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.189033] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.189034] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  392.189035] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  392.189037] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.189038] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.189040] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  392.189041] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  392.189042] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.189044] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.189045] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  392.189046] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  392.189048] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.189049] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.189050] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.189052] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  392.189053] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.189055] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.189056] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  392.189057] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.189059] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.189060] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  392.189240] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  392.189255] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  392.190861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  392.190875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  392.192880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  392.192884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  392.194878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  392.194894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  392.197145] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  392.197149] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.197151] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  392.197359] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-1
>[  392.197412] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  392.197492] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  392.221214] Console: switching to colour frame buffer device 240x75
>[  392.426244] Console: switching to colour dummy device 80x25
>[  392.426349] [IGT] kms_pipe_crc_basic: executing
>[  392.440428] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  392.440501] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  392.449229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.457928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.466616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.475368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.484024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.492701] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.501391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.510047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.518702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.527341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.535887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.544409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.552897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.561365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.569825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.578280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.586736] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.595191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.603666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.612171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.620627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.629082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.637538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.645994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.654449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.662905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.671359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.679814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.688270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.714060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.722530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.730986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.730995] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  392.730998] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  392.731010] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  392.731026] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  392.731902] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  392.733422] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  392.733438] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  392.733453] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  392.733479] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  392.734315] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  392.735028] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.735827] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  392.735863] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  392.735865] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  392.735867] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  392.735868] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  392.735870] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  392.735871] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.735873] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  392.735874] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  392.735875] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  392.735877] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.735878] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.735880] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  392.735881] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.735894] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  392.735909] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  392.735925] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  392.735932] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  392.735946] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  392.737881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.737897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.739875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  392.739879] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  392.741873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.741889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  392.743883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  392.743887] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.743889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  392.743903] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  392.743922] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  392.744370] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  392.744843] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  392.744860] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  392.744875] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  392.744901] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  392.745309] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  392.745623] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  392.746206] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  392.746208] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  392.746288] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  392.746289] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  392.746292] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.746293] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.746296] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  392.746297] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  392.746303] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  392.746305] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  392.746306] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  392.746307] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  392.746309] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  392.746310] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.746312] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  392.746313] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.746315] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  392.746316] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  392.746317] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  392.746319] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.746320] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  392.746321] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  392.746323] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  392.746324] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.746325] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  392.746327] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  392.746328] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  392.746329] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.746331] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  392.746332] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  392.746334] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  392.746335] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  392.746336] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  392.746338] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  392.746339] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  392.746340] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.746342] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  392.746343] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  392.746344] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.746346] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  392.746347] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  392.746378] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  392.746393] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  392.747861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  392.747875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  392.749876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  392.749880] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  392.751877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  392.751893] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  392.753880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  392.753884] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  392.753886] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  392.762602] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  392.762620] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  392.771072] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.779530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.787988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.796445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.804902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.813357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.821812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.830267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.838723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.847178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.855634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.864092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.872548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.881002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.889459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.897916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.906370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.914828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.923283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.931791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.940246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.948703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.957159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.965616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.974073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.982529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.990983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  392.999454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.007913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.016369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.024825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.033281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.033290] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  393.033293] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  393.033488] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  393.033503] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  393.034342] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  393.035930] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  393.035946] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  393.035960] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  393.035986] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  393.036827] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  393.037536] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.038320] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  393.038357] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  393.038359] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  393.038360] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  393.038362] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  393.038363] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  393.038365] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.038366] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  393.038367] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  393.038369] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  393.038370] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.038372] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.038373] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  393.038374] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.038536] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  393.038551] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  393.038568] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  393.039104] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  393.039119] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  393.040884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.040900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.042909] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.042912] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  393.045171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.045187] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.047448] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.047451] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.047454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  393.047638] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  393.047655] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  393.048302] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  393.048638] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  393.048655] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  393.048669] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  393.048725] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  393.049149] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  393.049461] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.049961] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  393.049962] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  393.050036] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  393.050037] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  393.050040] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.050041] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.050044] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.050045] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.050051] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  393.050052] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  393.050054] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  393.050055] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  393.050057] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  393.050058] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.050059] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.050061] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.050062] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.050064] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.050065] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  393.050066] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.050068] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.050069] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  393.050070] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  393.050072] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.050073] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.050074] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  393.050076] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  393.050077] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.050078] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.050080] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  393.050081] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  393.050083] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.050084] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  393.050085] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.050087] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  393.050088] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.050089] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.050091] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  393.050092] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.050093] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.050095] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  393.050273] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  393.050288] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  393.051792] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  393.051807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  393.053872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  393.053875] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  393.055874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  393.055890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  393.057871] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  393.057875] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.057877] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  393.058088] [IGT] kms_pipe_crc_basic: starting subtest bad-nb-words-3
>[  393.058146] [drm:display_crc_ctl_write [i915]] too many words, allowed <= 3
>[  393.058158] [drm:display_crc_ctl_write [i915]] tokenize failed, a command is 3 words
>[  393.058223] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  393.080105] Console: switching to colour frame buffer device 240x75
>[  393.286068] Console: switching to colour dummy device 80x25
>[  393.286367] [IGT] kms_pipe_crc_basic: executing
>[  393.304455] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  393.304537] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  393.313203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.321887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.330435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.338930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.347402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.355863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.364320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.372776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.381232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.389687] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.398157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.406614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.415071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.423529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.431984] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.440442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.448898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.457353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.465811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.474266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.482723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.491177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.499633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.508090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.516547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.525004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.533460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.541916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.550373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.558829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.567287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.575786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.575794] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  393.575798] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  393.575810] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  393.575826] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  393.576657] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  393.578180] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  393.578198] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  393.578224] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  393.578237] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  393.579033] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  393.579765] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.580551] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  393.580588] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  393.580590] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  393.580592] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  393.580593] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  393.580595] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  393.580596] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.580598] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  393.580599] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  393.580600] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  393.580602] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.580603] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.580605] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  393.580606] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.580620] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  393.580637] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  393.580650] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  393.580657] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  393.580671] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  393.581302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.581316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.582878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.582882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  393.584895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.584911] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.587170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.587173] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.587176] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  393.587185] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  393.587203] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  393.587653] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  393.588050] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  393.588067] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  393.588082] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  393.588097] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  393.588501] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  393.588847] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.589352] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  393.589353] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  393.589430] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  393.589432] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  393.589435] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.589436] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.589439] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.589440] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.589445] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  393.589447] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  393.589449] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  393.589450] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  393.589451] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  393.589453] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.589454] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.589455] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.589457] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.589458] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.589460] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  393.589461] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.589462] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.589464] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  393.589465] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  393.589466] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.589468] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.589469] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  393.589470] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  393.589472] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.589473] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.589475] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  393.589476] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  393.589477] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.589479] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  393.589480] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.589481] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  393.589483] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.589484] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.589485] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  393.589487] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.589488] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.589489] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  393.589517] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  393.589532] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  393.590786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  393.590800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  393.592887] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  393.592890] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  393.594874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  393.594890] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  393.596875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  393.596878] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.596881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  393.605389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  393.605406] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  393.613847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.622306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.630766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.639223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.647680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.656152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.664610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.673082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.681539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.689995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.717528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.725985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.734442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.742898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.751354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.759907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.768362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.776819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.785274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.793732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.802188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.810645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.819102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.827560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.836017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.844473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.852930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.861385] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.869842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.878299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.886756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.895212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  393.895220] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  393.895223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  393.895409] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  393.895423] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  393.896303] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  393.897826] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  393.897871] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  393.897886] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  393.897899] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  393.898692] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  393.899582] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.900365] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  393.900389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  393.900391] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  393.900393] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  393.900395] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  393.900396] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  393.900410] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.900412] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  393.900413] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  393.900414] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  393.900416] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.900417] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.900419] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  393.900420] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.900585] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  393.900600] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  393.900616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  393.901205] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  393.901221] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  393.902880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.902896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.904954] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  393.904958] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  393.907225] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.907241] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  393.909500] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  393.909504] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.909506] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  393.909822] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  393.909839] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  393.910313] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  393.910625] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  393.910641] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  393.910668] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  393.910680] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  393.911296] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  393.911607] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  393.912124] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  393.912126] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  393.912202] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  393.912204] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  393.912207] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.912208] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.912211] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  393.912212] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  393.912217] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  393.912219] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  393.912220] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  393.912222] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  393.912223] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  393.912225] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.912226] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  393.912227] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.912229] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  393.912230] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  393.912232] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  393.912233] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.912234] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  393.912236] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  393.912237] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  393.912238] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.912240] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  393.912241] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  393.912242] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  393.912244] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.912245] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  393.912246] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  393.912248] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  393.912249] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  393.912251] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  393.912252] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  393.912253] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  393.912255] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.912256] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  393.912257] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  393.912259] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.912260] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  393.912261] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  393.912432] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  393.912448] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  393.913785] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  393.913800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  393.915882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  393.915886] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  393.917876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  393.917892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  393.919873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  393.919876] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  393.919879] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  393.920085] [IGT] kms_pipe_crc_basic: starting subtest bad-pipe
>[  393.920140] [drm:display_crc_ctl_write [i915]] unknown pipe D
>[  393.920206] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  393.937916] Console: switching to colour frame buffer device 240x75
>[  394.160622] Console: switching to colour dummy device 80x25
>[  394.161257] [IGT] kms_pipe_crc_basic: executing
>[  394.178516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  394.178618] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  394.187270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.195968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.204559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.213061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.221535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.229995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.238451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.246908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.255362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.263817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.272273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.280728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.289184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.297640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.306096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.314551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.323006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.331462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.339916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.348370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.356826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.365282] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.373739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.382193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.390648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.399103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.407558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.416013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.424470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.432925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.441394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.449849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.449858] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  394.449862] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  394.449874] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  394.449889] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  394.450893] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  394.452414] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  394.452431] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  394.452446] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  394.452472] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  394.453290] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  394.454002] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  394.454820] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  394.454843] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  394.454845] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  394.454847] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  394.454848] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  394.454850] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  394.454851] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.454853] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  394.454854] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  394.454856] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  394.454857] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  394.454859] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  394.454860] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  394.454861] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.454875] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  394.454890] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  394.454907] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  394.454914] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  394.454929] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  394.456881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.456897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.458875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.458878] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  394.460880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.460895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.463159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.463163] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.463165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  394.463175] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  394.463193] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  394.463642] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  394.463961] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  394.463978] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  394.463992] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  394.464006] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  394.464410] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  394.464830] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  394.465323] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  394.465325] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  394.465400] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  394.465401] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  394.465404] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.465405] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.465408] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.465409] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.465414] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  394.465416] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  394.465418] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  394.465419] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  394.465420] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  394.465422] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.465423] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.465424] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.465426] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.465427] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  394.465429] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  394.465430] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.465431] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.465433] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  394.465434] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  394.465435] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.465437] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.465438] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  394.465439] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  394.465441] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.465442] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.465444] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  394.465445] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  394.465446] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  394.465448] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  394.465449] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  394.465450] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  394.465452] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.465453] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.465454] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  394.465456] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.465457] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.465458] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  394.465485] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  394.465500] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  394.466864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  394.466878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  394.468863] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  394.468866] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  394.470876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  394.470892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  394.472883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  394.472886] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.472888] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  394.481664] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  394.481683] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  394.490213] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.498673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.507204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.515662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.524143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.532599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.541163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.549618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.558073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.566533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.574990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.583445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.591900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.600354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.608810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.617264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.625719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.634174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.642629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.651084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.659539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.667995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.676451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.684905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.693359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.720894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.729348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.737804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.746259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.754715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.763266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.771722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  394.771731] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  394.771734] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  394.771923] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  394.771938] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  394.772822] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  394.774343] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  394.774359] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  394.774386] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  394.774399] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  394.775238] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  394.775947] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  394.776774] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  394.776799] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  394.776801] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  394.776803] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  394.776817] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  394.776819] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  394.776820] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.776822] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  394.776823] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  394.776825] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  394.776826] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  394.776828] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  394.776829] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  394.776830] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.777023] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  394.777038] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  394.777054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  394.777204] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  394.777219] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  394.778879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.778895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.780876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  394.780880] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  394.782878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.782894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  394.784877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  394.784880] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.784883] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  394.785071] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  394.785088] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  394.785537] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  394.786022] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  394.786038] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  394.786053] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  394.786067] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  394.786470] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  394.786847] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  394.787354] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  394.787356] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  394.787435] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  394.787436] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  394.787439] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.787440] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.787443] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  394.787444] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  394.787450] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  394.787452] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  394.787453] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  394.787454] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  394.787456] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  394.787457] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.787459] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  394.787460] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.787461] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  394.787463] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  394.787464] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  394.787465] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.787467] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  394.787468] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  394.787470] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  394.787471] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.787472] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  394.787474] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  394.787475] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  394.787476] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.787478] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  394.787479] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  394.787480] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  394.787482] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  394.787483] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  394.787485] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  394.787486] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  394.787487] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.787489] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  394.787490] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  394.787491] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.787493] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  394.787494] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  394.788469] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  394.788494] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  394.789886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  394.789901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  394.791880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  394.791884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  394.793886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  394.793902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  394.796161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  394.796165] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  394.796167] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  394.796381] [IGT] kms_pipe_crc_basic: starting subtest bad-source
>[  394.796523] [drm:intel_crtc_set_crc_source [i915]] unknown source foo
>[  394.796588] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  394.831672] Console: switching to colour frame buffer device 240x75
>[  395.080438] Console: switching to colour dummy device 80x25
>[  395.080810] [IGT] kms_pipe_crc_basic: executing
>[  395.099616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  395.099706] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  395.108435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.117131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.125777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.134319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.142811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.151280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.159739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.168196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.176653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.185156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.193613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.202070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.210526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.218981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.227450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.235905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.244361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.252817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.261273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.269732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.278188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.286644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.295100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.303557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.312015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.320471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.328928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.337397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.345853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.354309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.362765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.371223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.371232] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  395.371235] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  395.371252] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  395.371268] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  395.372107] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  395.373628] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  395.373645] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  395.373660] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  395.373674] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  395.374607] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  395.375320] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  395.376110] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  395.376146] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  395.376148] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  395.376150] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  395.376151] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  395.376153] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  395.376154] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.376155] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  395.376157] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  395.376158] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  395.376159] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  395.376161] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  395.376162] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  395.376164] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.376177] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  395.376192] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  395.376205] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  395.376213] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  395.376227] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  395.377881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.377897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.379874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.379878] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  395.381791] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.381807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.383876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.383880] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.383882] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  395.383891] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  395.383918] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  395.384367] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  395.384679] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  395.384892] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  395.384919] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  395.384932] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  395.385353] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  395.385666] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  395.386215] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  395.386217] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  395.386294] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  395.386295] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  395.386298] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.386299] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.386302] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.386303] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.386309] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  395.386310] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  395.386312] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  395.386313] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  395.386315] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  395.386316] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.386317] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.386320] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.386321] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.386323] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  395.386324] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  395.386325] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.386327] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.386328] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  395.386330] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  395.386331] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.386332] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.386334] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  395.386335] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  395.386336] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.386338] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.386339] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  395.386340] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  395.386342] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  395.386343] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  395.386345] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  395.386346] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  395.386347] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.386349] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.386350] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  395.386351] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.386353] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.386354] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  395.386381] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  395.386395] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  395.387786] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  395.387800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  395.389877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  395.389881] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  395.391877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  395.391893] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  395.393884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  395.393887] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.393890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  395.402703] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  395.402719] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  395.411175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.419634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.428092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.436548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.445005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.453461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.461916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.470375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.478832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.487288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.495744] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.504199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.512656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.521112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.529568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.538025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.546482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.554937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.563391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.571849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.580305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.588761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.597216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.605671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.614208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.622664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.631189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.639646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.648103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.656559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.665014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.673471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  395.673479] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  395.673482] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  395.673673] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  395.673688] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  395.674736] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  395.676271] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  395.676287] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  395.676302] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  395.676316] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  395.677114] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  395.677824] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  395.678596] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  395.678621] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  395.678623] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  395.678625] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  395.678626] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  395.678628] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  395.678629] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.678631] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  395.678633] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  395.678634] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  395.678636] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  395.678637] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  395.678639] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  395.678640] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.679209] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  395.679224] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  395.679240] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  395.679389] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  395.679404] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  395.680854] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.680870] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.682904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  395.682908] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  395.685169] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.685185] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  395.687451] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  395.687455] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.687457] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  395.687649] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  395.687667] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  395.688266] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  395.688579] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  395.688596] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  395.688611] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  395.688638] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  395.689135] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  395.689454] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  395.689954] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  395.689956] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  395.690035] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  395.690036] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  395.690039] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.690040] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.690043] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  395.690044] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  395.690050] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  395.690052] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  395.690053] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  395.690054] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  395.690056] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  395.690057] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.690059] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  395.690060] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.690062] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  395.690063] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  395.690065] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  395.690066] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.690067] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  395.690069] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  395.690070] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  395.690071] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.690073] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  395.690074] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  395.690076] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  395.690077] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.690079] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  395.690080] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  395.690081] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  395.690083] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  395.690084] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  395.690086] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  395.690087] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  395.690088] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.690090] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  395.690091] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  395.690093] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.690094] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  395.690095] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  395.690274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  395.690290] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  395.691793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  395.691808] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  395.693878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  395.693881] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  395.714370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  395.714384] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  395.715879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  395.715883] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  395.715885] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  395.716098] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-A
>[  395.716665] [drm:drm_mode_addfb2] [FB:68]
>[  395.722921] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  395.722931] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  395.748947] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  395.748998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  395.749017] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  395.749031] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  395.749088] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  395.766009] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  395.766029] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  395.766046] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  395.766067] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  395.766090] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  395.766123] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  395.772523] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  395.772543] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  395.772580] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  395.776894] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  395.776915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  395.776934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  395.776951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  395.776966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  395.776981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  395.776995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  395.777011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  395.777025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  395.777039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  395.777052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  395.777068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  395.777082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  395.777096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  395.777111] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  395.777130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  395.777148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  395.777164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  395.777180] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  395.777205] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  395.777221] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  395.789950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.798463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.806971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.815480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.823986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.832493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.841001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.849507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.858014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.866520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.875026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.883524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.892007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.900543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.909023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.917502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.925981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.934458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  395.942105] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  395.957582] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  395.957601] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  395.957646] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  395.958489] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  395.960006] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  395.962253] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  395.962271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  395.962287] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  395.962304] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  395.967616] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  395.967634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  395.972790] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  395.975309] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  395.975898] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  395.975929] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  395.975946] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  396.009427] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  396.009456] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.009501] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.009521] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  396.009540] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  396.009569] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  396.009589] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  396.012545] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  396.076439] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.076625] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.094639] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.094706] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  396.094894] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  396.095069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  396.095156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  396.095239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  396.095305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  396.095374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  396.095436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  396.095506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  396.095565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  396.095630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  396.095690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  396.095824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  396.095883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  396.095947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  396.096014] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  396.096098] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  396.096178] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.096256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  396.096330] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  396.096434] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  396.096505] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  396.096576] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  396.096672] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  396.096824] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.096913] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.096985] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  396.097043] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  396.097522] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.099397] [drm:drm_mode_addfb2] [FB:68]
>[  396.119600] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  396.119626] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  396.119819] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  396.119872] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  396.119927] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  396.119987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  396.120032] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  396.120082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.120131] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  396.120178] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  396.120224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  396.120269] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  396.120311] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.120322] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  396.120361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.120369] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  396.120410] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  396.120451] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  396.120491] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  396.120529] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.120569] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.120616] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  396.120657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.120696] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  396.120773] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  396.120811] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  396.120858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.120911] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  396.120956] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  396.121782] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.121817] [drm:intel_power_well_enable [i915]] enabling DC off
>[  396.122130] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  396.122183] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  396.122224] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  396.122314] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  396.122353] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  396.122410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  396.122460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  396.122504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  396.122546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  396.122585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  396.122624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  396.122664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  396.122702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  396.122782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  396.122823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  396.122865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  396.122902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  396.122941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  396.122986] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  396.123035] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.123082] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  396.123128] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  396.123183] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  396.123229] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  396.136322] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.145043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.153797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.162500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.171209] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.179915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.188661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.197552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.206257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.214963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.223658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.232398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.240977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.249520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.258031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.266530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.275015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.283496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  396.289457] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  396.304992] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  396.305007] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  396.305062] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  396.305908] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  396.306625] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  396.308461] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.308512] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.308570] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.308590] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.314458] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.314491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  396.319669] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.322140] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  396.322641] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  396.322677] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  396.322690] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  396.339471] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  396.339490] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.339524] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.423106] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.423260] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.441846] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.441913] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  396.441973] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  396.442081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  396.442137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  396.442193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  396.442241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  396.442288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  396.442334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  396.442380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  396.442423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  396.442466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  396.442507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  396.442552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  396.442594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  396.442634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  396.442682] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  396.442851] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  396.442932] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.443011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  396.443087] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  396.443192] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  396.443264] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  396.443336] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  396.443436] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  396.443538] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.443630] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.443704] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  396.443821] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  396.444908] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.447303] [drm:drm_mode_addfb2] [FB:68]
>[  396.508725] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  396.508753] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  396.508916] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  396.508975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.509037] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  396.509105] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  396.509172] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  396.509223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.509274] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  396.509321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  396.509367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  396.509411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.509453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.509460] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  396.509503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.509509] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  396.509551] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  396.509592] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  396.509632] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  396.509671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.509710] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.510563] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  396.510617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.510669] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  396.510718] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  396.510968] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  396.511047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  396.511110] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  396.511165] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  396.514031] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.514074] [drm:intel_power_well_enable [i915]] enabling DC off
>[  396.514380] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  396.514443] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  396.514498] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  396.514597] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  396.514639] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  396.514704] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  396.517337] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  396.517403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  396.517464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  396.517519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  396.517569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  396.517618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  396.517664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  396.517713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  396.518263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  396.518311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  396.518359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  396.518405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  396.518451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  396.518495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  396.518546] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  396.518604] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.518659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  396.518712] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  396.519327] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  396.519380] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  396.522937] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.522994] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.523045] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.523096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.524334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  396.524387] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  396.524436] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  396.525431] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  396.525481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.525528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  396.526505] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.526558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  396.527789] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.530148] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  396.531480] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  396.531563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  396.531613] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  396.531680] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.531923] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  396.531975] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  396.548445] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  396.548520] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.548632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.632030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.632185] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  396.632254] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  396.632363] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.650408] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.650474] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  396.650533] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  396.650641] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  396.651446] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  396.651505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  396.651569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  396.651625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  396.651677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  396.651758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  396.651804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  396.651853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  396.651900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  396.651944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  396.651988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  396.652037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  396.652078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  396.652121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  396.652170] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  396.652228] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  396.652281] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.652331] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  396.652381] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  396.652452] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  396.652501] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  396.652547] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  396.652611] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  396.652680] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.652770] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.652817] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  396.652858] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  396.653326] [drm:intel_power_well_disable [i915]] disabling always-on
>[  396.655241] [drm:drm_mode_addfb2] [FB:68]
>[  396.718993] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  396.719021] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  396.719184] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  396.719243] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  396.719305] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  396.719371] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  396.719424] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  396.719481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  396.719536] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  396.719587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  396.719638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  396.719686] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  396.719818] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  396.719834] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  396.719896] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  396.719912] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  396.719978] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  396.720045] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  396.720106] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  396.720176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  396.720239] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  396.720320] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  396.720382] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  396.720448] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  396.720509] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  396.720575] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  396.720678] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  396.720798] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  396.720874] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  396.723853] [drm:intel_power_well_enable [i915]] enabling always-on
>[  396.723893] [drm:intel_power_well_enable [i915]] enabling DC off
>[  396.724209] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  396.724268] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  396.724317] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  396.724411] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  396.724454] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  396.724520] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  396.726690] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  396.726797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  396.726859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  396.726913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  396.726962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  396.727009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  396.727056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  396.727104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  396.727148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  396.727192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  396.727236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  396.727280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  396.727324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  396.727367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  396.727417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  396.727473] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.727526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  396.727577] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  396.727640] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  396.727691] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  396.731584] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  396.731643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  396.731695] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  396.731803] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  396.732726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  396.732938] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  396.733011] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  396.733960] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  396.734037] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  396.734111] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  396.735160] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  396.735215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  396.736417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  396.738824] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  396.740245] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  396.740328] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  396.740379] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  396.740447] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  396.740567] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  396.740619] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  396.757192] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  396.757267] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.757379] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.840704] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  396.840926] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  396.840994] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  396.841101] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  396.857573] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  396.857641] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  396.857702] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  396.857881] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  396.858194] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  396.858277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  396.858339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  396.858391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  396.858440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  396.858488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  396.858534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  396.858582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  396.858626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  396.858669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  396.858712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  396.858819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  396.858863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  396.858905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  396.858955] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  396.859013] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  396.859069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  396.859119] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  396.859170] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  396.859238] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  396.859288] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  396.859334] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  396.859400] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  396.859468] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  396.859527] [drm:intel_power_well_disable [i915]] disabling DC off
>[  396.859575] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  396.859614] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  396.860097] [drm:intel_power_well_disable [i915]] disabling always-on
>[  404.725223] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  404.725280] drm/i915: Resetting chip after gpu hang
>[  404.725674] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8724]/0 marked guilty (score 10) banned? no
>[  404.725688] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x398f95
>[  404.726146] [drm] RC6 on
>[  404.738271] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  404.738288] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x398f95, 0x0]
>[  404.738861] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  404.738935] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  404.738988] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  404.739073] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  404.739105] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  404.739110] [drm] GuC firmware load skipped
>[  404.739523] [drm:drm_mode_addfb2] [FB:68]
>[  404.746564] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  404.746572] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  404.746619] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  404.746635] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  404.746651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  404.746669] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  404.746683] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  404.746842] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  404.746861] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  404.746879] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  404.746897] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  404.746929] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  404.746944] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  404.746948] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  404.746962] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  404.746964] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  404.746980] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  404.747010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  404.747023] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  404.747035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  404.747048] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  404.747063] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  404.747076] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  404.747089] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  404.747102] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  404.747114] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  404.747130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  404.747148] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  404.747163] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  404.747484] [drm:intel_power_well_enable [i915]] enabling always-on
>[  404.747497] [drm:intel_power_well_enable [i915]] enabling DC off
>[  404.747848] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  404.747890] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  404.747905] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  404.747930] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  404.747946] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  404.747967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  404.747987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  404.748003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  404.748019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  404.748035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  404.748050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  404.748065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  404.748080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  404.748094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  404.748109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  404.748123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  404.748137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  404.748150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  404.748166] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  404.748184] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  404.748219] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  404.748237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  404.748259] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  404.748278] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  404.760235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.768715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.777212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.785692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.794186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.802662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.811167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.819641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.828114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.836586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.845056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.853524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.861992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.870460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.878928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.887394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.895862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.904329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.912797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  404.915560] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  404.929385] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  404.929401] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  404.929474] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  404.930311] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  404.931048] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  404.932828] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  404.932846] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  404.932862] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  404.932879] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  404.938770] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  404.938786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  404.944021] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  404.946450] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  404.947019] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  404.947081] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  404.947095] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  404.963892] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  404.963912] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  404.963946] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.047662] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  405.047955] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.065058] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.065129] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  405.065190] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  405.065304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.065362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.065417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.065464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.065511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.065556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.065602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.065645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.065686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.065828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.065879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.065923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.065966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.066015] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  405.066073] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.066130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.066182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.066234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.066312] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  405.066359] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  405.066405] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.066469] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.066539] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  405.066598] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.066644] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  405.066684] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  405.067211] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.069653] [drm:drm_mode_addfb2] [FB:68]
>[  405.092019] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  405.092048] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  405.092209] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  405.092266] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  405.092326] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  405.092389] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  405.092439] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  405.092492] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.092545] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  405.092594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.092643] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  405.092690] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  405.092797] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.092810] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  405.092859] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.092868] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  405.092915] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  405.092963] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  405.093009] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.093055] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.093099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.093156] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  405.093201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.093246] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.093291] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.093336] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  405.093394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  405.093456] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  405.093510] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  405.094684] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.094744] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.095048] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  405.095110] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.095164] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.095266] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  405.095308] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  405.095373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.095428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.095476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.095522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.095566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.095609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.095653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.095694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.095788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.095835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.095886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.095932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.095976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.096029] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.096088] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.096142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.096197] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.096261] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  405.096315] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  405.109618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.118448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.127173] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.135933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.144657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.153512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.162227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.170945] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.179666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.188591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.197311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.206000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.214597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.223176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.231704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.240230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.248713] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.257182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.261432] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  405.276820] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  405.276836] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  405.276901] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  405.277740] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  405.278454] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  405.281064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  405.281081] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  405.281096] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  405.281113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  405.286582] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  405.286597] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  405.291741] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  405.294217] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  405.294693] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.294904] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.294920] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.311724] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  405.311747] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  405.311782] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.395511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  405.395713] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.412908] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.412978] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  405.413039] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  405.413153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.413210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.413266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.413313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.413359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.413405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.413452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.413496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.413538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.413580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.413625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.413666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.413707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.413846] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  405.413913] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.413972] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.414024] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.414078] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.414158] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  405.414230] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  405.414303] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.414405] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.414514] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  405.414607] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.414681] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  405.414813] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  405.415298] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.417646] [drm:drm_mode_addfb2] [FB:68]
>[  405.482085] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  405.482114] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  405.482280] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  405.482340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.482403] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  405.482469] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  405.482520] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  405.482574] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.482629] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  405.482681] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.483351] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  405.483403] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  405.483453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.483463] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  405.483512] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.483520] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  405.483569] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  405.483617] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  405.483662] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.483708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.484265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.484323] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  405.484374] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.484421] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.484467] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.484512] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  405.484590] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  405.484654] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  405.484708] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  405.488785] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.488828] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.489133] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  405.489197] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.489254] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.489356] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  405.489398] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  405.489464] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  405.489585] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  405.489642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.489696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.490330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.490383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.490431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.490479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.490527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.490572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.490615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.490658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.490701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.491232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.491279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.491331] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.491388] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.491441] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.491492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.491556] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  405.491608] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  405.495258] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  405.495316] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  405.495366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  405.495418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  405.496511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  405.496572] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  405.496623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  405.497790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  405.497845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  405.497895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  405.498852] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  405.498931] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  405.500141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  405.502582] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  405.504132] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.504221] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  405.504273] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  405.504341] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  405.504465] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.504517] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.521119] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  405.521197] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  405.521312] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.604723] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  405.604980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.605053] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  405.605177] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.621873] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.621943] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  405.622004] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  405.622117] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  405.626466] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  405.626532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.626595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.626650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.626698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.626843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.626892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.626948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.626994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.627039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.627085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.627137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.627182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.627227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.627278] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  405.627340] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.627397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.627451] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.627505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.627588] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  405.627638] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  405.627689] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.627793] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.627867] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  405.627931] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.627981] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  405.628024] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  405.628480] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.630423] [drm:drm_mode_addfb2] [FB:68]
>[  405.693994] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  405.694011] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  405.694104] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  405.694136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.694169] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  405.694205] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  405.694234] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  405.694264] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.694293] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  405.694321] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.694348] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  405.694373] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  405.694397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.694402] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  405.694425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.694429] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  405.694454] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  405.694478] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  405.694502] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.694525] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.694548] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.694577] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  405.694601] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.694624] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.694647] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.694670] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  405.695063] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  405.695100] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  405.695130] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  405.697182] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.697205] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.697490] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  405.697524] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.697549] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.697589] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  405.697612] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  405.697648] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  405.697895] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  405.697928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.697960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.697990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.698017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.698043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.698068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.698094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.698118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.698142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.698177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.698196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.698215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.698233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.698256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.698280] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.698304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.698326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.698354] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  405.698377] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  405.714260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  405.714277] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  405.714291] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  405.714319] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  405.715027] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  405.715071] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  405.715084] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  405.715797] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  405.715811] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  405.715824] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  405.716471] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  405.716499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  405.717570] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  405.719865] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  405.720315] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  405.720338] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  405.720351] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  405.720371] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  405.720408] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  405.720422] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  405.737201] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  405.737221] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  405.737253] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.820710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  405.820875] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  405.820919] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  405.820991] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  405.837471] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  405.837542] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  405.837603] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  405.837716] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  405.838421] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  405.838479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.838535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.838587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.838634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.838679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.839354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.839407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.839454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.839500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.839543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.839592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.839634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.839675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.839723] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  405.840392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.840448] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.840500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.840550] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.840623] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  405.840670] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  405.841195] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  405.841261] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  405.841338] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  405.841398] [drm:intel_power_well_disable [i915]] disabling DC off
>[  405.841446] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  405.841486] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  405.842671] [drm:intel_power_well_disable [i915]] disabling always-on
>[  405.844381] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  405.893353] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  405.893376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  405.893399] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  405.893424] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  405.893442] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  405.893463] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.893484] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  405.893502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  405.893521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  405.893538] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  405.893555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.893559] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  405.893576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.893579] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  405.893595] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  405.893612] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  405.893628] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.893644] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.893660] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.893680] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  405.893716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.893732] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  405.893748] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  405.893764] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  405.893788] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  405.893807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  405.893829] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  405.893852] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  405.893871] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  405.893890] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  405.893908] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  405.893925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  405.893941] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  405.893957] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  405.893972] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  405.893975] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  405.893990] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  405.893992] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  405.894008] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  405.894023] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  405.894038] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  405.894053] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  405.894068] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  405.894087] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  405.894103] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  405.894118] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  405.894133] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  405.894148] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  405.894167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  405.894190] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  405.894209] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  405.894228] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  405.894245] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  405.894313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  405.894328] [drm:intel_power_well_enable [i915]] enabling DC off
>[  405.894621] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  405.894647] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  405.894664] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  405.894723] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  405.894746] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  405.894765] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  405.894780] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  405.894804] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  405.898811] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  405.898828] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  405.900825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  405.900851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  405.900871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  405.900890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  405.900908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  405.900926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  405.900944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  405.900962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  405.900978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  405.900994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  405.901010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  405.901026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  405.901042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  405.901061] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  405.901082] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  405.901102] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  405.901121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  405.901145] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  405.901165] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  405.913302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.921840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.930354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.938864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.947402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.955909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.964418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.972927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.981436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.989949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  405.998457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.006966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.015493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.024002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.032511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.041020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.049528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.058037] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  406.065713] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  406.081076] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  406.081091] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  406.081118] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  406.081941] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  406.083747] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  406.085726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  406.085741] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  406.085754] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  406.085769] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  406.090919] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  406.090934] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  406.096095] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  406.098575] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  406.099114] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  406.099157] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  406.099171] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  406.099223] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  406.099236] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  406.101924] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  406.101940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  406.101954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  406.101968] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  406.102627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  406.102640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  406.102653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  406.103301] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  406.103314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  406.103327] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  406.103975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  406.103989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  406.104949] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  406.107210] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  406.107741] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  406.107777] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  406.107791] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  406.107812] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  406.124580] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  406.124602] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  406.124640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  406.124682] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  406.124721] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  406.124757] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  406.124921] Console: switching to colour frame buffer device 240x75
>[  406.529840] Console: switching to colour dummy device 80x25
>[  406.529959] [IGT] kms_pipe_crc_basic: executing
>[  406.543193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  406.543242] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  406.551762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.560281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.568803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.577321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.585838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.594357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.602877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.611395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.619911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.628422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.636968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.645460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.653921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.662376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.670832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.679286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.687741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.715812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.724267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.732722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.741177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.749631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.758184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.766639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.775094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.783549] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.792005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.800461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.808916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.817370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.825823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.834277] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.834286] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  406.834289] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  406.834302] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  406.834347] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  406.835191] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  406.836714] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  406.836733] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  406.836760] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  406.836773] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  406.837565] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  406.838275] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  406.839060] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  406.839085] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  406.839087] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  406.839089] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  406.839090] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  406.839092] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  406.839094] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  406.839095] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  406.839097] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  406.839098] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  406.839100] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  406.839101] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  406.839103] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  406.839104] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  406.839119] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  406.839134] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  406.839163] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  406.839174] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  406.839188] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  406.840881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  406.840896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  406.842877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  406.842882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  406.844873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  406.844889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  406.846880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  406.846883] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  406.846886] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  406.846895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  406.846913] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  406.847362] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  406.847674] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  406.847689] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  406.847753] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  406.847798] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  406.848271] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  406.848582] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  406.849099] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  406.849101] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  406.849176] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  406.849177] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  406.849180] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  406.849181] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  406.849184] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  406.849185] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  406.849193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  406.849195] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  406.849197] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  406.849198] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  406.849199] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  406.849201] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  406.849202] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  406.849204] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  406.849205] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  406.849206] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  406.849208] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  406.849209] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  406.849210] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  406.849212] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  406.849213] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  406.849214] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  406.849216] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  406.849217] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  406.849219] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  406.849220] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  406.849221] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  406.849223] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  406.849224] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  406.849225] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  406.849227] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  406.849228] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  406.849230] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  406.849231] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  406.849232] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  406.849234] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  406.849235] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  406.849236] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  406.849238] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  406.849264] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  406.849279] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  406.850862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  406.850876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  406.852880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  406.852897] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  406.854873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  406.854889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  406.856903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  406.856906] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  406.856909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  406.865467] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  406.865489] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  406.873944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.882401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.890857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.899312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.907768] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.916224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.924680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.933149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.941605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.950061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.958516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.966970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.975424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.983879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  406.992334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.000790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.009246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.017704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.026159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.034615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.043071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.051526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.059982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.068451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.076906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.085361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.093818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.102272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.110728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.119252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.127706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.136161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  407.136169] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  407.136172] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  407.136362] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  407.136379] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  407.137286] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  407.138810] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  407.138825] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  407.138852] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  407.138865] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  407.139656] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  407.140367] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  407.141218] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  407.141243] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  407.141245] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  407.141247] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  407.141261] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  407.141262] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  407.141264] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  407.141265] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  407.141267] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  407.141268] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  407.141269] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  407.141271] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  407.141272] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  407.141273] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  407.141434] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  407.141449] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  407.141465] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  407.141616] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  407.141631] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  407.142153] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  407.142167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  407.143878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  407.143882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  407.145911] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  407.145926] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  407.148186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  407.148190] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  407.148192] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  407.148379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  407.148396] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  407.148850] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  407.149163] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  407.149179] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  407.149193] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  407.149207] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  407.149610] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  407.149957] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  407.150446] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  407.150447] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  407.150525] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  407.150526] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  407.150529] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  407.150530] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  407.150533] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  407.150534] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  407.150539] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  407.150541] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  407.150543] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  407.150544] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  407.150545] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  407.150547] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  407.150548] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  407.150549] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  407.150551] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  407.150552] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  407.150554] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  407.150555] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  407.150556] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  407.150558] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  407.150559] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  407.150560] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  407.150562] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  407.150563] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  407.150565] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  407.150566] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  407.150567] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  407.150569] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  407.150570] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  407.150571] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  407.150573] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  407.150574] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  407.150575] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  407.150577] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  407.150578] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  407.150579] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  407.150581] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  407.150582] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  407.150583] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  407.151255] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  407.151270] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  407.152877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  407.152892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  407.154919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  407.154922] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  407.156875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  407.156891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  407.158936] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  407.158939] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  407.158941] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  407.159148] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-B
>[  407.159850] [drm:drm_mode_addfb2] [FB:69]
>[  407.166239] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  407.166284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  407.166367] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  407.168166] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  407.168186] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  407.168203] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  407.168237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  407.168252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  407.168268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  407.168282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  407.168295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  407.168309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  407.168323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  407.168335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  407.168346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  407.168358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  407.168369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  407.168381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  407.168393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  407.168406] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  407.168421] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  407.168436] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.168450] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  407.168464] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  407.174610] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  407.174626] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  407.174650] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  407.174668] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  407.176867] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  407.176876] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  407.176934] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  407.176950] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  407.176968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  407.176987] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  407.177002] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  407.177019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.177034] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  407.177049] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  407.177064] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  407.177077] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  407.177090] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.177093] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  407.177106] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.177108] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  407.177121] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  407.177133] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  407.177146] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.177158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.177170] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.177185] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  407.177198] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.177211] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  407.177223] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  407.177235] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  407.177248] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  407.177269] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  407.177287] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  407.177301] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  407.177616] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  407.177630] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  407.177650] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  407.177669] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  407.178169] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  407.191985] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  407.192004] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  407.192023] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  407.196286] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  407.196305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  407.196322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  407.196337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  407.196351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  407.196364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  407.196378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  407.196391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  407.196404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  407.196417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  407.196429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  407.196443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  407.196456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  407.196468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  407.196482] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  407.196499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  407.196515] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.196530] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  407.196544] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  407.196562] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  407.196577] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  407.208960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.217432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.225900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.234368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.242838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.251306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.259874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.268353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.276832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.285310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.293790] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.302271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.310749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.319226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.327706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.336188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.344668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.353266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.361744] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.362918] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  407.376638] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  407.376656] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  407.376716] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  407.377597] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  407.378338] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  407.380134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  407.380191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  407.380230] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  407.380249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  407.386108] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  407.386124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  407.391314] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  407.393848] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  407.395008] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  407.411934] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  407.411987] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  407.412113] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  407.412197] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  407.412309] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.428560] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  407.495560] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  407.495885] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  407.512837] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  407.512903] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  407.513014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  407.513069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  407.513123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  407.513169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  407.513214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  407.513257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  407.513303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  407.513345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  407.513386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  407.513426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  407.513469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  407.513509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  407.513548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  407.513596] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  407.513651] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  407.513703] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.513888] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  407.513970] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  407.514079] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  407.514168] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  407.514233] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.514327] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.514419] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  407.514492] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.514557] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  407.514615] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  407.515134] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.517616] [drm:drm_mode_addfb2] [FB:69]
>[  407.537933] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  407.537958] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  407.538109] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  407.538164] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  407.538219] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  407.538279] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  407.538328] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  407.538379] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.538430] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  407.538477] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  407.538522] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  407.538565] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  407.538607] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.538614] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  407.538655] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.538661] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  407.538704] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  407.538820] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  407.538878] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.538936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.538991] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.539059] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  407.539116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.539192] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  407.539252] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  407.539313] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  407.539386] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  407.539466] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  407.539539] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  407.540909] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.540969] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.541293] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  407.541391] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.541451] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.541612] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  407.541669] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  407.541810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  407.541886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  407.541948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  407.542011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  407.542074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  407.542132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  407.542193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  407.542250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  407.542305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  407.542359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  407.542417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  407.542471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  407.542524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  407.542584] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  407.542658] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.542722] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  407.542822] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  407.542897] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  407.542958] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  407.556122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.564808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.573484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.582204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.590922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.599641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.608482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.617199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.625913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.634622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.643294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.651965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.660578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.669149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.677680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.686204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.714129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  407.715224] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  407.723414] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  407.723431] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  407.723481] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  407.724321] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  407.725117] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  407.727754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  407.727797] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  407.727816] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  407.727835] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  407.733204] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  407.733238] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  407.738383] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  407.740903] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  407.741398] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  407.758237] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  407.758258] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  407.758292] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.841857] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  407.841990] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  407.860822] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  407.860889] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  407.861000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  407.861056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  407.861111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  407.861158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  407.861203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  407.861248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  407.861295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  407.861337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  407.861379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  407.861420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  407.861462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  407.861502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  407.861543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  407.861591] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  407.861648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  407.861700] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.861854] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  407.861935] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  407.862050] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  407.862126] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  407.862201] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  407.862302] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  407.862405] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  407.862485] [drm:intel_power_well_disable [i915]] disabling DC off
>[  407.862557] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  407.862620] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  407.863153] [drm:intel_power_well_disable [i915]] disabling always-on
>[  407.865877] [drm:drm_mode_addfb2] [FB:69]
>[  407.931308] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  407.931333] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  407.931476] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  407.931526] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  407.931578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  407.931634] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  407.931677] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  407.931770] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  407.931845] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  407.931916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  407.931986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  407.932055] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  407.932120] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  407.932137] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  407.932197] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  407.932212] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  407.932278] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  407.932342] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  407.932406] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  407.932461] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  407.932526] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  407.932602] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  407.932669] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  407.932730] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  407.932828] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  407.932892] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  407.932986] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  407.933063] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  407.933134] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  407.935785] [drm:intel_power_well_enable [i915]] enabling always-on
>[  407.935822] [drm:intel_power_well_enable [i915]] enabling DC off
>[  407.936120] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  407.936173] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  407.936219] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  407.936311] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  407.936348] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  407.936406] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  407.936556] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  407.936606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  407.936655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  407.936700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  407.936845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  407.936918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  407.936989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  407.937058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  407.937126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  407.937188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  407.937254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  407.937316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  407.937382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  407.937446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  407.937514] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  407.937592] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  407.937666] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  407.937774] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  407.937851] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  407.937920] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  407.941429] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  407.941481] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  407.941528] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  407.941574] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  407.942667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  407.942715] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  407.942948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  407.943932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  407.944085] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  407.944128] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  407.945073] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  407.945123] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  407.946288] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  407.948632] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  407.949869] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  407.949947] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  407.949991] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  407.950050] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  407.966851] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  407.966920] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  407.967024] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  408.050310] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.050466] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.050534] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  408.050643] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.068647] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  408.068713] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  408.068903] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  408.069376] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  408.069428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  408.069478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  408.069524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  408.069565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  408.069606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  408.069645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  408.069686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  408.069786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  408.069829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  408.069867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  408.069913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  408.069951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  408.069990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  408.070033] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  408.070085] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  408.070135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  408.070181] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  408.070225] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  408.070288] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  408.070330] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  408.070373] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.070431] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.070491] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  408.070536] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.070577] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  408.070613] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  408.071097] [drm:intel_power_well_disable [i915]] disabling always-on
>[  408.072781] [drm:drm_mode_addfb2] [FB:69]
>[  408.133816] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  408.133842] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  408.133985] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  408.134036] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  408.134088] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  408.134145] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  408.134189] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  408.134236] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  408.134284] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  408.134328] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  408.134371] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  408.134411] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  408.134450] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  408.134457] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  408.134496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  408.134502] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  408.134542] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  408.134580] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  408.134617] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  408.134654] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  408.134690] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  408.134790] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  408.134833] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  408.134872] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  408.134910] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  408.134948] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  408.135011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  408.135064] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  408.135111] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  408.137534] [drm:intel_power_well_enable [i915]] enabling always-on
>[  408.137571] [drm:intel_power_well_enable [i915]] enabling DC off
>[  408.137922] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  408.137976] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  408.138013] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  408.138080] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  408.138116] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  408.138173] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  408.138594] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  408.138646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  408.138694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  408.138915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  408.138958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  408.138999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  408.139042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  408.139085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  408.139126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  408.139165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  408.139202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  408.139242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  408.139280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  408.139319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  408.139363] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  408.139411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  408.139457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  408.139502] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  408.139556] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  408.139602] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  408.143115] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  408.143169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  408.143216] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  408.143264] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  408.144375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  408.144423] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  408.144467] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  408.145626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  408.145673] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  408.145715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  408.146853] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  408.146901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  408.148238] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  408.150532] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  408.151498] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  408.151563] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  408.151595] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  408.151638] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  408.168393] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  408.168442] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  408.168517] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  408.252046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  408.252204] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  408.252278] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  408.252389] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  408.270500] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  408.270566] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  408.270677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  408.270971] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  408.271029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  408.271087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  408.271139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  408.271186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  408.271233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  408.271277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  408.271323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  408.271366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  408.271409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  408.271450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  408.271497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  408.271538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  408.271579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  408.271628] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  408.271683] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  408.271834] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  408.271891] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  408.271943] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  408.272018] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  408.272080] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  408.272138] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  408.272200] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  408.272270] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  408.272320] [drm:intel_power_well_disable [i915]] disabling DC off
>[  408.272365] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  408.272404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  408.272902] [drm:intel_power_well_disable [i915]] disabling always-on
>[  416.757200] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  416.757267] drm/i915: Resetting chip after gpu hang
>[  416.758435] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8729]/0 marked guilty (score 10) banned? no
>[  416.758472] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x398fe8
>[  416.758982] [drm] RC6 on
>[  416.773734] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  416.773824] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x398fe8, 0x0]
>[  416.774001] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  416.774148] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  416.774291] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  416.774432] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  416.774529] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  416.774543] [drm] GuC firmware load skipped
>[  416.775660] [drm:drm_mode_addfb2] [FB:69]
>[  416.788164] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  416.788172] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  416.788219] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  416.788234] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  416.788251] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  416.788268] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  416.788281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  416.788295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  416.788310] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  416.788323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  416.788336] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  416.788349] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  416.788360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  416.788363] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  416.788374] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  416.788376] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  416.788388] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  416.788399] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  416.788410] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  416.788421] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  416.788431] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  416.788445] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  416.788457] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  416.788468] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  416.788479] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  416.788489] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  416.788503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  416.788519] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  416.788532] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  416.789089] [drm:intel_power_well_enable [i915]] enabling always-on
>[  416.789101] [drm:intel_power_well_enable [i915]] enabling DC off
>[  416.789374] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  416.789392] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  416.789404] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  416.789426] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  416.789437] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  416.789457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  416.789473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  416.789487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  416.789501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  416.789515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  416.789527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  416.789540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  416.789553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  416.789564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  416.789576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  416.789589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  416.789601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  416.789613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  416.789626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  416.789642] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  416.789657] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  416.789671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  416.789710] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  416.789897] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  416.802254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.810732] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.819207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.827685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.836177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.844661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.853233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.861705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.870174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.878644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.887112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.895586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.904057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.912526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.920995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.929463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.937932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.946400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.954868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  416.955793] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  416.971390] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  416.971407] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  416.971442] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  416.972279] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  416.973006] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  416.974810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  416.974828] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  416.974843] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  416.974860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  416.980769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  416.980785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  416.985922] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  416.988384] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  416.988882] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  417.005739] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  417.005762] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.005797] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.089466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.089633] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  417.108163] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  417.108231] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  417.108348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.108406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.108461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.108509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.108555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.108600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.108647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.108690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.109182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.109229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.109279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.109324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.109369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.109421] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  417.109481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.109537] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.109590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.109641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.109717] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  417.110207] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  417.110254] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  417.110318] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  417.110395] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.110448] [drm:intel_power_well_disable [i915]] disabling DC off
>[  417.110494] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  417.110533] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  417.111552] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.113434] [drm:drm_mode_addfb2] [FB:69]
>[  417.136001] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  417.136030] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  417.136192] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  417.136249] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  417.136308] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  417.136370] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  417.136418] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  417.136472] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.136524] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  417.136573] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  417.136623] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  417.136669] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.136713] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.137421] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  417.137469] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.137477] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  417.137525] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  417.137571] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  417.137615] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  417.137659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.137701] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.138228] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  417.138276] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.138323] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  417.138368] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  417.138412] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  417.138466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.138526] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  417.138576] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  417.140187] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.140227] [drm:intel_power_well_enable [i915]] enabling DC off
>[  417.140530] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  417.140588] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  417.140640] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  417.141093] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  417.141137] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  417.141203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.141260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.141311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.141358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.141404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.141449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.141497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.141540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.141582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.141624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.141668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.141709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.142475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.142525] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.142580] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.142629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.142676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.143038] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  417.143087] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  417.156337] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.165065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.173789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.182509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.191232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.199952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.208672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.217607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.226325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.235051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.243772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.252417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.261005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.269546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.278055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.286543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.295016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.303483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.309420] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  417.324915] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  417.324932] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  417.324966] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  417.325794] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  417.326509] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  417.329109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  417.329125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.329141] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.329157] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.334615] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.334631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  417.339770] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.342244] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  417.342800] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  417.359643] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  417.359665] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.359794] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.443381] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.443549] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  417.460228] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  417.460298] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  417.460415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.460474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.460530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.460577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.460623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.460667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.460713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.461312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.461362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.461408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.461457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.461501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.461544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.461594] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  417.461653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.461708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.462248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.462301] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.462375] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  417.462422] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  417.462467] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  417.462530] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  417.462605] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.462658] [drm:intel_power_well_disable [i915]] disabling DC off
>[  417.462704] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  417.463214] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  417.463666] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.465836] [drm:drm_mode_addfb2] [FB:69]
>[  417.530346] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  417.530375] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  417.530538] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  417.530593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  417.530652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  417.530714] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  417.530827] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  417.530889] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.530946] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  417.530999] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  417.531051] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  417.531102] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  417.531148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.531162] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  417.531206] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.531217] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  417.531263] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  417.531309] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  417.531354] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  417.531400] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.531446] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.531503] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  417.531550] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.531596] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  417.531637] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  417.531680] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  417.531813] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  417.531878] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  417.531932] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  417.535457] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.535497] [drm:intel_power_well_enable [i915]] enabling DC off
>[  417.535848] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  417.535908] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  417.535952] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  417.536020] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  417.536060] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  417.536130] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  417.538377] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  417.538444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.538507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.538562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.538612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.538660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.538707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.539232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.539282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.539331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.539378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.539426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.539472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.539519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.539571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.539633] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.539689] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.540257] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.540323] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  417.540378] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  417.544064] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  417.544123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.544174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.544226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.545442] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  417.545494] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  417.545542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  417.546634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  417.546686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  417.546936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  417.547941] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.547994] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  417.549337] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.551742] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  417.553167] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  417.553249] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  417.553300] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  417.553422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  417.570168] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  417.570247] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.570363] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.653886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.654056] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  417.654132] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  417.654250] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  417.670641] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  417.670710] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  417.670904] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  417.671261] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  417.671320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.671378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.671431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.671478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.671523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.671567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.671614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.671656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.671698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.671823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.671878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.671927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.671969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.672019] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  417.672080] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.672135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.672186] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.672238] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.672313] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  417.672361] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  417.672407] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  417.672473] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  417.672544] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.672598] [drm:intel_power_well_disable [i915]] disabling DC off
>[  417.672645] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  417.672687] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  417.673228] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.675045] [drm:drm_mode_addfb2] [FB:69]
>[  417.747197] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  417.747209] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  417.747276] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  417.747297] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  417.747320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  417.747344] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  417.747363] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  417.747383] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.747404] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  417.747423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  417.747441] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  417.747459] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  417.747476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.747479] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  417.747496] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.747498] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  417.747515] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  417.747532] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  417.747548] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  417.747564] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.747580] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.747600] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  417.747617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.747633] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  417.747649] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  417.747664] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  417.747691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  417.748203] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  417.748223] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  417.749582] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.749598] [drm:intel_power_well_enable [i915]] enabling DC off
>[  417.749955] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  417.749980] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  417.749997] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  417.750038] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  417.750060] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  417.750085] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  417.752393] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  417.752415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.752436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.752454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.752469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.752485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.752500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.752515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.752529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.752543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.752557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.752570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.752584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.752598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.752614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.752632] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.752649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.752665] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.752685] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  417.753100] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  417.756479] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  417.756497] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  417.756512] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  417.756529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  417.757345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  417.757360] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  417.757374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  417.758013] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  417.758028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  417.758041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  417.758674] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  417.758689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  417.759695] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  417.761996] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  417.762456] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  417.762481] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  417.762495] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  417.762514] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  417.779284] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  417.779305] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.779339] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.863093] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  417.863276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  417.863346] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  417.863477] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  417.879622] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  417.879691] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  417.879878] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  417.880098] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  417.880155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.880210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.880263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.880309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.880355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.880400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.880446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.880490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.880532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.880573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.880620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.880659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.880699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.880820] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  417.880881] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.880939] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.880991] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.881042] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.881116] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  417.881165] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  417.881213] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  417.881279] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  417.881351] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  417.881506] [drm:intel_power_well_disable [i915]] disabling DC off
>[  417.881555] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  417.881596] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  417.882083] [drm:intel_power_well_disable [i915]] disabling always-on
>[  417.883369] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  417.932352] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  417.932378] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  417.932406] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  417.932434] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  417.932457] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  417.932481] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.932505] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  417.932527] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  417.932549] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  417.932569] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  417.932589] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.932594] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  417.932614] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.932617] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  417.932637] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  417.932657] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  417.932676] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  417.932695] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.932735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.932760] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  417.932779] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.932797] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  417.932816] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  417.932835] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  417.932862] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  417.932883] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  417.932907] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  417.932934] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  417.932956] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  417.932979] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  417.932999] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  417.933019] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  417.933038] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  417.933057] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  417.933075] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  417.933078] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  417.933096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  417.933098] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  417.933117] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  417.933135] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  417.933153] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  417.933171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  417.933189] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  417.933211] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  417.933229] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  417.933247] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  417.933265] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  417.933283] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  417.933305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  417.933332] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  417.933354] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  417.933376] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  417.933397] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  417.933475] [drm:intel_power_well_enable [i915]] enabling always-on
>[  417.933492] [drm:intel_power_well_enable [i915]] enabling DC off
>[  417.933793] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  417.933836] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  417.933863] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  417.933911] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  417.933932] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  417.933955] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  417.933972] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  417.934069] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  417.934259] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  417.934276] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  417.934303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  417.934326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  417.934346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  417.934366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  417.934385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  417.934404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  417.934424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  417.934442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  417.934459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  417.934477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  417.934494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  417.934511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  417.934528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  417.934548] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  417.934571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  417.934593] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  417.934614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  417.934640] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  417.934661] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  417.946303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.954816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.963326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.971835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.980345] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.988854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  417.997363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.005874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.014384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.022894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.031404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.039924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.048439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.056948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.065457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.074067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.082576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.091104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  418.098996] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  418.114099] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  418.114113] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  418.114203] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  418.115034] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  418.117410] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  418.119468] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  418.119483] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  418.119497] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.119512] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  418.124659] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  418.124674] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  418.129831] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  418.132290] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  418.132827] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  418.132892] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  418.132907] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  418.132957] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  418.132971] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  418.136215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  418.136231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  418.136245] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.136260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  418.136921] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  418.136935] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  418.136948] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  418.137595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  418.137609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  418.137622] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  418.138269] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  418.138283] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  418.139241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  418.141501] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  418.142033] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  418.142068] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  418.142082] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  418.142103] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  418.158873] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  418.158895] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  418.158933] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  418.158974] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  418.158994] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  418.159029] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  418.159158] Console: switching to colour frame buffer device 240x75
>[  418.587009] Console: switching to colour dummy device 80x25
>[  418.587124] [IGT] kms_pipe_crc_basic: executing
>[  418.597514] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  418.597605] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  418.606140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.614600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.623055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.631510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.639966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.648420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.656874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.665328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.673782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.682236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.690691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.717382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.725843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.734300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.742761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.751217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.759675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.768158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.776615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.785071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.793526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.801982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.810451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.818978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.827445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.835902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.844358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.852815] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.861271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.869727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.878184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.886640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.886649] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  418.886653] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  418.886666] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  418.886682] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  418.887546] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  418.889068] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  418.889084] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  418.889099] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  418.889113] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  418.889909] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  418.890614] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  418.891410] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  418.891433] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  418.891435] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  418.891436] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  418.891438] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  418.891439] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  418.891440] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  418.891442] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  418.891443] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  418.891445] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  418.891446] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  418.891447] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  418.891449] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  418.891450] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  418.891463] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  418.891478] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  418.891495] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  418.891505] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  418.891519] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  418.892865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.892879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.894878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  418.894882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  418.896882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.896898] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  418.898875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  418.898882] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.898885] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  418.898895] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  418.898912] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  418.899360] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  418.899673] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  418.899688] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  418.899751] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  418.899765] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  418.900179] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  418.900492] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  418.900991] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  418.900993] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  418.901070] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  418.901072] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  418.901074] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  418.901075] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  418.901078] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  418.901079] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  418.901085] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  418.901087] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  418.901089] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  418.901090] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  418.901092] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  418.901093] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.901095] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  418.901096] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  418.901097] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  418.901099] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  418.901100] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  418.901101] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  418.901103] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  418.901104] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  418.901105] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  418.901107] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  418.901108] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  418.901109] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  418.901111] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  418.901112] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  418.901114] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  418.901115] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  418.901116] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  418.901118] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  418.901119] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  418.901120] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  418.901122] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  418.901123] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  418.901125] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  418.901126] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  418.901127] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  418.901129] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  418.901130] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  418.901156] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  418.901170] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  418.902834] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  418.902848] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  418.904874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  418.904883] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  418.906882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  418.906933] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  418.908897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  418.908907] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  418.908914] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  418.937851] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  418.937898] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  418.946442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.954960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.963448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.971921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.980393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.988850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  418.997304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.005760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.014214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.022670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.031185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.039641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.048097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.056552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.065007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.073464] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.081919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.090374] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.098830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.107284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.115740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.124296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.132761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.141217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.149673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.158183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.166638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.175096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.183552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.192007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.200463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.208920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  419.208928] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  419.208931] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  419.209107] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  419.209122] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  419.210056] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  419.211589] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  419.211606] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  419.211620] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  419.211647] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  419.212443] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  419.213153] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  419.213934] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  419.213969] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  419.213971] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  419.213973] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  419.213974] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  419.213976] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  419.213977] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  419.213978] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  419.213980] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  419.213981] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  419.213983] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  419.213984] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  419.213985] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  419.213987] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  419.214145] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  419.214160] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  419.214177] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  419.214339] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  419.214354] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  419.215881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  419.215897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  419.217874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  419.217878] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  419.219878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  419.219894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  419.221879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  419.221883] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  419.221885] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  419.222062] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  419.222079] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  419.222542] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  419.223011] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  419.223028] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  419.223055] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  419.223068] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  419.223469] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  419.223820] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  419.224315] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  419.224317] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  419.224391] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  419.224392] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  419.224395] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  419.224396] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  419.224399] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  419.224399] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  419.224405] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  419.224407] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  419.224408] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  419.224410] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  419.224411] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  419.224413] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  419.224414] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  419.224415] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  419.224417] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  419.224418] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  419.224420] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  419.224421] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  419.224422] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  419.224424] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  419.224425] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  419.224426] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  419.224428] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  419.224429] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  419.224430] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  419.224432] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  419.224433] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  419.224434] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  419.224436] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  419.224437] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  419.224439] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  419.224440] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  419.224441] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  419.224443] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  419.224444] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  419.224445] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  419.224447] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  419.224448] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  419.224449] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  419.224615] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  419.224629] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  419.225664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  419.225678] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  419.225969] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  419.225973] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  419.227872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  419.227888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  419.229875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  419.229878] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  419.229881] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  419.230083] [IGT] kms_pipe_crc_basic: starting subtest hang-read-crc-pipe-C
>[  419.230601] [drm:drm_mode_addfb2] [FB:70]
>[  419.236962] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  419.237006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  419.237092] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  419.251584] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  419.251604] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  419.251622] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  419.251673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  419.251688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  419.251916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  419.251929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  419.251960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  419.251972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  419.251985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  419.251996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  419.252009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  419.252021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  419.252032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  419.252043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  419.252053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  419.252066] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  419.252081] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  419.252094] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.252107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  419.252120] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  419.258906] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  419.258920] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  419.258943] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  419.258959] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  419.259024] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  419.259062] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.259109] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  419.259128] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  419.259181] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  419.276155] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  419.276174] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  419.276207] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  419.276393] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  419.276408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  419.276424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  419.276439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  419.276451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  419.276464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  419.276476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  419.276489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  419.276501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  419.276512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  419.276524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  419.276537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  419.276549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  419.276560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  419.276573] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  419.276588] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  419.276603] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.276616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  419.276630] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  419.276650] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  419.276663] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  419.276676] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  419.277077] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  419.277099] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  419.277113] [drm:intel_power_well_disable [i915]] disabling DC off
>[  419.277127] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  419.277139] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  419.277554] [drm:intel_power_well_disable [i915]] disabling always-on
>[  419.277643] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  419.277651] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  419.277692] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  419.277905] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  419.277923] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  419.277940] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  419.277954] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  419.277969] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  419.277984] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  419.277998] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  419.278011] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  419.278024] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  419.278036] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  419.278039] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  419.278051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  419.278053] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  419.278066] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  419.278078] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  419.278090] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  419.278101] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  419.278113] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  419.278127] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  419.278139] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  419.278151] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  419.278162] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  419.278174] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  419.278188] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.278204] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  419.278218] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  419.278533] [drm:intel_power_well_enable [i915]] enabling always-on
>[  419.278544] [drm:intel_power_well_enable [i915]] enabling DC off
>[  419.279257] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  419.279535] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  419.279548] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  419.279570] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  419.279591] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  419.279614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  419.279630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  419.279645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  419.279658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  419.279671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  419.279683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  419.279877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  419.279891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  419.279904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  419.279917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  419.279930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  419.279942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  419.279954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  419.279968] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  419.279983] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.279997] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  419.280011] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  419.280028] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  419.280043] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  419.292798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.301281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.309778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.318258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.326737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.335212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.343696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.352196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.360680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.369233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.377715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.386194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.394672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.403286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.411782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.420260] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.428738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.437216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.444863] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  419.460409] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  419.460426] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  419.460483] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  419.461327] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  419.462115] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  419.465081] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  419.465115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  419.465130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.465146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  419.470313] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  419.470346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  419.475633] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  419.478099] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  419.478626] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  419.495490] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  419.495514] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  419.495552] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.579187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.579373] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  419.597832] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  419.597898] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  419.598009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  419.598065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  419.598119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  419.598164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  419.598209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  419.598253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  419.598299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  419.598341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  419.598383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  419.598424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  419.598469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  419.598510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  419.598550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  419.598597] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  419.598654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  419.598707] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.598841] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  419.598898] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  419.598975] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  419.599025] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  419.599070] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  419.599147] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  419.599244] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  419.599323] [drm:intel_power_well_disable [i915]] disabling DC off
>[  419.599395] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  419.599459] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  419.599989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  419.602207] [drm:drm_mode_addfb2] [FB:70]
>[  419.623748] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  419.623775] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  419.623933] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  419.623988] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  419.624047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  419.624108] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  419.624158] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  419.624210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  419.624262] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  419.624311] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  419.624358] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  419.624403] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  419.624446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  419.624454] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  419.624497] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  419.624504] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  419.624547] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  419.624589] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  419.624630] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  419.624671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  419.624711] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  419.624852] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  419.624917] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  419.624988] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  419.625056] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  419.625124] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  419.625201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.625286] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  419.625363] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  419.626638] [drm:intel_power_well_enable [i915]] enabling always-on
>[  419.626703] [drm:intel_power_well_enable [i915]] enabling DC off
>[  419.627082] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  419.627177] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  419.627241] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  419.627344] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  419.627411] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  419.627503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  419.627584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  419.627660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  419.627733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  419.627866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  419.627941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  419.628018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  419.628088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  419.628159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  419.628227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  419.628298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  419.628365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  419.628434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  419.628510] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  419.628592] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.628670] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  419.628782] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  419.628871] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  419.628946] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  419.642166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.650884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.659592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.668297] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.677000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.685705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.704806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.720947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.729651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.738384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.746953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.755522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.764035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.772522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.781001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.789481] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  419.793753] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  419.809416] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  419.809432] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  419.809482] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  419.810324] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  419.811124] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  419.813752] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  419.813772] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  419.813789] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  419.813808] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  419.819222] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  419.819239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  419.824391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  419.826860] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  419.827396] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  419.844250] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  419.844276] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  419.844317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.928004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  419.928189] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  419.946665] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  419.946732] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  419.946993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  419.947074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  419.947158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  419.947225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  419.947295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  419.947358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  419.947430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  419.947490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  419.947556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  419.947614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  419.947683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  419.947806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  419.947870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  419.947937] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  419.948021] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  419.948100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  419.948176] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  419.948250] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  419.948357] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  419.948429] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  419.948498] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  419.948597] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  419.948702] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  419.948820] [drm:intel_power_well_disable [i915]] disabling DC off
>[  419.948892] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  419.948950] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  419.949430] [drm:intel_power_well_disable [i915]] disabling always-on
>[  419.951378] [drm:drm_mode_addfb2] [FB:70]
>[  420.022207] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  420.022233] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  420.022389] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  420.022445] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  420.022505] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  420.022568] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  420.022617] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  420.022669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  420.022721] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  420.022856] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  420.022932] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  420.023004] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  420.023071] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  420.023092] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  420.023156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  420.023172] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  420.023244] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  420.023308] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  420.023379] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  420.023443] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  420.023510] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  420.023584] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  420.023650] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  420.023710] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  420.023816] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  420.023874] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  420.023975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  420.024059] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  420.024128] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  420.027023] [drm:intel_power_well_enable [i915]] enabling always-on
>[  420.027063] [drm:intel_power_well_enable [i915]] enabling DC off
>[  420.027365] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  420.027421] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  420.027472] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  420.027572] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  420.027613] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  420.027677] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  420.027885] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  420.027967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  420.028042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  420.028118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  420.028182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  420.028251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  420.028313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  420.028382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  420.028441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  420.028505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  420.028564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  420.028627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  420.028684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  420.028817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  420.028888] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  420.028973] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  420.029052] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  420.029130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  420.029218] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  420.029286] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  420.032898] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  420.032956] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  420.033007] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  420.033058] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  420.034309] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  420.034366] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  420.034416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  420.035595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  420.035649] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  420.035699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  420.036952] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  420.037008] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  420.038549] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  420.041011] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  420.042503] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  420.042583] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  420.042634] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  420.042700] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  420.059456] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  420.059533] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  420.059646] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  420.143004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  420.143158] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  420.143226] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  420.143335] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  420.161489] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  420.161555] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  420.161665] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  420.163895] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  420.163960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  420.164022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  420.164078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  420.164127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  420.164176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  420.164223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  420.164272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  420.164317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  420.164361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  420.164405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  420.164454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  420.164498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  420.164541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  420.164592] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  420.164651] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  420.164706] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  420.164895] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  420.164969] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  420.165080] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  420.165152] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  420.165225] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  420.165324] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  420.165427] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  420.165504] [drm:intel_power_well_disable [i915]] disabling DC off
>[  420.165576] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  420.165640] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  420.166172] [drm:intel_power_well_disable [i915]] disabling always-on
>[  420.169005] [drm:drm_mode_addfb2] [FB:70]
>[  420.230253] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  420.230273] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  420.230393] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  420.230434] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  420.230478] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  420.230525] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  420.230562] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  420.230601] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  420.230640] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  420.230677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  420.230712] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  420.230789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  420.230822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  420.230835] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  420.230868] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  420.230874] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  420.230909] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  420.230943] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  420.230978] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  420.231011] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  420.231047] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  420.231087] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  420.231123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  420.231155] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  420.231191] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  420.231223] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  420.231278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  420.231326] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  420.231368] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  420.233444] [drm:intel_power_well_enable [i915]] enabling always-on
>[  420.233465] [drm:intel_power_well_enable [i915]] enabling DC off
>[  420.233774] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  420.233809] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  420.233834] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  420.233892] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  420.233922] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  420.233959] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  420.234138] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  420.234169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  420.234198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  420.234225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  420.234250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  420.234274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  420.234297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  420.234322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  420.234344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  420.234366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  420.234388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  420.234410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  420.234432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  420.234454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  420.234479] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  420.234508] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  420.234535] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  420.234561] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  420.234593] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  420.234620] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  420.237945] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  420.237975] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  420.238002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  420.238030] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  420.238754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  420.238775] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  420.238797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  420.239507] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  420.239532] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  420.239554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  420.240447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  420.240471] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  420.241474] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  420.243751] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  420.244299] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  420.244339] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  420.244358] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  420.244383] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  420.261127] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  420.261156] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  420.261200] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  420.344742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  420.344966] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  420.345034] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  420.345140] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  420.361571] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  420.361639] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  420.361869] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  420.364048] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  420.364113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  420.364174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  420.364230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  420.364280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  420.364327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  420.364374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  420.364423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  420.364468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  420.364512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  420.364557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  420.364607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  420.364650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  420.364692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  420.364856] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  420.364939] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  420.365017] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  420.365089] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  420.365162] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  420.365272] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  420.365344] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  420.365419] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  420.365518] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  420.365622] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  420.365701] [drm:intel_power_well_disable [i915]] disabling DC off
>[  420.365952] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  420.366018] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  420.366497] [drm:intel_power_well_disable [i915]] disabling always-on
>[  428.725260] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  428.725293] drm/i915: Resetting chip after gpu hang
>[  428.726205] [drm:i915_gem_reset [i915]] context kms_pipe_crc_ba[8734]/0 marked guilty (score 10) banned? no
>[  428.726221] [drm:i915_gem_reset [i915]] resetting render ring to restart from tail of request 0x39903b
>[  428.726562] [drm] RC6 on
>[  428.739046] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  428.739070] [drm:gen8_init_common_ring [i915]] Restarting render ring from requests [0x39903b, 0x0]
>[  428.739172] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  428.739232] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  428.739283] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  428.739333] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  428.739368] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  428.739373] [drm] GuC firmware load skipped
>[  428.740082] [drm:drm_mode_addfb2] [FB:70]
>[  428.747263] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  428.747271] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  428.747326] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  428.747343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  428.747362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  428.747382] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  428.747398] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  428.747414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  428.747431] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  428.747446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  428.747461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  428.747475] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  428.747489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  428.747492] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  428.747505] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  428.747507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  428.747521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  428.747535] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  428.747547] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  428.747560] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  428.747573] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  428.747589] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  428.747602] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  428.747615] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  428.747627] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  428.747640] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  428.747655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  428.747674] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  428.747716] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  428.748163] [drm:intel_power_well_enable [i915]] enabling always-on
>[  428.748182] [drm:intel_power_well_enable [i915]] enabling DC off
>[  428.748464] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  428.748492] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  428.748513] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  428.748549] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  428.748568] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  428.748596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  428.748620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  428.748642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  428.748662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  428.748683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  428.748755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  428.748796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  428.748815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  428.748837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  428.748857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  428.748879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  428.748898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  428.748919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  428.748940] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  428.748967] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  428.748991] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  428.749013] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  428.749041] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  428.749062] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  428.761350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.769831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.778312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.786792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.795276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.803755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.812246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.820719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.829188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.837659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.846129] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.854599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.863082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.871551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.880019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.888487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.896959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.905530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.913999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  428.914938] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  428.930426] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  428.930442] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  428.930596] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  428.931430] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  428.932153] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.933932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  428.933949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  428.933964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  428.933981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  428.939911] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  428.939927] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  428.945067] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  428.947543] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  428.948112] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  428.964987] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  428.965010] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  428.965046] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.048898] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.049095] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  429.067280] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  429.067350] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  429.067468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.067526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.067582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.067629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.067674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.067718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.067915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.067980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.068042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.068103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.068168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.068229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.068289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.068355] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  429.068442] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.068518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.068586] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.068658] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.068841] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  429.069026] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  429.069098] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  429.069196] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  429.069304] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  429.069382] [drm:intel_power_well_disable [i915]] disabling DC off
>[  429.069454] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  429.069513] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  429.070044] [drm:intel_power_well_disable [i915]] disabling always-on
>[  429.072469] [drm:drm_mode_addfb2] [FB:70]
>[  429.100323] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  429.100351] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  429.100513] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  429.100570] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  429.100630] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  429.100693] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  429.101122] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  429.101180] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  429.101235] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  429.101286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  429.101335] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  429.101382] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  429.101426] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  429.101436] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  429.101479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  429.101488] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  429.101532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  429.101577] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  429.101620] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  429.101661] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.101704] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  429.102334] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  429.102383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  429.102431] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  429.102477] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  429.102520] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  429.102573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.102631] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  429.102681] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  429.104299] [drm:intel_power_well_enable [i915]] enabling always-on
>[  429.104339] [drm:intel_power_well_enable [i915]] enabling DC off
>[  429.104641] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  429.104699] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  429.104964] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  429.105087] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  429.105132] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  429.105199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.105258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.105310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.105359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.105407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.105453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.105501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.105544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.105589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.105631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.105677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.106277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.106323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.106375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.106432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.106485] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.106535] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.106597] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  429.106648] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  429.119983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.128715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.137489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.146215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.154936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.163657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.172513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.181233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.189950] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.198582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.207148] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.215673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.224270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.232755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.241226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.249695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.258175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.266644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.274466] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  429.288452] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  429.288468] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  429.288544] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  429.289380] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  429.290087] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  429.291868] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  429.291885] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  429.291900] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  429.291917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  429.297838] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  429.297853] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  429.303017] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  429.305445] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  429.305980] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  429.322823] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  429.322845] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  429.322881] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.406667] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.407091] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  429.423909] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  429.423978] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  429.424095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.424152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.424207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.424254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.424298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.424342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.424389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.424432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.424474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.424516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.424561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.424601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.424642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.424690] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  429.425588] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.425645] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.425698] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.425968] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.426042] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  429.426089] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  429.426133] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  429.426197] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  429.426272] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  429.426323] [drm:intel_power_well_disable [i915]] disabling DC off
>[  429.426369] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  429.426409] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  429.427594] [drm:intel_power_well_disable [i915]] disabling always-on
>[  429.429588] [drm:drm_mode_addfb2] [FB:70]
>[  429.503034] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  429.503062] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  429.503226] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  429.503284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  429.503343] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  429.503407] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  429.503458] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  429.503510] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  429.503563] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  429.503612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  429.503659] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  429.503705] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  429.504429] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  429.504438] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  429.504488] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  429.504496] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  429.504545] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  429.504591] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  429.504637] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  429.504681] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.505262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  429.505316] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  429.505365] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  429.505413] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  429.505457] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  429.505500] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  429.505571] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  429.505632] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  429.505682] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  429.509912] [drm:intel_power_well_enable [i915]] enabling always-on
>[  429.509952] [drm:intel_power_well_enable [i915]] enabling DC off
>[  429.510254] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  429.510313] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  429.510363] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  429.510469] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  429.510513] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  429.510578] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  429.510698] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  429.511286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.511342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.511396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.511443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.511491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.511535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.511582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.511625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.511669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.511712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.512271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.512316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.512361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.512411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.512467] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.512518] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.512568] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.512628] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  429.512679] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  429.516570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  429.516610] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  429.516645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  429.516681] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  429.517693] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  429.517848] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  429.517884] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  429.518653] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  429.518688] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  429.518923] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  429.519690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  429.519870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  429.521099] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  429.523429] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  429.524484] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  429.524547] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  429.524582] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  429.524629] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  429.541398] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  429.541453] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  429.541534] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.625130] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.625310] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  429.625381] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  429.625506] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  429.641671] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  429.641815] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  429.641940] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  429.642210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  429.642269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.642326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.642376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.642422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.642465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.642508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.642554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.642596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.642637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.642678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.642802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.642847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.642890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.642937] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  429.642993] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.643047] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.643097] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.643146] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.643225] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  429.643273] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  429.643321] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  429.643387] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  429.643460] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  429.643512] [drm:intel_power_well_disable [i915]] disabling DC off
>[  429.643560] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  429.643601] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  429.644084] [drm:intel_power_well_disable [i915]] disabling always-on
>[  429.645866] [drm:drm_mode_addfb2] [FB:70]
>[  429.699717] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  429.699730] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  429.699804] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  429.699828] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  429.699854] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  429.699881] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  429.699902] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  429.699925] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  429.699948] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  429.699968] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  429.699989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  429.700008] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  429.700027] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  429.700030] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  429.700048] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  429.700051] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  429.700070] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  429.700088] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  429.700107] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  429.700125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.700142] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  429.700164] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  429.700182] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  429.700200] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  429.700218] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  429.700235] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  429.700265] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  429.700291] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  429.700312] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  429.701795] [drm:intel_power_well_enable [i915]] enabling always-on
>[  429.701810] [drm:intel_power_well_enable [i915]] enabling DC off
>[  429.702113] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  429.702136] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  429.702152] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  429.702182] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  429.702196] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  429.702220] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  429.702423] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  429.702443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.702463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.702482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.702499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.702515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.702532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.702548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.702564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.702579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.702593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.702608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.702623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.702637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.702654] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.702673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.702692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.702748] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.702781] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  429.702806] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  429.714972] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  429.714988] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  429.715002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  429.715029] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  429.715688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  429.715801] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  429.715833] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  429.716501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  429.716518] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  429.716533] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  429.717176] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  429.717192] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  429.718146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  429.720409] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  429.720925] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  429.720958] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  429.720971] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  429.720991] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  429.737756] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  429.737777] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  429.737810] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.821429] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  429.821589] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  429.821659] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  429.822185] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  429.838889] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  429.838957] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  429.839073] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  429.839277] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  429.839334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.839391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.839443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.839490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.839536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.839582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.839628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.839672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.839715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.840993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.841054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.841104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.841152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.841204] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  429.841263] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.841317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.841367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.841415] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.841490] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  429.841537] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  429.841583] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  429.841647] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  429.841719] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  429.842950] [drm:intel_power_well_disable [i915]] disabling DC off
>[  429.843027] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  429.843091] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  429.843571] [drm:intel_power_well_disable [i915]] disabling always-on
>[  429.845386] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  429.894268] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  429.894292] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  429.894315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  429.894340] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  429.894358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  429.894379] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  429.894399] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  429.894419] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  429.894437] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  429.894454] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  429.894471] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  429.894475] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  429.894491] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  429.894494] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  429.894511] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  429.894527] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  429.894543] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  429.894559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.894574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  429.894594] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  429.894610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  429.894625] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  429.894641] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  429.894656] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  429.894680] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  429.894718] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  429.894738] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  429.894760] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  429.894779] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  429.894798] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  429.894816] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  429.894833] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  429.894849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  429.894865] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  429.894880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  429.894883] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  429.894898] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  429.894901] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  429.894916] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  429.894932] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  429.894947] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  429.894962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  429.894977] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  429.894997] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  429.895013] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  429.895028] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  429.895044] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  429.895059] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  429.895079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  429.895102] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  429.895121] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  429.895140] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  429.895157] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  429.895225] [drm:intel_power_well_enable [i915]] enabling always-on
>[  429.895240] [drm:intel_power_well_enable [i915]] enabling DC off
>[  429.895516] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  429.895543] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  429.895560] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  429.895599] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  429.895622] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  429.895647] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  429.895662] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  429.895685] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  429.897894] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  429.897910] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  429.897936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  429.897959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  429.897978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  429.897996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  429.898013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  429.898030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  429.898048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  429.898065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  429.898082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  429.898098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  429.898114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  429.898130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  429.898146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  429.898164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  429.898186] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  429.898205] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  429.898224] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  429.898247] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  429.898266] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  429.910304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.918818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.927328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.935838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.944348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.952856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.961369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.969879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.978406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.986915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  429.995425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.003935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.012443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.020952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.029459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.037969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.046495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.055018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  430.062693] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  430.078072] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  430.078088] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  430.078114] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  430.078937] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  430.080725] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  430.082930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  430.082947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  430.082962] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  430.082979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  430.088409] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  430.088423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  430.093573] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  430.096069] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  430.096594] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  430.096634] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  430.096649] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  430.096714] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  430.096727] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  430.099969] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  430.099985] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  430.099999] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  430.100014] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  430.100667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  430.100681] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  430.100726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  430.101375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  430.101389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  430.101402] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  430.102059] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  430.102073] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  430.103032] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  430.105295] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  430.105823] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  430.105859] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  430.105873] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  430.105894] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  430.122673] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  430.122696] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  430.122751] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  430.122792] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  430.122812] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  430.122848] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  430.122979] Console: switching to colour frame buffer device 240x75
>[  430.546239] Console: switching to colour dummy device 80x25
>[  430.546542] [IGT] kms_pipe_crc_basic: executing
>[  430.563479] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  430.563556] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  430.572116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.580577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.589035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.597493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.605949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.614404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.622858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.631313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.639780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.648234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.656699] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.665176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.673633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.682091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.690545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.719113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.727570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.736026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.744481] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.752938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.761488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.769944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.778398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.786855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.795309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.803765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.812219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.820675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.829155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.837610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.846077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.854533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.854541] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  430.854545] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  430.854558] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  430.854574] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  430.855412] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  430.856944] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  430.856961] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  430.856988] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  430.857001] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  430.857808] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  430.858514] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  430.859300] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  430.859343] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  430.859345] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  430.859346] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  430.859348] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  430.859349] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  430.859350] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  430.859352] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  430.859353] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  430.859355] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  430.859356] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  430.859357] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  430.859359] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  430.859360] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  430.859375] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  430.859390] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  430.859406] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  430.859413] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  430.859427] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  430.860885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  430.860900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  430.862872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  430.862876] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  430.864877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  430.864893] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  430.866877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  430.866885] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  430.866887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  430.866897] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  430.866915] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  430.867364] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  430.867676] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  430.867692] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  430.867722] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  430.867736] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  430.868245] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  430.868557] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  430.869067] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  430.869069] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  430.869143] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  430.869144] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  430.869147] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  430.869148] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  430.869151] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  430.869152] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  430.869158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  430.869160] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  430.869161] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  430.869163] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  430.869164] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  430.869166] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  430.869167] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  430.869168] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  430.869170] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  430.869171] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  430.869173] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  430.869174] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  430.869175] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  430.869177] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  430.869178] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  430.869180] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  430.869181] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  430.869183] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  430.869184] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  430.869185] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  430.869187] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  430.869188] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  430.869190] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  430.869191] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  430.869192] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  430.869194] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  430.869195] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  430.869196] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  430.869198] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  430.869199] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  430.869200] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  430.869202] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  430.869203] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  430.869230] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  430.869245] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  430.870883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  430.870899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  430.872917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  430.872921] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  430.874881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  430.874896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  430.876896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  430.876900] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  430.876902] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  430.885782] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  430.885799] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  430.894251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.902708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.911164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.919622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.928080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.936536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.944991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.953447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.961900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.970356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.978811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.987266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  430.995722] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.004176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.012631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.021088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.029543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.037999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.046454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.055004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.063460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.071918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.080372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.088828] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.097284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.105740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.114194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.122648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.131104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.139560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.148016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.156471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  431.156479] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  431.156484] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  431.156672] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  431.156686] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  431.157658] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  431.159182] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  431.159227] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  431.159241] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  431.159254] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  431.160051] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  431.160780] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  431.161554] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  431.161591] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  431.161593] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  431.161594] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  431.161596] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  431.161597] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  431.161599] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  431.161600] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  431.161601] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  431.161603] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  431.161604] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  431.161605] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  431.161607] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  431.161608] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  431.162084] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  431.162099] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  431.162116] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  431.162267] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  431.162281] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  431.163883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  431.163899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  431.165901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  431.165905] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  431.168151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  431.168167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  431.170419] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  431.170423] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  431.170425] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  431.170613] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  431.170630] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  431.171145] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  431.171464] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  431.171480] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  431.171495] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  431.171521] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  431.171931] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  431.172243] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  431.172861] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  431.172879] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  431.172968] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  431.172969] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  431.172972] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  431.172973] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  431.172976] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  431.172977] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  431.172983] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  431.172985] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  431.172986] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  431.172988] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  431.172989] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  431.172991] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  431.172992] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  431.172994] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  431.172995] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  431.172996] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  431.172998] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  431.172999] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  431.173001] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  431.173002] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  431.173003] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  431.173005] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  431.173006] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  431.173008] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  431.173009] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  431.173010] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  431.173012] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  431.173013] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  431.173015] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  431.173016] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  431.173017] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  431.173019] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  431.173020] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  431.173022] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  431.173023] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  431.173024] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  431.173026] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  431.173027] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  431.173029] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  431.173209] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  431.173225] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  431.174833] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  431.174847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  431.176826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  431.176829] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  431.178834] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  431.178847] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  431.180836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  431.180839] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  431.180841] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  431.181051] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A
>[  431.181276] [drm:drm_mode_addfb2] [FB:68]
>[  431.187542] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  431.187551] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  431.214334] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  431.214489] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  431.214549] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  431.214598] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  431.214968] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  431.231861] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  431.231918] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  431.231971] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  431.232035] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  431.232093] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  431.232193] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  431.241174] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  431.241243] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  431.241355] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  431.243567] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  431.243637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  431.243700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  431.244082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  431.244139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  431.244192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  431.244243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  431.244295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  431.244343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  431.244390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  431.244436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  431.244487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  431.244533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  431.244577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  431.244629] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  431.244687] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  431.245389] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  431.245445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  431.245498] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  431.245580] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  431.245635] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  431.258881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.267582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.276270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.284954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.293637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.302539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.311220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.319907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.328629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.337402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.346084] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.354742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.363319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.371854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.380360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.388849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.397326] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.405795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.411928] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  431.426101] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  431.426121] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  431.426205] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  431.427616] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  431.430216] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  431.431570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  431.431586] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  431.431600] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  431.431627] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  431.436767] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  431.436783] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  431.441921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  431.444376] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  431.444972] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  431.445000] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  431.445014] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  431.478516] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  431.478537] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  431.478570] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  431.478585] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  431.478598] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  431.478621] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  431.478636] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  431.479498] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  431.562450] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  431.562654] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  431.579030] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  431.579100] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  431.579163] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  431.579277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  431.579334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  431.579389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  431.579438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  431.579484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  431.579530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  431.579577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  431.579620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  431.579663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  431.579705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  431.579893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  431.579959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  431.580019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  431.580086] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  431.580172] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  431.580247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  431.580320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  431.580394] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  431.580505] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  431.580578] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  431.580648] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  431.580818] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  431.580930] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  431.581023] [drm:intel_power_well_disable [i915]] disabling DC off
>[  431.581098] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  431.581163] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  431.581643] [drm:intel_power_well_disable [i915]] disabling always-on
>[  431.584068] [drm:drm_mode_addfb2] [FB:68]
>[  431.606349] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  431.606378] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  431.606543] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  431.606602] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  431.606665] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  431.606731] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  431.606854] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  431.606921] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  431.606981] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  431.607036] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  431.607095] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  431.607151] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  431.607199] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  431.607216] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  431.607262] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  431.607272] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  431.607327] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  431.607375] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  431.607425] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  431.607472] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  431.607518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  431.607581] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  431.607628] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  431.607676] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  431.607737] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  431.607783] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  431.607844] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  431.607905] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  431.607960] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  431.609146] [drm:intel_power_well_enable [i915]] enabling always-on
>[  431.609193] [drm:intel_power_well_enable [i915]] enabling DC off
>[  431.609499] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  431.609566] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  431.609624] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  431.609723] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  431.609821] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  431.609903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  431.609962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  431.610018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  431.610064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  431.610118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  431.610164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  431.610218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  431.610261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  431.610307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  431.610349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  431.610396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  431.610438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  431.610483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  431.610530] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  431.610587] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  431.610638] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  431.610692] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  431.610791] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  431.610849] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  431.624157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.632856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.641538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.650221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.658906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.667588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.676272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.684957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.693643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.719238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.727876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.736437] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.744966] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.753483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.761965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.770436] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  431.776571] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  431.791399] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  431.791416] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  431.791450] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  431.792274] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  431.794048] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  431.796223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  431.796240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  431.796255] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  431.796272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  431.801695] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  431.801720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  431.806859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  431.809322] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  431.809874] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  431.809920] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  431.809936] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  431.826740] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  431.826763] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  431.826799] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  431.927268] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  431.927472] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  431.944040] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  431.944109] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  431.944172] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  431.944285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  431.944341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  431.944397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  431.944446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  431.944492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  431.944536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  431.944583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  431.944626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  431.944668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  431.944710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  431.944842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  431.944890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  431.944941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  431.944991] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  431.945050] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  431.945107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  431.945160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  431.945212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  431.945287] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  431.945333] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  431.945380] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  431.945445] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  431.945516] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  431.945576] [drm:intel_power_well_disable [i915]] disabling DC off
>[  431.945624] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  431.945665] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  431.946168] [drm:intel_power_well_disable [i915]] disabling always-on
>[  431.948302] [drm:drm_mode_addfb2] [FB:68]
>[  432.011514] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  432.011540] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  432.011687] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  432.011887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  432.011946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  432.012006] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  432.012052] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  432.012102] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  432.012152] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  432.012199] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  432.012244] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  432.012290] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  432.012332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  432.012343] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  432.012382] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  432.012390] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  432.012432] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  432.012473] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  432.012514] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  432.012553] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  432.012593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  432.012641] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  432.012683] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  432.012942] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  432.012983] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  432.013024] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  432.013089] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  432.013144] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  432.013190] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  432.016446] [drm:intel_power_well_enable [i915]] enabling always-on
>[  432.016482] [drm:intel_power_well_enable [i915]] enabling DC off
>[  432.016886] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  432.017302] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  432.017351] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  432.017437] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  432.017475] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  432.017534] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  432.017866] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  432.017920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  432.017973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  432.018020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  432.018065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  432.018107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  432.018150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  432.018192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  432.018233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  432.018273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  432.018312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  432.018351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  432.018391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  432.018428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  432.018473] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  432.018523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.018571] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  432.018616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  432.018670] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  432.018717] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  432.022433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  432.022486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  432.022532] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  432.022580] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  432.023494] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  432.023539] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  432.023581] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  432.024615] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  432.024660] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  432.024702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  432.025839] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  432.025888] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  432.027232] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  432.029611] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  432.030969] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  432.031045] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  432.031090] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  432.031150] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  432.031536] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  432.031584] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  432.047953] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  432.048023] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  432.048125] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.148331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  432.148514] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  432.148587] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  432.148706] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  432.164828] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  432.164898] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  432.164959] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  432.165072] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  432.165280] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  432.165335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  432.165390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  432.165442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  432.165490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  432.165534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  432.165577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  432.165623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  432.165665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  432.165705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  432.165815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  432.165869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  432.165910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  432.165949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  432.165997] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  432.166055] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  432.166109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.166159] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  432.166209] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  432.166287] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  432.166334] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  432.166381] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  432.166447] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  432.166519] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  432.166579] [drm:intel_power_well_disable [i915]] disabling DC off
>[  432.166625] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  432.166666] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  432.167153] [drm:intel_power_well_disable [i915]] disabling always-on
>[  432.169188] [drm:drm_mode_addfb2] [FB:68]
>[  432.242328] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  432.242344] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  432.242437] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  432.242469] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  432.242502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  432.242538] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  432.242566] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  432.242597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  432.242627] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  432.242654] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  432.242682] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  432.243029] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  432.243057] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  432.243063] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  432.243088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  432.243092] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  432.243119] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  432.243145] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  432.243170] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  432.243195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  432.243219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  432.243249] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  432.243275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  432.243299] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  432.243322] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  432.243347] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  432.243388] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  432.243423] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  432.243451] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  432.245724] [drm:intel_power_well_enable [i915]] enabling always-on
>[  432.245748] [drm:intel_power_well_enable [i915]] enabling DC off
>[  432.246032] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  432.246067] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  432.246093] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  432.246154] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  432.246183] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  432.246218] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  432.248571] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  432.248608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  432.248643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  432.248671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  432.248698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  432.249004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  432.249034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  432.249062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  432.249087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  432.249112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  432.249136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  432.249160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  432.249183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  432.249206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  432.249234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  432.249265] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.249293] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  432.249320] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  432.249355] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  432.249382] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  432.252774] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  432.252805] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  432.252832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  432.252860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  432.253583] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  432.253609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  432.253633] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  432.254577] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  432.254604] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  432.254630] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  432.255404] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  432.255433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  432.256483] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  432.258810] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  432.259558] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  432.259602] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  432.259629] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  432.259666] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  432.259962] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  432.259992] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  432.276426] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  432.276468] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  432.276531] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.376977] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  432.377148] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  432.377227] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  432.377344] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  432.393892] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  432.393962] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  432.394023] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  432.394136] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  432.394342] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  432.394398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  432.394454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  432.394506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  432.394552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  432.394597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  432.394640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  432.394686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  432.394830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  432.394873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  432.394918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  432.394968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  432.395011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  432.395055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  432.395105] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  432.395164] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  432.395218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.395270] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  432.395321] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  432.395401] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  432.395449] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  432.395497] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  432.395562] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  432.395634] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  432.395694] [drm:intel_power_well_disable [i915]] disabling DC off
>[  432.395776] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  432.395818] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  432.396270] [drm:intel_power_well_disable [i915]] disabling always-on
>[  432.397437] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  432.446401] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  432.446429] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  432.446457] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  432.446485] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  432.446508] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  432.446533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  432.446558] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  432.446581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  432.446603] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  432.446625] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  432.446645] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  432.446650] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  432.446671] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  432.446674] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  432.446694] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  432.446737] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  432.446757] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  432.446776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  432.446795] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  432.446819] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  432.446839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  432.446859] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  432.446878] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  432.446897] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  432.446925] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  432.446947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  432.446971] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  432.446998] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  432.447020] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  432.447042] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  432.447063] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  432.447083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  432.447103] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  432.447122] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  432.447141] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  432.447144] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  432.447162] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  432.447165] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  432.447184] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  432.447202] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  432.447221] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  432.447239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  432.447257] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  432.447280] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  432.447298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  432.447317] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  432.447335] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  432.447352] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  432.447376] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  432.447403] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  432.447425] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  432.447448] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  432.447469] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  432.447547] [drm:intel_power_well_enable [i915]] enabling always-on
>[  432.447565] [drm:intel_power_well_enable [i915]] enabling DC off
>[  432.447861] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  432.447892] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  432.447912] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  432.447944] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  432.447964] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  432.447987] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  432.448006] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  432.448035] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  432.448232] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  432.448250] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  432.448277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  432.448302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  432.448324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  432.448345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  432.448366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  432.448386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  432.448407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  432.448426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  432.448445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  432.448465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  432.448483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  432.448502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  432.448520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  432.448541] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  432.448566] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.448589] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  432.448611] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  432.448638] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  432.448661] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  432.460606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.469122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.477633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.486143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.494652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.503160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.511670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.520210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.528720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.537230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.545739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.554248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.562756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.571266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.579777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.588286] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.596794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.605302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.613810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  432.614903] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  432.629518] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  432.629534] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  432.629559] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  432.630383] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  432.632195] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  432.634087] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  432.634102] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  432.634116] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  432.634130] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  432.639290] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  432.639305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  432.644464] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  432.646950] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  432.647556] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  432.647625] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  432.647639] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  432.647687] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  432.647713] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  432.650970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  432.650986] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  432.651000] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  432.651015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  432.651673] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  432.651687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  432.651726] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  432.652375] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  432.652388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  432.652401] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  432.653056] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  432.653070] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  432.654039] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  432.656304] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  432.656819] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  432.656849] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  432.656862] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  432.656882] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  432.673656] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  432.673676] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  432.673727] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  432.673766] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  432.673785] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  432.673818] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  432.674044] Console: switching to colour frame buffer device 240x75
>[  433.094075] Console: switching to colour dummy device 80x25
>[  433.094190] [IGT] kms_pipe_crc_basic: executing
>[  433.105030] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  433.105056] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  433.113514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.121974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.130430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.138886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.147339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.155794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.164247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.172704] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.181158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.189612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.198080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.206536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.214991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.223446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.231928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.240394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.248849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.257303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.265760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.274214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.282669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.291171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.299627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.308082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.316538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.324993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.333448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.341904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.350357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.358813] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.367276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.375736] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.375747] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  433.375751] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  433.375768] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  433.375785] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  433.376616] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  433.378140] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  433.378156] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  433.378170] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  433.378185] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  433.378982] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  433.379688] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  433.380492] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  433.380529] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  433.380532] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  433.380533] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  433.380535] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  433.380536] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  433.380538] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  433.380539] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  433.380540] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  433.380542] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  433.380543] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  433.380545] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  433.380546] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  433.380547] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  433.380561] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  433.380578] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  433.380594] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  433.380601] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  433.380615] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  433.382879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  433.382895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  433.384903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  433.384907] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  433.387170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  433.387186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  433.389448] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  433.389452] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  433.389454] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  433.389464] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  433.389481] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  433.389934] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  433.390248] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  433.390264] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  433.390279] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  433.390293] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  433.390698] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  433.391039] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  433.391539] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  433.391541] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  433.391621] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  433.391622] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  433.391625] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  433.391626] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  433.391629] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  433.391630] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  433.391635] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  433.391637] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  433.391638] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  433.391640] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  433.391641] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  433.391643] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  433.391644] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  433.391645] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  433.391647] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  433.391648] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  433.391650] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  433.391651] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  433.391652] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  433.391654] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  433.391655] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  433.391656] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  433.391658] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  433.391660] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  433.391661] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  433.391662] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  433.391664] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  433.391665] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  433.391666] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  433.391668] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  433.391669] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  433.391671] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  433.391672] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  433.391673] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  433.391675] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  433.391676] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  433.391677] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  433.391679] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  433.391680] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  433.391771] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  433.391800] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  433.393863] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  433.393877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  433.395897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  433.395900] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  433.398161] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  433.398176] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  433.400432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  433.400435] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  433.400438] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  433.409023] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  433.409040] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  433.417495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.425955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.434411] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.442868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.451324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.459779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.468236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.476694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.485163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.493619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.502075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.510531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.518986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.527452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.535908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.544426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.552881] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.561335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.569793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.578250] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.586706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.595160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.603615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.612082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.620536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.628993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.637449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.645904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.654361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.662817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.671276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.679733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  433.679741] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  433.679744] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  433.679919] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  433.679934] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  433.680907] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  433.682430] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  433.682447] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  433.682461] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  433.682475] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  433.683322] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  433.684035] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  433.684828] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  433.684853] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  433.684855] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  433.684870] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  433.684871] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  433.684872] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  433.684874] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  433.684875] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  433.684877] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  433.684878] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  433.684879] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  433.684881] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  433.684882] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  433.684883] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  433.685046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  433.685061] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  433.685078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  433.685234] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  433.685249] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  433.686889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  433.686905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  433.688875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  433.688879] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  433.690889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  433.690905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  433.693163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  433.693166] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  433.693168] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  433.693363] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  433.693380] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  433.714068] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  433.714386] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  433.714403] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  433.714418] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  433.714432] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  433.714847] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  433.715163] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  433.715672] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  433.715674] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  433.715802] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  433.715804] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  433.715807] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  433.715808] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  433.715811] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  433.715812] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  433.715818] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  433.715820] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  433.715822] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  433.715823] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  433.715825] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  433.715826] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  433.715829] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  433.715830] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  433.715832] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  433.715833] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  433.715835] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  433.715836] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  433.715838] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  433.715839] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  433.715840] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  433.715842] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  433.715843] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  433.715845] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  433.715846] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  433.715848] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  433.715849] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  433.715851] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  433.715853] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  433.715854] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  433.715855] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  433.715857] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  433.715858] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  433.715860] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  433.715861] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  433.715863] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  433.715864] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  433.715866] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  433.715867] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  433.716053] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  433.716069] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  433.717885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  433.717901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  433.719879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  433.719883] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  433.721888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  433.721904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  433.724164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  433.724167] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  433.724170] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  433.724377] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-A-frame-sequence
>[  433.724587] [drm:drm_mode_addfb2] [FB:69]
>[  433.730930] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  433.730939] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  433.748718] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  433.748777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  433.748803] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  433.748818] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  433.748889] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  433.766185] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  433.766209] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  433.766230] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  433.766256] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  433.766278] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  433.766325] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  433.774940] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  433.774966] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  433.775009] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  433.775238] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  433.775259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  433.775280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  433.775297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  433.775313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  433.775329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  433.775345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  433.775361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  433.775376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  433.775391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  433.775406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  433.775422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  433.775437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  433.775451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  433.775467] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  433.775487] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  433.775505] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  433.775523] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  433.775539] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  433.775570] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  433.775588] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  433.788333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.796867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.805428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.813965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.822577] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.831114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.839668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.848289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.856822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.865350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.873874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.882369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.890861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.899330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.907798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.916266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.924734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.933202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  433.941025] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  433.955901] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  433.955920] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  433.955952] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  433.956785] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  433.959023] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  433.960471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  433.960486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  433.960500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  433.960515] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  433.965682] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  433.965709] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  433.970861] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  433.973329] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  433.973884] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  433.973925] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  433.973939] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  434.007609] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  434.007687] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.007886] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.007948] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  434.008001] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  434.008084] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  434.008141] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  434.009405] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  434.091354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  434.091557] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  434.108028] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  434.108099] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  434.108161] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  434.108275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.108333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.108388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.108436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.108481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.108525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.108571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.108614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.108655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.108697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.108837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.108885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.108933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.108987] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  434.109047] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.109107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.109161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.109216] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.109294] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  434.109343] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  434.109390] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  434.109456] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  434.109530] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.109590] [drm:intel_power_well_disable [i915]] disabling DC off
>[  434.109639] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  434.109681] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  434.110181] [drm:intel_power_well_disable [i915]] disabling always-on
>[  434.112069] [drm:drm_mode_addfb2] [FB:69]
>[  434.134343] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  434.134371] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  434.134538] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  434.134597] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  434.134660] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  434.134726] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  434.134874] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  434.134959] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  434.135046] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  434.135125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  434.135206] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  434.135283] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  434.135359] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  434.135380] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  434.135447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  434.135462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  434.135532] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  434.135602] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  434.135673] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  434.135783] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  434.135850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  434.135929] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  434.135992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  434.136059] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  434.136127] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  434.136194] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  434.136267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  434.136352] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  434.136431] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  434.137764] [drm:intel_power_well_enable [i915]] enabling always-on
>[  434.137804] [drm:intel_power_well_enable [i915]] enabling DC off
>[  434.138107] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  434.138168] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  434.138220] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  434.138317] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  434.138360] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  434.138427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.138483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.138534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.138581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.138626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.138670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.138716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.138850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.138917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.138992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.139064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.139134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.139202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.139280] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.139364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.139445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.139522] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.139611] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  434.139687] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  434.152957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.161652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.170453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.179157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.187848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.196534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.205223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.213911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.222644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.231507] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.240204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.248802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.257358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.265877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.274375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.282857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.291329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.299799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.306035] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  434.320208] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  434.320228] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  434.320270] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  434.321825] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  434.324078] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  434.325523] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  434.325538] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  434.325552] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  434.325567] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  434.330720] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  434.330736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  434.335876] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  434.338355] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  434.338941] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  434.338989] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  434.339004] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  434.355794] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  434.355816] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.355852] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.456380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  434.456583] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  434.473106] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  434.473177] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  434.473238] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  434.473353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.473408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.473464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.473512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.473558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.473602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.473647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.473689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.473858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.473922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.473988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.474047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.474111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.474177] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  434.474262] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.474341] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.474419] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.474494] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.474602] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  434.474672] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  434.474789] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  434.474888] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  434.474993] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.475083] [drm:intel_power_well_disable [i915]] disabling DC off
>[  434.475266] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  434.475323] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  434.475849] [drm:intel_power_well_disable [i915]] disabling always-on
>[  434.479872] [drm:drm_mode_addfb2] [FB:69]
>[  434.541278] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  434.541304] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  434.541454] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  434.541507] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  434.541565] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  434.541626] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  434.541675] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  434.541725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  434.541837] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  434.541885] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  434.541936] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  434.541979] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  434.542022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  434.542032] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  434.542073] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  434.542080] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  434.542125] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  434.542166] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  434.542208] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  434.542249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  434.542291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  434.542341] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  434.542382] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  434.542422] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  434.542463] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  434.542501] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  434.542568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  434.542624] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  434.542672] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  434.545910] [drm:intel_power_well_enable [i915]] enabling always-on
>[  434.545949] [drm:intel_power_well_enable [i915]] enabling DC off
>[  434.546249] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  434.546306] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  434.546349] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  434.546442] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  434.546489] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  434.546549] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  434.548912] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  434.548971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.549027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.549075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.549118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.549161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.549203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.549246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.549285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.549325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.549364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.549403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.549442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.549480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.549525] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.549577] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.549625] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.549671] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.549727] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  434.550300] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  434.553895] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  434.553947] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  434.553993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  434.554042] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  434.555104] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  434.555150] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  434.555196] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  434.556284] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  434.556331] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  434.556374] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  434.557442] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  434.557491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  434.558905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  434.561287] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  434.562656] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  434.562920] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  434.562968] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  434.563029] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  434.563142] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  434.563189] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  434.579674] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  434.580039] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.580147] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.680094] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  434.680270] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  434.680343] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  434.680463] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  434.714553] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  434.714622] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  434.714682] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  434.714896] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  434.715296] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  434.715353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.715408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.715459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.715505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.715550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.715595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.715641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.715683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.715791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.715832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.715886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.715934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.715976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.716025] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  434.716087] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.716142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.716193] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.716244] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.716319] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  434.716367] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  434.716414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  434.716478] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  434.716549] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.716611] [drm:intel_power_well_disable [i915]] disabling DC off
>[  434.716658] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  434.716700] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  434.717202] [drm:intel_power_well_disable [i915]] disabling always-on
>[  434.718982] [drm:drm_mode_addfb2] [FB:69]
>[  434.769922] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  434.769936] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  434.770008] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  434.770032] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  434.770059] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  434.770086] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  434.770120] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  434.770140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  434.770159] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  434.770176] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  434.770194] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  434.770210] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  434.770225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  434.770228] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  434.770244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  434.770246] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  434.770262] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  434.770278] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  434.770293] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  434.770307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  434.770322] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  434.770341] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  434.770356] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  434.770370] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  434.770385] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  434.770399] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  434.770425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  434.770447] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  434.770465] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  434.772251] [drm:intel_power_well_enable [i915]] enabling always-on
>[  434.772265] [drm:intel_power_well_enable [i915]] enabling DC off
>[  434.772540] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  434.772563] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  434.772578] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  434.772617] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  434.772639] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  434.772663] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  434.774820] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  434.774845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.774869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.774889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.774907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.774924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.774941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.774959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.774974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.774990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.775006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.775021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.775036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.775052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.775070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.775091] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.775110] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.775129] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.775152] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  434.775171] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  434.777950] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  434.777968] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  434.777983] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  434.778000] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  434.778659] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  434.778674] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  434.778688] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  434.779499] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  434.779515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  434.779531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  434.780309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  434.780325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  434.781291] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  434.783563] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  434.784130] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  434.784167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  434.784182] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  434.784205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  434.784356] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  434.784373] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  434.801027] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  434.801052] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.801090] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.901519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  434.901691] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  434.901869] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  434.902001] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  434.918564] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  434.918633] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  434.918696] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  434.918890] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  434.919378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  434.919436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.919491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.919544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.919593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.919638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.919682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.919798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.919842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.919889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.919931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.919981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.920022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.920064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.920111] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  434.920168] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.920221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.920271] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.920321] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.920393] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  434.920439] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  434.920485] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  434.920549] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  434.920618] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  434.920677] [drm:intel_power_well_disable [i915]] disabling DC off
>[  434.920760] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  434.920800] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  434.921252] [drm:intel_power_well_disable [i915]] disabling always-on
>[  434.922422] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  434.971421] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  434.971448] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  434.971476] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  434.971505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  434.971527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  434.971550] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  434.971575] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  434.971597] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  434.971619] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  434.971639] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  434.971660] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  434.971664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  434.971684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  434.971720] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  434.971743] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  434.971764] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  434.971784] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  434.971803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  434.971821] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  434.971845] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  434.971864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  434.971883] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  434.971902] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  434.971920] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  434.971949] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  434.971970] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  434.971995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  434.972022] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  434.972044] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  434.972066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  434.972088] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  434.972108] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  434.972127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  434.972146] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  434.972165] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  434.972168] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  434.972186] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  434.972189] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  434.972208] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  434.972226] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  434.972245] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  434.972263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  434.972280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  434.972303] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  434.972321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  434.972339] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  434.972357] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  434.972375] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  434.972398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  434.972425] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  434.972448] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  434.972471] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  434.972491] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  434.972571] [drm:intel_power_well_enable [i915]] enabling always-on
>[  434.972589] [drm:intel_power_well_enable [i915]] enabling DC off
>[  434.972884] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  434.972915] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  434.972935] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  434.972986] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  434.973013] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  434.973039] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  434.973057] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  434.973084] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  434.973275] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  434.973292] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  434.973319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  434.973343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  434.973364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  434.973384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  434.973403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  434.973422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  434.973442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  434.973461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  434.973479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  434.973497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  434.973514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  434.973532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  434.973548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  434.973569] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  434.973592] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  434.973614] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  434.973635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  434.973660] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  434.973682] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  434.986307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  434.994820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.003331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.011840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.020351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.028864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.037376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.045885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.054410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.062920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.071430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.079940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.088449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.096958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.105467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.113975] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.122583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.131107] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.139616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  435.140714] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  435.155343] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  435.155361] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  435.155394] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  435.156384] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  435.159019] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  435.160364] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  435.160379] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  435.160392] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  435.160407] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  435.165556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  435.165571] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  435.170721] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  435.173175] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  435.173709] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  435.173785] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  435.173800] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  435.173852] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  435.173866] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  435.177108] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  435.177124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  435.177138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  435.177153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  435.177813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  435.177827] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  435.177840] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  435.178515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  435.178529] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  435.178542] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  435.179191] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  435.179205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  435.180162] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  435.182424] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  435.182952] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  435.182975] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  435.182989] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  435.183009] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  435.199782] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  435.199804] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  435.199843] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  435.199885] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  435.199905] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  435.199940] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  435.200108] Console: switching to colour frame buffer device 240x75
>[  435.638788] Console: switching to colour dummy device 80x25
>[  435.638894] [IGT] kms_pipe_crc_basic: executing
>[  435.653580] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  435.653677] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  435.662356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.670822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.679281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.687741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.715737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.724195] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.732654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.741113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.749570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.758118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.766575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.775033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.783491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.791948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.800404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.808862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.817318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.825773] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.834230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.842688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.851158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.859615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.868071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.876529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.884986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.893443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.901899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.910357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.918814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.927270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.935727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.944183] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.944192] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  435.944195] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  435.944209] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  435.944225] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  435.945061] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  435.946593] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  435.946609] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  435.946623] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  435.946638] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  435.947440] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  435.948153] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  435.948935] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  435.948971] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  435.948974] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  435.948975] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  435.948977] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  435.948978] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  435.948980] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  435.948981] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  435.948982] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  435.948984] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  435.948985] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  435.948986] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  435.948988] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  435.948989] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  435.949003] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  435.949017] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  435.949034] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  435.949041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  435.949056] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  435.950889] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  435.950905] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  435.952877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  435.952880] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  435.954880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  435.954896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  435.956877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  435.956881] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  435.956884] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  435.956893] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  435.956911] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  435.957363] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  435.957675] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  435.957691] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  435.957763] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  435.957796] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  435.958344] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  435.958658] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  435.959164] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  435.959166] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  435.959240] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  435.959242] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  435.959245] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  435.959246] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  435.959249] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  435.959250] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  435.959256] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  435.959257] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  435.959259] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  435.959260] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  435.959261] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  435.959263] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  435.959264] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  435.959266] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  435.959267] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  435.959268] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  435.959270] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  435.959271] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  435.959273] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  435.959274] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  435.959275] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  435.959277] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  435.959278] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  435.959279] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  435.959281] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  435.959282] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  435.959283] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  435.959285] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  435.959286] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  435.959288] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  435.959289] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  435.959290] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  435.959292] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  435.959293] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  435.959294] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  435.959296] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  435.959297] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  435.959298] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  435.959300] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  435.959326] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  435.959341] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  435.960863] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  435.960877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  435.962880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  435.962883] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  435.964878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  435.964894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  435.966884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  435.966887] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  435.966889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  435.975677] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  435.975693] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  435.984180] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  435.992641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.001100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.009556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.018013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.026469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.034927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.043396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.051853] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.060307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.068762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.077219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.085676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.094179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.102637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.111094] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.119550] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.128006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.136484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.144942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.153398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.161854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.170309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.178767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.187225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.195683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.204152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.212609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.221079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.229536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.237994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.246450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  436.246459] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  436.246462] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  436.246645] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  436.246659] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  436.247716] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  436.249257] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  436.249274] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  436.249289] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  436.249302] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  436.250100] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  436.250811] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  436.251584] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  436.251610] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  436.251612] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  436.251614] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  436.251615] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  436.251617] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  436.251631] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  436.251632] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  436.251634] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  436.251635] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  436.251636] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  436.251638] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  436.251639] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  436.251640] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  436.252167] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  436.252182] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  436.252195] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  436.252345] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  436.252359] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  436.253886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  436.253902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  436.255937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  436.255941] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  436.258190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  436.258205] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  436.260463] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  436.260467] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  436.260469] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  436.260656] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  436.260673] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  436.261259] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  436.261573] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  436.261589] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  436.261603] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  436.261617] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  436.262038] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  436.262350] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  436.262904] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  436.262906] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  436.262981] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  436.262982] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  436.262985] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  436.262986] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  436.262989] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  436.262990] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  436.262996] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  436.262998] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  436.262999] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  436.263001] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  436.263002] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  436.263003] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  436.263005] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  436.263006] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  436.263008] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  436.263009] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  436.263010] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  436.263012] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  436.263013] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  436.263014] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  436.263016] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  436.263017] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  436.263018] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  436.263020] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  436.263021] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  436.263023] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  436.263024] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  436.263025] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  436.263027] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  436.263028] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  436.263029] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  436.263031] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  436.263032] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  436.263033] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  436.263035] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  436.263036] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  436.263037] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  436.263039] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  436.263040] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  436.263214] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  436.263229] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  436.264879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  436.264894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  436.266880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  436.266883] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  436.268878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  436.268894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  436.270882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  436.270885] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  436.270888] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  436.271099] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B
>[  436.271335] [drm:drm_mode_addfb2] [FB:70]
>[  436.277661] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  436.277821] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  436.277911] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  436.292740] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  436.292781] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  436.292797] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  436.292831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  436.292846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  436.292861] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  436.292876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  436.292888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  436.292899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  436.292911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  436.292922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  436.292933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  436.292943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  436.292954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  436.292965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  436.292975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  436.292988] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  436.293002] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  436.293016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  436.293028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  436.293041] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  436.299825] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  436.299842] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  436.299868] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  436.299886] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  436.299978] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  436.299988] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  436.300036] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  436.300052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  436.300069] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  436.300088] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  436.300102] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  436.300117] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  436.300133] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  436.300147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  436.300161] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  436.300175] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  436.300187] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  436.300190] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  436.300202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  436.300204] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  436.300217] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  436.300230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  436.300242] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  436.300254] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  436.300266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  436.300281] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  436.300294] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  436.300307] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  436.300319] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  436.300331] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  436.300343] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  436.300363] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  436.300394] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  436.300409] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  436.300857] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  436.300878] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  436.300906] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  436.300935] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  436.300983] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  436.318017] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  436.318040] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  436.318063] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  436.320259] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  436.320283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  436.320304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  436.320322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  436.320338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  436.320353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  436.320369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  436.320385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  436.320399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  436.320413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  436.320427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  436.320443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  436.320457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  436.320471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  436.320487] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  436.320507] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  436.320524] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  436.320541] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  436.320558] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  436.320578] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  436.320595] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  436.333383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.341902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.350418] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.358935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.367513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.376028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.384543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.393061] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.401575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.410111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.418626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.427121] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.435603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.444088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.452557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.461027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.469495] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.477964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.486434] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.487512] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  436.502276] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  436.502295] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  436.502327] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  436.503259] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  436.505046] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  436.506934] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  436.506950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  436.506964] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  436.506991] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  436.512148] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  436.512163] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  436.517323] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  436.519805] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  436.520253] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  436.537130] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  436.537145] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  436.537183] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  436.537207] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  436.537240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  436.553828] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  436.637724] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  436.637983] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  436.655005] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  436.655073] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  436.655188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  436.655245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  436.655302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  436.655349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  436.655394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  436.655438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  436.655485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  436.655529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  436.655572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  436.655614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  436.655659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  436.655700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  436.655869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  436.655939] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  436.656029] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  436.656105] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  436.656179] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  436.656253] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  436.656364] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  436.656432] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  436.656503] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  436.656604] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  436.656711] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  436.656858] [drm:intel_power_well_disable [i915]] disabling DC off
>[  436.656935] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  436.657000] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  436.657482] [drm:intel_power_well_disable [i915]] disabling always-on
>[  436.660370] [drm:drm_mode_addfb2] [FB:70]
>[  436.690683] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  436.690735] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  436.690901] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  436.690961] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  436.691024] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  436.691090] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  436.691142] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  436.691199] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  436.691255] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  436.691307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  436.691359] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  436.691408] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  436.691454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  436.691462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  436.691507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  436.691513] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  436.691559] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  436.691604] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  436.691648] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  436.691691] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  436.691797] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  436.691857] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  436.691906] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  436.691952] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  436.691997] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  436.692043] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  436.692099] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  436.692163] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  436.692218] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  436.693390] [drm:intel_power_well_enable [i915]] enabling always-on
>[  436.693435] [drm:intel_power_well_enable [i915]] enabling DC off
>[  436.693833] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  436.714400] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  436.714448] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  436.714539] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  436.714577] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  436.714637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  436.714688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  436.714782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  436.714829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  436.714874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  436.714915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  436.714959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  436.715001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  436.715041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  436.715080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  436.715121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  436.715160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  436.715198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  436.715244] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  436.715294] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  436.715341] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  436.715386] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  436.715443] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  436.715490] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  436.728714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.737448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.746141] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.754849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.763538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.772225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.780919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.789651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.798480] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.807194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.815792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.824344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.832865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.841359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.849840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.858309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.866777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.875243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  436.881437] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  436.895969] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  436.895987] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  436.896022] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  436.896992] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  436.899626] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  436.900966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  436.900981] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  436.900995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  436.901011] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  436.906150] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  436.906166] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  436.911304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  436.913732] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  436.914207] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  436.931072] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  436.931094] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  436.931131] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.031648] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  437.031954] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  437.049049] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  437.049119] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  437.049235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  437.049291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  437.049347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  437.049394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  437.049439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  437.049483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  437.049529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  437.049571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  437.049613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  437.049654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  437.049697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  437.049837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  437.049886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  437.049941] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  437.050002] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  437.050057] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.050109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  437.050162] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  437.050250] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  437.050321] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  437.050391] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  437.050494] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  437.050600] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  437.050684] [drm:intel_power_well_disable [i915]] disabling DC off
>[  437.050834] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  437.050897] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  437.051378] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.053763] [drm:drm_mode_addfb2] [FB:70]
>[  437.116342] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  437.116368] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  437.116516] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  437.116568] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  437.116621] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  437.116676] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  437.116721] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  437.117298] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  437.117348] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  437.117393] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  437.117437] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  437.117478] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  437.117518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.117525] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  437.117565] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.117571] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  437.117610] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  437.117650] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  437.117688] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  437.118282] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.118324] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  437.118376] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  437.118420] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.118464] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  437.118505] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  437.118545] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  437.118611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  437.118665] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  437.118712] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  437.122379] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.122415] [drm:intel_power_well_enable [i915]] enabling DC off
>[  437.122713] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  437.123285] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  437.123327] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  437.123429] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  437.123469] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  437.123528] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  437.123726] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  437.124185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  437.124237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  437.124284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  437.124328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  437.124369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  437.124408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  437.124450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  437.124489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  437.124527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  437.124563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  437.124600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  437.124636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  437.124672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  437.124714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  437.125369] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.125417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  437.125461] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  437.125518] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  437.125563] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  437.129162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  437.129215] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  437.129261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  437.129309] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  437.130304] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  437.130352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  437.130395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  437.131282] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  437.131328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  437.131372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  437.132297] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  437.132351] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  437.133538] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  437.135997] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  437.137434] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  437.137519] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  437.137565] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  437.137626] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  437.154405] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  437.154475] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  437.154581] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.254718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  437.254939] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  437.255009] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.255125] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  437.271346] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  437.271413] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  437.271525] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  437.271686] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  437.272313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  437.272372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  437.272427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  437.272476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  437.272523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  437.272568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  437.272616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  437.272660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  437.272703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  437.273346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  437.273402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  437.273448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  437.273492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  437.273541] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  437.273599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  437.273653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.273705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  437.273814] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  437.273891] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  437.273963] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  437.274039] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  437.274143] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  437.274250] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  437.274316] [drm:intel_power_well_disable [i915]] disabling DC off
>[  437.274363] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  437.274404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  437.274898] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.277395] [drm:drm_mode_addfb2] [FB:70]
>[  437.341252] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  437.341273] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  437.341392] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  437.341433] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  437.341477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  437.341523] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  437.341560] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  437.341600] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  437.341639] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  437.341675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  437.341711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  437.341792] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  437.341829] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.341838] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  437.341872] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.341883] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  437.341917] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  437.341952] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  437.341987] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  437.342024] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.342058] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  437.342100] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  437.342136] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.342171] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  437.342206] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  437.342239] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  437.342296] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  437.342342] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  437.342380] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  437.344700] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.344736] [drm:intel_power_well_enable [i915]] enabling DC off
>[  437.345020] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  437.345054] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  437.345082] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  437.345138] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  437.345164] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  437.345199] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  437.347484] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  437.347521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  437.347557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  437.347586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  437.347613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  437.347639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  437.347664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  437.347689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  437.347767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  437.347795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  437.347825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  437.347856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  437.347885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  437.347915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  437.347947] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  437.347982] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.348016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  437.348047] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  437.348085] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  437.348117] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  437.351464] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  437.351489] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  437.351511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  437.351533] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  437.352295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  437.352317] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  437.352338] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  437.353073] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  437.353095] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  437.353115] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  437.353845] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  437.353868] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  437.354873] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  437.357149] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  437.357686] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  437.357754] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  437.357776] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  437.357804] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  437.374612] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  437.374641] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  437.374685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.475150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  437.475325] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  437.475400] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  437.475519] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  437.491550] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  437.491620] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  437.491734] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  437.492855] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  437.492915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  437.492980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  437.493034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  437.493085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  437.493132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  437.493181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  437.493228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  437.493273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  437.493315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  437.493359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  437.493407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  437.493449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  437.493489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  437.493538] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  437.493594] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  437.493647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.493697] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  437.493799] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  437.493887] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  437.493937] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  437.493989] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  437.494057] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  437.494130] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  437.494187] [drm:intel_power_well_disable [i915]] disabling DC off
>[  437.494235] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  437.494276] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  437.494781] [drm:intel_power_well_disable [i915]] disabling always-on
>[  437.496387] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  437.529386] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  437.529411] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  437.529439] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  437.529468] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  437.529491] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  437.529515] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  437.529539] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  437.529562] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  437.529584] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  437.529605] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  437.529625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.529629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  437.529649] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.529652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  437.529672] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  437.529691] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  437.529731] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  437.529751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.529769] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  437.529793] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  437.529813] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.529831] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  437.529850] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  437.529868] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  437.529896] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  437.529918] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  437.529942] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  437.529969] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  437.529992] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  437.530014] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  437.530036] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  437.530056] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  437.530075] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  437.530094] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  437.530112] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  437.530115] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  437.530133] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  437.530136] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  437.530155] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  437.530173] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  437.530192] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  437.530209] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  437.530227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  437.530249] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  437.530268] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  437.530286] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  437.530304] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  437.530321] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  437.530345] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  437.530372] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  437.530394] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  437.530417] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  437.530438] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  437.530512] [drm:intel_power_well_enable [i915]] enabling always-on
>[  437.530530] [drm:intel_power_well_enable [i915]] enabling DC off
>[  437.530824] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  437.530855] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  437.530875] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  437.530914] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  437.530933] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  437.530957] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  437.530976] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  437.531004] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  437.532900] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  437.532919] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  437.532951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  437.532977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  437.532999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  437.533021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  437.533041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  437.533061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  437.533082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  437.533101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  437.533120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  437.533139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  437.533158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  437.533176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  437.533194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  437.533216] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  437.533241] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.533264] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  437.533286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  437.533314] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  437.533336] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  437.545467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.553981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.562492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.570999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.579512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.588021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.596530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.605039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.613548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.622057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.630566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.639077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.647587] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.656098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.664606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.673114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.681693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.690220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  437.713965] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  437.713983] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  437.714118] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  437.715229] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  437.716664] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  437.717451] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  437.717465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  437.717479] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  437.717493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  437.724206] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  437.724261] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  437.730026] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  437.732550] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  437.733099] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  437.733137] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  437.733150] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  437.733200] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  437.733212] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  437.736458] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  437.736473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  437.736487] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  437.736514] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  437.737179] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  437.737192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  437.737205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  437.737867] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  437.737881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  437.737906] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  437.738565] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  437.738579] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  437.739537] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  437.741802] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  437.742300] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  437.742333] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  437.742346] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  437.742365] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  437.759136] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  437.759157] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  437.759192] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  437.759231] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  437.759249] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  437.759282] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  437.759474] Console: switching to colour frame buffer device 240x75
>[  438.160873] Console: switching to colour dummy device 80x25
>[  438.160987] [IGT] kms_pipe_crc_basic: executing
>[  438.174530] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  438.174604] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  438.183262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.191963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.200662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.209525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.218209] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.226968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.235665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.244505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.253199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.261808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.270354] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.278865] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.287359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.295832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.304290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.312746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.321200] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.329657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.338113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.346569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.355027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.363484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.371940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.380402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.388866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.397323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.405780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.414237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.422693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.431163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.439621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.448078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.448087] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  438.448091] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  438.448103] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  438.448120] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  438.448957] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  438.450478] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  438.450494] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  438.450509] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  438.450522] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  438.451336] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  438.452075] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  438.452862] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  438.452898] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  438.452900] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  438.452901] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  438.452903] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  438.452904] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  438.452906] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.452907] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  438.452909] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  438.452910] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  438.452911] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  438.452913] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  438.452914] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  438.452915] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.452929] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  438.452945] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  438.452962] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  438.452970] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  438.452984] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  438.454902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.454917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.456908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.456911] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  438.458876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.458892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.460877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.460888] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.460890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  438.460900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  438.460918] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  438.461367] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  438.461682] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  438.461721] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  438.461755] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  438.461777] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  438.462321] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  438.462637] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  438.463198] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  438.463199] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  438.463276] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  438.463278] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  438.463280] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  438.463281] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  438.463284] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  438.463285] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  438.463292] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  438.463294] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  438.463295] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  438.463296] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  438.463298] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  438.463299] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.463301] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.463302] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  438.463303] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  438.463305] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  438.463306] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  438.463307] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  438.463309] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  438.463310] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  438.463311] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  438.463313] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.463314] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.463316] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  438.463317] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  438.463318] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  438.463320] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  438.463321] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  438.463322] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  438.463324] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  438.463325] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  438.463326] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  438.463328] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  438.463329] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  438.463331] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  438.463332] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  438.463333] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.463335] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.463336] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  438.463362] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  438.463377] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  438.464789] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  438.464803] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  438.466836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  438.466840] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  438.468876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  438.468892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  438.470888] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  438.470891] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.470894] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  438.479287] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  438.479306] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  438.487762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.496221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.504678] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.513185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.521643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.530100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.538558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.547013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.555469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.563924] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.572379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.580834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.589289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.597746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.606201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.614656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.623112] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.631566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.640023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.648479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.656935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.665390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.673845] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.682300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.690758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.719095] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.727552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.736008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.744465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.752920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.761473] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.769929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  438.769937] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  438.769940] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  438.770114] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  438.770128] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  438.770965] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  438.772524] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  438.772540] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  438.772554] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  438.772569] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  438.773371] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  438.774137] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  438.774918] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  438.774943] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  438.774945] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  438.774947] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  438.774948] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  438.774950] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  438.774964] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.774966] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  438.774967] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  438.774968] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  438.774970] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  438.774971] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  438.774973] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  438.774974] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.775134] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  438.775149] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  438.775165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  438.775312] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  438.775326] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  438.776869] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.776883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.778876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  438.778879] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  438.780879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.780895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  438.782880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  438.782884] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.782886] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  438.783071] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  438.783087] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  438.783535] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  438.783855] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  438.783871] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  438.783898] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  438.783911] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  438.784314] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  438.784625] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  438.785129] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  438.785131] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  438.785209] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  438.785210] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  438.785213] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  438.785214] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  438.785216] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  438.785217] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  438.785223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  438.785225] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  438.785226] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  438.785228] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  438.785229] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  438.785231] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.785232] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  438.785233] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  438.785235] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  438.785236] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  438.785238] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  438.785239] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  438.785240] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  438.785242] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  438.785243] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  438.785244] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.785246] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  438.785247] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  438.785248] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  438.785250] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  438.785251] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  438.785253] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  438.785254] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  438.785255] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  438.785257] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  438.785258] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  438.785259] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  438.785261] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  438.785262] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  438.785263] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  438.785265] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.785266] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  438.785267] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  438.785447] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  438.785462] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  438.787102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  438.787116] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  438.788880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  438.788884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  438.790880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  438.790895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  438.792877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  438.792880] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  438.792883] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  438.793086] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-B-frame-sequence
>[  438.793290] [drm:drm_mode_addfb2] [FB:68]
>[  438.799549] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  438.799591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  438.799672] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  438.801157] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  438.801177] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  438.801194] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  438.801241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  438.801256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  438.801269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  438.801282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  438.801293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  438.801305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  438.801316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  438.801327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  438.801338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  438.801348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  438.801359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  438.801370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  438.801381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  438.801393] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  438.801407] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  438.801420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  438.801432] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  438.801445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  438.809168] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  438.809182] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  438.809205] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  438.809221] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  438.809292] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  438.809300] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  438.809342] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  438.809357] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  438.809372] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  438.809390] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  438.809404] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  438.809418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  438.809432] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  438.809446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  438.809459] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  438.809472] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  438.809484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  438.809486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  438.809498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  438.809500] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  438.809512] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  438.809523] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  438.809535] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  438.809546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  438.809557] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  438.809571] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  438.809583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  438.809595] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  438.809606] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  438.809617] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  438.809628] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  438.809646] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  438.809662] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  438.809676] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  438.810705] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  438.810717] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  438.810735] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  438.810753] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  438.810803] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  438.827803] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  438.827823] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  438.827844] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  438.829973] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  438.829995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  438.830014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  438.830029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  438.830044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  438.830058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  438.830072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  438.830086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  438.830099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  438.830112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  438.830125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  438.830139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  438.830152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  438.830165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  438.830179] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  438.830197] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  438.830213] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  438.830228] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  438.830243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  438.830262] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  438.830277] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  438.843087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.851562] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.860036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.868508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.876980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.885465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.893936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.902406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.910877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.919425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.927893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.936362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.944834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.953302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.961770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.970237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.978705] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.987171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.995639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  438.996516] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  439.012013] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  439.012030] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  439.012084] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  439.012918] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  439.014100] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  439.016681] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.016721] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.016734] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.016748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.021885] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.021914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  439.027168] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.029645] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  439.030243] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  439.047065] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  439.047080] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  439.047117] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  439.047141] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.047175] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.063789] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  439.147708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.147979] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  439.165128] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  439.165196] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  439.165313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  439.165371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  439.165426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  439.165473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  439.165519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  439.165564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  439.165611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  439.165654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  439.165696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  439.165873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  439.165938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  439.165997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  439.166061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  439.166128] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  439.166212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  439.166290] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.166367] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  439.166442] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  439.166553] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  439.166624] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  439.166694] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  439.166844] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  439.166953] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.167032] [drm:intel_power_well_disable [i915]] disabling DC off
>[  439.167102] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  439.167161] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  439.167639] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.170794] [drm:drm_mode_addfb2] [FB:68]
>[  439.193101] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  439.193131] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  439.193299] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  439.193358] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  439.193421] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  439.193487] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  439.193539] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  439.193597] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  439.193653] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  439.193705] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  439.193823] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  439.193878] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  439.193926] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.193934] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  439.193979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.193989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  439.194037] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  439.194084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  439.194131] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  439.194176] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.194219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.194276] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  439.194321] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.194367] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  439.194411] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  439.194455] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  439.194510] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.194574] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  439.194627] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  439.195822] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.195865] [drm:intel_power_well_enable [i915]] enabling DC off
>[  439.196171] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  439.196234] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  439.196279] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  439.196348] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  439.196391] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  439.196460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  439.196520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  439.196573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  439.196624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  439.196673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  439.196727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  439.196850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  439.196893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  439.196936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  439.196978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  439.197023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  439.197065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  439.197106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  439.197154] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  439.197210] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.197262] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  439.197313] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  439.197373] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  439.197422] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  439.210670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.219526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.228212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.236940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.245628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.254408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.263091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.271775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.280492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.289212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.297903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.306589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.315201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.323756] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.332275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.340789] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.349268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.357738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  439.363874] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  439.377875] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  439.377891] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  439.377937] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  439.378771] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  439.379485] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  439.381209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.381224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.381238] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.381253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.387270] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.387286] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  439.392423] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.394900] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  439.395375] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  439.412242] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  439.412264] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.412300] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.512919] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.513116] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  439.530046] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  439.530115] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  439.530232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  439.530290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  439.530346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  439.530395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  439.530441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  439.530486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  439.530534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  439.530578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  439.530620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  439.530662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  439.530707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  439.530887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  439.530948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  439.531023] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  439.531105] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  439.531186] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.531261] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  439.531335] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  439.531447] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  439.531520] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  439.531590] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  439.531691] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  439.531877] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.531961] [drm:intel_power_well_disable [i915]] disabling DC off
>[  439.532034] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  439.532098] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  439.532576] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.535419] [drm:drm_mode_addfb2] [FB:68]
>[  439.605715] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  439.605742] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  439.605886] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  439.605937] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  439.605990] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  439.606047] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  439.606092] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  439.606140] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  439.606188] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  439.606233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  439.606276] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  439.606317] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  439.606356] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.606363] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  439.606401] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.606407] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  439.606447] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  439.606486] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  439.606524] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  439.606561] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.606597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.606644] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  439.606681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.606802] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  439.606865] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  439.606929] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  439.607025] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  439.607105] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  439.607176] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  439.610578] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.610616] [drm:intel_power_well_enable [i915]] enabling DC off
>[  439.610993] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  439.611463] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  439.611522] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  439.611613] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  439.611672] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  439.611813] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  439.612055] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  439.612131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  439.612205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  439.612276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  439.612344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  439.612408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  439.612471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  439.612535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  439.612596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  439.612656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  439.612717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  439.612844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  439.612911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  439.612974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  439.613044] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  439.613121] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.613193] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  439.613262] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  439.613343] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  439.613410] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  439.617154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.617206] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.617252] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.617299] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.618162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  439.618207] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  439.618250] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  439.619334] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  439.619381] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  439.619425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  439.620432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.620481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  439.621848] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.624214] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  439.625521] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  439.625599] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  439.625644] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  439.625704] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  439.642487] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  439.642557] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.642662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.742947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.743116] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  439.743197] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  439.743312] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  439.759847] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  439.759915] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  439.760027] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  439.762380] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  439.762446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  439.762507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  439.762563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  439.762613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  439.762660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  439.762707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  439.762837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  439.762889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  439.762942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  439.762987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  439.763042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  439.763087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  439.763135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  439.763188] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  439.763251] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  439.763308] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.763363] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  439.763417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  439.763494] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  439.763544] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  439.763594] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  439.763661] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  439.763783] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.763839] [drm:intel_power_well_disable [i915]] disabling DC off
>[  439.763890] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  439.763937] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  439.764394] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.766236] [drm:drm_mode_addfb2] [FB:68]
>[  439.815484] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  439.815497] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  439.815562] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  439.815584] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  439.815607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  439.815631] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  439.815650] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  439.815671] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  439.815691] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  439.815736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  439.815755] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  439.815774] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  439.815793] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  439.815799] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  439.815816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  439.815821] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  439.815839] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  439.815856] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  439.815875] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  439.815892] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  439.815910] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  439.815932] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  439.815951] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  439.815969] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  439.815987] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  439.816005] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  439.816034] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  439.816059] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  439.816079] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  439.817386] [drm:intel_power_well_enable [i915]] enabling always-on
>[  439.817402] [drm:intel_power_well_enable [i915]] enabling DC off
>[  439.817678] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  439.817722] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  439.817738] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  439.817768] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  439.817787] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  439.817811] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  439.822189] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  439.822211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  439.822233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  439.822250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  439.822266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  439.822281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  439.822296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  439.822311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  439.822325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  439.822339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  439.822353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  439.822367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  439.822380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  439.822394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  439.822410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  439.822428] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.822445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  439.822462] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  439.822482] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  439.822499] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  439.825786] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  439.825804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  439.825820] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  439.825837] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  439.826493] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  439.826508] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  439.826522] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  439.827335] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  439.827351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  439.827366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  439.828016] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  439.828033] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  439.828996] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  439.831264] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  439.831802] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  439.831839] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  439.831854] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  439.831873] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  439.848713] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  439.848735] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.848770] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.949241] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  439.949415] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  439.949489] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  439.949609] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  439.965575] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  439.965644] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  439.965838] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  439.968103] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  439.968161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  439.968218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  439.968270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  439.968317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  439.968362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  439.968407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  439.968453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  439.968496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  439.968537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  439.968579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  439.968626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  439.968666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  439.968706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  439.968817] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  439.968879] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  439.968941] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  439.968994] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  439.969047] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  439.969125] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  439.969172] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  439.969221] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  439.969285] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  439.969357] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  439.969409] [drm:intel_power_well_disable [i915]] disabling DC off
>[  439.969456] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  439.969498] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  439.969998] [drm:intel_power_well_disable [i915]] disabling always-on
>[  439.971509] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  440.016405] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  440.016431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  440.016458] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  440.016487] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  440.016509] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  440.016532] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  440.016556] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  440.016577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  440.016599] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  440.016618] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  440.016638] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.016642] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  440.016661] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.016664] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  440.016684] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  440.016723] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  440.016742] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  440.016761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.016779] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  440.016803] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  440.016821] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.016840] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  440.016858] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  440.016876] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  440.016904] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  440.016925] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  440.016949] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  440.016975] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  440.016997] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  440.017019] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  440.017040] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  440.017060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  440.017079] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  440.017098] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  440.017116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  440.017119] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  440.017137] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  440.017140] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  440.017159] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  440.017178] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  440.017196] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  440.017214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  440.017232] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  440.017254] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  440.017272] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  440.017290] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  440.017308] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  440.017326] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  440.017349] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  440.017376] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  440.017398] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  440.017420] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  440.017441] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  440.017515] [drm:intel_power_well_enable [i915]] enabling always-on
>[  440.017533] [drm:intel_power_well_enable [i915]] enabling DC off
>[  440.017825] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  440.017856] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  440.017876] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  440.017928] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  440.017954] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  440.017977] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  440.017994] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  440.018022] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  440.019856] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  440.019876] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  440.019906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  440.019933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  440.019955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  440.019977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  440.019997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  440.020017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  440.020039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  440.020058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  440.020077] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  440.020096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  440.020115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  440.020133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  440.020152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  440.020173] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  440.020198] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  440.020221] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  440.020243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  440.020271] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  440.020294] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  440.032323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.040841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.049353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.057863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.066372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.074880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.083405] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.091915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.100424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.108934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.117492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.126007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.134517] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.143031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.151541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.160049] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.168558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.177067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  440.184938] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  440.200080] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  440.200095] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  440.200119] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  440.200941] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  440.202410] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  440.204649] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  440.204664] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  440.204677] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  440.204692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  440.209948] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  440.209962] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  440.215108] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  440.217592] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  440.218112] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  440.218168] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  440.218182] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  440.218229] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  440.218241] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  440.221488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  440.221504] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  440.221518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  440.221545] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  440.222215] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  440.222229] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  440.222242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  440.222916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  440.222943] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  440.222972] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  440.223617] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  440.223631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  440.224590] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  440.226866] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  440.227367] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  440.227401] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  440.227414] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  440.227433] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  440.244205] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  440.244225] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  440.244261] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  440.244299] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  440.244317] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  440.244350] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  440.244550] Console: switching to colour frame buffer device 240x75
>[  440.671060] Console: switching to colour dummy device 80x25
>[  440.671167] [IGT] kms_pipe_crc_basic: executing
>[  440.682501] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  440.682588] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  440.691151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.717316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.725774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.734228] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.742684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.751153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.759612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.768081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.776536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.784991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.793447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.801902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.810356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.818819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.827285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.835740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.844196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.852651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.861106] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.869561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.878018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.886474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.894932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.903399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.911854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.920310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.928765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.937220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.945675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.954187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.962642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.971098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  440.971106] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  440.971110] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  440.971123] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  440.971146] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  440.971995] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  440.973598] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  440.973616] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  440.973643] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  440.973656] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  440.974457] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  440.975175] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  440.975960] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  440.975984] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  440.975987] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  440.975988] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  440.975990] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  440.975991] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  440.975993] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.976007] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  440.976009] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  440.976010] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  440.976011] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  440.976013] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  440.976014] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  440.976015] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.976031] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  440.976046] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  440.976063] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  440.976071] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  440.976085] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  440.977879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  440.977895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  440.979891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  440.979894] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  440.981891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  440.981906] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  440.984166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  440.984170] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  440.984172] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  440.984182] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  440.984200] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  440.984649] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  440.984977] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  440.984994] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  440.985009] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  440.985036] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  440.985440] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  440.985780] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  440.986280] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  440.986282] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  440.986359] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  440.986360] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  440.986363] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.986364] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.986367] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  440.986368] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  440.986374] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  440.986376] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  440.986377] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  440.986378] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  440.986380] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  440.986381] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.986382] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  440.986384] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.986385] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  440.986387] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  440.986388] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  440.986389] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  440.986391] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  440.986392] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  440.986393] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  440.986395] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.986396] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  440.986397] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  440.986399] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  440.986400] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.986402] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  440.986403] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  440.986404] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  440.986406] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  440.986407] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  440.986408] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  440.986410] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  440.986411] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.986412] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  440.986414] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  440.986415] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.986417] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  440.986418] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  440.986448] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  440.986463] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  440.987862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  440.987876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  440.989813] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  440.989817] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  440.991904] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  440.991920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  440.993880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  440.993884] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  440.993886] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  441.002511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  441.002527] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  441.010983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.019454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.027910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.036363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.044821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.053293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.061749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.070202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.078658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.087114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.095572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.104028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.112483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.120940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.129394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.137849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.146304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.154760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.163215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.171671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.180169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.188624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.197082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.205540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.213996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.222452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.230908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.239362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.247818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.256274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.264731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.273186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  441.273194] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  441.273197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  441.273379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  441.273394] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  441.274302] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  441.275824] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  441.275841] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  441.275856] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  441.275870] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  441.276673] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  441.277532] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  441.278315] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  441.278339] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  441.278342] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  441.278343] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  441.278345] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  441.278347] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  441.278348] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  441.278350] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  441.278351] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  441.278353] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  441.278354] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  441.278356] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  441.278357] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  441.278358] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  441.278545] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  441.278560] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  441.278576] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  441.279048] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  441.279064] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  441.280885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  441.280901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  441.282886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  441.282889] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  441.285151] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  441.285167] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  441.287422] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  441.287426] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  441.287428] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  441.287842] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  441.287861] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  441.288332] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  441.288645] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  441.288661] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  441.288687] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  441.288853] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  441.289259] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  441.289570] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  441.290130] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  441.290132] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  441.290209] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  441.290210] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  441.290213] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  441.290214] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  441.290217] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  441.290218] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  441.290223] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  441.290225] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  441.290226] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  441.290228] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  441.290229] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  441.290231] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  441.290232] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  441.290233] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  441.290235] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  441.290236] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  441.290237] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  441.290239] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  441.290240] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  441.290242] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  441.290243] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  441.290244] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  441.290246] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  441.290247] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  441.290248] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  441.290250] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  441.290251] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  441.290252] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  441.290254] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  441.290255] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  441.290257] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  441.290258] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  441.290259] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  441.290261] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  441.290262] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  441.290263] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  441.290265] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  441.290266] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  441.290267] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  441.290440] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  441.290455] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  441.292352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  441.292367] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  441.293878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  441.293882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  441.295885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  441.295900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  441.298154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  441.298157] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  441.298160] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  441.298368] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C
>[  441.298587] [drm:drm_mode_addfb2] [FB:69]
>[  441.304912] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  441.304954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  441.305034] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  441.320117] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  441.320138] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  441.320157] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  441.320203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  441.320217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  441.320232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  441.320244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  441.320256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  441.320268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  441.320281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  441.320292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  441.320303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  441.320313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  441.320324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  441.320334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  441.320345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  441.320358] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  441.320372] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  441.320387] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  441.320399] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  441.320412] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  441.327571] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  441.327586] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  441.327609] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  441.327624] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  441.327840] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  441.327881] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  441.327943] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  441.327963] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  441.328014] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  441.344460] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  441.344482] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  441.344517] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  441.346670] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  441.346692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  441.346757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  441.346782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  441.346800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  441.346817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  441.346833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  441.346850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  441.346865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  441.346880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  441.346895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  441.346912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  441.346927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  441.346942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  441.346959] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  441.346979] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  441.346998] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  441.347016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  441.347035] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  441.347064] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  441.347081] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  441.347098] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  441.347122] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  441.347147] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  441.347165] [drm:intel_power_well_disable [i915]] disabling DC off
>[  441.347182] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  441.347196] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  441.347618] [drm:intel_power_well_disable [i915]] disabling always-on
>[  441.347738] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  441.347748] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  441.347799] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  441.347815] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  441.347834] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  441.347854] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  441.347870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  441.347888] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  441.347905] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  441.347921] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  441.347937] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  441.347952] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  441.347966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  441.347969] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  441.347983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  441.347986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  441.348000] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  441.348014] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  441.348028] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  441.348041] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  441.348055] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  441.348071] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  441.348085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  441.348099] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  441.348112] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  441.348126] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  441.348143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  441.348163] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  441.348179] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  441.348540] [drm:intel_power_well_enable [i915]] enabling always-on
>[  441.348553] [drm:intel_power_well_enable [i915]] enabling DC off
>[  441.348844] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  441.348865] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  441.348878] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  441.348925] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  441.348938] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  441.348959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  441.348976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  441.348993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  441.349008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  441.349023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  441.349037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  441.349052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  441.349067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  441.349081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  441.349094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  441.349109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  441.349123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  441.349136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  441.349152] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  441.349170] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  441.349187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  441.349203] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  441.349223] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  441.349239] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  441.362016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.370516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.379012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.387508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.396010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.404511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.413010] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.421508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.430005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.438503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.446995] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.455470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.463940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.472408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.480884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.489359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.497831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.506303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.514029] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  441.529669] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  441.529684] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  441.529731] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  441.530567] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  441.532015] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  441.534263] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  441.534278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  441.534292] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  441.534307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  441.539466] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  441.539481] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  441.544622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  441.547057] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  441.547548] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  441.564392] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  441.564415] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  441.564451] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  441.665029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  441.665233] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  441.681589] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  441.681658] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  441.681856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  441.681921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  441.681979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  441.682028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  441.682079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  441.682128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  441.682177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  441.682222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  441.682266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  441.682310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  441.682361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  441.682402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  441.682443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  441.682497] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  441.682553] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  441.682608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  441.682662] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  441.682714] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  441.682846] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  441.682894] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  441.682940] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  441.683005] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  441.683078] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  441.683130] [drm:intel_power_well_disable [i915]] disabling DC off
>[  441.683177] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  441.683219] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  441.683672] [drm:intel_power_well_disable [i915]] disabling always-on
>[  441.685826] [drm:drm_mode_addfb2] [FB:69]
>[  441.718127] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  441.718155] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  441.718321] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  441.718380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  441.718445] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  441.718513] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  441.718567] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  441.718622] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  441.718678] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  441.718730] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  441.719412] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  441.719464] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  441.719512] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  441.719521] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  441.719567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  441.719574] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  441.719622] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  441.719667] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  441.719712] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  441.720259] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  441.720308] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  441.720370] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  441.720422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  441.720474] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  441.720523] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  441.720570] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  441.720628] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  441.720692] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  441.721219] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  441.722500] [drm:intel_power_well_enable [i915]] enabling always-on
>[  441.722543] [drm:intel_power_well_enable [i915]] enabling DC off
>[  441.723032] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  441.723371] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  441.723422] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  441.723525] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  441.723568] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  441.723638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  441.723695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  441.724126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  441.724177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  441.724225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  441.724270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  441.724318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  441.724361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  441.724404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  441.724446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  441.724490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  441.724531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  441.724572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  441.724619] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  441.724672] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  441.724722] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  441.725415] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  441.725480] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  441.725533] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  441.738778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.747518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.756207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.764936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.773661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.782431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.791200] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.799912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.808628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.817461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.826025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.834555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.843057] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.851547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.860023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.868493] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.876962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.885429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  441.893267] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  441.907350] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  441.907369] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  441.907416] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  441.908866] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  441.911098] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  441.913168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  441.913185] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  441.913199] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  441.913214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  441.918356] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  441.918372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  441.923519] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  441.925998] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  441.926489] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  441.943339] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  441.943362] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  441.943398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.043966] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  442.044170] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  442.060944] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  442.061012] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  442.061130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  442.061188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  442.061244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  442.061291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  442.061336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  442.061380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  442.061427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  442.061469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  442.061512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  442.061553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  442.061597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  442.061637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  442.061678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  442.061725] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  442.063258] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  442.063346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.063431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  442.063510] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  442.063625] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  442.063688] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  442.064312] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  442.064412] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  442.064524] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  442.064602] [drm:intel_power_well_disable [i915]] disabling DC off
>[  442.064675] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  442.065218] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  442.065700] [drm:intel_power_well_disable [i915]] disabling always-on
>[  442.068192] [drm:drm_mode_addfb2] [FB:69]
>[  442.135628] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  442.135654] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  442.136207] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  442.136261] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  442.136318] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  442.136374] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  442.136419] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  442.136466] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  442.136514] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  442.136558] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  442.136602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  442.136642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  442.136681] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  442.137290] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  442.137353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  442.137363] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  442.137430] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  442.137489] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  442.137552] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  442.137609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  442.137668] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  442.137734] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  442.138204] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  442.138263] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  442.138324] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  442.138379] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  442.138470] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  442.138547] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  442.138608] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  442.142435] [drm:intel_power_well_enable [i915]] enabling always-on
>[  442.142469] [drm:intel_power_well_enable [i915]] enabling DC off
>[  442.143118] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  442.143463] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  442.143526] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  442.143688] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  442.144108] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  442.144197] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  442.144397] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  442.144450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  442.144500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  442.144545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  442.144588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  442.144629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  442.144669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  442.144710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  442.145214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  442.145272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  442.145333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  442.145388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  442.145448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  442.145501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  442.145567] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  442.145639] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.145708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  442.146310] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  442.146395] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  442.146464] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  442.150070] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  442.150122] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  442.150167] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  442.150215] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  442.151648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  442.151699] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  442.152127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  442.153109] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  442.153158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  442.153202] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  442.154141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  442.154211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  442.155405] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  442.157813] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  442.159215] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  442.159292] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  442.159338] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  442.159400] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  442.176141] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  442.176207] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  442.176307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.276584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  442.276917] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  442.277013] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  442.277185] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  442.293507] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  442.293576] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  442.293690] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  442.294039] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  442.294119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  442.294204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  442.294276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  442.294350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  442.294414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  442.294482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  442.294548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  442.294614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  442.294673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  442.294738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  442.294873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  442.294932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  442.294997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  442.295064] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  442.295148] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  442.295228] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.295304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  442.295374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  442.295487] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  442.295560] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  442.295631] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  442.295732] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  442.295900] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  442.295977] [drm:intel_power_well_disable [i915]] disabling DC off
>[  442.296049] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  442.296106] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  442.296583] [drm:intel_power_well_disable [i915]] disabling always-on
>[  442.298738] [drm:drm_mode_addfb2] [FB:69]
>[  442.354205] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  442.354219] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  442.354295] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  442.354321] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  442.354349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  442.354377] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  442.354399] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  442.354424] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  442.354448] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  442.354471] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  442.354493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  442.354515] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  442.354535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  442.354538] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  442.354558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  442.354561] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  442.354582] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  442.354602] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  442.354621] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  442.354640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  442.354659] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  442.354683] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  442.354731] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  442.354751] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  442.354774] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  442.354793] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  442.354825] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  442.354854] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  442.354878] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  442.356444] [drm:intel_power_well_enable [i915]] enabling always-on
>[  442.356463] [drm:intel_power_well_enable [i915]] enabling DC off
>[  442.356766] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  442.356795] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  442.356816] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  442.356854] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  442.356874] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  442.356903] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  442.359179] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  442.359203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  442.359225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  442.359245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  442.359262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  442.359280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  442.359297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  442.359314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  442.359330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  442.359346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  442.359361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  442.359377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  442.359393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  442.359408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  442.359426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  442.359447] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.359466] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  442.359485] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  442.359508] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  442.359527] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  442.361962] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  442.361984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  442.362002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  442.362021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  442.362679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  442.362749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  442.362765] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  442.363416] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  442.363431] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  442.363445] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  442.364095] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  442.364111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  442.365097] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  442.367368] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  442.367860] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  442.367895] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  442.367909] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  442.367928] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  442.384764] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  442.384786] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  442.384820] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.485161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  442.485338] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  442.485410] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  442.485529] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  442.501832] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  442.501902] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  442.502019] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  442.502264] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  442.502320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  442.502376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  442.502427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  442.502474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  442.502519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  442.502562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  442.502607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  442.502649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  442.502690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  442.502810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  442.502863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  442.502909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  442.502948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  442.502999] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  442.503060] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  442.503115] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.503166] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  442.503217] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  442.503298] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  442.503345] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  442.503392] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  442.503458] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  442.503531] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  442.503583] [drm:intel_power_well_disable [i915]] disabling DC off
>[  442.503631] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  442.503673] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  442.504127] [drm:intel_power_well_disable [i915]] disabling always-on
>[  442.505380] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  442.526428] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  442.526451] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  442.526474] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  442.526498] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  442.526517] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  442.526538] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  442.526558] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  442.526577] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  442.526596] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  442.526613] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  442.526629] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  442.526633] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  442.526650] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  442.526652] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  442.526669] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  442.526685] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  442.526731] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  442.526747] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  442.526762] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  442.526782] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  442.526798] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  442.526814] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  442.526829] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  442.526845] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  442.526869] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  442.526887] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  442.526906] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  442.526929] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  442.526947] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  442.526966] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  442.526984] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  442.527001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  442.527017] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  442.527033] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  442.527049] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  442.527051] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  442.527067] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  442.527069] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  442.527085] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  442.527101] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  442.527117] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  442.527132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  442.527147] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  442.527165] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  442.527180] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  442.527196] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  442.527211] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  442.527226] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  442.527245] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  442.527268] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  442.527287] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  442.527306] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  442.527323] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  442.527389] [drm:intel_power_well_enable [i915]] enabling always-on
>[  442.527404] [drm:intel_power_well_enable [i915]] enabling DC off
>[  442.527680] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  442.527720] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  442.527739] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  442.527785] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  442.527804] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  442.527823] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  442.527838] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  442.527861] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  442.528009] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  442.528023] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  442.528046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  442.528066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  442.528083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  442.528100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  442.528116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  442.528133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  442.528149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  442.528165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  442.528180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  442.528194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  442.528209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  442.528224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  442.528238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  442.528255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  442.528275] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.528293] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  442.528311] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  442.528332] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  442.528350] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  442.540294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.548811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.557323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.565834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.574342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.582852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.591360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.599869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.608378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.616886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.625401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.633920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.642428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.650938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.659448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.667957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.676466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.685070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  442.692945] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  442.714020] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  442.714035] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  442.714160] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  442.714990] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  442.715765] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  442.718374] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  442.718390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  442.718404] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  442.718420] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  442.723852] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  442.723880] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  442.729042] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  442.731524] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  442.732044] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  442.732103] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  442.732117] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  442.732164] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  442.732176] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  442.735438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  442.735454] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  442.735469] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  442.735484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  442.736178] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  442.736192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  442.736205] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  442.736865] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  442.736878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  442.736891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  442.737562] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  442.737576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  442.738533] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  442.740844] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  442.741360] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  442.741389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  442.741402] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  442.741422] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  442.758193] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  442.758213] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  442.758248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  442.758287] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  442.758305] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  442.758337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  442.758551] Console: switching to colour frame buffer device 240x75
>[  443.178417] Console: switching to colour dummy device 80x25
>[  443.178527] [IGT] kms_pipe_crc_basic: executing
>[  443.192501] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  443.192598] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  443.201155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.209611] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.218082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.226540] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.235000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.243458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.251915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.260370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.268826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.277279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.285740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.294197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.302655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.311111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.319567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.328024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.336481] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.344937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.353394] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.361850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.370305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.378761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.387216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.395671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.404312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.412775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.421235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.429693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.438163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.446622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.455081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.463537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.463549] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  443.463553] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  443.463565] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  443.463581] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  443.464417] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  443.465941] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  443.465958] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  443.465972] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  443.465986] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  443.466815] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  443.467521] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  443.468306] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  443.468346] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  443.468348] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  443.468350] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  443.468351] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  443.468353] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  443.468354] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  443.468356] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  443.468357] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  443.468358] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  443.468360] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  443.468361] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  443.468363] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  443.468364] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  443.468378] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  443.468392] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  443.468409] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  443.468416] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  443.468430] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  443.469892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  443.469907] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  443.471878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  443.471882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  443.473881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  443.473897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  443.475878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  443.475882] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  443.475885] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  443.475894] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  443.475912] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  443.476364] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  443.476676] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  443.476692] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  443.476721] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  443.476735] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  443.477143] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  443.477482] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  443.477976] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  443.477978] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  443.478052] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  443.478054] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  443.478057] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  443.478058] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  443.478061] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  443.478062] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  443.478067] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  443.478069] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  443.478071] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  443.478072] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  443.478073] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  443.478075] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  443.478076] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  443.478078] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  443.478079] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  443.478080] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  443.478082] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  443.478083] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  443.478085] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  443.478086] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  443.478087] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  443.478089] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  443.478090] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  443.478091] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  443.478093] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  443.478094] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  443.478095] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  443.478097] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  443.478098] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  443.478099] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  443.478101] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  443.478102] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  443.478104] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  443.478105] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  443.478106] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  443.478108] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  443.478109] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  443.478110] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  443.478112] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  443.478140] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  443.478155] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  443.479866] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  443.479880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  443.481896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  443.481898] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  443.483899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  443.483913] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  443.485874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  443.485877] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  443.485879] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  443.494561] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  443.494579] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  443.503034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.511492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.519949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.528406] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.536862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.545323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.553782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.562237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.570693] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.579162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.587617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.596076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.604531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.612987] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.621442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.629899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.638353] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.646809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.655266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.663723] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.672177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.680632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.689087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.717398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.725855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.734309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.742764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.751220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.759775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.768230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.776686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.785153] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  443.785162] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  443.785165] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  443.785355] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  443.785373] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  443.786298] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  443.787819] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  443.787849] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  443.787879] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  443.787892] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  443.788700] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  443.789533] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  443.790325] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  443.790349] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  443.790351] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  443.790353] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  443.790354] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  443.790356] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  443.790358] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  443.790359] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  443.790361] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  443.790362] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  443.790364] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  443.790365] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  443.790367] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  443.790381] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  443.790540] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  443.790555] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  443.790571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  443.791112] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  443.791127] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  443.792865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  443.792879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  443.794865] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  443.794867] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  443.796876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  443.796892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  443.798884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  443.798888] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  443.798890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  443.799077] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  443.799094] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  443.799542] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  443.800025] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  443.800042] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  443.800056] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  443.800070] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  443.800473] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  443.800866] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  443.801358] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  443.801360] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  443.801434] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  443.801435] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  443.801438] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  443.801439] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  443.801442] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  443.801443] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  443.801449] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  443.801450] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  443.801452] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  443.801453] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  443.801455] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  443.801456] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  443.801457] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  443.801459] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  443.801460] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  443.801462] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  443.801463] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  443.801464] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  443.801466] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  443.801467] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  443.801469] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  443.801470] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  443.801471] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  443.801473] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  443.801474] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  443.801475] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  443.801477] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  443.801478] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  443.801479] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  443.801481] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  443.801482] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  443.801484] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  443.801485] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  443.801486] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  443.801488] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  443.801489] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  443.801490] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  443.801492] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  443.801493] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  443.801678] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  443.801693] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  443.803841] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  443.803857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  443.805895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  443.805898] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  443.807882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  443.807898] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  443.809920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  443.809923] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  443.809926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  443.810139] [IGT] kms_pipe_crc_basic: starting subtest nonblocking-crc-pipe-C-frame-sequence
>[  443.810353] [drm:drm_mode_addfb2] [FB:70]
>[  443.816602] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  443.816651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  443.816884] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  443.833597] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  443.833616] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  443.833634] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  443.833680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  443.833813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  443.833829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  443.833843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  443.833856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  443.833869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  443.833882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  443.833894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  443.833905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  443.833918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  443.833929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  443.833941] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  443.833952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  443.833965] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  443.833980] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  443.833995] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  443.834008] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  443.834022] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  443.841519] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  443.841533] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  443.841555] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  443.841571] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  443.841644] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  443.841683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  443.841932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  443.841959] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  443.842002] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  443.858569] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  443.858591] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  443.858629] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  443.860981] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  443.861002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  443.861024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  443.861041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  443.861057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  443.861072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  443.861087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  443.861103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  443.861118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  443.861132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  443.861146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  443.861162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  443.861176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  443.861190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  443.861206] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  443.861225] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  443.861243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  443.861261] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  443.861277] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  443.861307] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  443.861324] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  443.861340] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  443.861363] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  443.861388] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  443.861406] [drm:intel_power_well_disable [i915]] disabling DC off
>[  443.861423] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  443.861436] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  443.862652] [drm:intel_power_well_disable [i915]] disabling always-on
>[  443.862858] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  443.862869] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  443.862927] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  443.862947] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  443.862968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  443.862991] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  443.863009] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  443.863028] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  443.863047] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  443.863064] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  443.863082] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  443.863098] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  443.863113] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  443.863116] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  443.863131] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  443.863134] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  443.863150] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  443.863165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  443.863180] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  443.863195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  443.863209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  443.863228] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  443.863243] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  443.863257] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  443.863272] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  443.863286] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  443.863304] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  443.863324] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  443.863342] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  443.864343] [drm:intel_power_well_enable [i915]] enabling always-on
>[  443.864357] [drm:intel_power_well_enable [i915]] enabling DC off
>[  443.864632] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  443.864654] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  443.864669] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  443.864888] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  443.864912] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  443.864939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  443.864960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  443.864978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  443.864995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  443.865012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  443.865027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  443.865043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  443.865059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  443.865073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  443.865088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  443.865104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  443.865118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  443.865132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  443.865149] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  443.865169] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  443.865187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  443.865204] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  443.865226] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  443.865244] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  443.878036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.886556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.895075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.903592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.912109] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.920624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.929143] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.937657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.946319] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.954836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.963341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.971836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.980309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.988778] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  443.997248] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.005719] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.014188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.022657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.031128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.032209] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  444.046997] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  444.047014] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  444.047072] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  444.047901] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  444.050154] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  444.051560] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  444.051576] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  444.051590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  444.051604] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  444.056746] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  444.056761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  444.061903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  444.064366] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  444.064936] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  444.081827] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  444.081850] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  444.081887] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.182411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  444.182613] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  444.201089] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  444.201158] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  444.201277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  444.201337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  444.201394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  444.201442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  444.201487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  444.201531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  444.201578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  444.201621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  444.201662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  444.201704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  444.201875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  444.201936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  444.202002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  444.202068] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  444.202150] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  444.202228] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.202302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  444.202376] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  444.202487] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  444.202559] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  444.202631] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  444.202732] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  444.202914] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  444.202996] [drm:intel_power_well_disable [i915]] disabling DC off
>[  444.203069] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  444.203131] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  444.203610] [drm:intel_power_well_disable [i915]] disabling always-on
>[  444.205926] [drm:drm_mode_addfb2] [FB:70]
>[  444.236852] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  444.236880] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  444.237039] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  444.237096] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  444.237156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  444.237218] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  444.237268] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  444.237320] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  444.237373] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  444.237422] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  444.237470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  444.237516] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  444.237559] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  444.237566] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  444.237609] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  444.237616] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  444.237660] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  444.237702] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  444.237835] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  444.237904] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  444.237964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  444.238037] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  444.238105] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  444.238172] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  444.238236] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  444.238298] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  444.238371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  444.238451] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  444.238523] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  444.239852] [drm:intel_power_well_enable [i915]] enabling always-on
>[  444.239894] [drm:intel_power_well_enable [i915]] enabling DC off
>[  444.240196] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  444.240256] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  444.240313] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  444.240411] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  444.240454] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  444.240520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  444.240576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  444.240627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  444.240674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  444.240903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  444.240969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  444.241038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  444.241100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  444.241162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  444.241225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  444.241287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  444.241347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  444.241406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  444.241472] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  444.241553] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.241626] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  444.241699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  444.241819] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  444.241888] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  444.255298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.263996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.272688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.281424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.290119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.298814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.307503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.316198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.324929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.333586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.342160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.350697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.359223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.367711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.376185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.384654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.393124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.401596] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  444.409421] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  444.423666] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  444.423685] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  444.423729] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  444.425276] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  444.427069] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  444.429014] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  444.429030] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  444.429044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  444.429071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  444.434211] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  444.434227] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  444.439368] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  444.441844] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  444.442332] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  444.459190] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  444.459213] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  444.459249] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.559721] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  444.559988] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  444.576958] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  444.577029] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  444.577146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  444.577205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  444.577261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  444.577309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  444.577354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  444.577398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  444.577444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  444.577487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  444.577529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  444.577570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  444.577614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  444.577654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  444.577695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  444.577837] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  444.577895] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  444.577947] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.577997] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  444.578046] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  444.578125] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  444.578171] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  444.578216] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  444.578280] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  444.578354] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  444.578404] [drm:intel_power_well_disable [i915]] disabling DC off
>[  444.578450] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  444.578490] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  444.578975] [drm:intel_power_well_disable [i915]] disabling always-on
>[  444.582463] [drm:drm_mode_addfb2] [FB:70]
>[  444.649409] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  444.649432] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  444.649566] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  444.649612] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  444.649661] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  444.649713] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  444.650516] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  444.650563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  444.650608] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  444.650648] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  444.650688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  444.651344] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  444.651385] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  444.651392] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  444.651431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  444.651437] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  444.651476] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  444.651513] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  444.651551] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  444.651587] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  444.651622] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  444.651665] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  444.651702] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  444.652872] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  444.652912] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  444.652949] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  444.653011] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  444.653063] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  444.653105] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  444.656675] [drm:intel_power_well_enable [i915]] enabling always-on
>[  444.656709] [drm:intel_power_well_enable [i915]] enabling DC off
>[  444.657389] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  444.657439] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  444.657480] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  444.657564] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  444.657601] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  444.657656] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  444.658474] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  444.658523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  444.658571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  444.658612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  444.658651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  444.658688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  444.659382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  444.659424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  444.659464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  444.659501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  444.659537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  444.659572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  444.659606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  444.659640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  444.659680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  444.660551] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.660595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  444.660636] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  444.660687] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  444.661252] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  444.664783] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  444.664830] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  444.664870] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  444.664912] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  444.666200] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  444.666245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  444.666286] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  444.667287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  444.667330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  444.667371] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  444.668447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  444.668493] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  444.670048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  444.672414] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  444.673781] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  444.673856] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  444.673898] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  444.673954] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  444.690730] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  444.690838] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  444.690935] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.791249] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  444.791427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  444.791498] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  444.791617] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  444.807690] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  444.807817] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  444.807933] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  444.810237] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  444.810304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  444.810367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  444.810421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  444.810472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  444.810521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  444.810569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  444.810620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  444.810666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  444.810710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  444.810884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  444.810956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  444.811016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  444.811074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  444.811141] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  444.811226] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  444.811305] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.811382] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  444.811457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  444.811576] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  444.811650] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  444.811724] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  444.811889] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  444.811998] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  444.812076] [drm:intel_power_well_disable [i915]] disabling DC off
>[  444.812145] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  444.812208] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  444.812687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  444.815918] [drm:drm_mode_addfb2] [FB:70]
>[  444.862983] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  444.862995] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  444.863059] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  444.863079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  444.863100] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  444.863123] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  444.863141] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  444.863161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  444.863180] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  444.863197] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  444.863215] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  444.863231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  444.863247] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  444.863250] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  444.863265] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  444.863268] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  444.863283] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  444.863299] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  444.863314] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  444.863328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  444.863343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  444.863361] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  444.863376] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  444.863391] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  444.863406] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  444.863421] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  444.863446] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  444.863467] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  444.863485] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  444.865437] [drm:intel_power_well_enable [i915]] enabling always-on
>[  444.865450] [drm:intel_power_well_enable [i915]] enabling DC off
>[  444.865918] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  444.866241] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  444.866262] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  444.866300] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  444.866321] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  444.866351] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  444.868603] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  444.868626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  444.868647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  444.868664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  444.868680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  444.868873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  444.868895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  444.868917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  444.868938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  444.868957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  444.868979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  444.868999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  444.869019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  444.869038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  444.869059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  444.869084] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.869109] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  444.869143] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  444.869168] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  444.869187] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  444.872465] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  444.872482] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  444.872508] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  444.872523] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  444.873329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  444.873345] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  444.873372] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  444.874068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  444.874083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  444.874097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  444.874829] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  444.874850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  444.875817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  444.878098] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  444.878549] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  444.878584] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  444.878597] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  444.878617] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  444.895385] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  444.895406] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  444.895441] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  444.995892] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  444.996059] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  444.996132] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  444.996248] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  445.012850] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  445.012919] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  445.013034] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  445.015461] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  445.015528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  445.015591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  445.015648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  445.015699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  445.015833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  445.015884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  445.015940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  445.015987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  445.016034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  445.016082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  445.016135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  445.016180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  445.016227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  445.016279] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  445.016340] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  445.016398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  445.016452] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  445.016506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  445.016591] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  445.016641] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  445.016691] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  445.016794] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  445.016869] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  445.016924] [drm:intel_power_well_disable [i915]] disabling DC off
>[  445.016973] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  445.017017] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  445.017472] [drm:intel_power_well_disable [i915]] disabling always-on
>[  445.019214] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  445.064304] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  445.064326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  445.064349] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  445.064373] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  445.064392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  445.064412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  445.064432] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  445.064451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  445.064470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  445.064487] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  445.064503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  445.064508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  445.064524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  445.064527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  445.064544] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  445.064560] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  445.064576] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  445.064592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  445.064608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  445.064627] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  445.064643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  445.064659] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  445.064674] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  445.064690] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  445.064729] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  445.064747] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  445.064768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  445.064790] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  445.064808] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  445.064828] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  445.064845] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  445.064862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  445.064879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  445.064895] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  445.064910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  445.064913] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  445.064928] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  445.064930] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  445.064947] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  445.064962] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  445.064978] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  445.064993] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  445.065008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  445.065027] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  445.065043] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  445.065058] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  445.065073] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  445.065089] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  445.065109] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  445.065132] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  445.065151] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  445.065171] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  445.065189] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  445.065263] [drm:intel_power_well_enable [i915]] enabling always-on
>[  445.065278] [drm:intel_power_well_enable [i915]] enabling DC off
>[  445.065554] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  445.065580] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  445.065596] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  445.065630] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  445.065654] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  445.065676] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  445.065691] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  445.065726] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  445.067905] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  445.067922] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  445.067949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  445.067973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  445.067992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  445.068011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  445.068029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  445.068047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  445.068065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  445.068082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  445.068098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  445.068115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  445.068131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  445.068147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  445.068163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  445.068181] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  445.068202] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  445.068222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  445.068241] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  445.068265] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  445.068284] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  445.080307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.088821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.097332] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.105842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.114351] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.122861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.131407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.139916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.148435] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.156953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.165465] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.173974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.182484] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.190993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.199502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.208012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.216520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.225028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.233634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  445.234731] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  445.249328] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  445.249346] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  445.249380] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  445.250371] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  445.252969] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  445.254679] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  445.254693] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  445.254723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  445.254737] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  445.259886] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  445.259901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  445.265048] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  445.267528] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  445.268067] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  445.268110] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  445.268125] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  445.268176] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  445.268190] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  445.271433] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  445.271449] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  445.271464] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  445.271479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  445.272242] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  445.272256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  445.272269] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  445.272919] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  445.272933] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  445.272946] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  445.273593] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  445.273607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  445.274564] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  445.276829] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  445.277348] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  445.277376] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  445.277390] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  445.277410] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  445.294182] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  445.294204] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  445.294243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  445.294285] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  445.294304] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  445.294339] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  445.294487] Console: switching to colour frame buffer device 240x75
>[  445.724992] Console: switching to colour dummy device 80x25
>[  445.725076] [IGT] kms_pipe_crc_basic: executing
>[  445.739571] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  445.739670] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  445.748291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.756751] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.765207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.773715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.782169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.790624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.799079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.807535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.815990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.824445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.832898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.841352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.849806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.858259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.866716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.875169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.883624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.892078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.900531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.908986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.917452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.925907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.934359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.942815] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.951269] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.959724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.968179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.976633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.985089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  445.993543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.001997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.010451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.010461] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  446.010464] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  446.010477] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  446.010499] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  446.011349] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  446.012918] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  446.012936] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  446.012950] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  446.012964] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  446.013809] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  446.014517] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  446.015310] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  446.015349] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  446.015351] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  446.015352] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  446.015354] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  446.015355] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  446.015357] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  446.015358] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  446.015359] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  446.015361] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  446.015362] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  446.015364] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  446.015365] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  446.015366] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.015380] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  446.015394] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  446.015408] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  446.015415] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  446.015429] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  446.016883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  446.016899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  446.018879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  446.018882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  446.020880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  446.020896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  446.023154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  446.023158] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  446.023161] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  446.023170] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  446.023188] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  446.023636] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  446.023958] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  446.023974] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  446.023989] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  446.024015] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  446.024421] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  446.024749] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  446.025245] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  446.025246] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  446.025321] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  446.025322] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  446.025325] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  446.025326] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  446.025329] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  446.025330] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  446.025335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  446.025337] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  446.025339] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  446.025340] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  446.025342] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  446.025343] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  446.025344] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  446.025346] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  446.025347] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  446.025349] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  446.025350] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  446.025351] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  446.025353] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  446.025354] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  446.025355] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  446.025357] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  446.025358] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  446.025360] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  446.025361] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  446.025362] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  446.025364] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  446.025365] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  446.025366] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  446.025368] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  446.025369] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  446.025370] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  446.025372] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  446.025373] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  446.025375] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  446.025376] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  446.025377] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.025379] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.025380] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  446.025406] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  446.025420] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  446.026861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  446.026875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  446.028920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  446.028922] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  446.030880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  446.030896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  446.032944] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  446.032948] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  446.032950] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  446.041473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  446.041492] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  446.049943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.058400] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.066856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.075311] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.083766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.092221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.100675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.109181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.117642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.126100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.134569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.143034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.151500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.159967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.168431] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.176896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.185359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.193908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.202373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.210838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.219299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.227758] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.236214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.244673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.253159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.261616] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.270073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.278529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.286985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.295453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.303911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.312365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  446.312374] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  446.312379] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  446.312557] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  446.312571] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  446.313405] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  446.314932] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  446.314961] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  446.314991] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  446.315004] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  446.315830] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  446.316537] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  446.317345] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  446.317367] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  446.317369] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  446.317371] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  446.317372] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  446.317374] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  446.317375] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  446.317376] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  446.317378] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  446.317379] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  446.317380] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  446.317382] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  446.317383] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  446.317385] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.317549] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  446.317564] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  446.317581] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  446.317871] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  446.317892] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  446.319883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  446.319899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  446.321900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  446.321904] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  446.324166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  446.324182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  446.326443] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  446.326447] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  446.326449] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  446.326631] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  446.326648] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  446.327151] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  446.327465] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  446.327481] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  446.327495] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  446.327509] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  446.327930] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  446.328256] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  446.328875] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  446.328877] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  446.328969] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  446.328970] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  446.328973] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  446.328974] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  446.328977] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  446.328978] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  446.328983] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  446.328985] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  446.328987] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  446.328988] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  446.328989] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  446.328991] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  446.328992] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  446.328994] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  446.328995] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  446.328996] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  446.328998] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  446.328999] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  446.329000] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  446.329002] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  446.329003] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  446.329004] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  446.329006] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  446.329007] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  446.329009] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  446.329010] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  446.329011] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  446.329013] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  446.329014] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  446.329015] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  446.329017] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  446.329018] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  446.329019] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  446.329021] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  446.329022] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  446.329024] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  446.329025] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.329026] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  446.329028] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  446.329198] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  446.329213] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  446.330861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  446.330875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  446.332882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  446.332885] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  446.334793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  446.334809] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  446.336881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  446.336885] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  446.336887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  446.337090] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A
>[  446.337305] [drm:drm_mode_addfb2] [FB:68]
>[  446.343557] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  446.343566] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  446.369127] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  446.369191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  446.369224] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  446.369242] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  446.369327] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  446.386435] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  446.386468] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  446.386493] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  446.386525] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  446.386553] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  446.386606] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  446.395195] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  446.395228] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  446.395283] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  446.395476] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  446.395503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  446.395530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  446.395553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  446.395575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  446.395596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  446.395616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  446.395638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  446.395658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  446.395678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  446.395698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  446.396315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  446.396339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  446.396362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  446.396386] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  446.396413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  446.396438] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  446.396462] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  446.396485] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  446.396523] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  446.396547] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  446.409404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.418015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.426632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.435241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.443955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.452574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.461284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.469902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.478612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.487226] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.495943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.504559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.513201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.521727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.530215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.538690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.547170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.555641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.563465] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  446.578308] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  446.578326] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  446.578360] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  446.579200] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  446.581015] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  446.582891] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  446.582907] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  446.582921] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  446.582936] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  446.588074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  446.588089] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  446.593228] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  446.595713] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  446.596174] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  446.596204] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  446.596219] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  446.629737] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  446.629762] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  446.629801] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  446.629819] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  446.629835] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  446.629862] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  446.629879] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  446.630931] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  446.714548] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  446.714906] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  446.731692] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  446.731804] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  446.731866] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  446.731981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  446.732037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  446.732093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  446.732140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  446.732186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  446.732230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  446.732276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  446.732318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  446.732360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  446.732402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  446.732445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  446.732485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  446.732525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  446.732572] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  446.732628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  446.732680] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  446.732866] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  446.732939] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  446.733048] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  446.733117] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  446.733187] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  446.733292] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  446.733393] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  446.733485] [drm:intel_power_well_disable [i915]] disabling DC off
>[  446.733557] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  446.733615] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  446.734157] [drm:intel_power_well_disable [i915]] disabling always-on
>[  446.736756] [drm:drm_mode_addfb2] [FB:68]
>[  446.759142] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  446.759169] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  446.759327] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  446.759382] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  446.759442] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  446.759506] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  446.759556] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  446.759610] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  446.759662] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  446.759711] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  446.759819] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  446.759870] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  446.759916] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  446.759924] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  446.759966] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  446.759976] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  446.760020] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  446.760066] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  446.760107] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  446.760150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  446.760193] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  446.760247] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  446.760290] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  446.760335] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  446.760377] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  446.760420] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  446.760473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  446.760535] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  446.760586] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  446.761784] [drm:intel_power_well_enable [i915]] enabling always-on
>[  446.761825] [drm:intel_power_well_enable [i915]] enabling DC off
>[  446.762127] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  446.762187] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  446.762237] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  446.762335] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  446.762377] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  446.762443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  446.762497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  446.762545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  446.762591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  446.762635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  446.762679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  446.762772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  446.762819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  446.762864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  446.762904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  446.762950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  446.762994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  446.763035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  446.763086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  446.763142] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  446.763193] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  446.763242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  446.763303] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  446.763354] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  446.776511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.785243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.793974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.802698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.811515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.820240] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.828967] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.837692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.846502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.855231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.863898] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.872487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.881043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.889561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.898054] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.906534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.915005] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.923475] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  446.931300] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  446.945197] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  446.945213] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  446.945247] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  446.946080] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  446.946805] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  446.948579] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  446.948596] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  446.948612] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  446.948628] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  446.954537] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  446.954552] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  446.959719] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  446.962178] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  446.962652] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  446.962748] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  446.962762] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  446.979596] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  446.979619] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  446.979656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.063347] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  447.063552] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  447.082048] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  447.082117] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  447.082179] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  447.082293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  447.082350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  447.082406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  447.082454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  447.082500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  447.082546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  447.082593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  447.082637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  447.082680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  447.082810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  447.082864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  447.082913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  447.082955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  447.083011] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  447.083075] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  447.083133] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.083187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  447.083242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  447.083315] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  447.083363] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  447.083416] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  447.083483] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  447.083553] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  447.083613] [drm:intel_power_well_disable [i915]] disabling DC off
>[  447.083661] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  447.083704] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  447.084203] [drm:intel_power_well_disable [i915]] disabling always-on
>[  447.086043] [drm:drm_mode_addfb2] [FB:68]
>[  447.150831] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  447.150858] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  447.151018] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  447.151076] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  447.151135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  447.151199] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  447.151248] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  447.151302] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  447.151354] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  447.151405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  447.151453] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  447.151498] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  447.151541] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  447.151549] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  447.151591] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  447.151598] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  447.151641] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  447.151684] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  447.151816] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  447.151885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  447.151952] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  447.152028] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  447.152090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  447.152161] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  447.152224] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  447.152292] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  447.152401] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  447.152488] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  447.152561] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  447.156495] [drm:intel_power_well_enable [i915]] enabling always-on
>[  447.156536] [drm:intel_power_well_enable [i915]] enabling DC off
>[  447.156913] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  447.157390] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  447.157456] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  447.157556] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  447.157615] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  447.157708] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  447.157962] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  447.158040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  447.158122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  447.158194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  447.158264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  447.158327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  447.158396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  447.158461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  447.158526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  447.158586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  447.158651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  447.158710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  447.158837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  447.158902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  447.158976] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  447.159059] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.159138] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  447.159216] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  447.159307] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  447.159378] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  447.163072] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  447.163130] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  447.163181] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  447.163232] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  447.164544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  447.164599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  447.164649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  447.165674] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  447.165727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  447.165885] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  447.166850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  447.166904] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  447.168269] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  447.170667] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  447.172184] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  447.172272] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  447.172322] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  447.172389] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  447.172515] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  447.172564] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  447.189174] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  447.189250] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  447.189364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.272843] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  447.273018] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  447.273089] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  447.273211] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  447.289850] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  447.289920] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  447.289983] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  447.290095] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  447.292342] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  447.292408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  447.292470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  447.292525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  447.292573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  447.292620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  447.292668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  447.292717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  447.292842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  447.292888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  447.292936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  447.292989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  447.293034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  447.293078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  447.293130] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  447.293190] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  447.293246] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.293298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  447.293351] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  447.293429] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  447.293478] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  447.293527] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  447.293594] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  447.293666] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  447.293761] [drm:intel_power_well_disable [i915]] disabling DC off
>[  447.293812] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  447.293855] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  447.294311] [drm:intel_power_well_disable [i915]] disabling always-on
>[  447.297860] [drm:drm_mode_addfb2] [FB:68]
>[  447.365578] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  447.365607] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  447.366116] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  447.366177] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  447.366238] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  447.366285] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  447.366322] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  447.366361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  447.366400] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  447.366437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  447.366471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  447.366504] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  447.366537] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  447.366543] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  447.366575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  447.366579] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  447.366612] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  447.366644] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  447.366675] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  447.366705] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  447.367117] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  447.367159] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  447.367199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  447.367235] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  447.367269] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  447.367303] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  447.367359] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  447.367404] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  447.367442] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  447.370158] [drm:intel_power_well_enable [i915]] enabling always-on
>[  447.370186] [drm:intel_power_well_enable [i915]] enabling DC off
>[  447.370491] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  447.370534] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  447.370562] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  447.370636] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  447.370676] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  447.370932] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  447.371107] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  447.371147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  447.371185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  447.371221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  447.371254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  447.371286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  447.371317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  447.371348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  447.371377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  447.371406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  447.371435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  447.371462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  447.371490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  447.371518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  447.371551] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  447.371588] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.371623] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  447.371656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  447.371698] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  447.372100] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  447.375456] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  447.375486] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  447.375513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  447.375541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  447.376422] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  447.376450] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  447.376475] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  447.377273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  447.377300] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  447.377325] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  447.378125] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  447.378154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  447.379202] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  447.381518] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  447.382274] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  447.382313] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  447.382336] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  447.382367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  447.382561] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  447.382584] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  447.399163] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  447.399191] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  447.399234] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.482975] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  447.483153] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  447.483225] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  447.483345] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  447.499419] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  447.499489] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  447.499549] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  447.499662] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  447.500371] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  447.500430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  447.500488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  447.500540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  447.500588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  447.500634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  447.500679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  447.500809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  447.500854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  447.500901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  447.500943] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  447.500993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  447.501034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  447.501075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  447.501122] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  447.501180] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  447.501233] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.501284] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  447.501334] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  447.501407] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  447.501455] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  447.501502] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  447.501565] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  447.501636] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  447.501694] [drm:intel_power_well_disable [i915]] disabling DC off
>[  447.501779] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  447.501821] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  447.502272] [drm:intel_power_well_disable [i915]] disabling always-on
>[  447.504730] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  447.554479] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  447.554504] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  447.554530] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  447.554556] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  447.554578] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  447.554599] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  447.554622] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  447.554643] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  447.554664] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  447.554683] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  447.554736] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  447.554740] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  447.554759] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  447.554762] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  447.554781] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  447.554799] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  447.554817] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  447.554835] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  447.554852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  447.554875] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  447.554893] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  447.554911] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  447.554928] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  447.554946] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  447.554972] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  447.554993] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  447.555015] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  447.555040] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  447.555060] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  447.555081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  447.555101] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  447.555119] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  447.555137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  447.555154] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  447.555171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  447.555174] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  447.555191] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  447.555194] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  447.555212] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  447.555230] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  447.555247] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  447.555264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  447.555281] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  447.555303] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  447.555320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  447.555337] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  447.555354] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  447.555371] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  447.555393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  447.555419] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  447.555439] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  447.555461] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  447.555481] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  447.555653] [drm:intel_power_well_enable [i915]] enabling always-on
>[  447.555669] [drm:intel_power_well_enable [i915]] enabling DC off
>[  447.555963] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  447.555992] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  447.556010] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  447.556049] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  447.556076] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  447.556104] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  447.556122] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  447.556150] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  447.556339] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  447.556355] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  447.556382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  447.556405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  447.556426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  447.556446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  447.556465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  447.556484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  447.556504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  447.556522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  447.556540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  447.556558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  447.556575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  447.556593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  447.556610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  447.556630] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  447.556653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.556675] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  447.556703] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  447.556747] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  447.556768] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  447.569304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.577817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.586327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.594836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.603345] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.611854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.620364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.628874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.637383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.645892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.654399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.662910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.671420] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.679970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.688497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.715714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  447.723590] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  447.738331] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  447.738349] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  447.738383] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  447.739234] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  447.741878] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  447.743223] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  447.743238] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  447.743251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  447.743266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  447.748412] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  447.748427] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  447.753574] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  447.756068] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  447.756673] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  447.756763] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  447.756776] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  447.756824] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  447.756836] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  447.760092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  447.760108] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  447.760122] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  447.760137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  447.760810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  447.760837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  447.760867] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  447.761514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  447.761541] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  447.761569] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  447.762216] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  447.762230] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  447.763185] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  447.765460] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  447.765973] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  447.765996] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  447.766008] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  447.766028] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  447.782800] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  447.782820] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  447.782856] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  447.782894] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  447.782912] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  447.782945] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  447.783149] Console: switching to colour frame buffer device 240x75
>[  447.966110] Console: switching to colour dummy device 80x25
>[  447.966214] [IGT] kms_pipe_crc_basic: executing
>[  447.974627] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  447.974700] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  447.983438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  447.992135] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.000765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.009296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.017784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.026262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.034730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.043185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.051639] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.060092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.068546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.077000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.085452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.093905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.102357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.110810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.119263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.127716] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.136168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.144622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.153076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.161532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.169986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.178451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.186905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.195357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.203812] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.212264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.220718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.229170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.237622] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.246076] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.246085] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  448.246088] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  448.246100] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  448.246115] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  448.246950] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  448.248468] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  448.248484] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  448.248498] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  448.248512] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  448.249310] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  448.250020] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  448.250800] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  448.250837] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  448.250839] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  448.250841] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  448.250842] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  448.250844] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  448.250845] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  448.250846] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  448.250848] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  448.250849] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  448.250851] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  448.250852] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  448.250853] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  448.250855] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  448.250868] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  448.250883] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  448.250899] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  448.250906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  448.250920] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  448.252881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  448.252897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  448.254879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  448.254882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  448.256930] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  448.256946] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  448.258884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  448.258887] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  448.258890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  448.258899] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  448.258917] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  448.259363] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  448.259673] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  448.259693] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  448.259723] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  448.259759] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  448.260162] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  448.260472] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  448.260964] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  448.260966] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  448.261044] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  448.261045] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  448.261048] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  448.261049] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  448.261052] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  448.261053] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  448.261059] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  448.261061] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  448.261062] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  448.261063] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  448.261065] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  448.261066] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  448.261067] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  448.261069] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  448.261070] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  448.261072] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  448.261073] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  448.261074] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  448.261076] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  448.261077] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  448.261078] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  448.261080] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  448.261081] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  448.261083] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  448.261084] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  448.261085] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  448.261087] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  448.261088] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  448.261089] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  448.261091] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  448.261092] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  448.261094] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  448.261095] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  448.261096] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  448.261098] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  448.261099] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  448.261100] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  448.261102] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  448.261103] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  448.261129] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  448.261144] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  448.262862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  448.262876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  448.264881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  448.264884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  448.266880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  448.266896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  448.268883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  448.268887] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  448.268889] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  448.277183] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  448.277200] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  448.285662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.294161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.302620] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.311078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.319539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.327996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.336452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.344909] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.353365] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.361825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.370281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.378738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.387193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.395649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.404105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.412649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.421106] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.429563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.438021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.446478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.454934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.463392] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.471849] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.480304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.488761] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.497217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.505674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.514164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.522621] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.531078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.539535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.547991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  448.548000] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  448.548003] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  448.548192] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  448.548206] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  448.549043] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  448.550583] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  448.550600] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  448.550614] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  448.550641] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  448.551440] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  448.552152] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  448.552960] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  448.552985] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  448.552999] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  448.553001] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  448.553003] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  448.553004] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  448.553005] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  448.553007] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  448.553008] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  448.553010] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  448.553011] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  448.553012] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  448.553014] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  448.553015] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  448.553274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  448.553289] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  448.553306] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  448.553451] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  448.553466] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  448.554841] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  448.554855] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  448.556876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  448.556879] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  448.558879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  448.558894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  448.560879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  448.560883] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  448.560885] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  448.561068] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  448.561084] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  448.561532] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  448.561896] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  448.561913] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  448.561928] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  448.561954] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  448.562374] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  448.562686] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  448.563261] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  448.563263] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  448.563337] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  448.563339] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  448.563342] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  448.563343] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  448.563346] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  448.563347] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  448.563352] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  448.563354] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  448.563356] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  448.563357] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  448.563358] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  448.563360] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  448.563361] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  448.563362] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  448.563364] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  448.563365] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  448.563367] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  448.563368] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  448.563369] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  448.563371] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  448.563372] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  448.563373] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  448.563375] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  448.563376] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  448.563377] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  448.563379] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  448.563380] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  448.563382] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  448.563383] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  448.563384] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  448.563386] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  448.563387] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  448.563388] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  448.563390] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  448.563391] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  448.563392] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  448.563394] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  448.563395] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  448.563396] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  448.563572] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  448.563587] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  448.564787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  448.564802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  448.566878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  448.566882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  448.568975] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  448.568991] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  448.570884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  448.570888] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  448.570890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  448.571104] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-A-frame-sequence
>[  448.571319] [drm:drm_mode_addfb2] [FB:69]
>[  448.577429] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  448.577438] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  448.607545] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  448.607598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  448.607618] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  448.607633] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  448.607691] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  448.624875] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  448.624897] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  448.624917] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  448.624942] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  448.624969] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  448.625006] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  448.633747] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  448.633772] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  448.633816] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  448.633991] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  448.634013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  448.634033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  448.634051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  448.634068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  448.634084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  448.634101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  448.634117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  448.634133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  448.634148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  448.634163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  448.634180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  448.634195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  448.634209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  448.634226] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  448.634247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  448.634266] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  448.634284] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  448.634301] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  448.634331] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  448.634349] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  448.647115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.655648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.664238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.672780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.681320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.689861] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.717433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.725972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.734511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.743033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.751547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.760032] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.768509] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.777097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.785569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.794039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  448.801864] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  448.816007] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  448.816026] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  448.816100] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  448.817369] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  448.819333] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  448.821233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  448.821249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  448.821263] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  448.821278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  448.826417] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  448.826433] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  448.831583] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  448.834072] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  448.834631] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  448.834661] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  448.834676] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  448.868179] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  448.868204] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  448.868242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  448.868261] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  448.868277] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  448.868303] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  448.868321] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  448.869340] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  448.935242] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  448.935409] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  448.954118] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  448.954188] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  448.954250] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  448.954364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  448.954421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  448.954476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  448.954523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  448.954569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  448.954614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  448.954661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  448.954704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  448.954893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  448.954955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  448.955027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  448.955085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  448.955150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  448.955224] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  448.955311] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  448.955392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  448.955469] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  448.955544] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  448.955651] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  448.955725] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  448.955855] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  448.955956] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  448.956063] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  448.956154] [drm:intel_power_well_disable [i915]] disabling DC off
>[  448.956228] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  448.956292] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  448.956827] [drm:intel_power_well_disable [i915]] disabling always-on
>[  448.960357] [drm:drm_mode_addfb2] [FB:69]
>[  448.982551] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  448.982581] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  448.982743] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  448.983078] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  448.983144] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  448.983214] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  448.983267] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  448.983325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  448.983381] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  448.983436] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  448.983489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  448.983539] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  448.983586] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  448.983595] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  448.983641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  448.983648] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  448.983696] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  448.984519] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  448.984568] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  448.984616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  448.984661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  448.984718] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  448.985078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  448.985126] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  448.985175] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  448.985220] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  448.985276] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  448.985340] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  448.985393] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  448.986960] [drm:intel_power_well_enable [i915]] enabling always-on
>[  448.987004] [drm:intel_power_well_enable [i915]] enabling DC off
>[  448.987309] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  448.987373] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  448.987424] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  448.987519] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  448.987572] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  448.987639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  448.987695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  448.988228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  448.988280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  448.988330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  448.988376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  448.988426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  448.988470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  448.988514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  448.988556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  448.988601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  448.988643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  448.988685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  448.989304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  448.989360] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  448.989411] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  448.989460] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  448.989520] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  448.989571] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  449.002851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.011653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.020526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.029243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.037969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.046690] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.055451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.064175] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.072942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.081665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.090539] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.099156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.107750] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.116275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.124800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.133287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.141777] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.150246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.156383] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  449.171425] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  449.171442] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  449.171493] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  449.172320] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  449.174109] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  449.175994] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  449.176010] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  449.176024] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  449.176039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  449.181190] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  449.181205] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  449.186358] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  449.188838] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  449.189301] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  449.189367] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  449.189381] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  449.206236] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  449.206256] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  449.206289] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.290022] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  449.290200] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  449.306820] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  449.306891] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  449.306952] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  449.307067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  449.307123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  449.307180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  449.307228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  449.307274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  449.307318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  449.307365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  449.307408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  449.307451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  449.307497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  449.307561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  449.307621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  449.307663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  449.307710] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  449.307859] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  449.307918] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.307971] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  449.308024] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  449.308103] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  449.308167] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  449.308229] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  449.308333] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  449.308439] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  449.308532] [drm:intel_power_well_disable [i915]] disabling DC off
>[  449.308604] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  449.308668] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  449.309196] [drm:intel_power_well_disable [i915]] disabling always-on
>[  449.311454] [drm:drm_mode_addfb2] [FB:69]
>[  449.382637] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  449.382666] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  449.382957] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  449.383041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  449.383128] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  449.383195] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  449.383248] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  449.383305] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  449.383360] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  449.383412] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  449.383462] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  449.383510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  449.383555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  449.383567] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  449.383610] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  449.383619] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  449.383665] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  449.383714] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  449.383831] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  449.383897] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  449.383958] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  449.384038] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  449.384106] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  449.384173] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  449.384235] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  449.384299] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  449.384404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  449.384490] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  449.384561] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  449.388294] [drm:intel_power_well_enable [i915]] enabling always-on
>[  449.388334] [drm:intel_power_well_enable [i915]] enabling DC off
>[  449.388636] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  449.388697] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  449.388828] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  449.388935] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  449.389001] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  449.389098] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  449.389308] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  449.389368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  449.389426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  449.389479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  449.389529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  449.389576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  449.389622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  449.389668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  449.389718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  449.389847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  449.389911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  449.389976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  449.390037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  449.390102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  449.390171] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  449.390251] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.390323] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  449.390396] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  449.390481] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  449.390551] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  449.394251] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  449.394310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  449.394361] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  449.394414] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  449.395457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  449.395510] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  449.395560] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  449.396546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  449.396598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  449.396645] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  449.397556] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  449.397610] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  449.398834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  449.401256] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  449.402711] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  449.402823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  449.402875] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  449.402943] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  449.403067] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  449.403118] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  449.419711] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  449.419839] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  449.419951] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.503230] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  449.503384] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  449.503450] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  449.503559] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  449.521811] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  449.521881] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  449.521950] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  449.522107] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  449.524316] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  449.524382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  449.524446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  449.524502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  449.524552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  449.524601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  449.524650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  449.524700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  449.524858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  449.524909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  449.524956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  449.525006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  449.525049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  449.525093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  449.525142] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  449.525200] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  449.525255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.525306] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  449.525358] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  449.525435] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  449.525483] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  449.525531] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  449.525597] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  449.525668] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  449.525770] [drm:intel_power_well_disable [i915]] disabling DC off
>[  449.525817] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  449.525859] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  449.526313] [drm:intel_power_well_disable [i915]] disabling always-on
>[  449.528525] [drm:drm_mode_addfb2] [FB:69]
>[  449.591928] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  449.591949] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  449.592066] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  449.592107] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  449.592150] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  449.592196] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  449.592232] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  449.592272] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  449.592310] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  449.592346] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  449.592381] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  449.592414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  449.592446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  449.592452] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  449.592484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  449.592489] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  449.592521] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  449.592553] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  449.592584] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  449.592614] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  449.592643] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  449.592681] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  449.592782] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  449.592830] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  449.592876] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  449.592918] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  449.592990] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  449.593051] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  449.593104] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  449.595074] [drm:intel_power_well_enable [i915]] enabling always-on
>[  449.595096] [drm:intel_power_well_enable [i915]] enabling DC off
>[  449.595379] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  449.595412] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  449.595434] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  449.595488] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  449.595521] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  449.595556] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  449.597767] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  449.597804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  449.597838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  449.597867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  449.597894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  449.597919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  449.597944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  449.597970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  449.597993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  449.598017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  449.598040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  449.598062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  449.598085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  449.598108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  449.598134] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  449.598177] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.598199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  449.598222] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  449.598250] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  449.598272] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  449.601605] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  449.601630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  449.601652] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  449.601675] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  449.602430] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  449.602452] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  449.602473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  449.603169] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  449.603186] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  449.603203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  449.603866] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  449.603885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  449.604859] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  449.607126] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  449.607666] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  449.607769] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  449.607788] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  449.607814] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  449.607990] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  449.608009] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  449.624510] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  449.624539] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  449.624582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.714467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  449.714626] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  449.714691] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  449.715526] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  449.725281] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  449.725348] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  449.725409] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  449.725519] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  449.725683] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  449.726236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  449.726295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  449.726348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  449.726395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  449.726441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  449.726486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  449.726533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  449.726576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  449.726618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  449.726660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  449.726709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  449.727521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  449.727571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  449.727624] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  449.727685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  449.728101] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.728161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  449.728213] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  449.728281] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  449.728328] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  449.728373] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  449.728437] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  449.728510] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  449.728568] [drm:intel_power_well_disable [i915]] disabling DC off
>[  449.728615] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  449.728655] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  449.730112] [drm:intel_power_well_disable [i915]] disabling always-on
>[  449.731444] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  449.761307] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  449.761328] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  449.761351] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  449.761375] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  449.761394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  449.761414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  449.761433] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  449.761451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  449.761470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  449.761487] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  449.761503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  449.761507] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  449.761523] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  449.761526] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  449.761542] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  449.761558] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  449.761574] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  449.761590] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  449.761606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  449.761625] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  449.761641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  449.761656] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  449.761671] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  449.761687] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  449.761725] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  449.761743] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  449.761764] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  449.761786] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  449.761805] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  449.761823] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  449.761842] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  449.761858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  449.761875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  449.761890] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  449.761906] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  449.761908] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  449.761924] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  449.761926] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  449.761942] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  449.761958] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  449.761973] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  449.761988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  449.762002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  449.762021] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  449.762036] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  449.762052] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  449.762067] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  449.762082] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  449.762101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  449.762123] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  449.762142] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  449.762161] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  449.762179] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  449.762242] [drm:intel_power_well_enable [i915]] enabling always-on
>[  449.762257] [drm:intel_power_well_enable [i915]] enabling DC off
>[  449.762533] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  449.762558] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  449.762575] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  449.762608] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  449.762632] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  449.762657] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  449.762672] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  449.762695] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  449.762883] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  449.762897] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  449.762919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  449.762939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  449.762956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  449.762973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  449.762989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  449.763005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  449.763021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  449.763037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  449.763052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  449.763066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  449.763081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  449.763096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  449.763110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  449.763139] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  449.763156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.763171] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  449.763187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  449.763205] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  449.763220] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  449.775283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.783795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.792305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.800814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.809323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.817832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.826339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.834847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.843355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.851862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.860381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.868897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.877408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.885920] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.894429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.902938] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.911449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.919958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.928468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  449.929563] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  449.944361] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  449.944424] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  449.944542] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  449.946346] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  449.949314] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  449.951822] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  449.951874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  449.951924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  449.951975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  449.957406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  449.957459] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  449.962901] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  449.965555] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  449.967207] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  449.967342] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  449.967393] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  449.967554] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  449.967602] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  449.971299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  449.971356] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  449.971405] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  449.971457] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  449.972438] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  449.972488] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  449.972535] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  449.973460] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  449.973509] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  449.973557] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  449.974475] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  449.974525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  449.975817] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  449.978213] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeae98
>[  449.979826] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  449.979905] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  449.979954] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  449.980024] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  449.996882] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  449.996960] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  449.997087] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  449.997225] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  449.997294] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  449.997412] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  449.997958] Console: switching to colour frame buffer device 240x75
>[  450.466211] Console: switching to colour dummy device 80x25
>[  450.466319] [IGT] kms_pipe_crc_basic: executing
>[  450.480485] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  450.480559] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  450.489166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.497627] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.506087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.514546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.523006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.531462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.539919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.548377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.556833] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.565292] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.573767] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.582224] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.590681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.599152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.607608] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.616080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.624537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.633077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.641535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.649992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.658448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.666907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.675363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.683818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.692276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.720745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.729200] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.737657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.746114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.754572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.763127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.771584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.771598] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  450.771604] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  450.771618] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  450.771633] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  450.772482] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  450.774005] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  450.774035] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  450.774064] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  450.774077] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  450.774874] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  450.775580] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  450.776362] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  450.776399] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  450.776401] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  450.776402] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  450.776404] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  450.776405] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  450.776407] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  450.776408] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  450.776409] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  450.776411] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  450.776412] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  450.776414] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  450.776415] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  450.776416] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  450.776430] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  450.776444] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  450.776457] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  450.776464] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  450.776478] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  450.777884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  450.777900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  450.779880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  450.779884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  450.781880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  450.781895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  450.783884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  450.783888] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  450.783890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  450.783900] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  450.783917] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  450.784376] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  450.784689] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  450.784720] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  450.784735] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  450.784749] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  450.785185] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  450.785496] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  450.785996] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  450.785998] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  450.786072] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  450.786074] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  450.786077] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  450.786078] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  450.786081] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  450.786082] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  450.786087] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  450.786089] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  450.786091] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  450.786092] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  450.786093] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  450.786095] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  450.786096] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  450.786098] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  450.786099] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  450.786100] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  450.786102] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  450.786103] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  450.786104] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  450.786106] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  450.786107] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  450.786109] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  450.786110] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  450.786111] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  450.786113] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  450.786114] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  450.786115] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  450.786117] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  450.786118] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  450.786120] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  450.786121] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  450.786122] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  450.786124] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  450.786125] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  450.786126] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  450.786128] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  450.786129] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  450.786130] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  450.786132] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  450.786158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  450.786173] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  450.787791] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  450.787805] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  450.789837] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  450.789839] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  450.791879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  450.791895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  450.793884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  450.793888] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  450.793890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  450.802522] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  450.802538] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  450.810993] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.819453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.827911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.836367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.844825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.853283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.861742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.870200] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.878658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.887118] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.895576] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.904033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.912492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.920951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.929407] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.937864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.946320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.954779] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.963236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.971695] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.980196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.988654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  450.997111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.005569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.014028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.022486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.030944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.039401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.047858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.056316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.064776] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.073234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  451.073244] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  451.073247] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  451.073433] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  451.073450] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  451.074390] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  451.075985] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  451.076001] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  451.076016] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  451.076030] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  451.076854] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  451.077564] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  451.078345] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  451.078372] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  451.078374] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  451.078376] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  451.078378] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  451.078379] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  451.078381] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  451.078383] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  451.078384] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  451.078386] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  451.078387] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  451.078389] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  451.078403] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  451.078404] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  451.078570] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  451.078585] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  451.078601] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  451.079200] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  451.079216] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  451.080883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  451.080899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  451.082883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  451.082887] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  451.085147] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  451.085163] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  451.087415] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  451.087419] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  451.087421] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  451.087618] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  451.087634] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  451.088181] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  451.088494] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  451.088510] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  451.088525] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  451.088539] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  451.088968] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  451.089293] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  451.089856] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  451.089858] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  451.089963] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  451.089964] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  451.089967] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  451.089968] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  451.089971] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  451.089972] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  451.089979] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  451.089980] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  451.089982] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  451.089983] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  451.089984] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  451.089986] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  451.089987] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  451.089989] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  451.089990] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  451.089992] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  451.089993] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  451.089994] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  451.089996] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  451.089997] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  451.089998] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  451.090000] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  451.090001] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  451.090003] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  451.090004] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  451.090005] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  451.090007] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  451.090008] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  451.090009] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  451.090011] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  451.090012] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  451.090013] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  451.090015] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  451.090016] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  451.090017] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  451.090019] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  451.090020] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  451.090021] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  451.090023] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  451.090194] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  451.090209] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  451.091880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  451.091896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  451.093877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  451.093881] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  451.095880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  451.095896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  451.097881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  451.097885] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  451.097887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  451.098100] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B
>[  451.098311] [drm:drm_mode_addfb2] [FB:70]
>[  451.104566] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  451.104609] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  451.104686] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  451.119688] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  451.119735] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  451.119751] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  451.119782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  451.119797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  451.119812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  451.119824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  451.119836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  451.119848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  451.119860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  451.119871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  451.119882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  451.119893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  451.119903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  451.119915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  451.119925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  451.119938] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  451.119952] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  451.119966] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.119979] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  451.119992] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  451.130067] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  451.130083] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  451.130108] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  451.130127] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  451.130235] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  451.130244] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  451.130294] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  451.130310] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  451.130327] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  451.130346] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  451.130360] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  451.130375] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  451.130391] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  451.130405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  451.130419] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  451.130433] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  451.130445] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  451.130448] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  451.130460] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  451.130462] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  451.130475] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  451.130487] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  451.130500] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  451.130512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  451.130524] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  451.130539] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  451.130552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  451.130565] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  451.130577] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  451.130589] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  451.130602] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  451.130624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.130642] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  451.130657] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  451.131621] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  451.131635] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  451.131656] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  451.131677] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  451.131934] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  451.148599] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  451.148624] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  451.148650] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  451.148930] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  451.148954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  451.148975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  451.148993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  451.149011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  451.149028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  451.149044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  451.149060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  451.149075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  451.149091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  451.149105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  451.149123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  451.149138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  451.149152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  451.149169] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  451.149189] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  451.149208] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.149226] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  451.149243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  451.149265] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  451.149283] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  451.162047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.170567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.179085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.187600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.196113] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.204626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.213139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.221651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.230232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.238745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.247251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.255741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.264222] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.272691] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.281174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.289642] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.298111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.306638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.315108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.316211] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  451.331017] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  451.331033] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  451.331084] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  451.331910] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  451.334155] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  451.335599] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  451.335615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  451.335629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  451.335644] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  451.340815] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  451.340831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  451.346001] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  451.348483] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  451.349027] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  451.365965] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  451.366016] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  451.366144] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  451.366231] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  451.366345] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.382675] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  451.449685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.450011] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  451.466430] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  451.466499] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  451.466616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  451.466673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  451.466858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  451.466918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  451.466966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  451.467010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  451.467058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  451.467102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  451.467145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  451.467187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  451.467233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  451.467275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  451.467316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  451.467364] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  451.467422] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  451.467476] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.467527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  451.467577] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  451.467656] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  451.467703] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  451.467788] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  451.467852] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  451.467923] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  451.467975] [drm:intel_power_well_disable [i915]] disabling DC off
>[  451.468022] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  451.468062] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  451.468513] [drm:intel_power_well_disable [i915]] disabling always-on
>[  451.470838] [drm:drm_mode_addfb2] [FB:70]
>[  451.493230] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  451.493259] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  451.493428] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  451.493486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  451.493551] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  451.493618] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  451.493671] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  451.493727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  451.493883] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  451.493960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  451.494043] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  451.494117] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  451.494189] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  451.494206] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  451.494274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  451.494290] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  451.494361] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  451.494433] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  451.494507] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  451.494580] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  451.494651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  451.494734] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  451.494843] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  451.494916] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  451.494992] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  451.495065] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  451.495148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.495238] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  451.495315] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  451.496627] [drm:intel_power_well_enable [i915]] enabling always-on
>[  451.496668] [drm:intel_power_well_enable [i915]] enabling DC off
>[  451.497062] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  451.497523] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  451.497587] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  451.497687] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  451.497818] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  451.497920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  451.498007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  451.498085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  451.498165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  451.498238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  451.498312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  451.498389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  451.498456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  451.498532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  451.498603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  451.498677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  451.498769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  451.498833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  451.498905] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  451.498988] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.499066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  451.499150] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  451.499241] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  451.499319] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  451.512615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.521470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.530210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.538937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.547663] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.556595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.565333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.574131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.582858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.591582] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.600261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.608862] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.617482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.625998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.634491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.642970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.651442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.659912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  451.666053] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  451.681154] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  451.681169] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  451.681221] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  451.682051] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  451.684311] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  451.685720] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  451.685735] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  451.685749] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  451.685764] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  451.690903] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  451.690919] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  451.715729] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  451.718213] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  451.718677] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  451.735583] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  451.735605] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  451.735640] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.819423] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  451.819626] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  451.837853] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  451.837920] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  451.838037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  451.838095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  451.838150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  451.838197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  451.838242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  451.838286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  451.838332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  451.838375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  451.838417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  451.838458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  451.838502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  451.838542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  451.838581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  451.838629] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  451.838685] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  451.838882] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.838960] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  451.839032] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  451.839147] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  451.839217] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  451.839287] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  451.839391] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  451.839500] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  451.839582] [drm:intel_power_well_disable [i915]] disabling DC off
>[  451.839655] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  451.839719] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  451.840272] [drm:intel_power_well_disable [i915]] disabling always-on
>[  451.842675] [drm:drm_mode_addfb2] [FB:70]
>[  451.908405] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  451.908435] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  451.908607] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  451.908665] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  451.908728] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  451.909436] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  451.909493] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  451.909551] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  451.909609] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  451.909662] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  451.909714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  451.910396] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  451.910446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  451.910455] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  451.910503] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  451.910510] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  451.910560] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  451.910607] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  451.910653] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  451.910698] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  451.911606] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  451.911664] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  451.911716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  451.912133] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  451.912183] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  451.912230] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  451.912308] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  451.912373] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  451.912426] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  451.916617] [drm:intel_power_well_enable [i915]] enabling always-on
>[  451.916660] [drm:intel_power_well_enable [i915]] enabling DC off
>[  451.917319] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  451.917646] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  451.917699] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  451.918148] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  451.918191] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  451.918258] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  451.920659] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  451.920727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  451.921169] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  451.921227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  451.921280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  451.921329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  451.921378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  451.921429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  451.921476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  451.921522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  451.921567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  451.921612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  451.921656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  451.921701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  451.922370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  451.922431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  451.922488] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  451.922541] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  451.922608] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  451.922662] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  451.924484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  451.924540] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  451.924590] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  451.924642] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  451.925561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  451.925611] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  451.925657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  451.926682] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  451.926780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  451.926828] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  451.927701] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  451.927855] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  451.929128] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  451.931530] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  451.932999] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  451.933083] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  451.933133] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  451.933201] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  451.950006] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  451.950084] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  451.950199] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  452.033663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  452.033980] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  452.034067] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  452.034239] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  452.050870] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  452.050938] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  452.051053] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  452.051299] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  452.051356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  452.051412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  452.051463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  452.051510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  452.051554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  452.051598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  452.051643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  452.051685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  452.051811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  452.051866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  452.051925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  452.051969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  452.052016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  452.052071] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  452.052133] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  452.052193] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  452.052247] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  452.052302] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  452.052385] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  452.052454] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  452.052528] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  452.052634] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  452.052740] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  452.052882] [drm:intel_power_well_disable [i915]] disabling DC off
>[  452.052959] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  452.053023] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  452.053525] [drm:intel_power_well_disable [i915]] disabling always-on
>[  452.055831] [drm:drm_mode_addfb2] [FB:70]
>[  452.116980] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  452.116996] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  452.117089] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  452.117118] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  452.117151] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  452.117186] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  452.117213] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  452.117241] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  452.117269] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  452.117295] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  452.117321] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  452.117345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  452.117368] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  452.117372] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  452.117395] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  452.117398] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  452.117422] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  452.117444] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  452.117467] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  452.117490] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  452.117511] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  452.117539] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  452.117561] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  452.117583] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  452.117605] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  452.117626] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  452.117663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  452.117694] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  452.117940] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  452.119862] [drm:intel_power_well_enable [i915]] enabling always-on
>[  452.119880] [drm:intel_power_well_enable [i915]] enabling DC off
>[  452.120158] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  452.120184] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  452.120202] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  452.120246] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  452.120274] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  452.120303] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  452.122588] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  452.122616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  452.122643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  452.122667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  452.122688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  452.122814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  452.122842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  452.122874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  452.122901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  452.122930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  452.122955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  452.122984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  452.123010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  452.123037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  452.123066] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  452.123101] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  452.123135] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  452.123165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  452.123204] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  452.123233] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  452.126501] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  452.126522] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  452.126540] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  452.126559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  452.127380] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  452.127400] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  452.127418] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  452.128204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  452.128224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  452.128242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  452.129044] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  452.129064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  452.130030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  452.132314] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  452.132886] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  452.132922] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  452.132939] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  452.132961] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  452.149729] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  452.149751] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  452.149785] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  452.233483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  452.233665] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  452.233902] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  452.234076] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  452.250135] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  452.250204] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  452.250319] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  452.250524] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  452.250581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  452.250637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  452.250690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  452.250840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  452.250913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  452.250977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  452.251047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  452.251116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  452.251178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  452.251244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  452.251316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  452.251376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  452.251442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  452.251509] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  452.251595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  452.251676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  452.251819] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  452.251896] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  452.252006] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  452.252079] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  452.252152] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  452.252252] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  452.252358] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  452.252439] [drm:intel_power_well_disable [i915]] disabling DC off
>[  452.252510] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  452.252570] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  452.253110] [drm:intel_power_well_disable [i915]] disabling always-on
>[  452.254811] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  452.305398] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  452.305423] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  452.305449] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  452.305476] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  452.305498] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  452.305521] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  452.305545] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  452.305565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  452.305586] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  452.305606] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  452.305625] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  452.305629] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  452.305648] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  452.305651] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  452.305670] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  452.305691] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  452.305732] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  452.305749] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  452.305767] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  452.305789] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  452.305807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  452.305824] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  452.305842] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  452.305859] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  452.305886] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  452.305907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  452.305929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  452.305954] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  452.305974] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  452.305996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  452.306015] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  452.306034] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  452.306052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  452.306070] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  452.306087] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  452.306090] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  452.306107] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  452.306109] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  452.306127] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  452.306144] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  452.306161] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  452.306178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  452.306195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  452.306216] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  452.306234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  452.306251] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  452.306267] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  452.306284] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  452.306306] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  452.306332] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  452.306352] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  452.306373] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  452.306392] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  452.306473] [drm:intel_power_well_enable [i915]] enabling always-on
>[  452.306489] [drm:intel_power_well_enable [i915]] enabling DC off
>[  452.306785] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  452.306815] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  452.306833] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  452.306870] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  452.306887] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  452.306909] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  452.306927] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  452.306954] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  452.307087] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  452.307103] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  452.307130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  452.307153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  452.307174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  452.307194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  452.307212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  452.307231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  452.307250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  452.307268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  452.307285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  452.307303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  452.307320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  452.307337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  452.307354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  452.307375] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  452.307398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  452.307420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  452.307442] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  452.307467] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  452.307488] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  452.319544] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.328058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.336568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.345078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.353586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.362098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.370612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.379125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.387638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.396147] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.404655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.413165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.421675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.430203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.438712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.447278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.455801] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.464312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.472824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  452.473921] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  452.488367] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  452.488385] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  452.488419] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  452.489556] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  452.492170] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  452.493515] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  452.493530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  452.493543] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  452.493558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  452.498719] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  452.498734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  452.503882] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  452.506404] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8958
>[  452.506943] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  452.506993] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  452.507007] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  452.507058] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  452.507071] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  452.509936] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  452.509952] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  452.509966] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  452.509981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  452.510640] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  452.510654] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  452.510667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  452.511316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  452.511330] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  452.511343] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  452.511989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  452.512003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  452.512961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  452.515223] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  452.515764] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  452.515789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  452.515803] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  452.515824] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  452.532593] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  452.532615] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  452.532653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  452.532694] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  452.532731] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  452.532767] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  452.532920] Console: switching to colour frame buffer device 240x75
>[  452.957399] Console: switching to colour dummy device 80x25
>[  452.957502] [IGT] kms_pipe_crc_basic: executing
>[  452.971524] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  452.971598] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  452.980251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  452.988708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  452.997163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.005617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.014087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.022541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.030996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.039451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.047907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.056359] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.064814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.073269] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.081724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.090178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.098634] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.107087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.115541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.123996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.132451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.140905] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.149360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.157814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.166269] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.174724] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.183179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.191633] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.200087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.208543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.216997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.225452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.233906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.242445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.242453] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  453.242457] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  453.242469] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  453.242498] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  453.243350] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  453.244917] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  453.244933] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  453.244947] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  453.244961] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  453.245807] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  453.246515] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  453.247304] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  453.247339] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  453.247342] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  453.247343] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  453.247345] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  453.247346] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  453.247347] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  453.247349] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  453.247350] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  453.247352] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  453.247353] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  453.247354] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  453.247356] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  453.247357] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  453.247370] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  453.247385] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  453.247403] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  453.247410] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  453.247424] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  453.248883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  453.248899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  453.250880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  453.250883] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  453.252879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  453.252895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  453.254878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  453.254881] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  453.254884] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  453.254893] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  453.254911] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  453.255359] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  453.255674] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  453.255690] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  453.255750] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  453.255795] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  453.256274] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  453.256598] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  453.257115] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  453.257117] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  453.257194] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  453.257196] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  453.257199] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  453.257200] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  453.257202] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  453.257203] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  453.257209] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  453.257211] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  453.257212] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  453.257214] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  453.257215] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  453.257217] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  453.257218] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  453.257220] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  453.257221] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  453.257222] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  453.257224] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  453.257225] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  453.257227] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  453.257228] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  453.257229] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  453.257231] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  453.257232] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  453.257234] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  453.257235] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  453.257236] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  453.257238] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  453.257239] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  453.257241] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  453.257242] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  453.257243] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  453.257245] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  453.257246] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  453.257248] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  453.257249] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  453.257250] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  453.257252] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  453.257253] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  453.257255] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  453.257282] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  453.257297] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  453.258864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  453.258878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  453.260937] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  453.260941] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  453.262879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  453.262895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  453.264923] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  453.264926] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  453.264928] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  453.273713] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  453.273734] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  453.282190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.290646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.299103] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.307558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.316013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.324470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.332926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.341381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.349837] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.358291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.366750] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.375208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.383665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.392219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.400674] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.409263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.417725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.426185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.434644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.443102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.451559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.460016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.468476] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.476934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.485393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.493851] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.502307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.510764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.519219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.527677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.536154] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.544609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  453.544618] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  453.544621] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  453.544896] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  453.544912] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  453.545757] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  453.547277] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  453.547293] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  453.547308] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  453.547322] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  453.548118] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  453.548827] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  453.549600] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  453.549625] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  453.549627] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  453.549629] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  453.549630] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  453.549632] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  453.549634] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  453.549648] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  453.549649] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  453.549651] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  453.549652] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  453.549653] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  453.549655] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  453.549656] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  453.549923] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  453.549953] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  453.549987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  453.550158] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  453.550172] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  453.551884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  453.551900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  453.553900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  453.553903] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  453.556156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  453.556172] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  453.558431] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  453.558435] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  453.558437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  453.558624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  453.558642] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  453.559095] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  453.559408] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  453.559424] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  453.559438] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  453.559451] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  453.559859] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  453.560171] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  453.560660] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  453.560662] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  453.560813] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  453.560815] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  453.560818] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  453.560819] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  453.560822] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  453.560824] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  453.560829] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  453.560831] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  453.560833] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  453.560835] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  453.560836] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  453.560838] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  453.560839] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  453.560841] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  453.560843] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  453.560844] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  453.560846] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  453.560847] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  453.560849] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  453.560850] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  453.560852] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  453.560853] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  453.560855] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  453.560856] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  453.560858] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  453.560859] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  453.560861] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  453.560863] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  453.560864] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  453.560866] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  453.560867] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  453.560869] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  453.560870] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  453.560872] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  453.560873] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  453.560875] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  453.560876] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  453.560878] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  453.560879] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  453.561060] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  453.561077] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  453.562839] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  453.562853] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  453.564884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  453.564888] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  453.566879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  453.566895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  453.568989] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  453.568994] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  453.568997] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  453.569220] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-B-frame-sequence
>[  453.569455] [drm:drm_mode_addfb2] [FB:68]
>[  453.575744] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  453.575801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  453.575876] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  453.592863] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  453.592883] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  453.592901] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  453.592934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  453.592961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  453.592976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  453.592988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  453.593001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  453.593012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  453.593024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  453.593035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  453.593046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  453.593057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  453.593067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  453.593078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  453.593088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  453.593101] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  453.593116] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  453.593130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  453.593143] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  453.593156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  453.599292] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  453.599306] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  453.599329] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  453.599345] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  453.599412] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  453.599420] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  453.599461] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  453.599475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  453.599492] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  453.599509] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  453.599522] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  453.599537] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  453.599551] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  453.599565] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  453.599578] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  453.599590] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  453.599602] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  453.599604] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  453.599616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  453.599618] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  453.599630] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  453.599642] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  453.599654] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  453.599665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  453.599676] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  453.599690] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  453.600227] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  453.600242] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  453.600255] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  453.600268] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  453.600280] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  453.600301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  453.600330] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  453.600344] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  453.600631] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  453.600643] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  453.600661] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  453.600680] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  453.601035] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  453.617626] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  453.617654] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  453.617678] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  453.620039] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  453.620063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  453.620084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  453.620101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  453.620117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  453.620133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  453.620148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  453.620163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  453.620178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  453.620192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  453.620206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  453.620222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  453.620236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  453.620250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  453.620267] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  453.620286] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  453.620304] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  453.620321] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  453.620338] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  453.620359] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  453.620376] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  453.633161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.641682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.650217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.658731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.667246] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.675765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.684275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.692811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.720796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.729290] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.737772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.746241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.754710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.763178] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.771649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.780117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.786252] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  453.800745] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  453.800764] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  453.800812] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  453.801823] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  453.804075] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  453.805491] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  453.805506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  453.805520] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  453.805535] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  453.810673] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  453.810688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  453.815875] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  453.818345] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049eded3d8
>[  453.818977] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  453.835821] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  453.835837] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  453.835877] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  453.835903] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  453.835940] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  453.852546] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  453.919655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  453.920069] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  453.937256] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  453.937326] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  453.937442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  453.937499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  453.937555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  453.937603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  453.937648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  453.937693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  453.937870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  453.937933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  453.938000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  453.938060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  453.938125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  453.938188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  453.938246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  453.938318] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  453.938401] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  453.938481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  453.938556] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  453.938631] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  453.938799] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  453.938875] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  453.938942] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  453.939043] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  453.939151] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  453.939238] [drm:intel_power_well_disable [i915]] disabling DC off
>[  453.939314] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  453.939383] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  453.939936] [drm:intel_power_well_disable [i915]] disabling always-on
>[  453.942554] [drm:drm_mode_addfb2] [FB:68]
>[  453.969314] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  453.969342] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  453.969501] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  453.969559] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  453.969621] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  453.969710] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  453.969871] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  453.969957] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  453.970040] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  453.970120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  453.970195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  453.970275] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  453.970347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  453.970366] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  453.970433] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  453.970449] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  453.970521] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  453.970593] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  453.970668] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  453.970737] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  453.970840] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  453.970923] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  453.970996] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  453.971069] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  453.971132] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  453.971199] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  453.971281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  453.971371] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  453.971446] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  453.972842] [drm:intel_power_well_enable [i915]] enabling always-on
>[  453.972884] [drm:intel_power_well_enable [i915]] enabling DC off
>[  453.973187] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  453.973246] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  453.973295] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  453.973391] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  453.973433] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  453.973499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  453.973556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  453.973606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  453.973654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  453.973710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  453.973859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  453.973934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  453.974013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  453.974079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  453.974151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  453.974224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  453.974297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  453.974367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  453.974445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  453.974530] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  453.974613] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  453.974691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  453.974818] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  453.974900] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  453.987883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  453.996610] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.005339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.014065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.022788] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.031503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.040220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.048937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.057654] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.066417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.075012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.083555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.092066] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.100554] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.109032] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.117503] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.125971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.134439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.142273] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  454.156443] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  454.156461] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  454.156491] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  454.157771] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  454.160027] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  454.161455] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  454.161471] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  454.161484] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  454.161499] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  454.166638] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  454.166653] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  454.171794] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  454.174270] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeefc8
>[  454.174795] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  454.191664] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  454.191687] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  454.191785] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.275331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  454.275464] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  454.294108] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  454.294176] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  454.294292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  454.294347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  454.294402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  454.294448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  454.294492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  454.294535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  454.294579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  454.294621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  454.294662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  454.294702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  454.294877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  454.294939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  454.294999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  454.295074] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  454.295161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  454.295243] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.295316] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  454.295393] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  454.295504] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  454.295577] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  454.295647] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  454.295797] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  454.295906] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  454.295988] [drm:intel_power_well_disable [i915]] disabling DC off
>[  454.296059] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  454.296117] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  454.296597] [drm:intel_power_well_disable [i915]] disabling always-on
>[  454.298733] [drm:drm_mode_addfb2] [FB:68]
>[  454.370073] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  454.370100] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  454.370268] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  454.370326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  454.370386] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  454.370450] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  454.370501] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  454.370556] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  454.370724] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  454.371268] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  454.371320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  454.371369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  454.371413] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  454.371423] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  454.371466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  454.371474] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  454.371520] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  454.371564] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  454.371607] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  454.371650] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  454.371692] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  454.372259] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  454.372310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  454.372359] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  454.372404] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  454.372447] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  454.372523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  454.372584] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  454.372635] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  454.376554] [drm:intel_power_well_enable [i915]] enabling always-on
>[  454.376595] [drm:intel_power_well_enable [i915]] enabling DC off
>[  454.377056] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  454.377419] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  454.377461] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  454.377586] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  454.377627] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  454.377698] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  454.380338] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  454.380405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  454.380468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  454.380523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  454.380573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  454.380621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  454.380667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  454.380716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  454.381297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  454.381353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  454.381406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  454.381450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  454.381493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  454.381534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  454.381583] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  454.381641] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.381694] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  454.382237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  454.382301] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  454.382351] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  454.386010] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  454.386069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  454.386119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  454.386172] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  454.387477] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  454.387530] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  454.387577] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  454.388688] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  454.388785] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  454.388832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  454.389703] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  454.390097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  454.391425] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  454.393823] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  454.395291] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  454.395381] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  454.395431] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  454.395499] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  454.412238] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  454.412310] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  454.412422] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.496018] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  454.496182] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  454.496253] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  454.496393] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  454.512826] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  454.512895] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  454.513009] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  454.513625] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  454.513683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  454.513857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  454.513916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  454.513964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  454.514010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  454.514055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  454.514102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  454.514143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  454.514184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  454.514225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  454.514272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  454.514313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  454.514353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  454.514401] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  454.514457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  454.514509] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.514559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  454.514608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  454.514686] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  454.514767] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  454.514814] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  454.514877] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  454.514946] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  454.514998] [drm:intel_power_well_disable [i915]] disabling DC off
>[  454.515044] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  454.515084] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  454.515535] [drm:intel_power_well_disable [i915]] disabling always-on
>[  454.518081] [drm:drm_mode_addfb2] [FB:68]
>[  454.579837] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  454.579853] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  454.579943] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  454.579973] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  454.580005] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  454.580038] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  454.580065] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  454.580093] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  454.580121] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  454.580147] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  454.580172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  454.580196] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  454.580218] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  454.580223] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  454.580246] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  454.580249] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  454.580272] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  454.580295] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  454.580317] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  454.580339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  454.580360] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  454.580387] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  454.580410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  454.580432] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  454.580453] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  454.580474] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  454.580511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  454.580543] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  454.580569] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  454.583644] [drm:intel_power_well_enable [i915]] enabling always-on
>[  454.583662] [drm:intel_power_well_enable [i915]] enabling DC off
>[  454.584068] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  454.584571] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  454.584599] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  454.584646] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  454.584664] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  454.584694] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  454.587156] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  454.587184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  454.587211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  454.587234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  454.587255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  454.587276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  454.587296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  454.587317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  454.587337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  454.587356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  454.587375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  454.587393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  454.587412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  454.587431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  454.587452] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  454.587477] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.587500] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  454.587522] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  454.587549] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  454.587572] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  454.590848] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  454.590869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  454.590888] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  454.590907] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  454.591576] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  454.591593] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  454.591609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  454.592473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  454.592493] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  454.592511] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  454.593312] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  454.593329] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  454.594290] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  454.596554] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeb7e8
>[  454.597140] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  454.597167] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  454.597183] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  454.597205] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  454.613962] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  454.613984] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  454.614018] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.724107] [IGT] kms_pipe_crc_basic: exiting, ret=99
>[  454.751203] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  454.751263] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  454.751328] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  454.751395] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  454.751448] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  454.751504] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  454.751560] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  454.751612] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  454.751663] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  454.751711] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  454.751796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  454.751806] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  454.751853] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  454.751860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  454.751908] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  454.751953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  454.751998] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  454.752042] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  454.752085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  454.752139] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  454.752184] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  454.752228] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  454.752271] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  454.752314] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  454.752369] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  454.752431] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 2
>[  454.752483] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe A
>[  454.752708] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  454.752792] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  454.752844] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  454.752904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  454.752960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  454.753009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  454.753055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  454.753100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  454.753145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  454.753191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  454.753235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  454.753278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  454.753321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  454.753364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  454.753407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  454.753449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  454.753498] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  454.753555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  454.753610] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  454.753661] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  454.764118] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 1, on? 0) for crtc 31
>[  454.764178] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  454.777417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.785944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.794460] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.802978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.811487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.819996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.828506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.837016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.845529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.854038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.862549] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.871059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.879572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.888163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.896672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.905202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.913711] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.922222] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.930731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  454.931845] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  454.946017] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  454.946031] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  454.946061] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  454.946892] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  454.947652] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  454.950277] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  454.950293] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  454.950308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  454.950325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  454.955744] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  454.955758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  454.960905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  454.963387] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  454.963928] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  454.963967] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  454.963981] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  454.980777] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  454.980799] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  454.980839] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  454.981012] Console: switching to colour frame buffer device 240x75
>[  455.154232] Console: switching to colour dummy device 80x25
>[  455.154339] [IGT] kms_pipe_crc_basic: executing
>[  455.165511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  455.165590] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  455.174254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.182955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.191644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.200424] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.209110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.217797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.226485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.235217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.243934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.252563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.261127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.269637] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.278124] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.286593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.295051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.303505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.311959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.320413] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.328867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.337320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.345774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.354229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.362683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.371150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.379605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.388119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.396574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.405028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.413482] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.421936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.430390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.438844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.438852] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  455.438855] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  455.438868] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  455.438883] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  455.439732] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  455.441250] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  455.441266] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  455.441280] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  455.441294] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  455.442091] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  455.442803] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  455.443585] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  455.443623] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  455.443625] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  455.443626] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  455.443628] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  455.443629] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  455.443630] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  455.443632] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  455.443633] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  455.443635] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  455.443636] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  455.443637] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  455.443639] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  455.443640] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  455.443653] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  455.443668] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  455.443723] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  455.443731] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  455.443784] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  455.445880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  455.445896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  455.447902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  455.447906] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  455.450165] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  455.450180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  455.452435] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  455.452439] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  455.452441] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  455.452452] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  455.452469] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  455.452924] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  455.453241] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  455.453257] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  455.453271] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  455.453297] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  455.453726] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  455.454054] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  455.454554] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  455.454555] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  455.454632] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  455.454633] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  455.454636] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  455.454637] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  455.454640] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  455.454641] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  455.454646] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  455.454648] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  455.454650] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  455.454651] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  455.454652] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  455.454654] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  455.454656] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  455.454657] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  455.454659] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  455.454660] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  455.454661] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  455.454663] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  455.454664] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  455.454665] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  455.454667] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  455.454668] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  455.454669] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  455.454671] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  455.454672] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  455.454674] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  455.454675] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  455.454676] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  455.454678] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  455.454679] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  455.454680] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  455.454694] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  455.454696] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  455.454712] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  455.454715] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  455.454717] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  455.454732] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  455.454735] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  455.454737] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  455.454810] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  455.454834] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  455.456867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  455.456881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  455.458914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  455.458918] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  455.461182] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  455.461198] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  455.463449] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  455.463453] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  455.463456] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  455.472124] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  455.472143] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  455.480600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.489059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.497515] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.505973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.514428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.522886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.531341] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.539796] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.548252] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.556707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.565162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.573619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.582078] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.590536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.598992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.607449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.615906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.624362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.632818] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.641273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.649729] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.658185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.666641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.675101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.683557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.692014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.719044] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.727501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.735959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.744416] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.752873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.761426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  455.761435] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  455.761438] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  455.761630] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  455.761646] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  455.762487] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  455.764011] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  455.764027] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  455.764054] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  455.764067] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  455.764888] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  455.765596] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  455.766375] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  455.766410] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  455.766413] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  455.766414] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  455.766416] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  455.766417] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  455.766418] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  455.766420] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  455.766421] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  455.766423] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  455.766424] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  455.766425] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  455.766427] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  455.766428] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  455.766589] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  455.766604] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  455.766620] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  455.767295] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  455.767310] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  455.768879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  455.768895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  455.770914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  455.770918] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  455.773179] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  455.773195] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  455.775458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  455.775462] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  455.775464] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  455.775653] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  455.775670] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  455.776331] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  455.776644] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  455.776674] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  455.776835] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  455.776849] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  455.777269] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  455.777581] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  455.778106] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  455.778107] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  455.778183] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  455.778184] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  455.778187] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  455.778188] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  455.778190] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  455.778191] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  455.778197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  455.778199] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  455.778200] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  455.778202] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  455.778203] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  455.778205] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  455.778206] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  455.778207] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  455.778209] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  455.778210] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  455.778212] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  455.778213] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  455.778214] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  455.778216] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  455.778217] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  455.778218] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  455.778220] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  455.778221] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  455.778222] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  455.778224] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  455.778225] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  455.778227] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  455.778228] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  455.778229] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  455.778231] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  455.778232] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  455.778233] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  455.778235] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  455.778236] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  455.778237] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  455.778239] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  455.778240] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  455.778241] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  455.778429] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  455.778444] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  455.779851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  455.779867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  455.781877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  455.781881] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  455.783882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  455.783897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  455.786144] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  455.786148] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  455.786150] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  455.786361] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C
>[  455.786579] [drm:drm_mode_addfb2] [FB:69]
>[  455.792949] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  455.793002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  455.793084] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  455.799265] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  455.799285] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 1, on? 1) for crtc 31
>[  455.799302] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  455.799346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  455.799360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  455.799374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  455.799386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  455.799398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  455.799409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  455.799422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  455.799433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  455.799444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  455.799454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  455.799465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  455.799475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  455.799486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  455.799498] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  455.799512] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  455.799526] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  455.799539] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  455.799551] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  455.814106] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  455.814156] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  455.814239] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  455.814297] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  455.814580] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  455.814717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  455.815302] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  455.815366] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  455.815953] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  455.832893] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  455.832962] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  455.833073] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  455.833279] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  455.833336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  455.833391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  455.833442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  455.833488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  455.833533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  455.833576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  455.833621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  455.833663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  455.833704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  455.834660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  455.834714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  455.834951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  455.835002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  455.835052] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  455.835110] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  455.835165] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  455.835214] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  455.835264] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  455.835337] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  455.835385] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  455.835430] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  455.835493] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  455.835563] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  455.835614] [drm:intel_power_well_disable [i915]] disabling DC off
>[  455.835660] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  455.835699] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  455.836911] [drm:intel_power_well_disable [i915]] disabling always-on
>[  455.837551] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  455.837577] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  455.837727] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  455.838052] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  455.838113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  455.838176] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  455.838225] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  455.838278] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  455.838330] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  455.838379] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  455.838428] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  455.838475] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  455.838517] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  455.838527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  455.838570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  455.838577] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  455.838620] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  455.838662] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  455.838703] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  455.839546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  455.839590] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  455.839643] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  455.839689] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  455.840068] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  455.840113] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  455.840158] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  455.840211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  455.840271] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  455.840322] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  455.841847] [drm:intel_power_well_enable [i915]] enabling always-on
>[  455.841887] [drm:intel_power_well_enable [i915]] enabling DC off
>[  455.842187] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  455.842245] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  455.842292] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  455.842394] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  455.842443] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  455.842510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  455.842565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  455.842613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  455.842659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  455.842705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  455.843365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  455.843417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  455.843463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  455.843507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  455.843551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  455.843596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  455.843639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  455.843681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  455.844162] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  455.844219] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  455.844269] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  455.844317] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  455.844377] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  455.844428] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  455.857643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.866534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.875233] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.883919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.892645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.901511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.910194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.918919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.927646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.936416] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.944992] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.953512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.962008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.970487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.978961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.987429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  455.995897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.004364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.012186] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  456.026181] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  456.026197] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  456.026314] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  456.027768] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  456.030348] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  456.031686] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  456.031713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  456.031727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  456.031742] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  456.036881] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  456.036896] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  456.042034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  456.044490] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  456.045023] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  456.061901] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  456.061924] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.061960] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.145663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  456.145951] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  456.162555] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  456.162817] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  456.162946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.163006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.163065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.163113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.163161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.163210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.163258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.163303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.163348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.163390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.163437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.163479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.163521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.163572] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  456.163629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.163684] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.163806] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.163858] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.163940] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  456.163988] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  456.164034] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  456.164099] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  456.164172] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.164224] [drm:intel_power_well_disable [i915]] disabling DC off
>[  456.164272] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  456.164313] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  456.164821] [drm:intel_power_well_disable [i915]] disabling always-on
>[  456.166992] [drm:drm_mode_addfb2] [FB:68]
>[  456.196135] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  456.196164] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  456.196323] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  456.196380] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  456.196440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  456.196502] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  456.196551] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  456.196604] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  456.196657] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  456.196717] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  456.196864] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  456.196915] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  456.196962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  456.196971] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  456.197013] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  456.197023] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  456.197070] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  456.197115] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  456.197157] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  456.197199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.197241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  456.197297] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  456.197340] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  456.197385] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  456.197426] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  456.197469] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  456.197523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  456.197585] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  456.197636] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  456.198866] [drm:intel_power_well_enable [i915]] enabling always-on
>[  456.198906] [drm:intel_power_well_enable [i915]] enabling DC off
>[  456.199207] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  456.199266] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  456.199307] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  456.199429] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  456.199470] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  456.199534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.199589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.199637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.199684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.199827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.199873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.199925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.199969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.200014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.200057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.200104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.200147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.200190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.200239] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.200296] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.200348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.200401] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.200461] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  456.200512] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  456.213802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.222528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.231251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.239976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.248697] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.257512] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.266234] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.274953] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.283677] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.292707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.301329] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.309873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.318381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.326885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.335363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.343834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.352302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.360772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.366723] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  456.382381] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  456.382397] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  456.382438] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  456.383276] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  456.383996] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  456.386596] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  456.386630] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  456.386646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  456.386662] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  456.392055] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  456.392071] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  456.397209] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  456.399639] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  456.400208] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  456.417078] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  456.417101] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.417137] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.500937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  456.501134] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  456.517801] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  456.517869] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  456.517984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.518042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.518098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.518146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.518192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.518239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.518286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.518329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.518372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.518413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.518455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.518495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.518535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.518583] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  456.518639] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.518691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.520499] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.520555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.520629] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  456.520676] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  456.521231] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  456.521298] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  456.521376] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.521427] [drm:intel_power_well_disable [i915]] disabling DC off
>[  456.521474] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  456.521514] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  456.523012] [drm:intel_power_well_disable [i915]] disabling always-on
>[  456.525021] [drm:drm_mode_addfb2] [FB:68]
>[  456.592618] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  456.592644] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  456.593155] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  456.593207] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  456.593261] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  456.593318] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  456.593363] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  456.593412] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  456.593458] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  456.593502] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  456.593546] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  456.593587] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  456.593627] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  456.593634] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  456.593674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  456.593680] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  456.594824] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  456.594871] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  456.594914] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  456.594956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.594995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  456.595044] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  456.595085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  456.595125] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  456.595164] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  456.595202] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  456.595267] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  456.595321] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  456.595366] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  456.599572] [drm:intel_power_well_enable [i915]] enabling always-on
>[  456.599608] [drm:intel_power_well_enable [i915]] enabling DC off
>[  456.600212] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  456.600558] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  456.600620] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  456.600930] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  456.600993] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  456.601079] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  456.601271] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  456.601323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.601373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.601419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.601460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.601501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.601540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.601581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.601620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.601657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.601694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.602000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.602054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.602111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.602171] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.602242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.602305] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.602370] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.602447] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  456.602507] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  456.605299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  456.605350] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  456.605396] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  456.605444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  456.606789] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  456.606837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  456.606882] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  456.607722] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  456.608175] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  456.608222] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  456.609293] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  456.609342] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  456.610520] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  456.612898] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  456.614297] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  456.614378] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  456.614422] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  456.614483] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  456.631221] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  456.631293] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.631444] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.714935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  456.715092] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  456.715154] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  456.715285] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  456.731344] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  456.731407] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  456.731510] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  456.731698] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  456.731853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.731924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.731991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.732049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.732107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.732163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.732222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.732276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.732329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.732383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.732445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.732500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.732552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.732611] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  456.732688] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.732831] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.732898] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.732965] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.733067] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  456.733134] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  456.733200] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  456.733292] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  456.733387] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.733458] [drm:intel_power_well_disable [i915]] disabling DC off
>[  456.733520] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  456.733578] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  456.734090] [drm:intel_power_well_disable [i915]] disabling always-on
>[  456.736545] [drm:drm_mode_addfb2] [FB:68]
>[  456.779512] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  456.779521] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  456.779571] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  456.779587] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  456.779603] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  456.779620] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  456.779633] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  456.779647] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  456.779661] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  456.779675] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  456.779691] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  456.779885] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  456.779898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  456.779901] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  456.779913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  456.779915] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  456.779927] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  456.779939] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  456.779950] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  456.779961] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.779973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  456.779987] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  456.779999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  456.780010] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  456.780021] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  456.780032] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  456.780052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  456.780069] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  456.780083] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  456.781305] [drm:intel_power_well_enable [i915]] enabling always-on
>[  456.781317] [drm:intel_power_well_enable [i915]] enabling DC off
>[  456.781589] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  456.781606] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  456.781617] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  456.781642] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  456.781659] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  456.781680] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  456.783955] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  456.783974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.783991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.784005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.784018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.784030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.784042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.784053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.784065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.784075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.784086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.784098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.784108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.784119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.784132] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.784147] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.784161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.784174] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.784190] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  456.784203] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  456.787448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  456.787465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  456.787492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  456.787506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  456.788325] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  456.788370] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  456.788384] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  456.789097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  456.789112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  456.789138] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  456.789818] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  456.789834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  456.790802] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  456.793074] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  456.793526] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  456.793554] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  456.793568] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  456.793587] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  456.810355] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  456.810376] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.810410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.894066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  456.894227] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  456.894299] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  456.894412] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  456.910825] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  456.910893] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  456.911009] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  456.911293] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  456.911349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.911406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.911456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.911503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.911548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.911593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.911638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.911681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.911847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.911910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.911987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.912046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.912106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.912172] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  456.912255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.912333] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.912407] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.912481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.912711] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  456.912861] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  456.912935] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  456.913039] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  456.913148] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  456.913227] [drm:intel_power_well_disable [i915]] disabling DC off
>[  456.913301] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  456.913365] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  456.913930] [drm:intel_power_well_disable [i915]] disabling always-on
>[  456.915556] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  456.964308] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  456.964330] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  456.964353] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  456.964376] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  456.964394] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  456.964414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  456.964434] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  456.964453] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  456.964471] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  456.964488] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  456.964504] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  456.964508] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  456.964525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  456.964527] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  456.964544] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  456.964560] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  456.964576] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  456.964592] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.964608] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  456.964628] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  456.964644] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  456.964660] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  456.964675] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  456.964691] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  456.964730] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  456.964748] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  456.964769] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  456.964791] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  456.964810] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  456.964829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  456.964847] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  456.964864] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  456.964880] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  456.964896] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  456.964911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  456.964914] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  456.964929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  456.964931] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  456.964948] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  456.964963] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  456.964978] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  456.964993] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  456.965008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  456.965027] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  456.965042] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  456.965058] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  456.965073] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  456.965088] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  456.965108] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  456.965130] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  456.965149] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  456.965168] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  456.965186] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  456.965249] [drm:intel_power_well_enable [i915]] enabling always-on
>[  456.965264] [drm:intel_power_well_enable [i915]] enabling DC off
>[  456.965540] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  456.965565] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  456.965582] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  456.965613] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  456.965629] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  456.965648] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  456.965664] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  456.965688] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  456.967807] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  456.967822] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  456.967846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  456.967868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  456.967886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  456.967904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  456.967921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  456.967938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  456.967955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  456.967971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  456.967988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  456.968003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  456.968019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  456.968034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  456.968049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  456.968067] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  456.968088] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  456.968107] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  456.968126] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  456.968149] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  456.968167] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  456.980316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.988830] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  456.997340] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.005850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.014360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.022869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.031376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.039885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.048422] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.056935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.065444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.073959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.082471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.090980] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.099489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.107997] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.116506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.125014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.133523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  457.134617] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  457.149331] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  457.149348] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  457.149382] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  457.150232] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  457.152845] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  457.154191] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  457.154205] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  457.154218] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  457.154233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  457.159381] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  457.159395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  457.164542] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  457.167022] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edea548
>[  457.167546] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  457.167604] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  457.167618] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  457.167669] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  457.167683] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  457.170943] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  457.170959] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  457.170973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  457.170988] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  457.171647] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  457.171661] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  457.171674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  457.172340] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  457.172353] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  457.172366] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  457.173012] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  457.173025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  457.173982] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  457.176251] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  457.176783] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  457.176809] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  457.176823] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  457.176844] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  457.193613] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  457.193635] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  457.193674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  457.193731] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  457.193751] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  457.193885] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  457.194045] Console: switching to colour frame buffer device 240x75
>[  457.616174] Console: switching to colour dummy device 80x25
>[  457.616286] [IGT] kms_pipe_crc_basic: executing
>[  457.630116] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  457.630146] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  457.638636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.647137] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.655638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.664116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.672575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.681036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.689496] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.717362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.725823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.734280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.742741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.751198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.759743] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.768199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.776656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.785115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.793573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.802031] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.810487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.818943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.827401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.835859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.844317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.852775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.861231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.869688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.878160] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.886619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.895077] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.903534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.911990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.920448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.920457] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  457.920460] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  457.920473] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  457.920489] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  457.921328] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  457.922959] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  457.922976] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  457.922990] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  457.923005] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  457.923930] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  457.924639] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  457.925425] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  457.925466] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  457.925468] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  457.925470] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  457.925471] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  457.925473] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  457.925474] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  457.925476] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  457.925477] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  457.925478] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  457.925480] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  457.925481] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  457.925483] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  457.925484] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  457.925498] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  457.925512] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  457.925529] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  457.925537] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  457.925551] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  457.926845] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  457.926859] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  457.928872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  457.928875] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  457.930892] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  457.930908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  457.933168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  457.933172] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  457.933174] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  457.933184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  457.933201] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  457.933650] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  457.933978] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  457.933995] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  457.934010] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  457.934037] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  457.934441] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  457.934764] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  457.935262] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  457.935264] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  457.935339] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  457.935340] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  457.935343] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  457.935344] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  457.935346] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  457.935347] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  457.935353] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  457.935355] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  457.935356] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  457.935358] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  457.935359] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  457.935360] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  457.935362] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  457.935363] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  457.935365] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  457.935366] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  457.935367] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  457.935369] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  457.935370] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  457.935372] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  457.935373] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  457.935374] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  457.935376] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  457.935377] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  457.935378] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  457.935380] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  457.935381] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  457.935382] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  457.935384] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  457.935385] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  457.935386] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  457.935388] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  457.935389] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  457.935391] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  457.935392] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  457.935393] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  457.935395] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  457.935396] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  457.935397] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  457.935424] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  457.935438] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  457.936880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  457.936896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  457.938934] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  457.938938] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  457.940878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  457.940894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  457.942903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  457.942907] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  457.942909] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  457.951320] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  457.951336] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  457.959791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.968251] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.976810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.985270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  457.993727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.002184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.010641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.019099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.027555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.036012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.044468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.052925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.061397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.069854] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.078312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.086771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.095227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.103684] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.112155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.120612] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.129083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.137541] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.145998] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.154454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.162910] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.171367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.179925] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.188382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.196841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.205298] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.213771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.222229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  458.222238] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  458.222241] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  458.222416] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  458.222432] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  458.223310] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  458.224834] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  458.224851] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  458.224866] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  458.224880] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  458.225671] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  458.226383] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  458.227194] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  458.227218] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  458.227220] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  458.227222] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  458.227223] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  458.227225] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  458.227226] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  458.227228] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  458.227229] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  458.227244] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  458.227245] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  458.227246] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  458.227248] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  458.227249] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  458.227409] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  458.227424] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  458.227440] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  458.227603] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  458.227618] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  458.229884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  458.229900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  458.231899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  458.231902] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  458.234166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  458.234181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  458.236440] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  458.236443] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  458.236446] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  458.236624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  458.236641] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  458.237201] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  458.237515] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  458.237531] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  458.237545] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  458.237559] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  458.238091] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  458.238403] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  458.238928] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  458.238929] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  458.239004] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  458.239005] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  458.239008] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  458.239009] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  458.239012] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  458.239013] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  458.239019] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  458.239020] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  458.239022] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  458.239023] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  458.239025] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  458.239026] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  458.239027] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  458.239029] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  458.239030] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  458.239032] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  458.239033] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  458.239034] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  458.239036] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  458.239037] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  458.239039] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  458.239040] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  458.239041] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  458.239043] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  458.239044] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  458.239045] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  458.239047] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  458.239048] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  458.239049] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  458.239051] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  458.239052] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  458.239053] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  458.239055] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  458.239056] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  458.239058] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  458.239059] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  458.239060] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  458.239062] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  458.239063] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  458.239229] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  458.239247] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  458.240903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  458.240917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  458.242879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  458.242882] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  458.244880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  458.244896] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  458.246882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  458.246885] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  458.246888] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  458.247092] [IGT] kms_pipe_crc_basic: starting subtest read-crc-pipe-C-frame-sequence
>[  458.247303] [drm:drm_mode_addfb2] [FB:69]
>[  458.253543] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  458.253594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  458.253666] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  458.269745] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  458.269764] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  458.269793] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  458.269826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  458.269840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  458.269854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  458.269866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  458.269878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  458.269890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  458.269902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  458.269912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  458.269923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  458.269934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  458.269945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  458.269956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  458.269966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  458.269978] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  458.269993] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  458.270007] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.270020] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  458.270033] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  458.276980] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  458.276994] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  458.277017] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  458.277033] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  458.277100] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  458.277139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.277186] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  458.277205] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  458.277328] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  458.295751] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  458.295773] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  458.295811] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  458.295976] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  458.295994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  458.296012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  458.296027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  458.296042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  458.296056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  458.296069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  458.296083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  458.296096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  458.296109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  458.296122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  458.296150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  458.296163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  458.296175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  458.296190] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  458.296208] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  458.296225] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.296240] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  458.296256] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  458.296282] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  458.296297] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  458.296312] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  458.296335] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  458.296358] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  458.296375] [drm:intel_power_well_disable [i915]] disabling DC off
>[  458.296390] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  458.296403] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  458.297581] [drm:intel_power_well_disable [i915]] disabling always-on
>[  458.297677] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  458.297760] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  458.297813] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  458.297831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  458.297850] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  458.297870] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  458.297886] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  458.297903] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  458.297920] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  458.297936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  458.297951] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  458.297966] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  458.297979] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  458.297982] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  458.297996] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  458.297998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  458.298012] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  458.298025] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  458.298039] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  458.298052] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.298065] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  458.298082] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  458.298095] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  458.298108] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  458.298122] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  458.298148] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  458.298163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.298182] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  458.298197] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  458.298552] [drm:intel_power_well_enable [i915]] enabling always-on
>[  458.298564] [drm:intel_power_well_enable [i915]] enabling DC off
>[  458.299324] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  458.299604] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  458.299617] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  458.299646] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  458.299665] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  458.299689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  458.299833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  458.299850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  458.299865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  458.299880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  458.299895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  458.299910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  458.299925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  458.299938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  458.299952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  458.299966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  458.299980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  458.299993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  458.300008] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  458.300025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.300041] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  458.300057] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  458.300076] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  458.300092] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  458.312886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.321397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.329911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.338419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.346927] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.355433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.363940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.372528] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.381040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.389548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.398055] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.406548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.415024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.423492] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.431961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.440428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.448932] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.457398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.465020] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  458.480492] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  458.480508] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  458.480566] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  458.481396] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  458.482862] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  458.484764] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  458.484781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  458.484797] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  458.484813] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  458.490265] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  458.490281] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  458.495553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  458.498011] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  458.498498] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  458.515357] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  458.515379] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  458.515415] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.599114] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.599280] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  458.615951] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  458.616019] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  458.616136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  458.616194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  458.616250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  458.616299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  458.616344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  458.616390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  458.616438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  458.616481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  458.616522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  458.616564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  458.616607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  458.616648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  458.616688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  458.616835] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  458.616901] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  458.616963] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.617016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  458.617070] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  458.617150] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  458.617196] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  458.617241] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  458.617310] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  458.617382] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  458.617432] [drm:intel_power_well_disable [i915]] disabling DC off
>[  458.617479] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  458.617519] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  458.618019] [drm:intel_power_well_disable [i915]] disabling always-on
>[  458.620105] [drm:drm_mode_addfb2] [FB:69]
>[  458.642370] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  458.642398] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  458.642569] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  458.642626] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  458.642685] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  458.642845] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  458.642922] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  458.643007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  458.643091] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  458.643171] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  458.643249] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  458.643325] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  458.643398] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  458.643418] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  458.643484] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  458.643499] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  458.643569] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  458.643640] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  458.643711] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  458.643813] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  458.643882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  458.643964] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  458.644035] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  458.644097] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  458.644163] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  458.644231] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  458.644305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.644392] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  458.644469] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  458.645780] [drm:intel_power_well_enable [i915]] enabling always-on
>[  458.645821] [drm:intel_power_well_enable [i915]] enabling DC off
>[  458.646137] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  458.646196] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  458.646252] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  458.646350] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  458.646392] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  458.646457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  458.646515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  458.646566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  458.646614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  458.646659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  458.646703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  458.646848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  458.646916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  458.646992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  458.647062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  458.647134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  458.647200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  458.647263] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  458.647339] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  458.647426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.647507] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  458.647586] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  458.647676] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  458.647772] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  458.661024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.669726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.678497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.687223] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.713968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.722657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.731429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.740119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.748805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.757453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.766025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.774556] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.783063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.791547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.800020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.808487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  458.814623] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  458.829612] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  458.829629] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  458.829663] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  458.830494] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  458.831927] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  458.833836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  458.833853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  458.833869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  458.833886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  458.839316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  458.839331] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  458.844490] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  458.846967] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  458.847453] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  458.864368] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  458.864391] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  458.864427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.947967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  458.948107] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  458.964960] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  458.965028] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  458.965146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  458.965204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  458.965259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  458.965307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  458.965353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  458.965399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  458.965446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  458.965488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  458.965529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  458.965570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  458.965614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  458.965655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  458.965695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  458.965840] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  458.965904] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  458.965961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  458.966013] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  458.966065] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  458.966145] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  458.966192] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  458.966238] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  458.966302] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  458.966374] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  458.966424] [drm:intel_power_well_disable [i915]] disabling DC off
>[  458.966471] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  458.966510] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  458.967006] [drm:intel_power_well_disable [i915]] disabling always-on
>[  458.969189] [drm:drm_mode_addfb2] [FB:69]
>[  459.032683] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  459.032732] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  459.032888] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  459.032942] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  459.032999] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  459.033060] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  459.033108] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  459.033158] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  459.033208] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  459.033255] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  459.033302] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  459.033345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  459.033387] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  459.033394] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  459.033436] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  459.033442] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  459.033485] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  459.033526] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  459.033566] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  459.033606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  459.033645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  459.033694] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  459.034787] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  459.034834] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  459.034881] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  459.034923] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  459.034993] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  459.035052] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  459.035101] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  459.038639] [drm:intel_power_well_enable [i915]] enabling always-on
>[  459.038678] [drm:intel_power_well_enable [i915]] enabling DC off
>[  459.039146] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  459.039500] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  459.039547] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  459.039638] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  459.039677] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  459.039991] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  459.042385] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  459.042446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  459.042502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  459.042551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  459.042597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  459.042640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  459.042683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  459.043086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  459.043131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  459.043174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  459.043215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  459.043256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  459.043297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  459.043337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  459.043384] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  459.043438] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.043488] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  459.043535] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  459.043593] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  459.043642] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  459.047233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  459.047285] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  459.047331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  459.047379] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  459.048510] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  459.048557] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  459.048601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  459.049664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  459.049709] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  459.049949] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  459.050935] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  459.050983] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  459.052224] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  459.054604] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  459.055950] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  459.056022] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  459.056068] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  459.056129] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  459.072936] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  459.073007] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  459.073113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.156603] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  459.156905] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  459.156987] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  459.157113] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  459.173938] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  459.174008] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  459.174122] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  459.176481] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  459.176549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  459.176614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  459.176670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  459.176722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  459.176865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  459.176916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  459.176973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  459.177023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  459.177069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  459.177117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  459.177170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  459.177215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  459.177261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  459.177312] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  459.177374] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  459.177431] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.177484] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  459.177536] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  459.177623] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  459.177673] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  459.177758] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  459.177825] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  459.177901] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  459.177955] [drm:intel_power_well_disable [i915]] disabling DC off
>[  459.178005] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  459.178049] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  459.178504] [drm:intel_power_well_disable [i915]] disabling always-on
>[  459.180345] [drm:drm_mode_addfb2] [FB:69]
>[  459.246025] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  459.246053] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  459.246218] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  459.246273] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  459.246333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  459.246396] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  459.246446] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  459.246500] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  459.246554] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  459.246604] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  459.246653] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  459.246699] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  459.246831] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  459.246855] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  459.246924] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  459.246937] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  459.247006] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  459.247073] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  459.247148] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  459.247210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  459.247277] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  459.247353] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  459.247426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  459.247493] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  459.247561] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  459.247625] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  459.247732] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  459.247855] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  459.247930] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  459.251269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  459.251297] [drm:intel_power_well_enable [i915]] enabling DC off
>[  459.251587] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  459.251629] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  459.251662] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  459.251791] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  459.251842] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  459.251909] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  459.252082] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  459.252139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  459.252192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  459.252245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  459.252291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  459.252339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  459.252382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  459.252432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  459.252475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  459.252520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  459.252561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  459.252605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  459.252645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  459.252688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  459.252793] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  459.252850] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.252906] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  459.252961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  459.253024] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  459.253076] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  459.256610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  459.256641] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  459.256669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  459.256697] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  459.257473] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  459.257500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  459.257526] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  459.258337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  459.258364] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  459.258388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  459.259202] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  459.259231] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  459.260263] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  459.262540] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede9bf8
>[  459.263237] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  459.263285] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  459.263307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  459.263338] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  459.280095] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  459.280130] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  459.280182] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.363883] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  459.364059] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  459.364130] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  459.364258] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  459.380344] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  459.380412] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  459.380527] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  459.382730] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  459.382845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  459.382910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  459.382966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  459.383016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  459.383064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  459.383112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  459.383162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  459.383207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  459.383252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  459.383297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  459.383348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  459.383392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  459.383436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  459.383487] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  459.383546] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  459.383602] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.383656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  459.383708] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  459.383894] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  459.383968] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  459.384041] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  459.384140] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  459.384247] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  459.384325] [drm:intel_power_well_disable [i915]] disabling DC off
>[  459.384398] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  459.384456] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  459.384984] [drm:intel_power_well_disable [i915]] disabling always-on
>[  459.386972] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  459.432257] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  459.432279] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  459.432302] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  459.432326] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  459.432345] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  459.432364] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  459.432384] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  459.432403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  459.432422] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  459.432439] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  459.432455] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  459.432459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  459.432476] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  459.432478] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  459.432495] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  459.432511] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  459.432527] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  459.432543] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  459.432558] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  459.432578] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  459.432593] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  459.432609] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  459.432625] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  459.432640] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  459.432662] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  459.432680] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  459.432700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  459.432739] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  459.432758] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  459.432776] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  459.432794] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  459.432810] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  459.432827] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  459.432842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  459.432857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  459.432860] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  459.432875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  459.432877] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  459.432893] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  459.432908] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  459.432923] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  459.432938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  459.432953] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  459.432971] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  459.432987] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  459.433002] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  459.433017] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  459.433031] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  459.433050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  459.433073] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  459.433092] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  459.433111] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  459.433129] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  459.433204] [drm:intel_power_well_enable [i915]] enabling always-on
>[  459.433219] [drm:intel_power_well_enable [i915]] enabling DC off
>[  459.433495] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  459.433521] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  459.433537] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  459.433575] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  459.433599] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  459.433619] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  459.433634] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  459.433657] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  459.437833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  459.437850] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  459.437875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  459.437897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  459.437916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  459.437934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  459.437952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  459.437969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  459.437987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  459.438003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  459.438019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  459.438035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  459.438051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  459.438066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  459.438082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  459.438101] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  459.438122] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.438141] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  459.438161] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  459.438184] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  459.438203] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  459.450478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.458990] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.467500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.476009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.484520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.493034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.501542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.510050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.518559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.527079] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.535599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.544114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.552624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.561133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.569641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.578149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.586661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.595191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.603715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  459.604811] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  459.619341] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  459.619360] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  459.619395] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  459.620385] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  459.623005] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  459.624717] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  459.624732] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  459.624746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  459.624761] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  459.629909] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  459.629923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  459.635116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  459.637596] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edec138
>[  459.638136] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  459.638177] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  459.638191] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  459.638242] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  459.638256] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  459.641500] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  459.641516] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  459.641531] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  459.641546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  459.642206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  459.642220] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  459.642233] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  459.642882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  459.642896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  459.642908] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  459.643555] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  459.643569] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  459.644527] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  459.646793] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  459.647409] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  459.647446] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  459.647460] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  459.647481] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  459.664247] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  459.664269] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  459.664307] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  459.664349] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  459.664369] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  459.664404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  459.664538] Console: switching to colour frame buffer device 240x75
>[  460.092978] Console: switching to colour dummy device 80x25
>[  460.093099] [IGT] kms_pipe_crc_basic: executing
>[  460.106519] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  460.106604] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  460.115176] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.123641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.132099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.140557] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.149013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.157469] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.165986] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.174443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.182900] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.191355] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.199814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.208270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.216726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.225180] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.233635] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.242091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.250547] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.259002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.267458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.275912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.284368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.292825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.301280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.309735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.318191] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.326646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.335104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.343560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.352015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.360471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.368930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.377399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.377409] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  460.377412] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  460.377425] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  460.377441] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  460.378278] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  460.379799] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  460.379815] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  460.379842] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  460.379854] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  460.380645] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  460.381372] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  460.382174] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  460.382214] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  460.382216] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  460.382218] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  460.382219] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  460.382221] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  460.382222] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.382223] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  460.382225] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  460.382226] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  460.382227] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  460.382229] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  460.382230] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  460.382231] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.382245] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  460.382260] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  460.382272] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  460.382279] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  460.382294] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  460.383884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  460.383900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  460.385882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  460.385885] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  460.387881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  460.387897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  460.389874] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  460.389878] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  460.389880] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  460.389890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  460.389907] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  460.390357] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  460.390669] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  460.390717] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  460.390833] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  460.390865] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  460.391279] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  460.391591] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  460.392111] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  460.392114] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  460.392201] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  460.392202] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  460.392205] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  460.392206] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  460.392209] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  460.392210] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  460.392216] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  460.392217] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  460.392219] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  460.392220] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  460.392222] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  460.392223] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  460.392224] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  460.392226] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  460.392227] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  460.392229] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  460.392230] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  460.392231] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  460.392233] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  460.392234] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  460.392235] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  460.392237] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.392238] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.392239] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  460.392241] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  460.392242] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.392244] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.392245] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  460.392246] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  460.392248] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  460.392249] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  460.392250] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  460.392252] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  460.392253] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.392254] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.392256] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  460.392257] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.392258] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.392260] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  460.392286] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  460.392301] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  460.393883] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  460.393899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  460.395895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  460.395898] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  460.397879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  460.397895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  460.399920] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  460.399924] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  460.399926] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  460.408590] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  460.408606] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  460.417062] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.425522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.433981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.442451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.450906] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.459362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.467915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.476371] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.484829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.493287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.501745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.510201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.518656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.527111] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.535570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.544028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.552483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.560939] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.569393] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.577848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.586303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.594762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.603217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.611672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.620207] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.628664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.637122] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.645580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.654035] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.662491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.671044] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.679500] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  460.679508] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  460.679511] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  460.679811] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  460.679827] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  460.680660] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  460.682183] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  460.682213] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  460.682242] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  460.682254] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  460.683051] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  460.683766] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  460.684539] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  460.684564] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  460.684567] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  460.684569] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  460.684570] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  460.684572] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  460.684573] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.684575] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  460.684576] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  460.684591] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  460.684592] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  460.684594] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  460.684595] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  460.684596] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.684937] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  460.684959] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  460.684978] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  460.685178] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  460.685193] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  460.686884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  460.686900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  460.688912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  460.688915] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  460.691181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  460.691197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  460.693458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  460.693462] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  460.693464] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  460.693653] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  460.693673] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  460.714449] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  460.714768] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  460.714785] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  460.714800] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  460.714826] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  460.715232] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  460.715544] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  460.716063] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  460.716065] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  460.716142] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  460.716143] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  460.716146] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  460.716147] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  460.716150] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  460.716151] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  460.716157] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  460.716158] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  460.716160] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  460.716161] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  460.716163] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  460.716164] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  460.716165] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  460.716167] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  460.716168] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  460.716170] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  460.716171] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  460.716172] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  460.716174] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  460.716175] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  460.716177] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  460.716178] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.716179] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  460.716181] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  460.716182] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  460.716183] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.716185] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  460.716186] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  460.716187] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  460.716189] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  460.716190] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  460.716192] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  460.716193] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  460.716194] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.716196] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  460.716197] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  460.716198] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.716200] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  460.716201] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  460.716381] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  460.716396] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  460.717881] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  460.717897] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  460.719880] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  460.719884] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  460.721879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  460.721895] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  460.723876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  460.723880] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  460.723882] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  460.724104] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-A
>[  460.771411] PM: Syncing filesystems ... done.
>[  460.774486] PM: Preparing system for sleep (mem)
>[  460.779014] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  460.780488] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  460.781859] PM: Suspending system (mem)
>[  460.781972] Suspending console(s) (use no_console_suspend to debug)
>[  460.783628] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  460.784679] e1000e: EEE TX LPI TIMER: 00000011
>[  460.784815] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  460.784833] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  460.784846] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  460.784860] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  460.785444] sd 0:0:0:0: [sda] Stopping disk
>[  460.799201] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  460.799223] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  460.799248] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  460.799273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  460.799293] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  460.799313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  460.799335] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  460.799356] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  460.799375] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  460.799393] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  460.799410] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  460.799414] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  460.799431] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  460.799434] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  460.799451] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  460.799468] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  460.799485] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  460.799502] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  460.799517] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  460.799538] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  460.799554] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  460.799572] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  460.799588] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  460.799604] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  460.799620] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  460.799644] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  460.799663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  460.799684] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  460.799718] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  460.799737] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  460.799757] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  460.799775] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  460.799793] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  460.799810] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  460.799826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  460.799842] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  460.799845] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  460.799861] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  460.799864] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  460.799880] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  460.799896] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  460.799912] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  460.799927] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  460.799942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  460.799962] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  460.799978] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  460.799995] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  460.800011] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  460.800027] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  460.800042] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  460.800066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  460.800090] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  460.800110] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  460.800129] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  460.800147] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  460.800233] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  460.808298] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  460.808359] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  460.808413] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  460.808528] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  460.808602] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  460.816240] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  460.816295] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  460.816393] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  460.818896] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  460.818948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  460.819002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  460.819045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  460.819087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  460.819127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  460.819174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  460.819222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  460.819266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  460.819303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  460.819336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  460.819369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  460.819401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  460.819433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  460.819471] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  460.819519] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  460.819561] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  460.819600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  460.819673] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  460.819758] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  460.819809] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  460.819863] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  460.819911] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  460.819960] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  460.819998] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  460.830846] PM: suspend of devices complete after 47.982 msecs
>[  460.834127] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  460.834169] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  460.834208] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  460.834245] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  460.834281] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  460.834316] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  460.834351] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  460.834386] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  460.834421] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  460.834472] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  460.834506] [drm:intel_power_well_disable [i915]] disabling DC off
>[  460.834544] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  460.834577] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  460.835079] [drm:intel_power_well_disable [i915]] disabling always-on
>[  460.835113] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  460.837861] [drm:intel_update_cdclk [i915]] Current CD clock rate: 24000 kHz, VCO: 0 kHz, ref: 24000 kHz
>[  460.837899] [drm:intel_power_well_disable [i915]] disabling MISC IO power well
>[  460.837941] [drm:skl_set_power_well [i915]] Disabling MISC IO power well
>[  460.837980] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for MISC IO power well forced on by DMC
>[  460.838018] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  460.838062] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  460.850018] PM: late suspend of devices complete after 19.162 msecs
>[  460.855862] e1000e 0000:00:1f.6: System wakeup enabled by ACPI
>[  460.856774] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  460.881800] PM: noirq suspend of devices complete after 31.776 msecs
>[  460.882403] ACPI: Preparing to enter system sleep state S3
>[  460.902866] PM: Saving platform NVS memory
>[  460.947543] Disabling non-boot CPUs ...
>[  460.962888] smpboot: CPU 1 is now offline
>[  460.977309] smpboot: CPU 2 is now offline
>[  460.996303] smpboot: CPU 3 is now offline
>[  461.013416] Broke affinity for irq 123
>[  461.015227] smpboot: CPU 4 is now offline
>[  461.028448] Broke affinity for irq 123
>[  461.029578] smpboot: CPU 5 is now offline
>[  461.044465] Broke affinity for irq 121
>[  461.044469] Broke affinity for irq 123
>[  461.045574] smpboot: CPU 6 is now offline
>[  461.058317] Broke affinity for irq 8
>[  461.058332] Broke affinity for irq 9
>[  461.058343] Broke affinity for irq 120
>[  461.058346] Broke affinity for irq 121
>[  461.058349] Broke affinity for irq 123
>[  461.059479] smpboot: CPU 7 is now offline
>[  461.062913] ACPI: Low-level resume complete
>[  461.063086] PM: Restoring platform NVS memory
>[  461.064854] Suspended for 16.420 seconds
>[  461.064947] Enabling non-boot CPUs ...
>[  461.065060] x86: Booting SMP configuration:
>[  461.065061] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  461.066499]  cache: parent cpu1 should not be sleeping
>[  461.067820] CPU1 is up
>[  461.067904] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  461.069083]  cache: parent cpu2 should not be sleeping
>[  461.070268] CPU2 is up
>[  461.070348] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  461.071580]  cache: parent cpu3 should not be sleeping
>[  461.072877] CPU3 is up
>[  461.072962] smpboot: Booting Node 0 Processor 4 APIC 0x1
>[  461.074519]  cache: parent cpu4 should not be sleeping
>[  461.075887] CPU4 is up
>[  461.075981] smpboot: Booting Node 0 Processor 5 APIC 0x3
>[  461.077312]  cache: parent cpu5 should not be sleeping
>[  461.078719] CPU5 is up
>[  461.078811] smpboot: Booting Node 0 Processor 6 APIC 0x5
>[  461.080118]  cache: parent cpu6 should not be sleeping
>[  461.081570] CPU6 is up
>[  461.081659] smpboot: Booting Node 0 Processor 7 APIC 0x7
>[  461.082983]  cache: parent cpu7 should not be sleeping
>[  461.084481] CPU7 is up
>[  461.132090] ACPI: Waking up from system sleep state S3
>[  461.216038] acpi LNXPOWER:16: Turning OFF
>[  461.216470] acpi LNXPOWER:15: Turning OFF
>[  461.216895] acpi LNXPOWER:14: Turning OFF
>[  461.217325] acpi LNXPOWER:13: Turning OFF
>[  461.217748] acpi LNXPOWER:12: Turning OFF
>[  461.218170] acpi LNXPOWER:11: Turning OFF
>[  461.218600] acpi LNXPOWER:10: Turning OFF
>[  461.219023] acpi LNXPOWER:0f: Turning OFF
>[  461.219453] acpi LNXPOWER:0e: Turning OFF
>[  461.219876] acpi LNXPOWER:0d: Turning OFF
>[  461.220305] acpi LNXPOWER:0c: Turning OFF
>[  461.220728] acpi LNXPOWER:0b: Turning OFF
>[  461.221151] acpi LNXPOWER:0a: Turning OFF
>[  461.221580] acpi LNXPOWER:09: Turning OFF
>[  461.222003] acpi LNXPOWER:08: Turning OFF
>[  461.222434] acpi LNXPOWER:07: Turning OFF
>[  461.222857] acpi LNXPOWER:06: Turning OFF
>[  461.223288] acpi LNXPOWER:05: Turning OFF
>[  461.223712] acpi LNXPOWER:04: Turning OFF
>[  461.224135] acpi LNXPOWER:03: Turning OFF
>[  461.238628] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  461.252369] PM: noirq resume of devices complete after 27.975 msecs
>[  461.252768] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  461.252801] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  461.252830] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  461.252869] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  461.256730] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  461.258196] [drm:intel_power_well_enable [i915]] enabling always-on
>[  461.258222] [drm:intel_power_well_enable [i915]] enabling DC off
>[  461.258249] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  461.258300] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  461.258329] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  461.258354] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  461.258378] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  461.258403] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  461.258427] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  461.258452] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  461.258476] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  461.258501] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  461.258527] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  461.304932] PM: early resume of devices complete after 52.497 msecs
>[  461.309301] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  461.309375] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  461.309406] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  461.309934] sd 0:0:0:0: [sda] Starting disk
>[  461.311948] e1000e 0000:00:1f.6: System wakeup disabled by ACPI
>[  461.319410] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  461.319456] [drm:intel_opregion_setup [i915]] ASLE supported
>[  461.319501] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  461.319542] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  461.321034] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  461.328383] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.336882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.345331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.353760] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.362202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.370638] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.379065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.387498] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.395940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.404385] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.412826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.421265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.429707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.438127] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.446551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.454976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.463397] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.471834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.480257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.488675] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.497091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.505506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.513982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.522398] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.530821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.539268] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.547698] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.556114] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.564537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.572960] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.581378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.589795] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.589804] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  461.589821] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH down
>[  461.590544] [drm:lspcon_wait_mode [i915]] Current LSPCON mode LS
>[  461.614874] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  461.617593] ata1.00: supports DRM functions and may not be fully accessible
>[  461.625549] ata1.00: supports DRM functions and may not be fully accessible
>[  461.630280] [drm:drm_lspcon_set_mode] LSPCON mode changed to PCON
>[  461.630329] [drm:lspcon_change_mode.constprop.4 [i915]] LSPCON mode changed done
>[  461.630370] [drm:lspcon_resume [i915]] LSPCON resume success
>[  461.630722] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  461.630885] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  461.630889] ata1.00: configured for UDMA/133
>[  461.631069] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  461.631263] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  461.631561] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  461.631697] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  461.631716] [drm] GuC firmware load skipped
>[  461.631796] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  461.632007] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  461.632080] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  461.632149] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  461.632215] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  461.632274] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  461.632361] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  461.632419] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  461.632478] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  461.632535] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  461.632584] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  461.632633] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  461.632680] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  461.632736] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  461.632783] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  461.632830] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  461.632878] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  461.632933] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  461.632979] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  461.633026] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  461.633072] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  461.633132] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  461.633190] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  461.633247] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  461.633346] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  461.633404] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  461.633462] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  461.633525] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  461.633578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  461.633630] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  461.633676] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  461.633682] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  461.633715] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  461.633720] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  461.633754] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  461.633786] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  461.633819] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  461.633856] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.633890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  461.633933] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  461.633968] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  461.634001] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  461.634032] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  461.634062] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  461.634091] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  461.634126] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  461.634155] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  461.634183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  461.634211] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  461.634216] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  461.634244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  461.634271] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  461.634301] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  461.634331] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  461.634359] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  461.634388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.634416] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  461.634454] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  461.634483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  461.634514] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  461.634544] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  461.634573] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  461.634602] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  461.634635] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  461.634664] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  461.634692] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  461.634720] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  461.634725] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  461.634753] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  461.634757] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  461.634786] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  461.634815] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  461.634843] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  461.634871] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.634899] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  461.634936] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  461.634967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  461.634996] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  461.635025] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  461.635053] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  461.635090] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  461.635232] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  461.635298] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  461.635331] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  461.635364] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  461.635396] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  461.635427] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  461.635458] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  461.635490] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  461.635521] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  461.635568] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  461.635599] [drm:intel_power_well_disable [i915]] disabling DC off
>[  461.635632] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  461.635660] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  461.636098] [drm:intel_power_well_disable [i915]] disabling always-on
>[  461.636186] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  461.636222] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  461.636265] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  461.636332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  461.636368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  461.636407] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  461.636445] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  461.636480] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  461.636515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  461.636547] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  461.636579] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  461.636585] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  461.636615] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  461.636620] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  461.636652] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  461.636683] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  461.636713] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  461.636743] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.636772] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  461.636809] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  461.636839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  461.636871] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  461.636901] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  461.636930] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  461.636959] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  461.637004] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  461.637039] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  461.637078] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  461.637121] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  461.637157] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  461.637195] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  461.637229] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  461.637281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  461.637314] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  461.637345] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  461.637375] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  461.637380] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  461.637410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  461.637415] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  461.637446] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  461.637476] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  461.637505] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  461.637534] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  461.637563] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  461.637600] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  461.637631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  461.637663] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  461.637693] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  461.637722] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  461.637751] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  461.637789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  461.637834] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  461.637871] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  461.637907] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  461.637942] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  461.638085] [drm:intel_power_well_enable [i915]] enabling always-on
>[  461.638114] [drm:intel_power_well_enable [i915]] enabling DC off
>[  461.638426] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  461.638474] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  461.638509] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  461.638593] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  461.638627] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  461.638665] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  461.638694] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  461.638743] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  461.639400] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  461.639429] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  461.639476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  461.639519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  461.639557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  461.639593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  461.639628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  461.639662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  461.639696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  461.639729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  461.639761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  461.639792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  461.639824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  461.639854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  461.639885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  461.639921] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  461.639957] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  461.639993] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  461.640029] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  461.640068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  461.640106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  461.640141] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  461.640176] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  461.640221] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  461.640258] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  461.643920] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  461.645408] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  461.645448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  461.645486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  461.645525] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  461.650876] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  461.650916] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  461.656261] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  461.658843] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edeca88
>[  461.660121] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  461.660200] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  461.660239] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  461.660395] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  461.660432] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  461.663908] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  461.663950] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  461.663987] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  461.664027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  461.664902] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  461.664939] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  461.664974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  461.665866] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  461.665902] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  461.665936] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  461.666754] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  461.666792] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  461.667921] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  461.670270] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049edee678
>[  461.671434] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  461.671493] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  461.671531] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  461.671584] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  461.688351] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  461.688403] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  461.688490] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  461.688586] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  461.688633] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  461.688715] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  461.688759] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  461.689118] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  461.689220] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  461.697751] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.706366] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.714965] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.723571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.732174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.740792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.749432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.758039] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.766641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.770666] PM: resume of devices complete after 465.727 msecs
>[  461.773013] PM: Finishing wakeup.
>[  461.773015] Restarting tasks ... done.
>[  461.775578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.786466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.795038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.803573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.812075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.820535] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.827553] video LNXVIDEO:00: Restoring backlight state
>[  461.829429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.837889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.846345] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.854807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.863267] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.871725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.880184] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.888646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.897108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.905568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.914028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.922486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.930944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.939404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.947863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.956323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.964781] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  461.964792] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  461.964796] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  461.964813] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  461.965651] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  461.967182] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  461.967198] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  461.967213] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  461.967228] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  461.968086] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  461.968802] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  461.969547] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  461.969564] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  461.969587] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  461.969602] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  461.971906] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  461.971922] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  461.974173] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  461.974178] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  461.976503] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  461.976519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  461.978781] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  461.978785] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  461.978788] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  461.978805] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  461.979293] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  461.979615] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  461.979645] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  461.979675] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  461.979688] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  461.980095] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  461.980435] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  461.980788] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  461.980806] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  461.983084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  461.983098] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  461.985358] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  461.985362] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  461.987703] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  461.987720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  461.990007] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  461.990011] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  461.990014] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  461.990431] [drm:drm_mode_addfb2] [FB:70]
>[  461.996792] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  461.996802] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  462.027319] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  462.027382] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.027403] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  462.027418] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  462.027484] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  462.045719] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  462.045744] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  462.045766] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  462.045792] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  462.045816] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  462.045857] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  462.055670] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  462.055698] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  462.055745] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  462.062131] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  462.062163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  462.062192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  462.062216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  462.062238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  462.062304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  462.062330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  462.062356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  462.062384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  462.062408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  462.062432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  462.062461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  462.062485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  462.062509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  462.062536] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  462.062575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  462.062615] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.062649] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  462.062682] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  462.062734] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  462.062768] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  462.075613] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.084202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.092869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.101479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.110073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.118670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.127266] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.135884] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.144477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.153064] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.161656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.170327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.178858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.187363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.195848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.204321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.212787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.221255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.229074] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  462.243186] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  462.243244] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  462.243354] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  462.244409] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  462.245447] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  462.247635] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  462.247690] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  462.247740] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  462.247791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  462.253950] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  462.253997] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  462.259504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  462.262127] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044517e678
>[  462.263392] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  462.263479] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  462.263526] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  462.297026] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  462.297086] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  462.297178] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.297223] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  462.297333] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  462.297411] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  462.297477] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  462.298657] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  462.364052] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.364256] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  462.381573] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  462.381644] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  462.381707] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  462.381821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  462.381878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  462.381935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  462.381984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  462.382031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  462.382075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  462.382121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  462.382164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  462.382204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  462.382244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  462.382389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  462.382440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  462.382486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  462.382535] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  462.382597] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  462.382656] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.382710] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  462.382764] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  462.382851] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  462.382922] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  462.382996] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  462.383099] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  462.383207] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  462.383367] [drm:intel_power_well_disable [i915]] disabling DC off
>[  462.383452] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  462.383518] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  462.384026] [drm:intel_power_well_disable [i915]] disabling always-on
>[  462.386427] [drm:drm_mode_addfb2] [FB:70]
>[  462.407094] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  462.407120] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  462.407273] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  462.407408] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  462.407490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  462.407576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  462.407634] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  462.407687] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  462.407736] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  462.407783] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  462.407827] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  462.407870] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  462.407911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  462.407922] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  462.407960] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  462.407968] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  462.408009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  462.408049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  462.408087] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  462.408125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  462.408164] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  462.408212] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  462.408251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  462.408349] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  462.408407] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  462.408466] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  462.408533] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.408607] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  462.408673] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  462.409816] [drm:intel_power_well_enable [i915]] enabling always-on
>[  462.409853] [drm:intel_power_well_enable [i915]] enabling DC off
>[  462.410151] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  462.410206] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  462.410253] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  462.410398] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  462.410438] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  462.410504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  462.410558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  462.410603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  462.410650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  462.410693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  462.410737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  462.410779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  462.410822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  462.410862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  462.410903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  462.410944] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  462.410985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  462.411023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  462.411069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  462.411120] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.411166] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  462.411212] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  462.411269] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  462.411353] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  462.424524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.433199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.441961] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.450636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.459320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.468038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.476762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.485491] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.494177] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.502951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.511636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.520295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.528873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.537423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.545942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.554439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.562918] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.571453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  462.577589] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  462.591790] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  462.591809] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  462.591860] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  462.593100] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  462.595690] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  462.597030] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  462.597045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  462.597059] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  462.597085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  462.602223] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  462.602239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  462.607445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  462.609918] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445178008
>[  462.610488] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  462.610555] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  462.610569] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  462.627373] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  462.627393] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  462.627426] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.711097] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.711411] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  462.728359] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  462.728429] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  462.728489] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  462.728602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  462.728659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  462.728715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  462.728764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  462.728811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  462.728857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  462.728904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  462.728947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  462.728988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  462.729029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  462.729073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  462.729115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  462.729156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  462.729204] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  462.729260] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  462.729402] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.729463] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  462.729516] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  462.729597] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  462.729650] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  462.729694] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  462.729760] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  462.729833] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  462.729893] [drm:intel_power_well_disable [i915]] disabling DC off
>[  462.729943] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  462.729983] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  462.730478] [drm:intel_power_well_disable [i915]] disabling always-on
>[  462.732639] [drm:drm_mode_addfb2] [FB:70]
>[  462.779032] [drm] RC6 on
>[  462.809358] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  462.809384] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  462.809544] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  462.809598] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  462.809654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  462.809713] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  462.809760] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  462.809811] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  462.809862] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  462.809909] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  462.809954] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  462.809998] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  462.810039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  462.810047] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  462.810088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  462.810095] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  462.810138] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  462.810178] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  462.810218] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  462.810257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  462.810350] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  462.810405] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  462.810473] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  462.810511] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  462.810551] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  462.810590] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  462.810655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  462.810711] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  462.810757] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  462.813826] [drm:intel_power_well_enable [i915]] enabling always-on
>[  462.813861] [drm:intel_power_well_enable [i915]] enabling DC off
>[  462.814166] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  462.814218] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  462.814258] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  462.814388] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  462.814426] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  462.814482] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  462.816762] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  462.816816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  462.816868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  462.816913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  462.816953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  462.816993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  462.817032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  462.817072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  462.817109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  462.817145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  462.817182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  462.817218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  462.817253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  462.817353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  462.817404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  462.817457] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.817506] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  462.817559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  462.817620] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  462.817669] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  462.821199] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  462.821249] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  462.821367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  462.821546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  462.822403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  462.822446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  462.822486] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  462.823343] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  462.823388] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  462.823431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  462.824232] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  462.824315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  462.825440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  462.827841] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044517a548
>[  462.828993] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  462.829064] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  462.829106] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  462.829161] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  462.829285] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  462.829411] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  462.845951] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  462.846021] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  462.846124] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.929523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  462.929670] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  462.929729] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  462.929854] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  462.948019] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  462.948080] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  462.948136] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  462.948237] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  462.950593] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  462.950652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  462.950707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  462.950756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  462.950800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  462.950843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  462.950885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  462.950929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  462.950970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  462.951009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  462.951049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  462.951093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  462.951132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  462.951170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  462.951215] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  462.951268] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  462.951397] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  462.951456] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  462.951509] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  462.951580] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  462.951628] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  462.951677] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  462.951740] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  462.951807] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  462.951866] [drm:intel_power_well_disable [i915]] disabling DC off
>[  462.951913] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  462.951952] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  462.952443] [drm:intel_power_well_disable [i915]] disabling always-on
>[  462.954109] [drm:drm_mode_addfb2] [FB:70]
>[  463.013121] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  463.013147] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  463.013391] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  463.013462] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  463.013540] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  463.013609] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  463.013656] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  463.013707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  463.013758] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  463.013804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  463.013850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  463.013893] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  463.013934] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  463.013944] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  463.013982] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  463.013991] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  463.014033] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  463.014070] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  463.014109] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  463.014149] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  463.014187] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  463.014234] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  463.014339] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  463.014394] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  463.014453] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  463.014512] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  463.014607] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  463.014680] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  463.014747] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  463.018091] [drm:intel_power_well_enable [i915]] enabling always-on
>[  463.018128] [drm:intel_power_well_enable [i915]] enabling DC off
>[  463.018514] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  463.018988] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  463.019031] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  463.019127] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  463.019164] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  463.019224] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  463.019513] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  463.019566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  463.019620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  463.019666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  463.019713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  463.019754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  463.019799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  463.019841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  463.019885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  463.019925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  463.019967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  463.020004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  463.020044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  463.020082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  463.020126] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  463.020174] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  463.020223] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  463.020270] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  463.020409] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  463.020477] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  463.024041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  463.024093] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  463.024140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  463.024187] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  463.025185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  463.025232] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  463.025362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  463.026219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  463.026265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  463.026390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  463.027240] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  463.027367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  463.028605] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  463.030978] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445179bf8
>[  463.032212] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  463.032323] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  463.032372] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[  463.032439] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  463.032577] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  463.032645] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  463.049165] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  463.049235] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  463.049418] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  463.132804] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  463.132989] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  463.133062] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  463.133207] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  463.150391] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  463.150462] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  463.150523] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  463.150635] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  463.153019] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  463.153087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  463.153150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  463.153207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  463.153257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  463.153397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  463.153458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  463.153520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  463.153570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  463.153621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  463.153673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  463.153735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  463.153784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  463.153835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  463.153894] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  463.153965] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  463.154025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  463.154081] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  463.154133] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  463.154218] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  463.154270] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  463.154368] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  463.154441] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  463.154517] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  463.154581] [drm:intel_power_well_disable [i915]] disabling DC off
>[  463.154631] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  463.154675] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  463.155142] [drm:intel_power_well_disable [i915]] disabling always-on
>[  463.156551] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  463.206135] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  463.206166] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  463.206198] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  463.206232] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  463.206298] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  463.206327] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  463.206356] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  463.206382] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  463.206407] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  463.206431] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  463.206454] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  463.206459] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  463.206482] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  463.206486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  463.206509] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  463.206532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  463.206554] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  463.206575] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  463.206597] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  463.206623] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  463.206645] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  463.206667] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  463.206688] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  463.206709] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  463.206742] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  463.206767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  463.206794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  463.206826] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  463.206852] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  463.206878] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  463.206902] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  463.206925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  463.206948] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  463.206970] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  463.206991] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  463.206995] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  463.207016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  463.207019] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  463.207041] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  463.207063] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  463.207084] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  463.207105] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  463.207125] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  463.207152] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  463.207173] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  463.207195] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  463.207216] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  463.207237] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  463.207281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  463.207313] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  463.207339] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  463.207365] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  463.207389] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  463.207500] [drm:intel_power_well_enable [i915]] enabling always-on
>[  463.207520] [drm:intel_power_well_enable [i915]] enabling DC off
>[  463.207818] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  463.207854] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  463.207877] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  463.207923] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  463.207958] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  463.207993] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  463.208014] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  463.208045] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  463.208580] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  463.208600] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  463.208633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  463.208662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  463.208687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  463.208712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  463.208736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  463.208759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  463.208782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  463.208802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  463.208823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  463.208844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  463.208865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  463.208885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  463.208906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  463.208929] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  463.208957] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  463.208983] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  463.209008] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  463.209038] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  463.209063] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  463.221033] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.229546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.238056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.246566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.255075] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.263584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.272259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.299786] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.308295] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.316804] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.325312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.333820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.342347] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.350855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.359364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.367872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  463.374051] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  463.388594] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  463.388612] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  463.388647] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  463.389750] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  463.392376] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  463.393724] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  463.393739] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  463.393753] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  463.393780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  463.398926] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  463.398940] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  463.404087] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  463.406575] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445178958
>[  463.407081] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  463.407147] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  463.407160] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  463.407207] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  463.407220] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  463.410484] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  463.410500] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  463.410514] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  463.410529] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  463.411187] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  463.411201] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  463.411214] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  463.411861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  463.411874] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  463.411887] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  463.412548] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  463.412562] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  463.413522] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  463.415792] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044517efc8
>[  463.416324] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  463.416350] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  463.416364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  463.416385] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  463.433163] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  463.433185] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  463.433224] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  463.433282] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  463.433302] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  463.433338] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  463.433469] Console: switching to colour frame buffer device 240x75
>[  463.619424] Console: switching to colour dummy device 80x25
>[  463.619515] [IGT] kms_pipe_crc_basic: executing
>[  463.635531] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  463.635555] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  463.644051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.652513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.660971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.669430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.677885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.686344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.694800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.703256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.711712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.720168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.728625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.737080] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.745537] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.753994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.762449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.770904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.779361] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.787816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.796275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.804731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.813188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.821643] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.830098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.838555] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.847011] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.855467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.863922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.872379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.880834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.889288] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.897745] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.906312] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.906327] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  463.906331] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  463.906343] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  463.906359] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  463.907207] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  463.908731] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  463.908748] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  463.908762] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  463.908776] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  463.909573] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  463.910296] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  463.911089] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  463.911113] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  463.911117] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  463.911119] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  463.911120] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  463.911121] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  463.911123] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  463.911124] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  463.911126] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  463.911127] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  463.911128] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  463.911130] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  463.911131] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  463.911132] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  463.911147] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  463.911162] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  463.911185] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  463.911192] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  463.911207] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  463.911512] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  463.911531] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  463.913455] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  463.913459] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  463.915449] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  463.915465] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  463.917444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  463.917448] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  463.917451] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  463.917461] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  463.917478] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  463.917933] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  463.918277] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  463.918315] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  463.918335] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  463.918357] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  463.918771] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  463.919098] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  463.919616] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  463.919618] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  463.919698] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  463.919700] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  463.919703] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  463.919704] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  463.919707] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  463.919708] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  463.919713] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  463.919715] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  463.919716] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  463.919718] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  463.919719] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  463.919721] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  463.919722] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  463.919723] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  463.919725] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  463.919726] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  463.919728] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  463.919729] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  463.919730] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  463.919732] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  463.919733] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  463.919734] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  463.919736] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  463.919737] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  463.919738] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  463.919740] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  463.919741] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  463.919742] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  463.919744] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  463.919745] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  463.919747] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  463.919748] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  463.919749] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  463.919751] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  463.919752] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  463.919753] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  463.919755] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  463.919756] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  463.919757] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  463.919783] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  463.919798] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  463.921428] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  463.921442] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  463.923458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  463.923461] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  463.925443] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  463.925459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  463.927490] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  463.927493] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  463.927496] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  463.936099] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  463.936116] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  463.944578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.953041] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.961499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.969957] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.978415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.986870] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  463.995327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.003784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.012317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.020772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.029229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.037709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.046166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.054625] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.063081] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.071538] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.079994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.088449] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.096907] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.105364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.113821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.122278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.130734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.139189] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.147645] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.156102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.164558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.173015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.181472] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.189928] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.198385] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.206841] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.206850] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  464.206853] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  464.207035] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  464.207051] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  464.207891] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  464.209436] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  464.209453] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  464.209480] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  464.209492] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  464.210297] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  464.211007] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  464.211788] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  464.211825] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  464.211827] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  464.211828] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  464.211830] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  464.211831] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  464.211833] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  464.211834] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  464.211836] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  464.211837] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  464.211838] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  464.211840] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  464.211841] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  464.211842] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  464.212041] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  464.212059] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  464.212078] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  464.212304] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  464.212321] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  464.214442] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  464.214458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  464.216470] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  464.216474] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  464.218753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  464.218769] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  464.221047] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  464.221051] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  464.221054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  464.221302] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  464.221320] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  464.221779] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  464.222093] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  464.222109] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  464.222123] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  464.222137] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  464.222558] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  464.222873] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  464.223387] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  464.223389] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  464.223470] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  464.223471] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  464.223474] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  464.223475] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  464.223478] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  464.223479] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  464.223486] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  464.223488] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  464.223489] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  464.223491] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  464.223492] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  464.223494] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  464.223495] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  464.223497] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  464.223498] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  464.223500] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  464.223501] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  464.223503] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  464.223504] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  464.223506] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  464.223507] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  464.223509] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  464.223510] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  464.223512] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  464.223513] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  464.223515] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  464.223516] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  464.223518] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  464.223519] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  464.223521] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  464.223522] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  464.223524] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  464.223525] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  464.223527] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  464.223528] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  464.223530] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  464.223531] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  464.223533] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  464.223534] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  464.223737] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  464.223754] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  464.226032] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  464.226049] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  464.228341] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  464.228345] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  464.230624] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  464.230641] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  464.232918] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  464.232922] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  464.232925] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  464.233148] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-B
>[  464.278037] PM: Syncing filesystems ... done.
>[  464.280856] PM: Preparing system for sleep (mem)
>[  464.281406] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[  464.282998] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  464.284552] PM: Suspending system (mem)
>[  464.284715] Suspending console(s) (use no_console_suspend to debug)
>[  464.286826] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  464.288189] e1000e: EEE TX LPI TIMER: 00000011
>[  464.288337] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  464.288360] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  464.288378] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  464.288396] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  464.289479] sd 0:0:0:0: [sda] Stopping disk
>[  464.301475] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  464.301506] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  464.301539] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  464.301573] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  464.301601] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  464.301630] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  464.301659] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  464.301687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  464.301714] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  464.301738] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  464.301761] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  464.301766] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  464.301789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  464.301792] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  464.301816] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  464.301838] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  464.301860] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  464.301881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  464.301903] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  464.301930] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  464.301952] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  464.301975] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  464.301997] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  464.302018] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  464.302042] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  464.302074] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  464.302100] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  464.302128] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  464.302159] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  464.302184] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  464.302210] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  464.302236] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  464.302288] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  464.302311] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  464.302334] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  464.302355] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  464.302359] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  464.302380] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  464.302384] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  464.302406] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  464.302446] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  464.302471] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  464.302497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  464.302522] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  464.302555] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  464.302581] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  464.302609] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  464.302635] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  464.302660] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  464.302685] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  464.302725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  464.302763] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  464.302795] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  464.302826] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  464.302855] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  464.302987] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  464.309744] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  464.309788] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  464.309826] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  464.309907] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  464.309961] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  464.318605] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  464.318660] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  464.318764] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  464.321033] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  464.321096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  464.321161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  464.321213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  464.321277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  464.321409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  464.321455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  464.321506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  464.321547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  464.321589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  464.321630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  464.321671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  464.321711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  464.321751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  464.321797] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  464.321850] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  464.321901] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  464.321950] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  464.322041] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  464.322095] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  464.322156] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  464.322215] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  464.322268] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  464.322371] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  464.322422] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  464.336761] PM: suspend of devices complete after 50.830 msecs
>[  464.340865] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  464.340917] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  464.340965] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  464.341011] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  464.341055] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  464.341098] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  464.341142] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  464.341185] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  464.341229] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  464.341307] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  464.341366] [drm:intel_power_well_disable [i915]] disabling DC off
>[  464.341416] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  464.341457] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  464.341907] [drm:intel_power_well_disable [i915]] disabling always-on
>[  464.341948] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  464.342210] [drm:intel_update_cdclk [i915]] Current CD clock rate: 24000 kHz, VCO: 0 kHz, ref: 24000 kHz
>[  464.342252] [drm:intel_power_well_disable [i915]] disabling MISC IO power well
>[  464.342325] [drm:skl_set_power_well [i915]] Disabling MISC IO power well
>[  464.342369] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for MISC IO power well forced on by DMC
>[  464.342412] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  464.342463] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  464.354419] PM: late suspend of devices complete after 17.648 msecs
>[  464.366496] e1000e 0000:00:1f.6: System wakeup enabled by ACPI
>[  464.375884] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  464.399398] PM: noirq suspend of devices complete after 44.971 msecs
>[  464.400135] ACPI: Preparing to enter system sleep state S3
>[  464.423893] PM: Saving platform NVS memory
>[  464.424150] Disabling non-boot CPUs ...
>[  464.439402] smpboot: CPU 1 is now offline
>[  464.453804] smpboot: CPU 2 is now offline
>[  464.472863] smpboot: CPU 3 is now offline
>[  464.487724] Broke affinity for irq 123
>[  464.489709] smpboot: CPU 4 is now offline
>[  464.503469] Broke affinity for irq 123
>[  464.504619] smpboot: CPU 5 is now offline
>[  464.524251] Broke affinity for irq 121
>[  464.524256] Broke affinity for irq 123
>[  464.525392] smpboot: CPU 6 is now offline
>[  464.533598] Broke affinity for irq 8
>[  464.533613] Broke affinity for irq 9
>[  464.533626] Broke affinity for irq 120
>[  464.533630] Broke affinity for irq 121
>[  464.533633] Broke affinity for irq 123
>[  464.534747] smpboot: CPU 7 is now offline
>[  464.538127] ACPI: Low-level resume complete
>[  464.538301] PM: Restoring platform NVS memory
>[  464.539179] Suspended for 15.529 seconds
>[  464.539272] Enabling non-boot CPUs ...
>[  464.539385] x86: Booting SMP configuration:
>[  464.539386] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  464.540825]  cache: parent cpu1 should not be sleeping
>[  464.542121] CPU1 is up
>[  464.542204] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  464.543391]  cache: parent cpu2 should not be sleeping
>[  464.544564] CPU2 is up
>[  464.544641] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  464.545818]  cache: parent cpu3 should not be sleeping
>[  464.547103] CPU3 is up
>[  464.547187] smpboot: Booting Node 0 Processor 4 APIC 0x1
>[  464.548588]  cache: parent cpu4 should not be sleeping
>[  464.549911] CPU4 is up
>[  464.550040] smpboot: Booting Node 0 Processor 5 APIC 0x3
>[  464.551333]  cache: parent cpu5 should not be sleeping
>[  464.552702] CPU5 is up
>[  464.552789] smpboot: Booting Node 0 Processor 6 APIC 0x5
>[  464.554087]  cache: parent cpu6 should not be sleeping
>[  464.555484] CPU6 is up
>[  464.555570] smpboot: Booting Node 0 Processor 7 APIC 0x7
>[  464.556913]  cache: parent cpu7 should not be sleeping
>[  464.558388] CPU7 is up
>[  464.564436] ACPI: Waking up from system sleep state S3
>[  464.649058] acpi LNXPOWER:16: Turning OFF
>[  464.649489] acpi LNXPOWER:15: Turning OFF
>[  464.649919] acpi LNXPOWER:14: Turning OFF
>[  464.650357] acpi LNXPOWER:13: Turning OFF
>[  464.650786] acpi LNXPOWER:12: Turning OFF
>[  464.651224] acpi LNXPOWER:11: Turning OFF
>[  464.651653] acpi LNXPOWER:10: Turning OFF
>[  464.652091] acpi LNXPOWER:0f: Turning OFF
>[  464.652520] acpi LNXPOWER:0e: Turning OFF
>[  464.652949] acpi LNXPOWER:0d: Turning OFF
>[  464.653386] acpi LNXPOWER:0c: Turning OFF
>[  464.653814] acpi LNXPOWER:0b: Turning OFF
>[  464.654251] acpi LNXPOWER:0a: Turning OFF
>[  464.654679] acpi LNXPOWER:09: Turning OFF
>[  464.655116] acpi LNXPOWER:08: Turning OFF
>[  464.655545] acpi LNXPOWER:07: Turning OFF
>[  464.655995] acpi LNXPOWER:06: Turning OFF
>[  464.656437] acpi LNXPOWER:05: Turning OFF
>[  464.656865] acpi LNXPOWER:04: Turning OFF
>[  464.657301] acpi LNXPOWER:03: Turning OFF
>[  464.674755] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  464.686116] PM: noirq resume of devices complete after 28.560 msecs
>[  464.687119] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  464.687155] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  464.687186] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  464.687228] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  464.690885] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  464.692454] [drm:intel_power_well_enable [i915]] enabling always-on
>[  464.692481] [drm:intel_power_well_enable [i915]] enabling DC off
>[  464.692510] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  464.692546] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  464.692576] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  464.692603] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  464.692629] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  464.692657] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  464.692682] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  464.692708] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  464.692733] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  464.692759] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  464.692786] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  464.741759] PM: early resume of devices complete after 55.251 msecs
>[  464.746322] sd 0:0:0:0: [sda] Starting disk
>[  464.746894] e1000e 0000:00:1f.6: System wakeup disabled by ACPI
>[  464.746939] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  464.747051] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  464.747091] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  464.756441] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  464.756476] [drm:intel_opregion_setup [i915]] ASLE supported
>[  464.756506] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  464.756537] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  464.758799] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  464.765327] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.773803] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.782237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.790665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.799105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.807529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.815956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.824408] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.832832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.841249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.849672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.858099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.866525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.874947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.883391] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.891809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.900237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.908665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.917174] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.925590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.934018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.942433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.950848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.959263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.967694] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.976126] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.984546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  464.992971] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.001396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.009811] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.018225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.026644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.026653] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  465.026669] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH down
>[  465.027404] [drm:lspcon_wait_mode [i915]] Current LSPCON mode LS
>[  465.050549] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  465.053265] ata1.00: supports DRM functions and may not be fully accessible
>[  465.061161] ata1.00: supports DRM functions and may not be fully accessible
>[  465.066554] ata1.00: configured for UDMA/133
>[  465.068022] [drm:drm_lspcon_set_mode] LSPCON mode changed to PCON
>[  465.068075] [drm:lspcon_change_mode.constprop.4 [i915]] LSPCON mode changed done
>[  465.068117] [drm:lspcon_resume [i915]] LSPCON resume success
>[  465.068477] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  465.068627] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  465.068753] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  465.068876] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  465.069021] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  465.069109] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  465.069123] [drm] GuC firmware load skipped
>[  465.069180] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  465.069373] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  465.069425] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  465.069473] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  465.069518] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  465.069559] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  465.069599] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  465.069639] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  465.069681] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  465.069720] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  465.069755] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  465.069788] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  465.069822] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  465.069860] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  465.069893] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  465.069926] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  465.069959] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  465.070021] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  465.070053] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  465.070086] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  465.070118] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  465.070158] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  465.070198] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  465.070237] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  465.070275] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  465.070314] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  465.070353] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  465.070398] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  465.070437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  465.070475] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  465.070511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.070518] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  465.070553] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.070558] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  465.070595] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  465.070631] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  465.070666] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  465.070701] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.070734] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.070776] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.070810] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.070846] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  465.070880] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  465.070913] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  465.070946] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  465.070982] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  465.071045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  465.071077] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  465.071109] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.071115] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  465.071146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.071151] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  465.071183] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  465.071214] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  465.071246] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  465.071278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.071309] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.071350] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.071383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.071417] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  465.071449] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  465.071481] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  465.071512] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  465.071548] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  465.071578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  465.071609] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  465.071639] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.071644] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  465.071674] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.071679] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  465.071710] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  465.071740] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  465.071771] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  465.071802] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.071833] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.071873] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.071905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.071937] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  465.071968] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  465.072021] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  465.072061] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  465.072214] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  465.072251] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  465.072287] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  465.072322] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  465.072356] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  465.072390] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  465.072424] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  465.072458] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  465.072491] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  465.072542] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  465.072576] [drm:intel_power_well_disable [i915]] disabling DC off
>[  465.072612] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  465.072643] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  465.073122] [drm:intel_power_well_disable [i915]] disabling always-on
>[  465.073217] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  465.073257] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  465.073303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  465.073353] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  465.073392] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  465.073434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.073475] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  465.073512] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  465.073550] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  465.073584] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  465.073618] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.073624] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  465.073657] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.073662] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  465.073698] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  465.073732] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  465.073765] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.073798] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.073830] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.073871] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.073903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.073938] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  465.073971] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  465.074026] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  465.074058] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  465.074106] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  465.074144] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  465.074186] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  465.074233] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  465.074272] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  465.074313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.074350] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  465.074386] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  465.074420] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  465.074454] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  465.074487] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.074493] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  465.074525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.074530] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  465.074564] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  465.074596] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  465.074628] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.074659] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.074691] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.074731] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.074764] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.074799] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  465.074832] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  465.074863] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  465.074894] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  465.074935] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  465.074983] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  465.075045] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  465.075085] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  465.075123] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  465.075283] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.075314] [drm:intel_power_well_enable [i915]] enabling DC off
>[  465.075624] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  465.075676] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.075714] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.075808] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  465.075844] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  465.075886] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  465.075919] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  465.075971] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  465.076675] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  465.076707] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  465.076759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  465.076805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  465.076846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  465.076885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  465.076924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  465.076961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  465.077026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  465.077061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  465.077096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  465.077130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  465.077163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  465.077197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  465.077229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  465.077268] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  465.077308] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  465.077347] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  465.077386] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  465.077430] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  465.077471] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  465.077510] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  465.077549] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  465.077597] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  465.077638] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  465.081261] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  465.082761] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  465.082804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  465.082844] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.082886] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  465.088263] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  465.088305] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  465.093704] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  465.096285] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044517d3d8
>[  465.097753] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  465.097877] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  465.097918] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  465.098064] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  465.098104] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  465.101620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  465.101662] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  465.101699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.101736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  465.102644] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  465.102684] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  465.102721] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  465.103632] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  465.103667] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  465.103700] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  465.104549] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  465.104589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  465.105739] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  465.108106] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044517ca88
>[  465.109322] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  465.109389] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  465.109425] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  465.109477] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  465.126246] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  465.126295] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  465.126382] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  465.126477] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  465.126525] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  465.126607] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  465.126651] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  465.127035] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  465.127136] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  465.135640] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.144241] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.152844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.161447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.170048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.178648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.187247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.195848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.203686] PM: resume of devices complete after 461.921 msecs
>[  465.204446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.206248] PM: Finishing wakeup.
>[  465.206251] Restarting tasks ... done.
>[  465.225203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.233782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.242364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.252934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.261440] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.266299] video LNXVIDEO:00: Restoring backlight state
>[  465.271553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.280003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.288462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.296921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.305379] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.313840] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.322299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.330757] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.339215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.347671] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.356128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.364585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.373043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.381499] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.389956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.398439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.406899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.415358] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  465.415368] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  465.415372] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  465.415388] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  465.416260] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  465.417817] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  465.417833] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  465.417848] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  465.417862] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  465.418679] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  465.419405] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  465.420151] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  465.420168] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  465.420192] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  465.420219] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  465.422483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  465.422499] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  465.424758] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  465.424763] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  465.427061] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  465.427077] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  465.429353] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  465.429357] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  465.429360] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  465.429376] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  465.429842] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  465.430294] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  465.430310] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  465.430337] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  465.430350] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  465.430759] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  465.431129] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  465.431478] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  465.431495] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  465.433762] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  465.433776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  465.436074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  465.436077] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  465.438346] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  465.438362] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  465.440638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  465.440642] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  465.440645] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  465.440933] [drm:drm_mode_addfb2] [FB:68]
>[  465.447155] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  465.447198] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  465.447282] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  465.449765] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  465.449784] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  465.449802] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  465.449851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  465.449865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  465.449880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  465.449892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  465.449904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  465.449916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  465.449928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  465.449940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  465.449951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  465.449962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  465.450030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  465.450055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  465.450081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  465.450097] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  465.450113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  465.450130] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  465.450145] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  465.450160] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  465.459548] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  465.459564] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  465.459588] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  465.459607] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  465.459700] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  465.459708] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  465.459756] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  465.459771] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  465.459788] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  465.459806] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  465.459819] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  465.459833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.459848] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  465.459862] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  465.459875] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  465.459888] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  465.459900] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.459902] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  465.459914] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.459915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  465.459928] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  465.459940] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  465.459951] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.459962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.460078] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.460098] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.460116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.460134] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  465.460150] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  465.460167] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  465.460182] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  465.460206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.460226] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  465.460243] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  465.460638] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  465.460652] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  465.460674] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  465.460693] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  465.460749] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  465.477629] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  465.477651] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  465.477678] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  465.478067] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  465.478092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  465.478115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  465.478135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  465.478153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  465.478171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  465.478188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  465.478220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  465.478239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  465.478255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  465.478269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  465.478292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  465.478311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  465.478341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  465.478364] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  465.478392] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  465.478417] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  465.478441] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  465.478464] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  465.478493] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  465.478516] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  465.491046] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.499518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.508006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.516486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.524962] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.533448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.541921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.550395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.558869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.567339] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.575806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.584273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.592740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.601208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.609750] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.618218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.626685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.635152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.643619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.644716] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  465.658816] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  465.658849] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  465.658880] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  465.660283] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  465.662880] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  465.664222] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  465.664237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  465.664251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  465.664266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  465.669425] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  465.669442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  465.674582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  465.677066] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445295d28
>[  465.677531] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  465.694387] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  465.694403] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  465.694444] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  465.694471] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  465.694507] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  465.711056] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  465.778115] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.778294] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  465.796719] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  465.796780] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  465.796883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  465.796935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  465.796988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  465.797149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  465.797209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  465.797268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  465.797333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  465.797390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  465.797451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  465.797505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  465.797568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  465.797622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  465.797680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  465.797740] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  465.797818] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  465.797891] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  465.797956] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  465.798047] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  465.798149] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  465.798214] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  465.798281] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  465.798372] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  465.798467] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  465.798540] [drm:intel_power_well_disable [i915]] disabling DC off
>[  465.798605] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  465.798658] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  465.799201] [drm:intel_power_well_disable [i915]] disabling always-on
>[  465.801248] [drm:drm_mode_addfb2] [FB:68]
>[  465.821279] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  465.821303] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  465.821442] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  465.821490] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  465.821541] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  465.821595] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  465.821637] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  465.821683] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  465.821729] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  465.821771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  465.821812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  465.821851] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  465.821889] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  465.821895] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  465.821932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  465.821938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  465.821976] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  465.822065] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  465.822106] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  465.822150] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  465.822188] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  465.822239] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  465.822282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  465.822323] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  465.822367] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  465.822406] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  465.822456] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  465.822512] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  465.822562] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  465.823600] [drm:intel_power_well_enable [i915]] enabling always-on
>[  465.823638] [drm:intel_power_well_enable [i915]] enabling DC off
>[  465.823954] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  465.824062] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  465.824115] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  465.824214] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  465.824254] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  465.824312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  465.824360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  465.824401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  465.824442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  465.824480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  465.824519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  465.824559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  465.824597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  465.824633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  465.824670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  465.824707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  465.824743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  465.824778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  465.824818] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  465.824862] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  465.824904] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  465.824946] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  465.824996] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  465.825070] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  465.838215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.846903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.855673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.864370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.873058] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.881791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.890478] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.899209] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.907894] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.916571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.925255] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.933937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.942685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.951261] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.959794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.968301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.976787] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.985259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  465.991410] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  466.005478] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  466.005496] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  466.005554] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  466.007037] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  466.009385] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  466.010808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.010823] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.010836] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.010851] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.015992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.016007] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  466.021144] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.023614] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e412a8
>[  466.024123] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  466.040971] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  466.041016] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  466.041052] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.124611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.124779] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  466.143004] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  466.143132] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  466.143237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  466.143293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  466.143343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  466.143387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  466.143429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  466.143469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  466.143511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  466.143549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  466.143585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  466.143621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  466.143660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  466.143697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  466.143732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  466.143775] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  466.143826] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  466.143873] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.143918] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  466.143964] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  466.144139] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  466.144210] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  466.144278] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  466.144370] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  466.144466] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  466.144540] [drm:intel_power_well_disable [i915]] disabling DC off
>[  466.144606] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  466.144669] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  466.145198] [drm:intel_power_well_disable [i915]] disabling always-on
>[  466.147369] [drm:drm_mode_addfb2] [FB:68]
>[  466.223575] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  466.223601] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  466.223756] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  466.223808] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  466.223865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  466.223946] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  466.224012] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  466.224146] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  466.224205] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  466.224257] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  466.224306] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  466.224349] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  466.224394] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  466.224406] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  466.224447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  466.224461] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  466.224502] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  466.224544] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  466.224591] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  466.224632] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  466.224671] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  466.224719] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  466.224760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  466.224803] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  466.224842] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  466.224882] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  466.224973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  466.225094] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  466.225149] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  466.228637] [drm:intel_power_well_enable [i915]] enabling always-on
>[  466.228675] [drm:intel_power_well_enable [i915]] enabling DC off
>[  466.229003] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  466.229547] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  466.229585] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  466.229653] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  466.229689] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  466.229748] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  466.232248] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  466.232308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  466.232366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  466.232416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  466.232461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  466.232504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  466.232548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  466.232591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  466.232630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  466.232669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  466.232707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  466.232745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  466.232782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  466.232819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  466.232864] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  466.232915] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.232962] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  466.233073] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  466.233138] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  466.233189] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  466.236713] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.236890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.236938] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.236985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.237968] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  466.238083] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  466.238136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  466.239112] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  466.239158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  466.239200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  466.240121] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.240178] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  466.241359] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.243722] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e41bf8
>[  466.244941] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  466.245063] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  466.245116] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  466.245186] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  466.261894] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  466.261964] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  466.262154] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.345443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.345593] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  466.345659] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  466.345765] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  466.362102] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  466.362163] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  466.362267] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  466.365384] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  466.365444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  466.365502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  466.365552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  466.365596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  466.365640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  466.365682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  466.365726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  466.365767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  466.365807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  466.365847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  466.365893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  466.365932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  466.365971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  466.366108] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  466.366171] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  466.366239] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.366297] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  466.366353] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  466.366435] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  466.366499] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  466.366565] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  466.366663] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  466.366762] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  466.366836] [drm:intel_power_well_disable [i915]] disabling DC off
>[  466.366903] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  466.366962] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  466.367507] [drm:intel_power_well_disable [i915]] disabling always-on
>[  466.369290] [drm:drm_mode_addfb2] [FB:68]
>[  466.411656] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  466.411667] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  466.411731] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  466.411752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  466.411774] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  466.411797] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  466.411816] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  466.411834] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  466.411854] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  466.411872] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  466.411890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  466.411907] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  466.411923] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  466.411926] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  466.411941] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  466.411944] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  466.411960] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  466.412002] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  466.412018] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  466.412034] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  466.412052] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  466.412073] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  466.412090] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  466.412107] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  466.412124] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  466.412141] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  466.412170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  466.412193] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[  466.412213] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  466.413403] [drm:intel_power_well_enable [i915]] enabling always-on
>[  466.413414] [drm:intel_power_well_enable [i915]] enabling DC off
>[  466.413701] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  466.413720] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  466.413732] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  466.413766] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  466.413784] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  466.413806] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  466.416040] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  466.416060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  466.416079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  466.416095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  466.416111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  466.416125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  466.416140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  466.416154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  466.416168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  466.416181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  466.416194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  466.416207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  466.416220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  466.416233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  466.416248] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  466.416266] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.416283] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  466.416298] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  466.416318] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[  466.416334] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  466.419574] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.419590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.419605] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.419632] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.420294] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  466.420310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  466.420324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  466.421012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  466.421034] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  466.421068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  466.421720] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.421734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  466.422687] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.424957] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e46678
>[  466.425454] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  466.425483] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  466.425497] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  466.425515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  466.442352] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  466.442372] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  466.442406] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.526212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  466.526384] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  466.526460] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  466.526577] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  466.543162] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[  466.543231] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  466.543346] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  466.543551] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  466.543607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  466.543662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  466.543713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  466.543761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  466.543806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  466.543848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  466.543892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  466.543933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  466.543973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  466.544114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  466.544176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  466.544222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  466.544264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  466.544313] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  466.544377] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  466.544433] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.544487] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  466.544544] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  466.544633] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  466.544706] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  466.544783] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  466.544886] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  466.544995] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  466.545139] [drm:intel_power_well_disable [i915]] disabling DC off
>[  466.545216] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  466.545280] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  466.545769] [drm:intel_power_well_disable [i915]] disabling always-on
>[  466.547464] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  466.549765] [drm] RC6 on
>[  466.587246] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  466.587305] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  466.587368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  466.587434] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  466.587485] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  466.587539] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  466.587594] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  466.587645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  466.587696] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  466.587743] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  466.587789] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  466.587798] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  466.587843] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  466.587850] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  466.587897] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  466.587943] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  466.587987] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  466.588063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  466.588106] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  466.588161] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  466.588205] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  466.588249] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  466.588291] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  466.588334] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  466.588398] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  466.588448] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  466.588503] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  466.588565] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  466.588615] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  466.588668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  466.588718] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  466.588765] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  466.588812] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  466.588856] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  466.588899] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  466.588906] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  466.588950] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  466.588956] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  466.589001] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  466.589070] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  466.589113] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  466.589155] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  466.589197] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  466.589250] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  466.589295] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  466.589338] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  466.589380] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  466.589423] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  466.589476] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  466.589537] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  466.589590] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  466.589642] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  466.589691] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  466.589903] [drm:intel_power_well_enable [i915]] enabling always-on
>[  466.589940] [drm:intel_power_well_enable [i915]] enabling DC off
>[  466.590285] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  466.590348] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  466.590390] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  466.590499] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  466.590544] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  466.590590] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  466.590626] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  466.590682] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  466.590916] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  466.590951] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  466.591004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  466.591081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  466.591124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  466.591165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  466.591204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  466.591243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  466.591283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  466.591320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  466.591357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  466.591394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  466.591430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  466.591465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  466.591500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  466.591542] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  466.591590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.591635] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  466.591679] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  466.591733] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  466.591776] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  466.603791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.612342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.620863] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.629378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.637890] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.646402] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.654955] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.663483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.671994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.680506] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.689015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.697525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.706034] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.714542] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.723052] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.731561] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.740070] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.748579] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  466.756454] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  466.771287] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  466.771343] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  466.771454] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  466.773373] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  466.776353] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  466.778074] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.778121] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.778166] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.778212] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.783601] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.783647] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  466.789081] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.791715] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e44a88
>[  466.793207] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  466.793308] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  466.793354] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  466.793498] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  466.793542] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  466.797185] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  466.797235] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  466.797279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  466.797325] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  466.798226] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  466.798269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  466.798311] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  466.799204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  466.799247] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  466.799288] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  466.800169] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  466.800214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  466.801410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  466.803798] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e437e8
>[  466.805249] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  466.805328] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  466.805372] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  466.805435] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  466.822239] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  466.822309] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  466.822424] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  466.822549] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  466.822611] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  466.822717] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  466.823187] Console: switching to colour frame buffer device 240x75
>[  467.097713] Console: switching to colour dummy device 80x25
>[  467.097816] [IGT] kms_pipe_crc_basic: executing
>[  467.118769] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  467.118851] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  467.127489] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.136188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.144800] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.153320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.161798] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.170256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.178710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.187164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.195618] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.204074] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.212527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.220982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.229438] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.237893] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.246362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.254817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.263273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.271728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.280182] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.288636] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.297090] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.305546] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.314000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.322452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.330908] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.339362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.347817] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.356360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.364815] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.373270] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.381726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.390181] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.390190] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  467.390193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  467.390205] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  467.390220] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  467.391083] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  467.392606] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  467.392623] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  467.392637] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  467.392664] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  467.393467] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  467.394179] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  467.394994] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  467.395023] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  467.395026] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  467.395046] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  467.395048] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  467.395049] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  467.395051] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  467.395053] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  467.395055] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  467.395057] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  467.395059] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  467.395060] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  467.395062] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  467.395063] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  467.395094] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  467.395111] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  467.395134] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  467.395143] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  467.395159] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  467.397459] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  467.397475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  467.399753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  467.399864] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  467.401205] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  467.401221] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  467.403500] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  467.403504] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  467.403506] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  467.403516] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  467.403533] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  467.404004] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  467.404317] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  467.404333] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  467.404347] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  467.404373] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  467.404779] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  467.405105] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  467.405602] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  467.405604] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  467.405678] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  467.405680] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  467.405683] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  467.405684] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  467.405687] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  467.405687] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  467.405693] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  467.405695] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  467.405697] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  467.405698] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  467.405699] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  467.405701] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  467.405702] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  467.405704] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  467.405705] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  467.405706] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  467.405708] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  467.405709] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  467.405711] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  467.405712] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  467.405713] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  467.405715] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  467.405716] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  467.405717] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  467.405719] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  467.405720] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  467.405722] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  467.405723] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  467.405724] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  467.405726] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  467.405727] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  467.405728] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  467.405730] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  467.405731] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  467.405732] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  467.405734] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  467.405735] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  467.405736] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  467.405738] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  467.405765] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  467.405781] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  467.408080] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  467.408096] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  467.410375] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  467.410378] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  467.412655] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  467.412671] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  467.414950] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  467.414954] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  467.414956] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  467.423969] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  467.423985] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  467.432443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.440904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.449363] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.457820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.466276] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.474731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.483187] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.491641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.500096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.508551] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.517009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.525466] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.533922] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.542377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.550832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.559287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.567742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.576197] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.584651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.593105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.601560] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.610016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.618470] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.626926] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.635382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.643838] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.652293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.660749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.669203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.677659] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.686170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.694624] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  467.694633] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  467.694636] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  467.694822] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  467.694839] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  467.695682] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  467.697214] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  467.697231] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  467.697258] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  467.697271] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  467.698087] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  467.698802] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  467.699580] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  467.699605] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  467.699607] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  467.699609] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  467.699624] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  467.699625] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  467.699626] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  467.699628] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  467.699629] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  467.699631] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  467.699632] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  467.699633] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  467.699635] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  467.699636] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  467.699805] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  467.699820] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  467.699842] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  467.700096] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  467.700112] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  467.702170] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  467.702186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  467.704245] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  467.704249] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  467.706529] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  467.706545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  467.708825] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  467.708830] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  467.708832] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  467.709133] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  467.709151] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  467.709607] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  467.709919] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  467.709934] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  467.709948] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  467.709975] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  467.710391] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  467.710702] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  467.711193] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  467.711195] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  467.711269] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  467.711271] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  467.711273] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  467.711274] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  467.711277] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  467.711278] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  467.711284] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  467.711286] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  467.711287] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  467.711288] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  467.711290] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  467.711291] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  467.711293] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  467.711294] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  467.711296] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  467.711297] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  467.711298] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  467.711300] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  467.711301] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  467.711302] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  467.711304] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  467.711305] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  467.711307] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  467.711308] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  467.711309] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  467.711311] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  467.711312] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  467.711313] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  467.711315] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  467.711316] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  467.711318] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  467.711319] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  467.711320] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  467.711322] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  467.711323] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  467.711324] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  467.711326] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  467.711327] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  467.711328] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  467.711501] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  467.711516] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  467.713067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  467.713081] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  467.715119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  467.715122] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  467.717115] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  467.717128] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  467.719156] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  467.719165] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  467.719173] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  467.720028] [IGT] kms_pipe_crc_basic: starting subtest suspend-read-crc-pipe-C
>[  467.800320] PM: Syncing filesystems ... done.
>[  467.803745] PM: Preparing system for sleep (mem)
>[  467.805079] Freezing user space processes ... (elapsed 0.002 seconds) done.
>[  467.807243] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[  467.809112] PM: Suspending system (mem)
>[  467.809353] Suspending console(s) (use no_console_suspend to debug)
>[  467.813485] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  467.816318] sd 0:0:0:0: [sda] Stopping disk
>[  467.816343] e1000e: EEE TX LPI TIMER: 00000011
>[  467.816712] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  467.816776] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  467.816817] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  467.816860] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  467.829437] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  467.829494] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  467.829560] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  467.829626] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  467.829675] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  467.829727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  467.829780] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  467.829828] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  467.829876] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  467.829922] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  467.829966] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  467.830024] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  467.830069] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  467.830076] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  467.830120] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  467.830163] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  467.830205] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  467.830247] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  467.830288] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  467.830339] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  467.830381] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  467.830425] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  467.830465] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  467.830505] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  467.830545] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  467.830606] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  467.830653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  467.830705] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  467.830764] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  467.830811] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  467.830859] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  467.830905] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  467.830947] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  467.830989] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  467.831071] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  467.831111] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  467.831118] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  467.831157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  467.831163] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  467.831204] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  467.831242] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  467.831281] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  467.831319] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  467.831357] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  467.831406] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  467.831445] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  467.831487] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  467.831527] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  467.831565] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  467.831603] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  467.831665] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 337500 kHz
>[  467.831726] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  467.831775] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  467.831824] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  467.831870] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  467.832145] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  467.844677] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  467.844744] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  467.844805] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  467.844934] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  467.845059] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  467.857601] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  467.857667] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  467.857792] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  467.858049] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  467.858105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  467.858166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  467.858214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  467.858260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  467.858304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  467.858347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  467.858405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  467.858447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  467.858488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  467.858530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  467.858571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  467.858612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  467.858652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  467.858699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  467.858753] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  467.858803] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  467.858852] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  467.858943] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  467.858998] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  467.859095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  467.859155] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  467.859220] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  467.859289] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  467.859338] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  467.868845] PM: suspend of devices complete after 57.104 msecs
>[  467.872895] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  467.872947] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  467.872995] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  467.873086] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  467.873131] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  467.873174] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  467.873218] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  467.873261] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  467.873305] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  467.873367] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  467.873410] [drm:intel_power_well_disable [i915]] disabling DC off
>[  467.873456] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  467.873497] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  467.873947] [drm:intel_power_well_disable [i915]] disabling always-on
>[  467.873989] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  467.876650] [drm:intel_update_cdclk [i915]] Current CD clock rate: 24000 kHz, VCO: 0 kHz, ref: 24000 kHz
>[  467.876697] [drm:intel_power_well_disable [i915]] disabling MISC IO power well
>[  467.876748] [drm:skl_set_power_well [i915]] Disabling MISC IO power well
>[  467.876794] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for MISC IO power well forced on by DMC
>[  467.876840] [drm:intel_power_well_disable [i915]] disabling power well 1
>[  467.876892] [drm:skl_set_power_well [i915]] Clearing auxiliary requests for power well 1 forced on by DMC
>[  467.888220] PM: late suspend of devices complete after 19.367 msecs
>[  467.899484] e1000e 0000:00:1f.6: System wakeup enabled by ACPI
>[  467.901700] xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
>[  467.924126] PM: noirq suspend of devices complete after 35.896 msecs
>[  467.924864] ACPI: Preparing to enter system sleep state S3
>[  467.948448] PM: Saving platform NVS memory
>[  467.948724] Disabling non-boot CPUs ...
>[  467.964739] smpboot: CPU 1 is now offline
>[  467.980791] smpboot: CPU 2 is now offline
>[  468.001387] smpboot: CPU 3 is now offline
>[  468.015359] Broke affinity for irq 123
>[  468.017349] smpboot: CPU 4 is now offline
>[  468.035246] Broke affinity for irq 123
>[  468.036373] smpboot: CPU 5 is now offline
>[  468.055691] Broke affinity for irq 121
>[  468.055696] Broke affinity for irq 123
>[  468.056853] smpboot: CPU 6 is now offline
>[  468.070240] Broke affinity for irq 8
>[  468.070255] Broke affinity for irq 9
>[  468.070269] Broke affinity for irq 120
>[  468.070272] Broke affinity for irq 121
>[  468.070276] Broke affinity for irq 123
>[  468.071441] smpboot: CPU 7 is now offline
>[  468.074965] ACPI: Low-level resume complete
>[  468.075141] PM: Restoring platform NVS memory
>[  468.076020] Suspended for 16.466 seconds
>[  468.076153] Enabling non-boot CPUs ...
>[  468.076262] x86: Booting SMP configuration:
>[  468.076263] smpboot: Booting Node 0 Processor 1 APIC 0x2
>[  468.077693]  cache: parent cpu1 should not be sleeping
>[  468.079002] CPU1 is up
>[  468.079086] smpboot: Booting Node 0 Processor 2 APIC 0x4
>[  468.080274]  cache: parent cpu2 should not be sleeping
>[  468.081444] CPU2 is up
>[  468.081524] smpboot: Booting Node 0 Processor 3 APIC 0x6
>[  468.082732]  cache: parent cpu3 should not be sleeping
>[  468.084018] CPU3 is up
>[  468.084102] smpboot: Booting Node 0 Processor 4 APIC 0x1
>[  468.085507]  cache: parent cpu4 should not be sleeping
>[  468.086857] CPU4 is up
>[  468.086946] smpboot: Booting Node 0 Processor 5 APIC 0x3
>[  468.088235]  cache: parent cpu5 should not be sleeping
>[  468.089581] CPU5 is up
>[  468.089666] smpboot: Booting Node 0 Processor 6 APIC 0x5
>[  468.090943]  cache: parent cpu6 should not be sleeping
>[  468.092361] CPU6 is up
>[  468.092447] smpboot: Booting Node 0 Processor 7 APIC 0x7
>[  468.093772]  cache: parent cpu7 should not be sleeping
>[  468.095217] CPU7 is up
>[  468.101191] ACPI: Waking up from system sleep state S3
>[  468.186420] acpi LNXPOWER:16: Turning OFF
>[  468.186872] acpi LNXPOWER:15: Turning OFF
>[  468.187307] acpi LNXPOWER:14: Turning OFF
>[  468.187749] acpi LNXPOWER:13: Turning OFF
>[  468.188183] acpi LNXPOWER:12: Turning OFF
>[  468.188616] acpi LNXPOWER:11: Turning OFF
>[  468.189057] acpi LNXPOWER:10: Turning OFF
>[  468.189488] acpi LNXPOWER:0f: Turning OFF
>[  468.189929] acpi LNXPOWER:0e: Turning OFF
>[  468.190361] acpi LNXPOWER:0d: Turning OFF
>[  468.190809] acpi LNXPOWER:0c: Turning OFF
>[  468.191243] acpi LNXPOWER:0b: Turning OFF
>[  468.191675] acpi LNXPOWER:0a: Turning OFF
>[  468.192115] acpi LNXPOWER:09: Turning OFF
>[  468.192548] acpi LNXPOWER:08: Turning OFF
>[  468.192989] acpi LNXPOWER:07: Turning OFF
>[  468.193421] acpi LNXPOWER:06: Turning OFF
>[  468.193888] acpi LNXPOWER:05: Turning OFF
>[  468.194320] acpi LNXPOWER:04: Turning OFF
>[  468.194770] acpi LNXPOWER:03: Turning OFF
>[  468.213015] xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
>[  468.226887] PM: noirq resume of devices complete after 31.856 msecs
>[  468.227793] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  468.227832] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  468.227867] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  468.227915] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  468.230556] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  468.232216] [drm:intel_power_well_enable [i915]] enabling always-on
>[  468.232245] [drm:intel_power_well_enable [i915]] enabling DC off
>[  468.232276] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  468.232314] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  468.232346] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  468.232376] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  468.232403] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  468.232431] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  468.232459] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  468.232487] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  468.232514] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  468.232542] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  468.232572] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  468.283592] PM: early resume of devices complete after 56.630 msecs
>[  468.285991] e1000e 0000:00:1f.6: System wakeup disabled by ACPI
>[  468.288189] sd 0:0:0:0: [sda] Starting disk
>[  468.288391] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  468.288459] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  468.288490] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  468.299290] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  468.299325] [drm:intel_opregion_setup [i915]] ASLE supported
>[  468.299355] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  468.299385] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  468.300805] rtc_cmos 00:04: System wakeup disabled by ACPI
>[  468.308194] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.316680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.325152] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.333570] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.341999] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.350444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.358875] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.367302] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.375735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.384167] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.392588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.401004] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.409447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.417873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.426306] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.434725] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.443149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.451564] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.459981] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.468409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.476825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.485242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.493740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.502163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.510599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.519020] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.527477] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.535902] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.544316] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.552733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.561148] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.569568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.569577] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  468.569593] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH down
>[  468.570317] [drm:lspcon_wait_mode [i915]] Current LSPCON mode LS
>[  468.598580] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[  468.601252] ata1.00: supports DRM functions and may not be fully accessible
>[  468.608457] [drm:drm_lspcon_set_mode] LSPCON mode changed to PCON
>[  468.608480] [drm:lspcon_change_mode.constprop.4 [i915]] LSPCON mode changed done
>[  468.608498] [drm:lspcon_resume [i915]] LSPCON resume success
>[  468.608802] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  468.608862] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  468.608911] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  468.608959] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  468.609005] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  468.609044] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  468.609049] [drm] GuC firmware load skipped
>[  468.609071] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  468.609167] ata1.00: supports DRM functions and may not be fully accessible
>[  468.609198] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  468.609216] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  468.609233] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  468.609249] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  468.609263] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  468.609277] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  468.609290] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  468.609305] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  468.609318] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  468.609330] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  468.609342] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  468.609353] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  468.609366] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  468.609377] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  468.609389] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  468.609400] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  468.609413] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  468.609424] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  468.609435] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  468.609446] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  468.609459] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  468.609473] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  468.609493] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  468.609510] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  468.609524] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  468.609537] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  468.609553] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  468.609566] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  468.609579] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  468.609592] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  468.609594] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  468.609607] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  468.609608] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  468.609621] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  468.609633] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  468.609645] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  468.609657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.609668] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  468.609683] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  468.609695] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  468.609707] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  468.609728] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  468.609739] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  468.609751] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  468.609764] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  468.609775] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  468.609786] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  468.609796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  468.609798] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  468.609809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  468.609810] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  468.609821] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  468.609832] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  468.609843] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  468.609854] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.609865] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  468.609879] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  468.609890] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  468.609902] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  468.609913] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  468.609925] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  468.609936] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  468.609949] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  468.609960] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  468.609970] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  468.609981] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  468.609983] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  468.609994] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  468.609995] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  468.610006] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  468.610017] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  468.610028] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  468.610038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.610049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  468.610063] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  468.610074] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  468.610085] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  468.610097] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  468.610108] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  468.610122] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  468.610182] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  468.610195] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  468.610208] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  468.610220] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  468.610232] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  468.610244] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  468.610256] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  468.610268] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  468.610280] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  468.610299] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  468.610311] [drm:intel_power_well_disable [i915]] disabling DC off
>[  468.610324] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  468.610335] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  468.610777] [drm:intel_power_well_disable [i915]] disabling always-on
>[  468.610811] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  468.610825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  468.610842] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  468.610859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  468.610873] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  468.610887] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  468.610901] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  468.610914] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  468.610927] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  468.610939] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  468.610951] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  468.610953] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  468.610964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  468.610966] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  468.610978] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  468.610990] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  468.611002] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  468.611013] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.611024] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  468.611038] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  468.611050] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  468.611062] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  468.611073] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  468.611084] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  468.611095] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  468.611112] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  468.611125] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  468.611140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  468.611156] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  468.611170] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  468.611183] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  468.611196] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  468.611208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  468.611220] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  468.611231] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  468.611242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  468.611244] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  468.611255] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  468.611257] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  468.611269] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  468.611280] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  468.611291] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  468.611302] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  468.611313] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  468.611327] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  468.611338] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  468.611349] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  468.611360] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  468.611371] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  468.611382] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  468.611396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  468.611413] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  468.611426] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  468.611440] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  468.611453] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  468.611510] [drm:intel_power_well_enable [i915]] enabling always-on
>[  468.611521] [drm:intel_power_well_enable [i915]] enabling DC off
>[  468.611811] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  468.611830] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  468.611842] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  468.611869] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  468.611886] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  468.611901] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  468.611912] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  468.611931] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  468.614023] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  468.614034] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  468.614572] ata1.00: configured for UDMA/133
>[  468.616159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  468.616178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  468.616193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  468.616208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  468.616221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  468.616234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  468.616248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  468.616261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  468.616274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  468.616286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  468.616299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  468.616311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  468.616323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  468.616337] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:47:DP-1]
>[  468.616353] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:56:DP-3]
>[  468.616367] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:60:HDMI-A-1]
>[  468.616381] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:67:HDMI-A-2]
>[  468.616398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  468.616413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  468.616427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  468.616442] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  468.616460] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  468.616475] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  468.619693] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  468.621041] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  468.621056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  468.621070] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  468.621085] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  468.626256] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  468.626271] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  468.631441] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  468.633867] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e412a8
>[  468.634366] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  468.634401] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  468.634415] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  468.634465] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  468.634479] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  468.637697] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  468.637727] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  468.637741] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  468.637755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  468.638446] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  468.638460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  468.638473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  468.639126] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  468.639140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  468.639153] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  468.639819] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  468.639833] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  468.640794] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  468.643060] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e41bf8
>[  468.643551] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  468.643577] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  468.643591] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  468.643611] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  468.660353] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  468.660375] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  468.660413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  468.660455] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  468.660478] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  468.660585] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  468.660604] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  468.660810] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  468.660853] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  468.669284] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.677762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.686237] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.694710] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.703202] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.711676] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.720157] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.728644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.737119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.743748] PM: resume of devices complete after 460.152 msecs
>[  468.744942] PM: Finishing wakeup.
>[  468.744943] Restarting tasks ... 
>[  468.745615] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.746632] done.
>[  468.754148] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.770868] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.779369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.787835] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.794030] video LNXVIDEO:00: Restoring backlight state
>[  468.797583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.806038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.814487] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.822940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.831419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.839879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.848336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.856797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.865259] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.873734] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.882192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.890651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.899108] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.907567] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.916025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.924483] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.932956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.941412] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  468.941423] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  468.941427] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  468.941442] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  468.942319] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  468.943849] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  468.943866] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  468.943893] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  468.943906] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  468.944703] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  468.946177] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  468.946923] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  468.946941] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  468.946965] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  468.946981] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  468.949289] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  468.949305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  468.951579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  468.951583] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  468.953861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  468.953877] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  468.956160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  468.956164] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  468.956167] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  468.956183] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  468.956643] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  468.957053] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  468.957070] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  468.957085] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  468.957099] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  468.957508] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  468.957862] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  468.958212] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  468.958229] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  468.960523] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  468.960537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  468.962818] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  468.962821] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  468.965087] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  468.965102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  468.967367] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  468.967370] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  468.967373] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  468.967680] [drm:drm_mode_addfb2] [FB:69]
>[  468.973947] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  468.973994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  468.974091] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  468.987110] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  468.987129] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  468.987147] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  468.987193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  468.987208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  468.987223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  468.987236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  468.987248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  468.987260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  468.987272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  468.987283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  468.987294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  468.987305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  468.987315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  468.987326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  468.987338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  468.987350] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  468.987364] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  468.987378] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  468.987391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  468.987404] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  468.993771] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  468.993785] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  468.993809] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  468.993825] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  468.993899] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  468.993938] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  468.993987] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  468.994007] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  468.994057] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  469.010840] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  469.010860] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  469.010897] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  469.011032] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  469.011048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.011065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.011080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.011094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.011107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.011120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.011133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.011145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.011157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.011170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.011183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.011195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.011207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.011220] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  469.011236] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.011251] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.011266] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.011280] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.011305] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  469.011319] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  469.011332] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  469.011352] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  469.011373] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  469.011388] [drm:intel_power_well_disable [i915]] disabling DC off
>[  469.011402] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  469.011414] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  469.011861] [drm:intel_power_well_disable [i915]] disabling always-on
>[  469.011963] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  469.011977] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  469.012052] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  469.012073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  469.012098] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  469.012124] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  469.012145] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  469.012162] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  469.012178] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  469.012193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  469.012207] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  469.012221] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  469.012234] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  469.012238] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  469.012250] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  469.012253] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  469.012266] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  469.012279] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  469.012292] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  469.012304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  469.012316] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  469.012332] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  469.012345] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  469.012358] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  469.012370] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  469.012382] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  469.012398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.012416] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  469.012431] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  469.012770] [drm:intel_power_well_enable [i915]] enabling always-on
>[  469.012782] [drm:intel_power_well_enable [i915]] enabling DC off
>[  469.013075] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  469.013104] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  469.013123] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  469.013154] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  469.013173] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  469.013200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.013223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.013244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.013258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.013271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.013284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.013297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.013309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.013321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.013333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.013346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.013357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.013369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.013382] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.013398] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.013413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.013427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.013444] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  469.013459] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  469.026236] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.034783] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.043334] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.051856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.060370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.068885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.077399] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.085913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.094429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.102944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.111457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.119970] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.128463] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.136942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.145421] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.153891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.162356] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.170826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.178447] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  469.193905] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  469.193920] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  469.193989] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  469.194818] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  469.196265] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  469.198168] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  469.198211] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  469.198253] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  469.198270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  469.203640] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  469.203656] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  469.208794] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  469.211225] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b50958
>[  469.211701] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  469.228573] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  469.228594] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  469.228628] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.312340] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.312546] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  469.329169] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  469.329237] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  469.329355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.329413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.329469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.329516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.329562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.329608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.329655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.329698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.329841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.329889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.329942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.329987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.330031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.330085] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  469.330144] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.330201] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.330258] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.330310] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.330395] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  469.330447] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  469.330492] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  469.330556] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  469.330628] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  469.330681] [drm:intel_power_well_disable [i915]] disabling DC off
>[  469.330727] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  469.330816] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  469.331281] [drm:intel_power_well_disable [i915]] disabling always-on
>[  469.333122] [drm:drm_mode_addfb2] [FB:69]
>[  469.354759] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  469.354784] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  469.354933] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  469.354984] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  469.355038] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  469.355094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  469.355139] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  469.355186] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  469.355233] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  469.355276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  469.355319] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  469.355359] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  469.355398] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  469.355405] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  469.355444] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  469.355450] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  469.355490] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  469.355528] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  469.355566] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  469.355603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  469.355639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  469.355685] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  469.355722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  469.355810] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  469.355856] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  469.355894] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  469.355946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.356007] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  469.356057] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  469.357269] [drm:intel_power_well_enable [i915]] enabling always-on
>[  469.357311] [drm:intel_power_well_enable [i915]] enabling DC off
>[  469.357625] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  469.357685] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  469.357738] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  469.357905] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  469.357974] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  469.358066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.358149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.358203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.358251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.358301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.358346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.358397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.358441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.358488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.358530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.358578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.358619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.358665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.358713] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.358803] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.358859] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.358911] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.358980] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  469.359036] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  469.372414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.381131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.389821] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.398504] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.407238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.415921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.424605] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.433285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.441968] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.450656] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.459428] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.468064] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.476628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.485155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.493658] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.502142] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.510614] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.519082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  469.525217] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  469.539485] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  469.539504] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  469.539536] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  469.540797] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  469.543399] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  469.544741] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  469.544756] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  469.544770] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  469.544785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  469.549938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  469.549953] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  469.555115] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  469.557597] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445279bf8
>[  469.558105] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  469.575048] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  469.575070] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  469.575106] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.658887] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.659090] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  469.676103] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  469.676287] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  469.676404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.676463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.676519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.676566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.676611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.676654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.676701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.676887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.676955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.677029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.677104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.677172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.677242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.677317] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  469.677410] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.677494] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.677573] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.677652] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.677829] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  469.677908] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  469.677976] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  469.678077] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  469.678185] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  469.678265] [drm:intel_power_well_disable [i915]] disabling DC off
>[  469.678338] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  469.678403] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  469.678964] [drm:intel_power_well_disable [i915]] disabling always-on
>[  469.681336] [drm:drm_mode_addfb2] [FB:69]
>[  469.743151] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  469.743176] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  469.743331] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  469.743384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  469.743441] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  469.743500] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  469.743548] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  469.743598] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  469.743647] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  469.743693] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  469.743738] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  469.743842] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  469.743888] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  469.743902] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  469.743946] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  469.743959] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  469.744004] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  469.744051] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  469.744095] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  469.744143] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  469.744184] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  469.744240] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  469.744283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  469.744331] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  469.744373] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  469.744420] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  469.744491] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  469.744551] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  469.744601] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  469.747909] [drm:intel_power_well_enable [i915]] enabling always-on
>[  469.747946] [drm:intel_power_well_enable [i915]] enabling DC off
>[  469.748253] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  469.748306] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  469.748347] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  469.748448] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  469.748491] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  469.748550] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  469.750837] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  469.750901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.750959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.751007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.751051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.751094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.751137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.751180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.751221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.751261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.751301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.751340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.751379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.751417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.751463] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.751514] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.751562] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.751608] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.751666] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  469.751713] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  469.755316] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  469.755369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  469.755416] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  469.755464] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  469.756406] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  469.756451] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  469.756492] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  469.757405] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  469.757447] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  469.757488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  469.758390] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  469.758434] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  469.759579] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  469.761142] [drm] RC6 on
>[  469.762085] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445279bf8
>[  469.763335] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  469.763409] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  469.763454] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  469.763515] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  469.780303] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  469.780375] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  469.780481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.863952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  469.864105] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  469.864168] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  469.864269] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  469.880460] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  469.880521] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  469.880623] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  469.880868] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  469.880919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.880975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.881023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.881067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.881108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.881150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.881193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.881234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.881275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.881314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.881358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.881397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.881436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.881480] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  469.881533] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.881582] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.881629] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.881676] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.881801] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  469.881850] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  469.881896] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  469.881959] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  469.882026] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  469.882073] [drm:intel_power_well_disable [i915]] disabling DC off
>[  469.882117] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  469.882159] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  469.882627] [drm:intel_power_well_disable [i915]] disabling always-on
>[  469.884371] [drm:drm_mode_addfb2] [FB:69]
>[  469.943519] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  469.943544] [drm:drm_mode_setcrtc] [CONNECTOR:63:DP-4]
>[  469.943700] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  469.943836] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  469.943916] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  469.944001] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  469.944066] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  469.944136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  469.944208] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[  469.944256] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  469.944299] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  469.944342] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  469.944383] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  469.944394] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  469.944432] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  469.944440] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  469.944481] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  469.944522] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  469.944562] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  469.944599] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  469.944638] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  469.944688] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  469.944728] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  469.944835] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  469.944893] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  469.944952] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  469.945047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  469.945124] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[  469.945192] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[  469.948502] [drm:intel_power_well_enable [i915]] enabling always-on
>[  469.948539] [drm:intel_power_well_enable [i915]] enabling DC off
>[  469.948917] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  469.949403] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  469.949442] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  469.949506] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  469.949542] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  469.949600] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  469.951932] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  469.951995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  469.952054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  469.952104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  469.952149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  469.952193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  469.952235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  469.952280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  469.952320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  469.952359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  469.952398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  469.952438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  469.952476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  469.952514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  469.952559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  469.952610] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  469.952659] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  469.952705] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  469.952851] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[  469.952904] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  469.956521] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  469.956574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  469.956619] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  469.956667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  469.957660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  469.957712] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  469.957835] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  469.958699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  469.958802] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  469.958854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  469.959701] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  469.959800] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  469.960967] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  469.963332] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445279bf8
>[  469.964562] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  469.964644] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  469.964690] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[  469.964799] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  469.981560] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  469.981631] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  469.981736] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.065167] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  470.065349] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[  470.065421] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  470.065543] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  470.081845] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[  470.081913] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  470.082030] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  470.084377] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  470.084445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  470.084507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  470.084564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  470.084613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  470.084661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  470.084708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  470.084886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  470.084953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  470.085023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  470.085088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  470.085166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  470.085228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  470.085294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  470.085362] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  470.085446] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  470.085524] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.085600] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  470.085674] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  470.085848] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  470.085925] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  470.085999] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  470.086100] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  470.086205] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[  470.086283] [drm:intel_power_well_disable [i915]] disabling DC off
>[  470.086354] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  470.086412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  470.086976] [drm:intel_power_well_disable [i915]] disabling always-on
>[  470.088632] [IGT] kms_pipe_crc_basic: exiting, ret=0
>[  470.114112] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  470.114171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  470.114234] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  470.114300] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  470.114352] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  470.114406] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  470.114461] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  470.114513] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  470.114563] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  470.114611] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  470.114657] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  470.114666] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  470.114711] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  470.114754] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  470.114802] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  470.114849] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  470.114893] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  470.114936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.114979] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  470.115033] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  470.115078] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  470.115121] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  470.115163] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  470.115205] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  470.115269] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  470.115319] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  470.115374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  470.115437] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  470.115489] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  470.115541] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  470.115590] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  470.115637] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  470.115683] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  470.115726] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  470.115795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  470.115803] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  470.115846] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  470.115852] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  470.115897] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  470.115940] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  470.115983] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  470.116025] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.116067] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  470.116119] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  470.116162] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  470.116205] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  470.116248] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  470.116290] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  470.116344] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  470.116406] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  470.116459] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  470.116511] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  470.116561] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  470.116732] [drm:intel_power_well_enable [i915]] enabling always-on
>[  470.116806] [drm:intel_power_well_enable [i915]] enabling DC off
>[  470.117123] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  470.117191] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  470.117236] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  470.117321] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  470.117365] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  470.117420] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  470.117463] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  470.117528] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  470.118894] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  470.118938] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  470.120915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  470.120981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  470.121035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  470.121085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  470.121133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  470.121180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  470.121229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  470.121275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  470.121319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  470.121364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  470.121408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  470.121451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  470.121495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  470.121545] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  470.121616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.121655] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  470.121691] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  470.121763] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  470.121800] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  470.134726] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.143304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.151820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.160330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.168839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.177348] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.185856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.194364] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.202874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.211384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.219892] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.228401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.236911] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.245502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.254011] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.262520] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.271028] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.279536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.287409] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  470.302172] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  470.302187] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  470.302265] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  470.303096] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  470.305699] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  470.307058] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  470.307073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  470.307086] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  470.307101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  470.312249] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  470.312263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  470.317409] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  470.319900] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445279bf8
>[  470.320404] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  470.320468] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  470.320482] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  470.320529] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  470.320541] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  470.323792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  470.323808] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  470.323822] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  470.323850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  470.324522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  470.324536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  470.324549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  470.325210] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  470.325223] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  470.325236] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  470.325894] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  470.325908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  470.326864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  470.329138] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044527a548
>[  470.329637] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  470.329660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  470.329673] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  470.329692] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  470.346471] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  470.346491] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  470.346527] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.346565] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  470.346583] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  470.346616] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  470.346825] Console: switching to colour frame buffer device 240x75
>[  470.544685] Console: switching to colour dummy device 80x25
>[  470.544808] [IGT] kms_setmode: executing
>[  470.557542] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
>[  470.558106] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  470.558263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  470.558496] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  470.572873] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  470.572946] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  470.573009] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  470.573127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  470.573185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  470.573240] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  470.573289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  470.573336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  470.573381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  470.573427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  470.573469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  470.573511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  470.573552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  470.573593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  470.573633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  470.573673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  470.573722] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  470.573849] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  470.573912] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.573969] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  470.574026] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  470.579890] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  470.579944] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  470.580033] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  470.580095] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  470.582535] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  470.582696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  470.582889] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  470.582965] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  470.583081] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  470.598374] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  470.598441] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  470.598547] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  470.600834] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  470.600901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  470.600967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  470.601022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  470.601072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  470.601121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  470.601167] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  470.601216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  470.601261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  470.601305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  470.601348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  470.601398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  470.601442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  470.601485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  470.601535] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  470.601592] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  470.601647] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.601699] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  470.601820] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  470.601909] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  470.601962] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  470.602017] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  470.602089] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  470.602166] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  470.602224] [drm:intel_power_well_disable [i915]] disabling DC off
>[  470.602275] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  470.602321] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  470.602833] [drm:intel_power_well_disable [i915]] disabling always-on
>[  470.603426] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  470.604205] [drm:drm_mode_addfb2] [FB:69]
>[  470.661261] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  470.661604] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  470.661653] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  470.662274] [drm:drm_mode_addfb2] [FB:110]
>[  470.671383] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  470.671793] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  470.672251] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  470.672358] [drm:drm_mode_addfb2] [FB:113]
>[  470.679696] [IGT] kms_setmode: exiting, ret=0
>[  470.699105] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  470.699122] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  470.699140] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  470.699158] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  470.699172] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  470.699187] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  470.699203] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  470.699218] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  470.699232] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  470.699244] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  470.699257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  470.699260] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  470.699272] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  470.699274] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  470.699286] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  470.699298] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  470.699310] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  470.699322] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.699333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  470.699348] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  470.699360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  470.699372] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  470.699383] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  470.699394] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  470.699411] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  470.699425] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  470.699440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  470.699456] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  470.699470] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  470.699484] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  470.699497] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  470.699509] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  470.699521] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  470.699533] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  470.699544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  470.699546] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  470.699557] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  470.699559] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  470.699571] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  470.699582] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  470.699594] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  470.699605] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  470.699616] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  470.699630] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  470.699641] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  470.699653] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  470.699664] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  470.699675] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  470.699690] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  470.699707] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  470.699784] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  470.699801] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  470.699833] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  470.699900] [drm:intel_power_well_enable [i915]] enabling always-on
>[  470.699913] [drm:intel_power_well_enable [i915]] enabling DC off
>[  470.700212] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  470.700232] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  470.700245] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  470.700268] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  470.700284] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  470.700305] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  470.700320] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  470.700339] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  470.700668] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  470.700679] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  470.700699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  470.700751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  470.700767] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  470.700783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  470.700797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  470.700826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  470.700840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  470.700855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  470.700868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  470.700881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  470.700895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  470.700909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  470.700921] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  470.700937] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  470.700954] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.700969] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  470.700984] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  470.701002] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  470.701017] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  470.713291] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.721794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.730301] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.738808] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.747313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.755819] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.764324] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.772831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.781336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.790065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.798575] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.807082] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.815588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.824093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.832598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.841117] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.849623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.858128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  470.865981] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  470.881122] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  470.881139] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  470.881224] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  470.882065] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  470.882780] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  470.884570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  470.884587] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  470.884603] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  470.884619] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  470.890524] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  470.890540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  470.895685] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  470.898167] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b50958
>[  470.898637] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  470.898697] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  470.898712] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  470.898787] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  470.898809] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  470.902057] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  470.902074] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  470.902088] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  470.902104] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  470.902763] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  470.902780] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  470.902795] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  470.903434] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  470.903448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  470.903462] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  470.904100] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  470.904115] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  470.905076] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  470.907342] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b56678
>[  470.907827] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  470.907857] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  470.907872] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  470.907892] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  470.924744] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  470.924766] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  470.924803] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  470.924841] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  470.924861] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  470.924894] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  470.941468] Console: switching to colour frame buffer device 240x75
>[  471.179507] Console: switching to colour dummy device 80x25
>[  471.179904] [IGT] kms_sink_crc_basic: executing
>[  471.231329] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  471.231381] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  471.239937] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.248432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.256896] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.265350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.273807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.282262] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.290730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.299185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.307641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.316097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.324552] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.333006] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.341462] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.349916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.358370] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.366832] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.375296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.383755] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.392211] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.400668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.409125] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.417583] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.426040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.434497] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.442954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.451410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.459867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.468323] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.476782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.485238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.493762] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.502218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  471.502227] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  471.502231] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  471.502414] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  471.502430] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  471.503285] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  471.504810] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  471.504827] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  471.504854] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  471.504867] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  471.505659] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  471.506370] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  471.507204] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  471.507241] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  471.507244] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  471.507245] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  471.507247] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  471.507248] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  471.507250] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  471.507251] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  471.507252] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  471.507254] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  471.507255] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  471.507257] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  471.507258] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  471.507260] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  471.507432] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  471.507448] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  471.507470] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  471.507632] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  471.507647] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  471.507970] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  471.507990] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  471.509914] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  471.509917] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  471.511962] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  471.511978] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  471.514253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  471.514257] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  471.514259] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  471.514459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  471.514477] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  471.514939] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  471.515254] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  471.515270] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  471.515285] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  471.515298] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  471.515701] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  471.516037] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  471.516533] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  471.516535] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  471.516611] [drm:drm_mode_debug_printmodeline] Modeline 148:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  471.516612] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  471.516615] [drm:drm_mode_debug_printmodeline] Modeline 150:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  471.516616] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  471.516619] [drm:drm_mode_debug_printmodeline] Modeline 161:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  471.516620] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  471.516626] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  471.516628] [drm:drm_mode_debug_printmodeline] Modeline 84:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  471.516629] [drm:drm_mode_debug_printmodeline] Modeline 85:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  471.516631] [drm:drm_mode_debug_printmodeline] Modeline 88:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  471.516632] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  471.516634] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  471.516635] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  471.516636] [drm:drm_mode_debug_printmodeline] Modeline 105:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  471.516638] [drm:drm_mode_debug_printmodeline] Modeline 122:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  471.516640] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  471.516641] [drm:drm_mode_debug_printmodeline] Modeline 106:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  471.516642] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  471.516644] [drm:drm_mode_debug_printmodeline] Modeline 121:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  471.516645] [drm:drm_mode_debug_printmodeline] Modeline 90:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  471.516647] [drm:drm_mode_debug_printmodeline] Modeline 89:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  471.516648] [drm:drm_mode_debug_printmodeline] Modeline 98:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  471.516649] [drm:drm_mode_debug_printmodeline] Modeline 91:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  471.516651] [drm:drm_mode_debug_printmodeline] Modeline 92:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  471.516652] [drm:drm_mode_debug_printmodeline] Modeline 93:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  471.516654] [drm:drm_mode_debug_printmodeline] Modeline 87:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  471.516655] [drm:drm_mode_debug_printmodeline] Modeline 118:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  471.516657] [drm:drm_mode_debug_printmodeline] Modeline 108:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  471.516658] [drm:drm_mode_debug_printmodeline] Modeline 99:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  471.516659] [drm:drm_mode_debug_printmodeline] Modeline 100:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  471.516661] [drm:drm_mode_debug_printmodeline] Modeline 101:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  471.516662] [drm:drm_mode_debug_printmodeline] Modeline 94:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  471.516663] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  471.516665] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  471.516666] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  471.516668] [drm:drm_mode_debug_printmodeline] Modeline 95:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  471.516669] [drm:drm_mode_debug_printmodeline] Modeline 119:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  471.516670] [drm:drm_mode_debug_printmodeline] Modeline 96:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  471.516672] [drm:drm_mode_debug_printmodeline] Modeline 97:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  471.516998] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  471.517021] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  471.518903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  471.518919] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  471.520903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  471.520907] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  471.522969] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  471.523030] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  471.524998] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  471.525012] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  471.525021] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  471.525914] [IGT] kms_sink_crc_basic: exiting, ret=77
>[  471.575140] Console: switching to colour frame buffer device 240x75
>[  471.607572] e1000e: eno1 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None
>[  471.831345] Console: switching to colour dummy device 80x25
>[  471.831444] [IGT] pm_backlight: executing
>[  471.831602] [IGT] pm_backlight: exiting, ret=77
>[  471.841456] Console: switching to colour frame buffer device 240x75
>[  472.055484] Console: switching to colour dummy device 80x25
>[  472.055772] [IGT] pm_rpm: executing
>[  472.075344] [drm:drm_mode_addfb2] [FB:68]
>[  472.142531] ahci 0000:00:17.0: port does not support device sleep
>[  473.145152] [IGT] pm_rpm: starting subtest basic-pci-d3-state
>[  473.145265] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  473.145425] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  473.145675] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  473.151372] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  473.151440] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  473.151501] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  473.151611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  473.151667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  473.151721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  473.151860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  473.151917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  473.151973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  473.152026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  473.152082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  473.152128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  473.152179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  473.152223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  473.152271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  473.152314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  473.152368] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  473.152427] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  473.152481] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  473.152535] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  473.152590] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  473.158197] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  473.158251] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  473.158338] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  473.158398] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  473.160949] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  473.161125] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.161305] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  473.161375] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  473.161492] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  473.176727] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  473.176864] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  473.177007] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  473.177228] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  473.177285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  473.177340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  473.177391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  473.177438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  473.177483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  473.177528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  473.177574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  473.177616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  473.177658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  473.177698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  473.177829] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  473.177881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  473.177931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  473.177981] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  473.178042] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  473.178099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  473.178152] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  473.178205] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  473.178283] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  473.178332] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  473.178381] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  473.178449] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  473.178523] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  473.178577] [drm:intel_power_well_disable [i915]] disabling DC off
>[  473.178627] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  473.178674] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  473.179183] [drm:intel_power_well_disable [i915]] disabling always-on
>[  473.179921] [drm:intel_runtime_suspend [i915]] Suspending device
>[  473.181457] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  473.185106] [drm:intel_runtime_suspend [i915]] Device suspended
>[  473.288191] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  473.288201] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  473.288263] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  473.288283] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  473.288303] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  473.288325] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  473.288342] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  473.288361] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  473.288379] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  473.288396] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  473.288413] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  473.288429] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  473.288444] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  473.288447] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  473.288462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  473.288464] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  473.288480] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  473.288495] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  473.288509] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  473.288524] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  473.288537] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  473.288555] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  473.288570] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  473.288584] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  473.288599] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  473.288613] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  473.288630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  473.288650] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  473.288667] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  473.300933] [drm:intel_runtime_resume [i915]] Resuming device
>[  473.304786] [drm:intel_runtime_resume [i915]] Device resumed
>[  473.305504] [drm:intel_runtime_suspend [i915]] Suspending device
>[  473.308366] [drm:intel_runtime_suspend [i915]] Device suspended
>[  473.332096] [drm:intel_runtime_resume [i915]] Resuming device
>[  473.340365] [drm:intel_runtime_resume [i915]] Device resumed
>[  473.340421] [drm:intel_power_well_enable [i915]] enabling always-on
>[  473.340464] [drm:intel_power_well_enable [i915]] enabling DC off
>[  473.340869] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  473.341345] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  473.341408] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  473.341514] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  473.341575] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  473.341673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  473.341752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  473.341890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  473.341965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  473.342036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  473.342105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  473.342182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  473.342247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  473.342316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  473.342377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  473.342447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  473.342508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  473.342576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  473.342648] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  473.342730] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  473.342844] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  473.342914] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  473.342972] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  473.342995] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  473.355759] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.364239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.372709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.381193] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.389661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.398128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.406595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.415062] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.423533] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.432001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.440468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.448934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.457455] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.465921] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.474388] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.482858] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.491325] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.499792] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.508258] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  473.509342] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  473.523395] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  473.523412] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  473.523499] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  473.524995] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  473.527236] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  473.528660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  473.528676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  473.528701] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  473.528782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  473.533925] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  473.533941] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  473.539083] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  473.541572] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b55d28
>[  473.542071] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  473.542147] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  473.542162] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  473.558962] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  473.558984] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  473.559020] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  473.559136] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  473.568991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.575887] ahci 0000:00:17.0: port does not support device sleep
>[  473.577501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.586328] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.594764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.603185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.611607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.620030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.628452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.636873] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.645296] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.653730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.662171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.670593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.679017] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.687439] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.695860] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.704281] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.712702] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.721136] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.729558] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.737979] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.746401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.754822] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.763243] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.771664] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.780087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.788510] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.796940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.805362] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.813784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.822204] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.830626] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.830636] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  473.830639] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  473.830655] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  473.831576] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  473.833108] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  473.833125] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  473.833139] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  473.833153] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  473.833968] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  473.834679] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  473.835426] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  473.835442] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  473.835479] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  473.835493] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  473.837809] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  473.837825] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  473.840094] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  473.840098] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  473.842405] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  473.842421] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  473.844701] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  473.844717] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  473.844719] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  473.844735] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  473.845194] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  473.845512] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  473.845528] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  473.845542] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  473.845556] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  473.845991] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  473.846309] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  473.846659] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  473.846675] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  473.849011] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  473.849024] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  473.851303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  473.851306] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  473.853595] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  473.853608] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  473.855900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  473.855903] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  473.855905] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  473.855944] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  473.864375] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.872802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.881225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.889649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.898085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.906508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.914929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.923349] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.931770] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.940190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.948609] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.957030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.965451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.973872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.982294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.990728] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  473.999149] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.007571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.015994] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.024414] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.032836] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.041257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.049679] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.058100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.066523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.074946] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.083372] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.091797] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.100218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.108641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.117065] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.125488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.125497] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  474.125500] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  474.125516] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  474.126378] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  474.127951] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  474.127968] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  474.127982] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  474.127996] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  474.128839] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  474.129552] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  474.130297] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  474.130314] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  474.130338] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  474.130353] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  474.132665] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  474.132680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  474.133019] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  474.133023] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  474.135319] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  474.135335] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  474.137615] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  474.137619] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  474.137621] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  474.137638] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  474.138146] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  474.138466] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  474.138512] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  474.138526] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  474.138539] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  474.138993] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  474.139310] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  474.139657] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  474.139673] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  474.140021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  474.140041] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  474.142336] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  474.142340] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  474.144625] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  474.144641] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  474.146984] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  474.146988] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  474.146990] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  474.147163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  474.147417] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  474.160568] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  474.160605] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  474.160631] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  474.160675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  474.160691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  474.160708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  474.160741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  474.160754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  474.160769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  474.160783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  474.160797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  474.160812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  474.160826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  474.160840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  474.160852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  474.160865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  474.160880] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  474.160898] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  474.160914] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  474.160929] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  474.160944] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  474.160973] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  474.160998] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  474.161012] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  474.161054] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  474.161082] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  474.161103] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.161118] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.161130] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.161561] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.161665] [drm:intel_runtime_suspend [i915]] Suspending device
>[  474.161757] [IGT] pm_rpm: exiting, ret=0
>[  474.163971] [drm:intel_runtime_suspend [i915]] Device suspended
>[  474.187952] [drm:intel_runtime_resume [i915]] Resuming device
>[  474.191074] [drm:intel_runtime_resume [i915]] Device resumed
>[  474.191297] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  474.191313] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.191327] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.191622] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.202904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.211335] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.219774] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.228214] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.236657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.245102] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.253545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.261988] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.270430] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.278871] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.287308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.295737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.304158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.312580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.321001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.329423] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.337844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.346265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.354703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.363139] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.371559] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.379982] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.388403] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.396823] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.405244] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.413665] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.422087] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.430508] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.438930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.447350] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.455771] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.464192] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.464202] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  474.464216] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.464244] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.464271] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.464687] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.464768] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  474.464803] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  474.464824] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.464841] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.465225] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.465249] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  474.465279] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  474.475935] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.484360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.492784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.501208] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.509629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.518051] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.526474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.534897] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.543318] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.551738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.560159] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.568581] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.577003] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.585441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.593864] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.602285] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.610707] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.619144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.627566] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  474.628400] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 05 01 81 02 01 04 01 0f 00 00
>[  474.629952] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  474.629968] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  474.629983] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  474.630009] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  474.630846] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  474.631558] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  474.632314] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  474.632347] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  474.632372] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.632384] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.632394] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.632871] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.632878] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  474.632914] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  474.632933] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.632949] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.633345] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.633369] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  474.633386] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  474.633422] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  474.633448] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  474.633466] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.633496] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.633510] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.634005] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.634009] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  474.634045] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  474.634078] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.636381] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  474.636397] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  474.638686] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  474.638690] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  474.639778] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  474.639797] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  474.642075] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  474.642079] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  474.642091] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.642095] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  474.642112] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  474.642124] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.642134] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.642420] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.642436] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  474.642448] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  474.642910] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  474.643254] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  474.643274] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  474.643321] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  474.643341] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  474.643365] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  474.643406] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  474.643426] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  474.644371] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  474.645564] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  474.646690] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  474.647822] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  474.647852] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  474.648097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  474.648113] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  474.648727] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  474.648786] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  474.648799] [drm:intel_power_well_disable [i915]] disabling DC off
>[  474.648813] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  474.648825] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  474.650388] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  474.650391] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  474.652680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  474.652692] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  474.652977] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  474.652979] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  474.652991] [drm:intel_power_well_disable [i915]] disabling always-on
>[  474.652994] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  474.653009] [drm:intel_runtime_suspend [i915]] Suspending device
>[  474.653414] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  474.653430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  474.653446] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  474.653463] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  474.653476] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  474.653491] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  474.653505] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  474.653519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  474.653532] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  474.653544] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  474.653555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  474.653558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  474.653569] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  474.653571] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  474.653583] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  474.653594] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  474.653605] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  474.653616] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  474.653627] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  474.653641] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  474.653653] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  474.653663] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  474.653674] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  474.653685] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  474.653701] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  474.653826] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  474.653843] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  474.653863] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  474.653877] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  474.653892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  474.653921] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  474.653936] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  474.653950] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  474.653963] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  474.653976] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  474.653980] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  474.653992] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  474.654008] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  474.654020] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  474.654032] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  474.654045] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  474.654056] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  474.654069] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  474.654083] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  474.654096] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  474.654108] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  474.654120] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  474.654132] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  474.654148] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  474.654165] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  474.654180] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  474.654195] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  474.654209] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  474.657990] [drm:intel_runtime_suspend [i915]] Device suspended
>[  474.681877] [drm:intel_runtime_resume [i915]] Resuming device
>[  474.685154] [drm:intel_runtime_resume [i915]] Device resumed
>[  474.685319] [drm:intel_power_well_enable [i915]] enabling always-on
>[  474.685331] [drm:intel_power_well_enable [i915]] enabling DC off
>[  474.685621] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  474.685641] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  474.685654] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  474.685683] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  474.685701] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  474.685741] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  474.685753] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  474.685773] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  474.686090] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  474.686103] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  474.686124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  474.686141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  474.686156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  474.686170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  474.686184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  474.686197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  474.686211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  474.686224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  474.686237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  474.686249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  474.686262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  474.686274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  474.686287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  474.686301] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  474.686318] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  474.686333] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  474.686348] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  474.686367] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  474.686382] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  474.689563] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  474.690910] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  474.690925] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  474.690939] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  474.690954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  474.696122] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  474.696137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  474.701304] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  474.703794] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044527ae98
>[  474.704265] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  474.704314] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  474.704329] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  474.704377] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  474.704391] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  474.707634] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  474.707651] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  474.707665] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  474.707680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  474.708337] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  474.708352] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  474.708365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  474.709012] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  474.709026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  474.709040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  474.709676] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  474.709690] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  474.710684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  474.712971] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445278958
>[  474.713437] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  474.713467] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  474.713481] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  474.713501] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  474.730229] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  474.730255] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  474.730309] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  474.730356] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  474.730380] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  474.730420] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  474.730557] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  474.739043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.747536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.756227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.764749] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.773343] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.781855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.790369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.798857] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.807342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.815834] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.824333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.832831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.841304] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.849775] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.858230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.866686] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.875155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.883617] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.892073] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.900527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.908983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.917461] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.925933] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.934419] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.942882] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.951357] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.959820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.968278] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.976733] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.985190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  474.993661] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.002116] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.002126] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  475.002130] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  475.002146] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  475.003003] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  475.004552] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  475.004567] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  475.004581] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  475.004594] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  475.005408] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  475.006123] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  475.006870] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  475.006886] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  475.006922] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  475.006936] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  475.009219] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  475.009235] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  475.011509] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  475.011517] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  475.013815] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  475.013831] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  475.016057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  475.016060] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  475.016063] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  475.016079] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  475.016535] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  475.016851] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  475.016880] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  475.016910] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  475.016923] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  475.017327] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  475.017653] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  475.018014] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  475.018029] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  475.019960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  475.019997] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  475.021894] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  475.021898] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  475.023917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  475.023932] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  475.026207] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  475.026211] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  475.026214] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  475.026259] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  475.034742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.043221] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.051714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.060215] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.068703] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.084951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.093427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.101899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.110368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.118839] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.127305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.135766] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.144225] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.152681] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.161133] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.169591] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.178045] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.186502] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.194976] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.203452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.211929] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.220417] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.228912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.237396] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.245874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.255826] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.264308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.272799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.281263] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.289715] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.298188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.306648] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  475.306658] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  475.306662] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  475.306678] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  475.307556] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  475.309086] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  475.309101] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  475.309114] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  475.309128] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  475.309940] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  475.310652] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  475.311395] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  475.311410] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  475.311433] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  475.311448] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  475.313775] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  475.313790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  475.316065] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  475.316068] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  475.317882] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  475.317898] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  475.320173] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  475.320176] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  475.320179] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  475.320195] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  475.320658] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  475.320978] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  475.320993] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  475.321007] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  475.321033] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  475.321449] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  475.321770] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  475.322119] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  475.322135] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  475.324419] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  475.324432] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  475.326705] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  475.326720] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  475.328994] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  475.329006] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  475.331283] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  475.331285] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  475.331287] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  475.347032] Console: switching to colour frame buffer device 240x75
>[  475.569394] Console: switching to colour dummy device 80x25
>[  475.569489] [IGT] pm_rpm: executing
>[  475.582593] [drm:drm_mode_addfb2] [FB:110]
>[  475.636887] ahci 0000:00:17.0: port does not support device sleep
>[  476.637637] [IGT] pm_rpm: starting subtest basic-rte
>[  476.637987] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  476.638154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  476.638409] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  476.640398] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  476.640467] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  476.640529] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  476.640637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  476.640694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  476.640880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  476.640952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  476.641020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  476.641084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  476.641155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  476.641223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  476.641277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  476.641319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  476.641364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  476.641405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  476.641450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  476.641498] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  476.641559] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  476.641612] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  476.641664] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  476.641718] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  476.647116] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  476.647171] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  476.647257] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  476.647316] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  476.647476] [drm:drm_mode_setcrtc] [CRTC:38:pipe B]
>[  476.647629] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  476.647899] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  476.647996] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  476.648125] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  476.665531] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  476.665601] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  476.665711] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  476.665976] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  476.666039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  476.666102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  476.666157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  476.666209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  476.666258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  476.666305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  476.666353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  476.666398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  476.666443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  476.666488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  476.666537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  476.666578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  476.666621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  476.666670] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  476.666729] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  476.666876] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  476.666950] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  476.667025] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  476.667138] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  476.667208] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  476.667283] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  476.667348] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  476.667424] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  476.667478] [drm:intel_power_well_disable [i915]] disabling DC off
>[  476.667526] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  476.667568] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  476.668117] [drm:intel_power_well_disable [i915]] disabling always-on
>[  476.668222] [drm:intel_runtime_suspend [i915]] Suspending device
>[  476.671186] [drm:intel_runtime_suspend [i915]] Device suspended
>[  476.671320] [drm:drm_mode_setcrtc] [CRTC:45:pipe C]
>[  476.771663] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  476.771693] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  476.772022] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  476.772083] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  476.772146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  476.772213] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  476.772263] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  476.772318] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  476.772372] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  476.772423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  476.772473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  476.772519] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  476.772563] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  476.772572] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  476.772616] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  476.772625] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  476.772668] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  476.772713] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  476.772847] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  476.772913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  476.772980] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  476.773057] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  476.773119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  476.773187] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  476.773251] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  476.773318] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  476.773391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  476.773478] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  476.773549] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  476.785093] [drm:intel_runtime_resume [i915]] Resuming device
>[  476.795014] [drm:intel_runtime_resume [i915]] Device resumed
>[  476.796455] [drm:intel_runtime_suspend [i915]] Suspending device
>[  476.802960] [drm:intel_runtime_suspend [i915]] Device suspended
>[  476.827082] [drm:intel_runtime_resume [i915]] Resuming device
>[  476.837874] [drm:intel_runtime_resume [i915]] Device resumed
>[  476.837929] [drm:intel_power_well_enable [i915]] enabling always-on
>[  476.837972] [drm:intel_power_well_enable [i915]] enabling DC off
>[  476.838339] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  476.838412] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  476.838468] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  476.838577] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  476.838620] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  476.838692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  476.838815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  476.838872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  476.838934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  476.838985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  476.839036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  476.839091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  476.839142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  476.839195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  476.839243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  476.839294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  476.839343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  476.839393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  476.839445] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  476.839509] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  476.839563] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  476.839618] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  476.839683] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  476.839736] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  476.852985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.861468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.869947] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.878425] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.886903] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.895380] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.903856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.912331] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.920809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.929287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.937764] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.946239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.954730] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.963206] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.971683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.980190] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.988696] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  476.997198] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.004903] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  477.021885] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  477.021903] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  477.021964] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  477.022659] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  477.023479] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  477.024211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  477.024228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  477.024243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  477.024260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  477.030060] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  477.030076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  477.035223] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  477.037742] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b56fc8
>[  477.038588] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  477.038639] [drm:intel_fbc_enable [i915]] reserved 18432000 bytes of contiguous stolen space for FBC, threshold: 1
>[  477.038654] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  477.055470] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  477.055493] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  477.055538] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  477.055615] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  477.064038] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.068953] ahci 0000:00:17.0: port does not support device sleep
>[  477.072479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.081673] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.090110] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.098543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.106977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.115410] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.123843] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.132275] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.140708] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.149155] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.157589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.166024] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.174457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.182915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.191346] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.199780] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.208212] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.216644] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.225092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.233526] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.242053] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.250485] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.258919] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.267352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.275785] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.284217] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.292649] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.301083] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.309623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.318056] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.326488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.326499] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  477.326502] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  477.326518] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  477.327371] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  477.328965] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  477.328981] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  477.328996] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  477.329010] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  477.329852] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  477.330568] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  477.331325] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  477.331342] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  477.331366] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  477.331385] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  477.333705] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  477.333735] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  477.336016] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  477.336020] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  477.338303] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  477.338319] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  477.340604] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  477.340609] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  477.340611] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  477.340627] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  477.341171] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  477.341497] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  477.341543] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  477.341556] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  477.341570] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  477.342136] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  477.342477] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  477.342847] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  477.342865] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  477.345121] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  477.345136] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  477.347429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  477.347432] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  477.349732] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  477.349761] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  477.352057] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  477.352060] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  477.352063] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  477.352116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  477.352171] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  477.356806] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  477.356826] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  477.356844] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  477.356903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  477.356917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  477.356932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  477.356945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  477.356957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  477.356968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  477.356980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  477.356991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  477.357002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  477.357012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  477.357023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  477.357034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  477.357044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  477.357056] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  477.357072] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  477.357086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  477.357100] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  477.357113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  477.357132] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  477.357145] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  477.357158] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  477.357182] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  477.357201] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  477.357217] [drm:intel_power_well_disable [i915]] disabling DC off
>[  477.357231] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  477.357241] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  477.357675] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.358016] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  477.358029] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.358040] [drm:intel_power_well_enable [i915]] enabling DC off
>[  477.358341] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  477.358342] [IGT] pm_rpm: exiting, ret=0
>[  477.366782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.375216] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.383651] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.392098] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.400531] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.408963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.417409] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.425842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.434274] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.442706] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.451158] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.459592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.468025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.476457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.484889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.493320] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.501768] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.510199] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.518631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.527063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.535568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.544001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.552445] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.560876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.569307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.577739] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.586170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.594601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.603105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.611536] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.619969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.628415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.628425] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  477.628439] [drm:intel_power_well_disable [i915]] disabling DC off
>[  477.628454] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  477.628466] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  477.628972] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.628991] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  477.629007] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  477.629020] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.629033] [drm:intel_power_well_enable [i915]] enabling DC off
>[  477.629603] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  477.629994] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  477.630008] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  477.640516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.648951] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.657384] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.665816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.674247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.682680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.691138] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.699571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.708002] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.716446] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.724878] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.733309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.741741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.750172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.758603] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.767036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.775467] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.783899] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.792330] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  477.793167] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 05 01 81 02 01 04 01 0f 00 00
>[  477.794706] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  477.794736] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  477.794763] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  477.794776] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  477.795577] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  477.796298] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  477.797057] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  477.797084] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  477.797098] [drm:intel_power_well_disable [i915]] disabling DC off
>[  477.797124] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  477.797135] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  477.797567] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.797571] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  477.797585] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  477.797596] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.797605] [drm:intel_power_well_enable [i915]] enabling DC off
>[  477.797616] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  477.797634] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  477.797646] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  477.797686] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  477.797780] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  477.797808] [drm:intel_power_well_disable [i915]] disabling DC off
>[  477.797825] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  477.797851] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  477.798298] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.798301] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  477.798315] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  477.798326] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.800621] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  477.800637] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  477.802956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  477.802959] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  477.805247] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  477.805263] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  477.807545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  477.807549] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  477.807561] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.807565] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  477.807581] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  477.807593] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.807604] [drm:intel_power_well_enable [i915]] enabling DC off
>[  477.808438] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  477.808455] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  477.808492] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  477.808508] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  477.809015] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  477.809045] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  477.809884] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  477.810346] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  477.811370] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  477.811389] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  477.811405] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  477.811420] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  477.812641] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  477.813667] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  477.814766] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  477.814793] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  477.814819] [drm:intel_power_well_disable [i915]] disabling DC off
>[  477.814833] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  477.814844] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  477.815275] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.815278] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  477.815293] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  477.815304] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.817584] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  477.817597] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  477.819878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  477.819881] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  477.822164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  477.822177] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  477.824458] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  477.824461] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  477.824471] [drm:intel_power_well_disable [i915]] disabling always-on
>[  477.824475] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  477.824494] [drm:intel_runtime_suspend [i915]] Suspending device
>[  477.825892] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  477.825911] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  477.825929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  477.825951] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  477.825968] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  477.825987] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  477.826004] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  477.826022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  477.826039] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  477.826053] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  477.826066] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  477.826068] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  477.826081] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  477.826083] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  477.826096] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  477.826110] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  477.826123] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  477.826135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  477.826149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  477.826169] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  477.826186] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  477.826200] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  477.826216] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  477.826231] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  477.826254] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  477.826272] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  477.826292] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  477.826315] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  477.826333] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  477.826352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  477.826370] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  477.826387] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  477.826404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  477.826420] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  477.826436] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  477.826439] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  477.826455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  477.826458] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  477.826475] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  477.826491] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  477.826507] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  477.826523] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  477.826538] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  477.826557] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  477.826573] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  477.826589] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  477.826605] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  477.826620] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  477.826640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  477.826663] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  477.826682] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  477.826700] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  477.826776] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  477.827936] [drm:intel_runtime_suspend [i915]] Device suspended
>[  477.851883] [drm:intel_runtime_resume [i915]] Resuming device
>[  477.856391] [drm:intel_runtime_resume [i915]] Device resumed
>[  477.856411] [drm:intel_runtime_suspend [i915]] Suspending device
>[  477.860030] [drm:intel_runtime_suspend [i915]] Device suspended
>[  477.883899] [drm:intel_runtime_resume [i915]] Resuming device
>[  477.888434] [drm:intel_runtime_resume [i915]] Device resumed
>[  477.888469] [drm:intel_power_well_enable [i915]] enabling always-on
>[  477.888482] [drm:intel_power_well_enable [i915]] enabling DC off
>[  477.888896] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  477.888922] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  477.888941] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  477.888985] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  477.889006] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  477.889024] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  477.889038] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  477.889061] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  477.889403] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  477.889418] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  477.889441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  477.889460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  477.889476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  477.889492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  477.889507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  477.889522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  477.889537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  477.889551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  477.889565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  477.889578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  477.889592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  477.889605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  477.889619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  477.889634] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  477.889653] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  477.889670] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  477.889686] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  477.889707] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  477.889753] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  477.893051] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  477.894421] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  477.894440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  477.894458] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  477.894477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  477.899736] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  477.899755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  477.904945] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  477.907460] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b50958
>[  477.908519] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  477.908574] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  477.908595] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  477.908680] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  477.908699] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  477.911992] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  477.912018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  477.912041] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  477.912066] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  477.912808] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  477.912834] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  477.912858] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  477.913569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  477.913592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  477.913613] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  477.914338] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  477.914367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  477.915388] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  477.917678] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b55d28
>[  477.918813] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  477.918851] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  477.918874] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  477.918911] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  477.935820] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  477.935871] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  477.935961] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  477.936060] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  477.936106] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  477.936189] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  477.936425] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  477.945071] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.953802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.962524] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.971201] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.979978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.988799] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  477.997511] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.006218] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.014931] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.023641] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.032309] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.040930] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.049486] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.058007] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.066505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.074983] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.083452] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.091915] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.100378] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.108842] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.117307] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.125784] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.134249] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.142712] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.151188] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.159652] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.168115] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.176578] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.185042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.193505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.201969] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.210442] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.210451] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  478.210454] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  478.210471] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  478.211335] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  478.212874] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  478.212890] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  478.212904] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  478.212917] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  478.213730] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  478.214446] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  478.215195] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  478.215211] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  478.215246] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  478.215260] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  478.217560] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  478.217575] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  478.219867] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  478.219871] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  478.222162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  478.222177] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  478.224469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  478.224473] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  478.224475] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  478.224491] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  478.224961] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  478.225286] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  478.225302] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  478.225328] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  478.225341] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  478.225758] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  478.226082] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  478.226437] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  478.226454] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  478.228736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  478.228763] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  478.231043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  478.231047] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  478.233333] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  478.233350] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  478.235633] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  478.235637] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  478.235639] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  478.235664] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  478.244128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.252595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.261063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.269527] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.277991] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.286458] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.294923] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.303386] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.311850] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.320313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.328791] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.337256] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.345731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.354196] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.362660] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.371123] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.379586] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.388050] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.396514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.404977] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.413441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.421904] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.430367] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.438831] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.447294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.455757] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.464219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.472683] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.481163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.489628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.498104] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.506568] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  478.506577] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  478.506580] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from disconnected to disconnected
>[  478.506596] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  478.507445] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  478.508984] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  478.508999] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  478.509013] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  478.509026] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  478.509832] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  478.510548] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  478.511295] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from connected to connected
>[  478.511311] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  478.511335] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from disconnected to disconnected
>[  478.511349] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  478.513657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  478.513672] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  478.515981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  478.515985] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  478.518268] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  478.518284] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  478.520577] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  478.520580] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  478.520583] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from disconnected to disconnected
>[  478.520599] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  478.521069] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  478.521407] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  478.521423] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  478.521437] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  478.521450] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  478.521881] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  478.522204] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  478.522558] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from connected to connected
>[  478.522575] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  478.524873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  478.524886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  478.527174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  478.527177] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  478.529477] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  478.529492] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  478.531793] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  478.531797] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  478.531799] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from disconnected to disconnected
>[  478.542658] Console: switching to colour frame buffer device 240x75
>[  478.773639] Console: switching to colour dummy device 80x25
>[  478.774005] [IGT] pm_rps: executing
>[  478.804126] [IGT] pm_rps: starting subtest basic-api
>[  478.810897] [IGT] pm_rps: exiting, ret=0
>[  478.869449] Console: switching to colour frame buffer device 240x75
>[  479.078310] Console: switching to colour dummy device 80x25
>[  479.078406] [IGT] prime_busy: executing
>[  479.194028] [IGT] prime_busy: starting subtest basic-after-default
>[  480.738185] [IGT] prime_busy: exiting, ret=0
>[  480.786232] Console: switching to colour frame buffer device 240x75
>[  480.993391] Console: switching to colour dummy device 80x25
>[  480.993503] [IGT] prime_busy: executing
>[  481.021181] [IGT] prime_busy: starting subtest basic-before-default
>[  482.696164] [IGT] prime_busy: exiting, ret=0
>[  482.746487] Console: switching to colour frame buffer device 240x75
>[  482.941731] Console: switching to colour dummy device 80x25
>[  482.941822] [IGT] prime_busy: executing
>[  483.078950] [IGT] prime_busy: starting subtest basic-wait-after-default
>[  484.678164] [IGT] prime_busy: exiting, ret=0
>[  484.736451] Console: switching to colour frame buffer device 240x75
>[  484.915620] Console: switching to colour dummy device 80x25
>[  484.915761] [IGT] prime_busy: executing
>[  484.981102] [IGT] prime_busy: starting subtest basic-wait-before-default
>[  486.672191] [IGT] prime_busy: exiting, ret=0
>[  486.719942] Console: switching to colour frame buffer device 240x75
>[  486.894675] Console: switching to colour dummy device 80x25
>[  486.894916] [IGT] prime_self_import: executing
>[  486.895020] [IGT] prime_self_import: starting subtest basic-llseek-bad
>[  486.907049] [IGT] prime_self_import: exiting, ret=0
>[  486.953300] Console: switching to colour frame buffer device 240x75
>[  487.160283] Console: switching to colour dummy device 80x25
>[  487.160393] [IGT] prime_self_import: executing
>[  487.160622] [IGT] prime_self_import: starting subtest basic-llseek-size
>[  487.174689] [IGT] prime_self_import: exiting, ret=0
>[  487.233554] Console: switching to colour frame buffer device 240x75
>[  487.410590] Console: switching to colour dummy device 80x25
>[  487.410759] [IGT] prime_self_import: executing
>[  487.410917] [IGT] prime_self_import: starting subtest basic-with_fd_dup
>[  487.450415] [IGT] prime_self_import: exiting, ret=0
>[  487.503310] Console: switching to colour frame buffer device 240x75
>[  487.717989] Console: switching to colour dummy device 80x25
>[  487.718093] [IGT] prime_self_import: executing
>[  487.718212] [IGT] prime_self_import: starting subtest basic-with_one_bo
>[  487.770234] [IGT] prime_self_import: exiting, ret=0
>[  487.786410] Console: switching to colour frame buffer device 240x75
>[  487.997543] Console: switching to colour dummy device 80x25
>[  487.997642] [IGT] prime_self_import: executing
>[  487.997778] [IGT] prime_self_import: starting subtest basic-with_one_bo_two_files
>[  488.010288] [IGT] prime_self_import: exiting, ret=0
>[  488.053407] Console: switching to colour frame buffer device 240x75
>[  488.235925] Console: switching to colour dummy device 80x25
>[  488.236026] [IGT] prime_self_import: executing
>[  488.236138] [IGT] prime_self_import: starting subtest basic-with_two_bos
>[  488.275290] [IGT] prime_self_import: exiting, ret=0
>[  488.320053] Console: switching to colour frame buffer device 240x75
>[  488.497913] Console: switching to colour dummy device 80x25
>[  488.498228] [IGT] prime_vgem: executing
>[  488.543225] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  488.576137] [IGT] prime_vgem: starting subtest basic-busy-default
>[  488.588071] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  488.591506] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  488.591777] [IGT] prime_vgem: exiting, ret=0
>[  488.653352] Console: switching to colour frame buffer device 240x75
>[  488.845856] Console: switching to colour dummy device 80x25
>[  488.845949] [IGT] prime_vgem: executing
>[  488.871122] [IGT] prime_vgem: starting subtest basic-fence-flip
>[  488.871158] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  488.873118] [drm:drm_mode_addfb2] [FB:68]
>[  488.873138] [drm:vgem_gem_dumb_create [vgem]] Created object of size 3145728
>[  488.875097] [drm:drm_mode_addfb2] [FB:69]
>[  488.875137] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  488.875168] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  488.883666] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.892165] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.900657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.909130] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.917598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.926164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.934628] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.943105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.951571] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.960036] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.968501] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.976964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.985426] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  488.993889] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.002352] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.010815] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.019279] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.027743] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.036206] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.044668] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.053131] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.061595] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.070156] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.078619] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.087085] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.095548] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.104012] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.112474] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.120940] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.129413] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.137877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.146342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  489.146350] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  489.146354] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  489.146360] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  489.146376] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  489.147299] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  489.148831] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  489.148847] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  489.148861] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  489.148875] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  489.149684] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  489.150399] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  489.151201] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  489.151227] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  489.151242] [drm:drm_mode_debug_printmodeline] Modeline 71:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  489.151244] [drm:drm_mode_debug_printmodeline] Modeline 72:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  489.151245] [drm:drm_mode_debug_printmodeline] Modeline 78:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  489.151247] [drm:drm_mode_debug_printmodeline] Modeline 73:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  489.151248] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  489.151249] [drm:drm_mode_debug_printmodeline] Modeline 77:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  489.151251] [drm:drm_mode_debug_printmodeline] Modeline 75:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  489.151252] [drm:drm_mode_debug_printmodeline] Modeline 76:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  489.151254] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  489.151255] [drm:drm_mode_debug_printmodeline] Modeline 79:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  489.151256] [drm:drm_mode_debug_printmodeline] Modeline 80:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  489.151258] [drm:drm_mode_debug_printmodeline] Modeline 81:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  489.151288] [drm:drm_mode_setcrtc] [CRTC:31:pipe A]
>[  489.151295] [drm:drm_mode_setcrtc] [CONNECTOR:51:DP-2]
>[  489.151339] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  489.151353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  489.151368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 65000KHz
>[  489.151384] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  489.151397] [drm:intel_dp_compute_config [i915]] DP link bw required 195000 available 324000
>[  489.151410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  489.151424] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  489.151437] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  489.151449] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2524349, gmch_n: 4194304, link_m: 105181, link_n: 262144, tu: 64
>[  489.151461] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  489.151472] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  489.151474] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  489.151485] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  489.151486] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  489.151498] [drm:intel_dump_pipe_config [i915]] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  489.151509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 65000
>[  489.151519] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  489.151530] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  489.151541] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  489.151554] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  489.151565] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  489.151577] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] FB:112, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  489.151587] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[  489.151598] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  489.151608] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  489.151622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  489.151640] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  489.151653] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  489.152161] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  489.168828] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  489.168849] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  489.168881] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  489.168900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  489.168914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  489.168927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  489.168939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  489.168951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  489.168963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  489.168976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  489.168987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  489.168998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  489.169009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  489.169020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  489.169030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  489.169041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  489.169053] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  489.169068] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  489.169081] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  489.169095] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  489.169110] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  489.169123] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  489.181974] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.190494] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.199009] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.207523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.216040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.224553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.233067] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.241580] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.250093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.258606] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.267119] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.275631] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.284145] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.292657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.301169] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.309682] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.318231] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.326746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.334621] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  489.349607] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  489.349623] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  489.349694] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  489.350558] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  489.352031] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  489.353952] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  489.353970] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  489.354006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  489.354024] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  489.359418] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  489.359448] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  489.364593] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  489.367097] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88044517a548
>[  489.367979] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  489.368010] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  489.368024] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  489.384821] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  489.384852] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  489.384892] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  489.785371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  489.785664] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  489.803375] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  489.803443] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  489.803505] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  489.803644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  489.803700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  489.803821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  489.803882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  489.803936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  489.803987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  489.804040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  489.804087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  489.804134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  489.804182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  489.804227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  489.804271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  489.804320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  489.804372] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  489.804435] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  489.804492] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  489.804547] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  489.804599] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  489.819869] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  489.819926] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  489.820019] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  489.820084] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  489.820620] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  489.821024] [IGT] prime_vgem: exiting, ret=0
>[  489.850300] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  489.850361] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  489.850424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  489.850491] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  489.850542] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  489.850596] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  489.850651] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  489.850704] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  489.850850] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  489.850909] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  489.850964] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  489.850978] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  489.851029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  489.851046] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  489.851098] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  489.851155] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  489.851203] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  489.851257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  489.851304] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  489.851366] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  489.851413] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  489.851467] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  489.851513] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  489.851565] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  489.851624] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  489.851706] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  489.851791] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  489.852000] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  489.852053] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  489.852107] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  489.852173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  489.852230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  489.852280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  489.852332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  489.852380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  489.852429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  489.852478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  489.852525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  489.852571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  489.852617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  489.852662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  489.852708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  489.852793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  489.852847] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  489.852915] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  489.852972] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  489.853030] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  489.869823] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  489.869884] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  489.883166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.892008] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.900824] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.909601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.918415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.927273] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.936063] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.944847] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.953629] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.962404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.971185] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.980045] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.988820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  489.997545] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  490.006186] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  490.014782] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  490.023344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  490.031883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  490.036391] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  490.050479] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  490.050497] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  490.050588] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  490.052127] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  490.054740] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  490.056111] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  490.056126] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  490.056140] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  490.056156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  490.061303] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  490.061318] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  490.066484] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  490.068976] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88045aefa548
>[  490.069866] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  490.069915] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  490.069929] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  490.086785] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  490.086808] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  490.086851] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  490.103532] Console: switching to colour frame buffer device 240x75
>[  490.325265] Console: switching to colour dummy device 80x25
>[  490.325576] [IGT] prime_vgem: executing
>[  490.369407] [IGT] prime_vgem: starting subtest basic-fence-mmap
>[  490.369593] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  490.393674] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  490.394024] [IGT] prime_vgem: exiting, ret=0
>[  490.454160] Console: switching to colour frame buffer device 240x75
>[  490.666016] Console: switching to colour dummy device 80x25
>[  490.666112] [IGT] prime_vgem: executing
>[  490.699530] [IGT] prime_vgem: starting subtest basic-fence-read
>[  490.699821] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  490.717840] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  490.717931] [IGT] prime_vgem: exiting, ret=0
>[  490.771151] Console: switching to colour frame buffer device 240x75
>[  490.972729] Console: switching to colour dummy device 80x25
>[  490.972830] [IGT] prime_vgem: executing
>[  490.998223] [IGT] prime_vgem: starting subtest basic-fence-wait-default
>[  491.018938] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  492.023457] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  492.023833] [IGT] prime_vgem: exiting, ret=0
>[  492.087021] Console: switching to colour frame buffer device 240x75
>[  492.264021] Console: switching to colour dummy device 80x25
>[  492.264131] [IGT] prime_vgem: executing
>[  492.290105] [IGT] prime_vgem: starting subtest basic-gtt
>[  492.290167] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  492.300748] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  492.300813] [IGT] prime_vgem: exiting, ret=0
>[  492.339168] Console: switching to colour frame buffer device 240x75
>[  492.544540] Console: switching to colour dummy device 80x25
>[  492.544999] [IGT] prime_vgem: executing
>[  492.587488] [IGT] prime_vgem: starting subtest basic-read
>[  492.587584] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  492.614269] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  492.614478] [IGT] prime_vgem: exiting, ret=0
>[  492.672680] Console: switching to colour frame buffer device 240x75
>[  492.896684] Console: switching to colour dummy device 80x25
>[  492.896936] [IGT] prime_vgem: executing
>[  492.931061] [IGT] prime_vgem: starting subtest basic-sync-default
>[  492.943274] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  492.946683] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  492.947033] [IGT] prime_vgem: exiting, ret=0
>[  492.989683] Console: switching to colour frame buffer device 240x75
>[  493.199238] Console: switching to colour dummy device 80x25
>[  493.199339] [IGT] prime_vgem: executing
>[  493.231186] [IGT] prime_vgem: starting subtest basic-wait-default
>[  493.246884] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  493.248350] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  493.248539] [IGT] prime_vgem: exiting, ret=0
>[  493.306616] Console: switching to colour frame buffer device 240x75
>[  493.499191] Console: switching to colour dummy device 80x25
>[  493.499302] [IGT] prime_vgem: executing
>[  493.531094] [IGT] prime_vgem: starting subtest basic-write
>[  493.531134] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  493.544632] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4
>[  493.544801] [IGT] prime_vgem: exiting, ret=0
>[  493.603621] Console: switching to colour frame buffer device 240x75
>[  493.818250] Console: switching to colour dummy device 80x25
>[  493.818439] [IGT] vgem_basic: executing
>[  493.840356] [IGT] vgem_basic: starting subtest create
>[  493.840472] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1
>[  493.840575] [drm:vgem_gem_dumb_create [vgem]] Created object of size 1048576
>[  493.840659] [drm:vgem_gem_dumb_create [vgem]] Created object of size 2147483648
>[  493.840990] [IGT] vgem_basic: exiting, ret=0
>[  493.857138] Console: switching to colour frame buffer device 240x75
>[  494.037365] Console: switching to colour dummy device 80x25
>[  494.037597] [IGT] vgem_basic: executing
>[  494.057102] [IGT] vgem_basic: starting subtest debugfs
>[  494.057804] [IGT] vgem_basic: exiting, ret=0
>[  494.073881] Console: switching to colour frame buffer device 240x75
>[  494.256632] Console: switching to colour dummy device 80x25
>[  494.257263] [IGT] vgem_basic: executing
>[  494.273996] [IGT] vgem_basic: starting subtest dmabuf-export
>[  494.290310] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  494.290690] [IGT] vgem_basic: exiting, ret=0
>[  494.353654] Console: switching to colour frame buffer device 240x75
>[  494.583016] Console: switching to colour dummy device 80x25
>[  494.583126] [IGT] vgem_basic: executing
>[  494.603466] [IGT] vgem_basic: starting subtest dmabuf-fence
>[  494.603510] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  494.604120] [IGT] vgem_basic: exiting, ret=0
>[  494.620023] Console: switching to colour frame buffer device 240x75
>[  494.815310] Console: switching to colour dummy device 80x25
>[  494.815415] [IGT] vgem_basic: executing
>[  494.836788] [IGT] vgem_basic: starting subtest dmabuf-fence-before
>[  494.836836] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  494.836921] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  494.837019] [IGT] vgem_basic: exiting, ret=0
>[  494.853474] Console: switching to colour frame buffer device 240x75
>[  495.033186] Console: switching to colour dummy device 80x25
>[  495.033306] [IGT] vgem_basic: executing
>[  495.053506] [IGT] vgem_basic: starting subtest dmabuf-mmap
>[  495.053549] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  495.053868] [IGT] vgem_basic: exiting, ret=0
>[  495.070144] Console: switching to colour frame buffer device 240x75
>[  495.264150] Console: switching to colour dummy device 80x25
>[  495.264240] [IGT] vgem_basic: executing
>[  495.274511] [IGT] vgem_basic: starting subtest mmap
>[  495.274545] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4194304
>[  495.274655] [IGT] vgem_basic: exiting, ret=0
>[  495.291274] Console: switching to colour frame buffer device 240x75
>[  495.492842] Console: switching to colour dummy device 80x25
>[  495.492948] [IGT] vgem_basic: executing
>[  495.508150] [IGT] vgem_basic: starting subtest second-client
>[  495.553560] [IGT] vgem_basic: exiting, ret=0
>[  495.570371] Console: switching to colour frame buffer device 240x75
>[  495.777691] Console: switching to colour dummy device 80x25
>[  495.778040] [IGT] vgem_basic: executing
>[  495.808685] [IGT] vgem_basic: starting subtest sysfs
>[  495.810002] [IGT] vgem_basic: exiting, ret=0
>[  495.825295] Console: switching to colour frame buffer device 240x75
>[  496.034641] Console: switching to colour dummy device 80x25
>[  496.035078] [IGT] vgem_basic: executing
>[  496.035399] [IGT] vgem_basic: starting subtest unload
>[  496.089530] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  496.123771] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  496.170775] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  496.187090] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  496.249833] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  496.259087] [drm:vgem_gem_dumb_create [vgem]] Created object of size 4096
>[  496.306223] [drm] Initialized vgem 1.0.0 20120112 for virtual device on minor 1
>[  496.325748] [IGT] vgem_basic: exiting, ret=0
>[  496.342285] Console: switching to colour frame buffer device 240x75
>[  496.559979] Console: switching to colour dummy device 80x25
>[  496.560079] [IGT] drv_module_reload: executing
>[  496.560485] [IGT] drv_module_reload: starting subtest basic-reload
>[  496.666223] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  496.666247] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  496.666278] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  496.666294] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  496.666319] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  496.666333] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  496.666352] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  496.666366] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  496.738945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  496.739837] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  496.744747] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  496.744879] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  496.744948] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  496.745069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  496.745108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  496.745147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  496.745181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  496.745214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  496.745245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  496.745278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  496.745309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  496.745339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  496.745368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  496.745396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  496.745424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  496.745451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  496.745483] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  496.745522] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  496.745560] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  496.745595] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  496.745630] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  496.753465] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  496.753518] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  496.753607] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  496.753667] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  496.754131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  496.754362] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  496.754479] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  496.772172] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  496.772242] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  496.772378] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  496.773980] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  496.774040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  496.774101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  496.774156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  496.774207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  496.774255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  496.774302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  496.774350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  496.774395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  496.774439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  496.774481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  496.774529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  496.774570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  496.774610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  496.774657] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  496.774713] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  496.774823] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  496.774881] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  496.774937] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  496.775022] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  496.775075] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  496.775127] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  496.775308] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  496.775387] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  496.775441] [drm:intel_power_well_disable [i915]] disabling DC off
>[  496.775492] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  496.775534] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  496.776084] [drm:intel_power_well_disable [i915]] disabling always-on
>[  496.776490] [drm:intel_runtime_pm_get_noresume [i915]] RPM wakelock ref not held during HW access
>[  496.826998] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  496.830188] [drm:intel_power_well_enable [i915]] enabling always-on
>[  496.830208] [drm:intel_power_well_enable [i915]] enabling DC off
>[  496.830501] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  496.830530] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  496.830550] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  496.830632] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  496.830652] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  496.830670] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  496.830690] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  496.830707] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  496.830753] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  496.830771] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  496.830795] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  497.084846] [drm:i915_driver_load [i915]] Found SunrisePoint PCH
>[  497.084878] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  497.086581] [drm:intel_device_info_dump [i915]] i915 device info: platform=SKYLAKE gen=9 pciid=0x193b rev=0x09
>[  497.086605] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  497.086628] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  497.086649] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  497.086669] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  497.086689] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  497.086708] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  497.086750] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  497.086770] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  497.086793] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  497.086814] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  497.086833] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  497.086854] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  497.086872] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  497.086892] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  497.086911] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  497.086930] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  497.086949] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  497.086970] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  497.086988] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  497.087008] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  497.087026] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  497.087047] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  497.087072] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  497.087101] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  497.087130] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  497.087160] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  497.087187] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  497.087215] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  497.087241] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  497.087268] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  497.087288] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  497.087305] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  497.087323] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  497.087347] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  497.087385] [drm] Found 128MB of eDRAM
>[  497.089755] [drm:intel_device_info_runtime_init [i915]] slice mask: 0007
>[  497.089777] [drm:intel_device_info_runtime_init [i915]] slice total: 3
>[  497.089796] [drm:intel_device_info_runtime_init [i915]] subslice total: 9
>[  497.089814] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  497.089831] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  497.089848] [drm:intel_device_info_runtime_init [i915]] EU total: 72
>[  497.089864] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  497.089884] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  497.089909] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  497.089932] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  497.089961] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  497.089987] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  497.090031] [drm] Memory usable by graphics device = 4096M
>[  497.090064] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  497.090094] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  497.090103] [drm] Replacing VGA console driver
>[  497.090188] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  497.090321] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  497.090382] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  497.090413] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  497.095850] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  497.095874] [drm:intel_opregion_setup [i915]] ASLE supported
>[  497.095895] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  497.095913] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  497.096091] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  497.096097] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  497.096097] [drm] Driver supports precise vblank timestamp query.
>[  497.096122] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  497.096142] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 206
>[  497.096161] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  497.096178] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  497.097785] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  497.097812] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  497.097834] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  497.097857] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  497.097860] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  497.097878] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  497.097895] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  497.097911] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  497.097927] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 206 not known; assuming 38
>[  497.097946] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  497.097962] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  497.097977] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  497.097991] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  497.098005] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  497.098019] [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  497.098033] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8
>[  497.098308] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  497.098354] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  497.098376] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  497.098430] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  497.098454] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  497.098477] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  497.100836] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  497.100861] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  497.100887] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  497.100922] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.100941] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.100960] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  497.100982] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.101000] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  497.101017] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  497.101033] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  497.101050] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  497.101067] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  497.101103] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_26.bin
>[  497.102630] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  497.103813] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  497.103833] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  497.103850] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  497.103866] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  497.103882] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  497.103897] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  497.103912] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  497.103927] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  497.103952] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  497.104235] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  497.104483] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_26.bin (v1.26)
>[  497.104580] [drm:intel_dp_init_connector [i915]] Adding DP connector on port A
>[  497.104643] [drm:intel_dp_init_connector [i915]] using AUX A for port A (platform default)
>[  497.104712] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  497.104804] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  497.104846] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  497.115532] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.123964] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.132395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.140825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.149264] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.157692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.166146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.174574] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.183001] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.191427] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.199856] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.208283] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.216709] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.225146] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.233573] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.242000] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.250429] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.258855] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.267280] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  497.268007] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  497.268815] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  497.269496] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  497.269520] [drm:lspcon_init [i915]] LSPCON detected
>[  497.270321] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  497.285017] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  497.285849] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  497.286651] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  497.286674] [drm:lspcon_init [i915]] Success: LSPCON init
>[  497.286696] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  497.286748] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  497.286784] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  497.286836] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  497.286869] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  497.286910] [drm:intel_dp_init_connector [i915]] Adding DP connector on port D
>[  497.286938] [drm:intel_dp_init_connector [i915]] using AUX D for port D (VBT)
>[  497.286986] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port D
>[  497.287018] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT)
>[  497.287073] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  497.287097] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  497.287119] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  497.287140] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  497.287159] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  497.287177] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  497.287195] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  497.287213] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  497.287230] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  497.287245] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  497.287259] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  497.287274] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  497.287290] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  497.287304] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  497.287317] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  497.287331] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  497.287346] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  497.287360] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  497.287373] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  497.287387] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  497.287403] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  497.287419] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  497.287434] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  497.287450] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  497.287466] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  497.287481] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  497.287502] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  497.287519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  497.287536] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  497.287552] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  497.287554] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  497.287570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  497.287572] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  497.287587] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  497.287602] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  497.287617] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  497.287631] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  497.287645] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  497.287665] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  497.287681] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  497.287696] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  497.287710] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  497.287741] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  497.287757] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  497.287771] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  497.287785] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  497.287800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  497.287805] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  497.287818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  497.287821] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  497.287836] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  497.287851] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  497.287866] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  497.287880] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  497.287894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  497.287914] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  497.287931] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  497.287945] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  497.287961] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  497.287975] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  497.287992] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  497.288006] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  497.288020] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  497.288035] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  497.288038] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  497.288051] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  497.288055] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  497.288069] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  497.288083] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  497.288097] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  497.288111] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  497.288125] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  497.288145] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  497.288160] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  497.288175] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  497.288190] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  497.288204] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  497.288223] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  497.288292] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  497.288317] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  497.288337] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  497.288358] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  497.288377] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  497.288395] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  497.288414] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  497.288431] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  497.288449] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.288483] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.288500] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.288518] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.288534] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.288976] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.289004] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/skl_huc_ver01_07_1398.bin
>[  497.289026] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  497.289181] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/skl_huc_ver01_07_1398.bin succeeded, fw ffff8804451da458
>[  497.289200] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  497.289471] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff8804a1dd8040
>[  497.289855] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  497.289940] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  497.290026] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  497.291700] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  497.291778] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  497.291834] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  497.291886] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  497.291937] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  497.291982] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  497.291988] [drm] GuC firmware load skipped
>[  497.292555] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  497.292592] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  497.292615] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  497.292636] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  497.292655] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  497.293062] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  497.293092] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.293112] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.293407] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.294412] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-DP-1
>[  497.295493] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-2
>[  497.296305] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-3
>[  497.297342] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card0-DP-4
>[  497.298095] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  497.299302] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  497.301883] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.310333] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.315583] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  497.318806] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.319897] [drm:asle_work [i915]] bclp = 0x80000002
>[  497.319973] [drm:asle_work [i915]] updating opregion backlight 2/255
>[  497.321636] [drm:asle_work [i915]] bclp = 0x800000ff
>[  497.321660] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  497.322639] acpi device:0f: registered as cooling_device13
>[  497.323525] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input11
>[  497.324279] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  497.324281] [drm] DRM_I915_DEBUG enabled
>[  497.324281] [drm] DRM_I915_DEBUG_GEM enabled
>[  497.327289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.339827] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.342436] [drm:asle_work [i915]] bclp = 0x800000ff
>[  497.342464] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  497.348315] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.356748] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.365168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.373587] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.382026] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.390457] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.398886] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.407314] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.415740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.424166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.432593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.441019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.449447] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.457874] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.466300] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.474740] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.483166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.491592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.500018] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.508443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.516869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.525293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.533718] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.542227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.550655] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.559097] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.567523] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.567533] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  497.567558] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.567580] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.567618] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.568117] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.568120] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from unknown to disconnected
>[  497.568146] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  497.568165] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.568182] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.568584] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.568605] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.568623] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.569594] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  497.571133] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  497.571156] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  497.571177] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  497.571195] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  497.572003] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  497.572721] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  497.575010] [drm:drm_dp_i2c_do_msg] native defer
>[  497.576066] [drm:drm_dp_i2c_do_msg] native defer
>[  497.577537] [drm:drm_dp_i2c_do_msg] native defer
>[  497.579249] [drm:drm_dp_i2c_do_msg] native defer
>[  497.580320] [drm:drm_dp_i2c_do_msg] native defer
>[  497.581663] [drm:drm_dp_i2c_do_msg] native defer
>[  497.583372] [drm:drm_dp_i2c_do_msg] native defer
>[  497.584438] [drm:drm_dp_i2c_do_msg] native defer
>[  497.585844] [drm:drm_dp_i2c_do_msg] native defer
>[  497.586985] [drm:drm_dp_i2c_do_msg] native defer
>[  497.588395] [drm:drm_dp_i2c_do_msg] native defer
>[  497.589456] [drm:drm_dp_i2c_do_msg] native defer
>[  497.590853] [drm:drm_dp_i2c_do_msg] native defer
>[  497.591993] [drm:drm_dp_i2c_do_msg] native defer
>[  497.593837] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.593888] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.593906] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.593924] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.593939] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.594376] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.594378] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from unknown to connected
>[  497.594402] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  497.594419] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.594433] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.594448] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.594466] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.594481] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.594519] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.594540] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.594554] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.594570] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.594583] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.595082] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.595085] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from unknown to disconnected
>[  497.595130] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  497.595168] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.597502] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  497.597525] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  497.599828] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  497.599833] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  497.602120] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  497.602144] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  497.604429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  497.604434] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  497.604455] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.604457] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from unknown to disconnected
>[  497.604481] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  497.604502] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.604518] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.604877] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.604921] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.604942] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.605441] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  497.605799] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  497.605840] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  497.605879] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  497.605896] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  497.606328] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  497.606649] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  497.612998] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  497.613321] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.613349] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.613368] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.613387] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.613404] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.613868] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.613872] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from unknown to connected
>[  497.613897] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  497.613921] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.616190] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  497.616211] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  497.618481] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  497.618484] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  497.620778] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  497.620803] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  497.623082] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  497.623087] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  497.623110] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.623112] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from unknown to disconnected
>[  497.623241] [drm:drm_setup_crtcs] 
>[  497.623244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  497.623275] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  497.623309] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.623328] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.623671] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.632171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.640607] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.649047] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.657479] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.665912] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.674342] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.682859] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.691287] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.699717] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.708161] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.716590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.725019] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.733448] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.741876] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.750305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.758735] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.767166] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.775594] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.784023] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.792450] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.800880] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.809308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.817737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.826164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.834593] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.843021] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.851453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.859885] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.868313] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.876743] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.885171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.893600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  497.893609] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  497.893633] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.893675] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.893693] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.894181] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.894190] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  497.894193] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  497.894224] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  497.894251] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.894275] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.894671] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.894701] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.894741] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.895841] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  497.897375] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  497.897436] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  497.897455] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  497.897472] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  497.898288] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  497.899028] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  497.899857] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.899889] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.899925] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.899943] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.899958] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.900391] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.900431] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  497.900435] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  497.900437] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  497.900439] [drm:drm_mode_debug_printmodeline] Modeline 70:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  497.900440] [drm:drm_mode_debug_printmodeline] Modeline 76:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  497.900442] [drm:drm_mode_debug_printmodeline] Modeline 71:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  497.900443] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  497.900445] [drm:drm_mode_debug_printmodeline] Modeline 75:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  497.900446] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  497.900448] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  497.900449] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  497.900450] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  497.900452] [drm:drm_mode_debug_printmodeline] Modeline 78:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  497.900453] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  497.900455] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  497.900478] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  497.900494] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.900509] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.900975] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.901025] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.901050] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.901126] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.901175] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.901198] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.901222] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.901242] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.901700] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.901716] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  497.901719] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  497.901774] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  497.901799] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.904174] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  497.904235] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  497.906506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  497.906515] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  497.908826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  497.908879] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  497.911202] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  497.911213] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  497.911275] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.911282] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  497.911286] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  497.911356] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  497.911416] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.911465] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.911857] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.912322] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.912388] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.912986] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  497.913385] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  497.913432] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  497.913473] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  497.913511] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  497.914065] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  497.914456] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  497.914923] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  497.914979] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  497.915018] [drm:intel_power_well_disable [i915]] disabling DC off
>[  497.915057] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  497.915091] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  497.915547] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.915881] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  497.915885] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  497.915963] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  497.915966] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  497.915972] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  497.915975] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  497.915981] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  497.915983] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  497.915995] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  497.915999] [drm:drm_mode_debug_printmodeline] Modeline 82:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  497.916002] [drm:drm_mode_debug_printmodeline] Modeline 83:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  497.916005] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  497.916008] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  497.916011] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  497.916014] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  497.916017] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  497.916020] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  497.916023] [drm:drm_mode_debug_printmodeline] Modeline 101:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  497.916026] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  497.916029] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  497.916033] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  497.916036] [drm:drm_mode_debug_printmodeline] Modeline 88:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  497.916039] [drm:drm_mode_debug_printmodeline] Modeline 87:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  497.916042] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  497.916045] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  497.916048] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  497.916051] [drm:drm_mode_debug_printmodeline] Modeline 91:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  497.916054] [drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  497.916057] [drm:drm_mode_debug_printmodeline] Modeline 116:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  497.916060] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  497.916063] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  497.916066] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  497.916069] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  497.916072] [drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  497.916075] [drm:drm_mode_debug_printmodeline] Modeline 107:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  497.916078] [drm:drm_mode_debug_printmodeline] Modeline 122:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  497.916081] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  497.916084] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  497.916087] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  497.916090] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  497.916093] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  497.916096] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  497.916147] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  497.916187] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.918464] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  497.918515] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  497.920846] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  497.920854] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  497.923168] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  497.923219] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  497.925531] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  497.925540] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  497.925587] [drm:intel_power_well_disable [i915]] disabling always-on
>[  497.925591] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  497.925612] [drm:drm_setup_crtcs] connector 47 enabled? no
>[  497.925614] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  497.925616] [drm:drm_setup_crtcs] connector 56 enabled? no
>[  497.925618] [drm:drm_setup_crtcs] connector 60 enabled? no
>[  497.925620] [drm:drm_setup_crtcs] connector 63 enabled? yes
>[  497.925622] [drm:drm_setup_crtcs] connector 67 enabled? no
>[  497.925678] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  497.925723] [drm:intel_fb_initial_config [i915]] connector DP-2 has no encoder or crtc, skipping
>[  497.925806] [drm:intel_fb_initial_config [i915]] connector DP-3 not enabled, skipping
>[  497.925851] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 not enabled, skipping
>[  497.925890] [drm:intel_fb_initial_config [i915]] connector DP-4 has no encoder or crtc, skipping
>[  497.925927] [drm:intel_fb_initial_config [i915]] connector HDMI-A-2 not enabled, skipping
>[  497.925966] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  497.926002] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  497.926038] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  497.926049] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  497.926052] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  497.926055] [drm:drm_setup_crtcs] found mode 1920x1200
>[  497.926058] [drm:drm_setup_crtcs] looking for cmdline mode on connector 63
>[  497.926060] [drm:drm_setup_crtcs] looking for preferred mode on connector 63 0
>[  497.926063] [drm:drm_setup_crtcs] found mode 3840x2160
>[  497.926066] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  497.926106] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 31 (0,0)
>[  497.926114] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 38 (0,0)
>[  497.926162] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  497.957664] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000
>[  497.958917] fbcon: inteldrmfb (fb0) is primary device
>[  497.960326] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  497.960392] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  497.960460] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  497.960527] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  497.960581] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  497.960644] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  497.960703] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  497.960786] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  497.960840] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  497.960889] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  497.960935] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  497.960943] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  497.960988] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  497.960994] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  497.961040] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  497.961084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  497.961127] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  497.961169] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  497.961210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  497.961267] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  497.961311] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  497.961354] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  497.961395] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  497.961436] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  497.961500] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  497.961548] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  497.961610] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  497.961672] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  497.961725] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  497.961810] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  497.961865] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  497.961916] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  497.961963] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  497.962007] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  497.962049] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  497.962055] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  497.962096] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  497.962102] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  497.962143] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  497.962183] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  497.962223] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  497.962263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  497.962303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  497.962359] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  497.962401] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  497.962433] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  497.962460] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  497.962487] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  497.962523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  497.962567] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  497.962603] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  497.962635] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  497.962672] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  497.962708] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  497.962768] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  497.963067] [drm:intel_power_well_enable [i915]] enabling always-on
>[  497.963104] [drm:intel_power_well_enable [i915]] enabling DC off
>[  497.963422] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  497.963473] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  497.963508] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  497.963592] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  497.963626] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  497.963683] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  497.963732] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  497.963815] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  497.964614] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  497.964656] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  497.964713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  497.964779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  497.964820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  497.964856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  497.964890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  497.964923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  497.964956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  497.964986] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  497.965016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  497.965045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  497.965074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  497.965103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  497.965131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  497.965167] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  497.965205] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  497.965242] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  497.965276] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  497.965377] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  497.965415] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  497.969024] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  497.970480] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  497.970524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  497.970562] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  497.970600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  497.975900] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  497.975942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  497.981241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  497.983817] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a2f9d3d8
>[  497.984926] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  497.985058] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  497.985102] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  497.985241] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  497.985281] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  497.988714] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  497.988790] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  497.988832] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  497.988873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  497.989666] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  497.989703] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  497.989767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  497.990544] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  497.990578] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  497.990610] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  497.991380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  497.991417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  497.992500] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  497.994831] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a2f98958
>[  497.995872] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  497.995939] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  497.995977] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  497.996093] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  498.012877] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  498.012931] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  498.013016] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  498.013106] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  498.013153] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  498.013230] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  498.013519] Console: switching to colour frame buffer device 240x75
>[  498.039015] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  498.069283] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  498.090432] [drm] RC6 on
>[  498.102867] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  498.102873] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  498.102877] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  498.102880] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  498.102882] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  498.102885] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  498.175199] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  498.175261] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  498.175315] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  498.175366] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  498.175414] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  498.175463] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  498.175545] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  498.175591] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  498.207191] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input12
>[  498.213140] input: HDA Intel PCH Speaker as /devices/pci0000:00/0000:00:1f.3/sound/card0/input13
>[  498.215618] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input14
>[  498.217506] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input15
>[  498.219513] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input16
>[  498.221255] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input17
>[  498.222340] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input18
>[  498.479953] [IGT] drv_module_reload: exiting, ret=0
>[  498.657900] Console: switching to colour dummy device 80x25
>[  498.658193] [IGT] drv_module_reload: executing
>[  498.659333] [IGT] drv_module_reload: starting subtest basic-no-display
>[  498.785343] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  498.785388] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  498.785524] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  498.785548] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  498.785573] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  498.785595] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  498.785623] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  498.785645] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  498.821934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  498.822060] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  498.837121] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  498.837198] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  498.837232] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  498.837302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  498.837328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  498.837349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  498.837368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  498.837385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  498.837402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  498.837421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  498.837437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  498.837453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  498.837469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  498.837484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  498.837499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  498.837515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  498.837533] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  498.837555] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  498.837575] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  498.837594] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  498.837612] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  498.846071] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  498.846095] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  498.846133] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  498.846160] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  498.846326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  498.846408] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  498.846457] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  498.863712] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  498.863829] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  498.863940] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  498.865261] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  498.865326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  498.865398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  498.865463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  498.865539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  498.865613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  498.865684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  498.865759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  498.865873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  498.865925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  498.865976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  498.866028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  498.866075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  498.866121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  498.866172] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  498.866241] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  498.866321] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  498.866399] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  498.866474] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  498.866580] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  498.866628] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  498.866676] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  498.866785] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  498.866860] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  498.866919] [drm:intel_power_well_disable [i915]] disabling DC off
>[  498.866992] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  498.867059] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  498.867559] [drm:intel_power_well_disable [i915]] disabling always-on
>[  498.868490] [drm:intel_runtime_pm_get_noresume [i915]] RPM wakelock ref not held during HW access
>[  498.913967] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  498.916836] [drm:intel_power_well_enable [i915]] enabling always-on
>[  498.916856] [drm:intel_power_well_enable [i915]] enabling DC off
>[  498.917148] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  498.917173] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  498.917193] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  498.917250] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  498.917269] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  498.917287] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  498.917306] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  498.917323] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  498.917341] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  498.917359] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  498.917377] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  499.064258] [drm:i915_driver_load [i915]] Found SunrisePoint PCH
>[  499.064284] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  499.066012] [drm:intel_device_info_dump [i915]] i915 device info: platform=SKYLAKE gen=9 pciid=0x193b rev=0x09
>[  499.066040] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  499.066064] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  499.066088] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  499.066112] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  499.066134] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  499.066156] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  499.066177] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  499.066197] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  499.066219] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  499.066240] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  499.066277] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  499.066297] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  499.066316] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  499.066336] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  499.066355] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  499.066374] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  499.066393] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  499.066412] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  499.066431] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  499.066451] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  499.066470] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  499.066489] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  499.066508] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  499.066527] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  499.066547] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  499.066567] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  499.066587] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  499.066607] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  499.066627] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  499.066646] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  499.066664] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  499.066684] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  499.066703] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  499.066747] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  499.066777] [drm] Found 128MB of eDRAM
>[  499.069130] [drm] Display disabled (module parameter)
>[  499.069160] [drm:intel_device_info_runtime_init [i915]] slice mask: 0007
>[  499.069181] [drm:intel_device_info_runtime_init [i915]] slice total: 3
>[  499.069200] [drm:intel_device_info_runtime_init [i915]] subslice total: 9
>[  499.069217] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  499.069234] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  499.069268] [drm:intel_device_info_runtime_init [i915]] EU total: 72
>[  499.069284] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  499.069299] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  499.069314] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  499.069329] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  499.069347] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  499.069364] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  499.069391] [drm] Memory usable by graphics device = 4096M
>[  499.069413] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  499.069433] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  499.069439] [drm] Replacing VGA console driver
>[  499.069495] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  499.069605] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  499.069659] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  499.069679] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  499.075436] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  499.075461] [drm:intel_opregion_setup [i915]] ASLE supported
>[  499.075482] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  499.075502] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  499.075683] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  499.075710] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  499.075756] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 206
>[  499.075776] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  499.075798] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  499.077842] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  499.077867] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  499.077887] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  499.077911] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  499.077914] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  499.077931] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  499.077947] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  499.077963] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  499.077978] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 206 not known; assuming 38
>[  499.077996] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  499.078010] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  499.078024] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  499.078038] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  499.078052] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  499.078065] [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  499.078079] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8
>[  499.078332] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  499.078379] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  499.078400] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  499.078452] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  499.078475] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  499.078498] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  499.080977] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  499.081000] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  499.081025] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  499.081058] [drm:intel_power_well_enable [i915]] enabling always-on
>[  499.081076] [drm:intel_power_well_enable [i915]] enabling DC off
>[  499.081094] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  499.081114] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  499.081131] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  499.081147] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  499.081162] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  499.081178] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  499.081194] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  499.081228] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_26.bin
>[  499.082508] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_26.bin (v1.26)
>[  499.084514] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  499.084549] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  499.084573] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  499.084596] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  499.084618] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  499.084640] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  499.084661] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  499.084682] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  499.084702] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  499.084780] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/skl_huc_ver01_07_1398.bin
>[  499.084831] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  499.085029] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/skl_huc_ver01_07_1398.bin succeeded, fw ffff8804a24ed428
>[  499.085075] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  499.085483] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff8804a1dd8040
>[  499.085606] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  499.085795] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  499.085923] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  499.087362] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  499.087427] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  499.087479] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  499.087572] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  499.087621] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  499.087691] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  499.087696] [drm] GuC firmware load skipped
>[  499.088091] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  499.088900] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  499.089604] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  499.089605] [drm] DRM_I915_DEBUG enabled
>[  499.089605] [drm] DRM_I915_DEBUG_GEM enabled
>[  499.093120] [IGT] drv_module_reload: exiting, ret=0
>[  499.097627] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  499.109627] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  499.109630] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  499.109631] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  499.109632] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  499.109633] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  499.109633] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  499.227671] [IGT] drv_module_reload: executing
>[  499.228145] [IGT] drv_module_reload: starting subtest basic-reload-inject
>[  500.157647] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  500.160922] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  500.171435] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input19
>[  500.173106] input: HDA Intel PCH Speaker as /devices/pci0000:00/0000:00:1f.3/sound/card0/input20
>[  500.174140] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input21
>[  500.378050] Setting dangerous option inject_load_failure - tainting kernel
>[  500.388632] [drm:i915_driver_load [i915]] Found SunrisePoint PCH
>[  500.388657] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  500.390333] [drm:intel_device_info_dump [i915]] i915 device info: platform=SKYLAKE gen=9 pciid=0x193b rev=0x09
>[  500.390360] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  500.390385] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  500.390408] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  500.390430] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  500.390451] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  500.390472] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  500.390492] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  500.390513] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  500.390533] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  500.390554] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  500.390574] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  500.390593] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  500.390613] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  500.390632] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  500.390652] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  500.390671] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  500.390691] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  500.390711] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  500.390753] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  500.390774] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  500.390797] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  500.390819] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  500.390841] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  500.390863] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  500.390885] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  500.390907] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  500.390929] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  500.390950] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  500.390971] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  500.390993] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  500.391014] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  500.391035] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  500.391056] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  500.391076] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  500.391107] [drm] Found 128MB of eDRAM
>[  500.393494] [drm:intel_device_info_runtime_init [i915]] slice mask: 0007
>[  500.393514] [drm:intel_device_info_runtime_init [i915]] slice total: 3
>[  500.393532] [drm:intel_device_info_runtime_init [i915]] subslice total: 9
>[  500.393549] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  500.393565] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  500.393581] [drm:intel_device_info_runtime_init [i915]] EU total: 72
>[  500.393596] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  500.393611] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  500.393626] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  500.393640] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  500.393659] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  500.393676] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  500.393732] [drm] Memory usable by graphics device = 4096M
>[  500.393762] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  500.393790] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  500.393803] [drm] Replacing VGA console driver
>[  500.393881] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  500.394006] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  500.394061] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  500.394089] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  500.400401] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  500.400426] [drm:intel_opregion_setup [i915]] ASLE supported
>[  500.400447] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  500.400468] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  500.400648] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  500.400654] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  500.400655] [drm] Driver supports precise vblank timestamp query.
>[  500.400680] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  500.400702] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 206
>[  500.400748] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  500.400766] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  500.402834] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  500.402859] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  500.402880] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  500.402903] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  500.402907] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  500.402924] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  500.402941] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  500.402957] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  500.402971] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 206 not known; assuming 38
>[  500.402989] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  500.403004] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  500.403018] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  500.403031] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  500.403045] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  500.403058] [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  500.403071] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8
>[  500.403328] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  500.403374] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  500.403396] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  500.403445] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  500.403467] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  500.403490] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  500.406016] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  500.406041] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  500.406067] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  500.406102] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.406122] [drm:intel_power_well_enable [i915]] enabling DC off
>[  500.406140] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  500.406162] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  500.406180] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  500.406197] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  500.406213] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  500.406229] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  500.406247] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  500.406283] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_26.bin
>[  500.407382] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_26.bin (v1.26)
>[  500.408795] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  500.408822] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  500.408842] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  500.408860] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  500.408876] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  500.408893] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  500.408909] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  500.408924] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  500.408940] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  500.408966] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  500.409187] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  500.409533] [drm:intel_dp_init_connector [i915]] Adding DP connector on port A
>[  500.409596] [drm:intel_dp_init_connector [i915]] using AUX A for port A (platform default)
>[  500.409669] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  500.409702] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  500.409778] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  500.420454] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.428887] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.437317] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.445746] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.454171] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.462599] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.471027] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.479453] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.487879] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.496303] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.504727] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.513151] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.521588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.530025] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.538456] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.546891] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.555321] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.563752] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.572179] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  500.572909] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  500.573731] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  500.574414] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  500.574440] [drm:lspcon_init [i915]] LSPCON detected
>[  500.575183] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  500.589809] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  500.590634] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  500.591454] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  500.591479] [drm:lspcon_init [i915]] Success: LSPCON init
>[  500.591502] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  500.591556] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  500.591588] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  500.591632] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  500.591662] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  500.591699] [drm:intel_dp_init_connector [i915]] Adding DP connector on port D
>[  500.591792] [drm:intel_dp_init_connector [i915]] using AUX D for port D (VBT)
>[  500.591875] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port D
>[  500.591945] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT)
>[  500.592007] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  500.592031] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  500.592071] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  500.592091] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  500.592109] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  500.592127] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  500.592144] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  500.592161] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  500.592177] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  500.592191] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  500.592206] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  500.592220] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  500.592235] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  500.592248] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  500.592262] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  500.592275] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  500.592290] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  500.592303] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  500.592317] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  500.592329] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  500.592345] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  500.592361] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  500.592376] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  500.592391] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  500.592407] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  500.592422] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  500.592442] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  500.592458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  500.592474] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  500.592489] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  500.592492] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  500.592507] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  500.592509] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  500.592524] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  500.592538] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  500.592552] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  500.592565] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  500.592579] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  500.592598] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  500.592612] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  500.592625] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  500.592639] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  500.592652] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  500.592667] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  500.592680] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  500.592693] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  500.592705] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  500.592722] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  500.592754] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  500.592780] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  500.592795] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  500.592829] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  500.592845] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  500.592860] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  500.592875] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  500.592897] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  500.592912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  500.592926] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  500.592941] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  500.592955] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  500.592971] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  500.592986] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  500.593000] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  500.593014] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  500.593018] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  500.593030] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  500.593034] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  500.593048] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  500.593062] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  500.593076] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  500.593090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  500.593104] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  500.593126] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  500.593142] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  500.593157] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  500.593172] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  500.593187] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  500.593206] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  500.593285] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  500.593322] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  500.593353] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  500.593399] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  500.593424] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  500.593450] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  500.593474] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  500.593498] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  500.593522] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  500.593572] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  500.593597] [drm:intel_power_well_disable [i915]] disabling DC off
>[  500.593623] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  500.593641] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  500.594108] [drm:intel_power_well_disable [i915]] disabling always-on
>[  500.594158] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/skl_huc_ver01_07_1398.bin
>[  500.594180] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  500.594376] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/skl_huc_ver01_07_1398.bin succeeded, fw ffff8804a2ed08a8
>[  500.594395] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  500.594666] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880446eb0040
>[  500.595082] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  500.595189] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  500.595306] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  500.596934] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  500.596999] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  500.597051] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  500.597101] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  500.597150] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  500.597193] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  500.597199] [drm] GuC firmware load skipped
>[  500.597819] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  500.597887] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  500.597915] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  500.597942] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  500.597964] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  500.598411] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  500.598480] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.598498] [drm:intel_power_well_enable [i915]] enabling DC off
>[  500.598865] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  500.599603] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-DP-1
>[  500.600401] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-2
>[  500.601221] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-3
>[  500.602300] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card0-DP-4
>[  500.603170] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  500.604383] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  500.607389] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.615848] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.620405] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  500.624308] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.624410] [drm:asle_work [i915]] bclp = 0x80000002
>[  500.624495] [drm:asle_work [i915]] updating opregion backlight 2/255
>[  500.625884] [drm:asle_work [i915]] bclp = 0x800000ff
>[  500.625917] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  500.626915] acpi device:0f: registered as cooling_device13
>[  500.627851] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input22
>[  500.628425] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  500.628426] [drm] DRM_I915_DEBUG enabled
>[  500.628427] [drm] DRM_I915_DEBUG_GEM enabled
>[  500.633563] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.642048] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.642182] [drm:asle_work [i915]] bclp = 0x800000ff
>[  500.642217] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  500.650505] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.658936] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.667360] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.675809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.684239] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.692670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.701100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.709534] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.717963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.726389] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.734816] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.743242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.751669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.760096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.768522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.776948] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.785373] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.793809] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.802235] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.810662] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.819089] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.827516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.835942] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.844369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.852793] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.861219] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.869646] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.869655] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  500.869680] [drm:intel_power_well_disable [i915]] disabling DC off
>[  500.869723] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  500.869795] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  500.870281] [drm:intel_power_well_disable [i915]] disabling always-on
>[  500.870285] [drm:drm_helper_hpd_irq_event] [CONNECTOR:47:DP-1] status updated from unknown to disconnected
>[  500.870317] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  500.870342] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.870365] [drm:intel_power_well_enable [i915]] enabling DC off
>[  500.870822] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  500.870854] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  500.870880] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  500.871795] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  500.873330] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  500.873354] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  500.873391] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  500.873408] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  500.874225] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  500.874948] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  500.877218] [drm:drm_dp_i2c_do_msg] native defer
>[  500.878275] [drm:drm_dp_i2c_do_msg] native defer
>[  500.879691] [drm:drm_dp_i2c_do_msg] native defer
>[  500.880835] [drm:drm_dp_i2c_do_msg] native defer
>[  500.882245] [drm:drm_dp_i2c_do_msg] native defer
>[  500.883306] [drm:drm_dp_i2c_do_msg] native defer
>[  500.884628] [drm:drm_dp_i2c_do_msg] native defer
>[  500.885772] [drm:drm_dp_i2c_do_msg] native defer
>[  500.887227] [drm:drm_dp_i2c_do_msg] native defer
>[  500.888335] [drm:drm_dp_i2c_do_msg] native defer
>[  500.889666] [drm:drm_dp_i2c_do_msg] native defer
>[  500.891377] [drm:drm_dp_i2c_do_msg] native defer
>[  500.892434] [drm:drm_dp_i2c_do_msg] native defer
>[  500.893764] [drm:drm_dp_i2c_do_msg] native defer
>[  500.894904] [drm:drm_dp_i2c_do_msg] native defer
>[  500.896749] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  500.896821] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  500.896840] [drm:intel_power_well_disable [i915]] disabling DC off
>[  500.896858] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  500.896874] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  500.897294] [drm:intel_power_well_disable [i915]] disabling always-on
>[  500.897296] [drm:drm_helper_hpd_irq_event] [CONNECTOR:51:DP-2] status updated from unknown to connected
>[  500.897320] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  500.897337] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.897351] [drm:intel_power_well_enable [i915]] enabling DC off
>[  500.897365] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  500.897384] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  500.897399] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  500.897441] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  500.897462] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  500.897476] [drm:intel_power_well_disable [i915]] disabling DC off
>[  500.897491] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  500.897505] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  500.898035] [drm:intel_power_well_disable [i915]] disabling always-on
>[  500.898041] [drm:drm_helper_hpd_irq_event] [CONNECTOR:56:DP-3] status updated from unknown to disconnected
>[  500.898093] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  500.898116] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.900465] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  500.900488] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  500.902787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  500.902791] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  500.905073] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  500.905095] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  500.907376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  500.907380] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  500.907401] [drm:intel_power_well_disable [i915]] disabling always-on
>[  500.907404] [drm:drm_helper_hpd_irq_event] [CONNECTOR:60:HDMI-A-1] status updated from unknown to disconnected
>[  500.907428] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  500.907448] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.907465] [drm:intel_power_well_enable [i915]] enabling DC off
>[  500.907824] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  500.907848] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  500.907888] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  500.908366] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  500.908691] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  500.908731] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  500.908814] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  500.908834] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  500.909250] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  500.909584] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  500.915922] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  500.916244] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  500.916272] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  500.916291] [drm:intel_power_well_disable [i915]] disabling DC off
>[  500.916310] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  500.916327] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  500.916778] [drm:intel_power_well_disable [i915]] disabling always-on
>[  500.916780] [drm:drm_helper_hpd_irq_event] [CONNECTOR:63:DP-4] status updated from unknown to connected
>[  500.916805] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  500.916824] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.919097] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  500.919118] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  500.921376] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  500.921379] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  500.923638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  500.923657] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  500.925956] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  500.925959] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  500.925980] [drm:intel_power_well_disable [i915]] disabling always-on
>[  500.925982] [drm:drm_helper_hpd_irq_event] [CONNECTOR:67:HDMI-A-2] status updated from unknown to disconnected
>[  500.926110] [drm:drm_setup_crtcs] 
>[  500.926113] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  500.926143] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  500.926177] [drm:intel_power_well_enable [i915]] enabling always-on
>[  500.926197] [drm:intel_power_well_enable [i915]] enabling DC off
>[  500.926523] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  500.934985] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.943444] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.951877] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.960310] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.968741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.977170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.985597] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  500.994030] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.002468] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.010973] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.019415] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.027844] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.036271] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.044700] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.053140] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.061569] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.069996] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.078433] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.086867] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.095293] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.103720] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.112162] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.120589] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.129015] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.137443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.145869] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.154305] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.162742] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.171172] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.179601] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.188029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.196459] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  501.196469] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  501.196493] [drm:intel_power_well_disable [i915]] disabling DC off
>[  501.196515] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  501.196553] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  501.197039] [drm:intel_power_well_disable [i915]] disabling always-on
>[  501.197064] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  501.197068] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  501.197092] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  501.197112] [drm:intel_power_well_enable [i915]] enabling always-on
>[  501.197131] [drm:intel_power_well_enable [i915]] enabling DC off
>[  501.197496] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  501.197516] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  501.197551] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  501.198438] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  501.199976] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  501.199999] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  501.200036] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  501.200053] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  501.200858] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  501.201592] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  501.202383] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  501.202414] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  501.202434] [drm:intel_power_well_disable [i915]] disabling DC off
>[  501.202471] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  501.202487] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  501.202989] [drm:intel_power_well_disable [i915]] disabling always-on
>[  501.203049] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  501.203054] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  501.203057] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  501.203059] [drm:drm_mode_debug_printmodeline] Modeline 70:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  501.203060] [drm:drm_mode_debug_printmodeline] Modeline 76:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  501.203062] [drm:drm_mode_debug_printmodeline] Modeline 71:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  501.203064] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  501.203065] [drm:drm_mode_debug_printmodeline] Modeline 75:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  501.203067] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  501.203068] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  501.203070] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  501.203072] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  501.203074] [drm:drm_mode_debug_printmodeline] Modeline 78:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  501.203075] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  501.203077] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  501.203101] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  501.203121] [drm:intel_power_well_enable [i915]] enabling always-on
>[  501.203138] [drm:intel_power_well_enable [i915]] enabling DC off
>[  501.203442] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  501.203462] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  501.203477] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  501.203538] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  501.203559] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  501.203574] [drm:intel_power_well_disable [i915]] disabling DC off
>[  501.203589] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  501.203602] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  501.204072] [drm:intel_power_well_disable [i915]] disabling always-on
>[  501.204097] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  501.204099] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  501.204141] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  501.204161] [drm:intel_power_well_enable [i915]] enabling always-on
>[  501.206470] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  501.206491] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  501.208799] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  501.208803] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  501.211088] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  501.211111] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  501.213394] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  501.213398] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  501.213420] [drm:intel_power_well_disable [i915]] disabling always-on
>[  501.213422] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  501.213424] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  501.213447] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  501.213467] [drm:intel_power_well_enable [i915]] enabling always-on
>[  501.213485] [drm:intel_power_well_enable [i915]] enabling DC off
>[  501.213843] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  501.214318] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  501.214360] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  501.214840] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  501.215171] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  501.215194] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  501.215214] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  501.215232] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  501.215644] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  501.216001] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  501.216368] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  501.216395] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  501.216432] [drm:intel_power_well_disable [i915]] disabling DC off
>[  501.216449] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  501.216464] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  501.216959] [drm:intel_power_well_disable [i915]] disabling always-on
>[  501.217190] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  501.217192] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  501.217229] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  501.217230] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  501.217234] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  501.217235] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  501.217238] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  501.217239] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  501.217244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  501.217246] [drm:drm_mode_debug_printmodeline] Modeline 82:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  501.217248] [drm:drm_mode_debug_printmodeline] Modeline 83:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  501.217249] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  501.217251] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  501.217252] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  501.217254] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  501.217255] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  501.217257] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  501.217258] [drm:drm_mode_debug_printmodeline] Modeline 101:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  501.217260] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  501.217261] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  501.217263] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  501.217264] [drm:drm_mode_debug_printmodeline] Modeline 88:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  501.217266] [drm:drm_mode_debug_printmodeline] Modeline 87:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  501.217267] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  501.217268] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  501.217288] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  501.217289] [drm:drm_mode_debug_printmodeline] Modeline 91:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  501.217290] [drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  501.217292] [drm:drm_mode_debug_printmodeline] Modeline 116:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  501.217293] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  501.217295] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  501.217296] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  501.217297] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  501.217299] [drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  501.217300] [drm:drm_mode_debug_printmodeline] Modeline 107:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  501.217302] [drm:drm_mode_debug_printmodeline] Modeline 122:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  501.217303] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  501.217304] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  501.217306] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  501.217307] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  501.217308] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  501.217310] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  501.217333] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  501.217351] [drm:intel_power_well_enable [i915]] enabling always-on
>[  501.219636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  501.219659] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  501.220680] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  501.220683] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  501.221787] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  501.221804] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  501.224084] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  501.224088] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  501.224109] [drm:intel_power_well_disable [i915]] disabling always-on
>[  501.224111] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  501.224120] [drm:drm_setup_crtcs] connector 47 enabled? no
>[  501.224121] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  501.224122] [drm:drm_setup_crtcs] connector 56 enabled? no
>[  501.224123] [drm:drm_setup_crtcs] connector 60 enabled? no
>[  501.224124] [drm:drm_setup_crtcs] connector 63 enabled? yes
>[  501.224125] [drm:drm_setup_crtcs] connector 67 enabled? no
>[  501.224150] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  501.224171] [drm:intel_fb_initial_config [i915]] connector DP-2 has no encoder or crtc, skipping
>[  501.224190] [drm:intel_fb_initial_config [i915]] connector DP-3 not enabled, skipping
>[  501.224207] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 not enabled, skipping
>[  501.224223] [drm:intel_fb_initial_config [i915]] connector DP-4 has no encoder or crtc, skipping
>[  501.224238] [drm:intel_fb_initial_config [i915]] connector HDMI-A-2 not enabled, skipping
>[  501.224253] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  501.224268] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  501.224282] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  501.224286] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  501.224287] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  501.224288] [drm:drm_setup_crtcs] found mode 1920x1200
>[  501.224289] [drm:drm_setup_crtcs] looking for cmdline mode on connector 63
>[  501.224290] [drm:drm_setup_crtcs] looking for preferred mode on connector 63 0
>[  501.224290] [drm:drm_setup_crtcs] found mode 3840x2160
>[  501.224291] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  501.224309] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 31 (0,0)
>[  501.224312] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 38 (0,0)
>[  501.224334] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  501.239999] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000
>[  501.240472] fbcon: inteldrmfb (fb0) is primary device
>[  501.240967] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  501.240992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  501.241017] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  501.241041] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  501.241060] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  501.241082] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  501.241103] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  501.241122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  501.241140] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  501.241156] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  501.241171] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  501.241174] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  501.241189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  501.241191] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  501.241206] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  501.241221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  501.241235] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  501.241249] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  501.241262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  501.241283] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  501.241298] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  501.241312] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  501.241325] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  501.241339] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  501.241360] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  501.241376] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  501.241398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  501.241420] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  501.241438] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  501.241456] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  501.241474] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  501.241489] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  501.241504] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  501.241519] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  501.241532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  501.241535] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  501.241548] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  501.241550] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  501.241564] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  501.241577] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  501.241590] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  501.241603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  501.241616] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  501.241635] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  501.241649] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  501.241663] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  501.241677] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  501.241690] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  501.241708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  501.241751] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  501.241772] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  501.241788] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  501.241806] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  501.241822] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  501.241838] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  501.242003] [drm:intel_power_well_enable [i915]] enabling always-on
>[  501.242021] [drm:intel_power_well_enable [i915]] enabling DC off
>[  501.242319] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  501.242345] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  501.242363] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  501.242407] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  501.242424] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  501.242443] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  501.242459] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  501.242485] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  501.242964] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  501.242984] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  501.243010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  501.243032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  501.243051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  501.243069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  501.243085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  501.243101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  501.243117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  501.243157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  501.243173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  501.243215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  501.243235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  501.243255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  501.243293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  501.243333] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  501.243361] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  501.243387] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  501.243413] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  501.243466] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  501.243486] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  501.246770] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  501.248128] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  501.248167] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  501.248187] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  501.248206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  501.253403] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  501.253444] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  501.258624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  501.261137] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b55d28
>[  501.261789] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  501.261853] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  501.261874] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  501.261947] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  501.261967] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  501.265232] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  501.265256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  501.265276] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  501.265297] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  501.265970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  501.265989] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  501.266006] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  501.266668] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  501.266686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  501.266702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  501.267376] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  501.267395] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  501.268366] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  501.270639] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff880445b56fc8
>[  501.271215] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  501.271246] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  501.271265] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  501.271323] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  501.288080] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  501.288107] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  501.288150] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  501.288197] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  501.288221] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  501.288261] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  501.288406] Console: switching to colour frame buffer device 240x75
>[  501.309312] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  501.319104] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  501.320222] Console: switching to colour dummy device 80x25
>[  501.344675] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  501.344679] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  501.344681] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  501.344683] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  501.344685] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  501.344686] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  501.763174] [drm] RC6 on
>[  502.404442] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  502.404459] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  502.404475] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  502.404489] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  502.404504] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  502.404517] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  502.404542] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  502.404555] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  502.412381] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input23
>[  502.413817] input: HDA Intel PCH Speaker as /devices/pci0000:00/0000:00:1f.3/sound/card0/input24
>[  502.414444] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input25
>[  502.415044] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input26
>[  502.415648] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input27
>[  502.416335] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input28
>[  502.417090] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input29
>[  502.536719] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  502.536761] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  502.536785] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  502.536808] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  502.536829] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  502.536850] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  502.536877] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  502.536898] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  502.576965] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  502.577091] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  502.581712] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  502.581815] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  502.581843] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  502.581886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  502.581904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  502.581919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  502.581932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  502.581945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  502.581957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  502.581970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  502.581982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  502.581994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  502.582007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  502.582019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  502.582031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  502.582042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  502.582055] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  502.582071] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  502.582086] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  502.582099] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  502.582113] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  502.588029] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  502.588045] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  502.588072] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  502.588090] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  502.588204] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  502.588259] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  502.588312] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  502.605264] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  502.605298] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  502.605355] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  502.607533] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  502.607566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  502.607597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  502.607625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  502.607650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  502.607675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  502.607699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  502.607783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  502.607820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  502.607851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  502.607887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  502.607926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  502.607957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  502.607991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  502.608026] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  502.608069] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  502.608111] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  502.608149] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  502.608187] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  502.608241] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  502.608277] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  502.608312] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  502.608363] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  502.608416] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  502.608457] [drm:intel_power_well_disable [i915]] disabling DC off
>[  502.608493] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  502.608523] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  502.609015] [drm:intel_power_well_disable [i915]] disabling always-on
>[  502.618836] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  502.622804] [drm:intel_power_well_enable [i915]] enabling always-on
>[  502.622849] [drm:intel_power_well_enable [i915]] enabling DC off
>[  502.623165] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  502.623219] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  502.623260] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  502.623382] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  502.623423] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  502.623461] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  502.623501] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  502.623539] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  502.623578] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  502.623615] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  502.623654] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  502.795214] Setting dangerous option inject_load_failure - tainting kernel
>[  502.806283] [drm] Injecting failure at checkpoint 1 [i915_driver_init_early:815]
>[  502.806315] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  502.813024] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  502.824760] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  502.824762] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  502.824763] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  502.824764] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  502.824764] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  502.824765] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  502.875271] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  502.880036] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  502.895794] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input30
>[  502.898302] input: HDA Intel PCH Speaker as /devices/pci0000:00/0000:00:1f.3/sound/card0/input31
>[  502.899595] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input32
>[  503.057037] Setting dangerous option inject_load_failure - tainting kernel
>[  503.067537] [drm:i915_driver_load [i915]] Found SunrisePoint PCH
>[  503.067562] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  503.068758] [drm:intel_device_info_dump [i915]] i915 device info: platform=SKYLAKE gen=9 pciid=0x193b rev=0x09
>[  503.068777] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  503.068793] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  503.068809] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  503.068824] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  503.068839] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  503.068854] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  503.068868] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  503.068882] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  503.068896] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  503.068910] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  503.068924] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  503.068937] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  503.068951] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  503.068965] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  503.068978] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  503.068991] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  503.069004] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  503.069017] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  503.069031] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  503.069044] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  503.069057] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  503.069070] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  503.069083] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  503.069096] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  503.069108] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  503.069121] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  503.069134] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  503.069147] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  503.069160] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  503.069173] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  503.069186] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  503.069199] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  503.069212] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  503.069224] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  503.069226] [drm] Injecting failure at checkpoint 2 [i915_driver_init_mmio:948]
>[  503.100946] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  503.114975] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  503.127198] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  503.127201] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  503.127202] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  503.127204] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  503.127205] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  503.127206] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  503.182897] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  503.188281] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  503.202227] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input33
>[  503.204138] input: HDA Intel PCH Speaker as /devices/pci0000:00/0000:00:1f.3/sound/card0/input34
>[  503.205203] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input35
>[  504.359124] Setting dangerous option inject_load_failure - tainting kernel
>[  504.371123] [drm:i915_driver_load [i915]] Found SunrisePoint PCH
>[  504.371149] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  504.372359] [drm:intel_device_info_dump [i915]] i915 device info: platform=SKYLAKE gen=9 pciid=0x193b rev=0x09
>[  504.372378] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  504.372396] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  504.372413] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  504.372429] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  504.372444] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  504.372459] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  504.372475] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  504.372490] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  504.372505] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  504.372519] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  504.372534] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  504.372548] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  504.372562] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  504.372576] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  504.372590] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  504.372604] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  504.372617] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  504.372631] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  504.372644] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  504.372658] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  504.372672] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  504.372685] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  504.372698] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  504.372716] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  504.372744] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  504.372759] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  504.372774] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  504.372789] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  504.372803] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  504.372817] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  504.372831] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  504.372845] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  504.372860] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  504.372874] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  504.372901] [drm] Found 128MB of eDRAM
>[  504.375194] [drm] Injecting failure at checkpoint 3 [i915_driver_init_hw:1012]
>[  504.412250] i915 0000:00:02.0: [drm:i915_driver_load [i915]] Device initialization failed (-19)
>[  504.424888] [IGT] drv_module_reload: exiting, ret=0
>[  504.429909] snd_hda_intel 0000:00:1f.3: failed to add i915 component master (-19)
>[  504.443526] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  504.443529] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  504.443531] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  504.443533] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  504.443534] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  504.443536] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  504.571021] [IGT] drv_module_reload: executing
>[  504.572128] [IGT] drv_module_reload: starting subtest basic-reload-final
>[  506.497402] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  506.500475] snd_hda_codec_hdmi hdaudioC0D2: No i915 binding for Intel HDMI/DP codec
>[  506.509236] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input36
>[  506.510908] input: HDA Intel PCH Speaker as /devices/pci0000:00/0000:00:1f.3/sound/card0/input37
>[  506.511585] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input38
>[  506.678173] [drm:i915_driver_load [i915]] Found SunrisePoint PCH
>[  506.678200] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  506.679516] [drm:intel_device_info_dump [i915]] i915 device info: platform=SKYLAKE gen=9 pciid=0x193b rev=0x09
>[  506.679544] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  506.679570] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  506.679595] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  506.679619] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  506.679642] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  506.679665] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  506.679687] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  506.679709] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  506.679756] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  506.679780] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  506.679803] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  506.679828] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  506.679853] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  506.679877] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  506.679901] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  506.679924] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  506.679948] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  506.679972] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  506.679995] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  506.680018] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  506.680041] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  506.680065] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  506.680087] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  506.680109] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  506.680131] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  506.680154] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  506.680178] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  506.680201] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  506.680223] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  506.680264] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  506.680286] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  506.680309] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  506.680331] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  506.680354] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  506.680383] [drm] Found 128MB of eDRAM
>[  506.682794] [drm:intel_device_info_runtime_init [i915]] slice mask: 0007
>[  506.682815] [drm:intel_device_info_runtime_init [i915]] slice total: 3
>[  506.682832] [drm:intel_device_info_runtime_init [i915]] subslice total: 9
>[  506.682849] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  506.682865] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  506.682881] [drm:intel_device_info_runtime_init [i915]] EU total: 72
>[  506.682896] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  506.682917] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  506.682938] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  506.682953] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  506.682970] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  506.682988] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  506.683018] [drm] Memory usable by graphics device = 4096M
>[  506.683042] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  506.683069] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  506.683077] [drm] Replacing VGA console driver
>[  506.683157] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  506.683284] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  506.683340] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  506.683369] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  506.688839] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  506.688863] [drm:intel_opregion_setup [i915]] ASLE supported
>[  506.688884] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  506.688902] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  506.689090] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[  506.689096] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  506.689097] [drm] Driver supports precise vblank timestamp query.
>[  506.689121] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  506.689142] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 206
>[  506.689162] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  506.689179] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  506.690797] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  506.690831] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  506.690860] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  506.690892] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  506.690897] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  506.690915] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  506.690932] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  506.690948] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  506.690963] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 206 not known; assuming 38
>[  506.690981] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  506.690997] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  506.691011] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  506.691025] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  506.691039] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  506.691053] [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  506.691066] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8
>[  506.691329] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  506.691377] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  506.691399] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  506.691456] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  506.691479] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  506.691504] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  506.693837] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  506.693861] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  506.695833] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  506.695870] [drm:intel_power_well_enable [i915]] enabling always-on
>[  506.695890] [drm:intel_power_well_enable [i915]] enabling DC off
>[  506.695909] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  506.695932] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  506.695950] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  506.695967] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  506.695984] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  506.696000] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  506.696018] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  506.696054] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_26.bin
>[  506.697406] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_26.bin (v1.26)
>[  506.698438] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  506.698475] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  506.698502] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  506.698527] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  506.698551] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  506.698574] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  506.698597] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  506.698619] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  506.698642] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  506.698678] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  506.699061] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  506.699423] [drm:intel_dp_init_connector [i915]] Adding DP connector on port A
>[  506.699521] [drm:intel_dp_init_connector [i915]] using AUX A for port A (platform default)
>[  506.699618] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  506.699667] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  506.699753] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  506.710390] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.718825] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.727257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.735688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.744150] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.752584] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.761013] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.769443] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.777872] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.786299] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.794741] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.803168] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.811598] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.820101] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.828529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.836956] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.845382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.853810] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.862238] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  506.862966] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  506.863780] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  506.864465] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  506.864493] [drm:lspcon_init [i915]] LSPCON detected
>[  506.865226] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  506.880696] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  506.881854] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  506.882917] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  506.883032] [drm:lspcon_init [i915]] Success: LSPCON init
>[  506.883127] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  506.883252] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  506.883372] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  506.883544] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  506.883656] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  506.883865] [drm:intel_dp_init_connector [i915]] Adding DP connector on port D
>[  506.883992] [drm:intel_dp_init_connector [i915]] using AUX D for port D (VBT)
>[  506.884260] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port D
>[  506.884413] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT)
>[  506.884576] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  506.884662] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  506.884740] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  506.884879] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  506.884962] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  506.885030] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  506.885098] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  506.885170] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  506.885260] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  506.885341] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  506.885424] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  506.885505] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  506.885577] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  506.885631] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  506.885681] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  506.885732] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  506.885836] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  506.885892] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  506.885943] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  506.885999] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  506.886063] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  506.886126] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  506.886198] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  506.886280] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  506.886373] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  506.886462] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  506.886568] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  506.886660] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  506.886750] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  506.886862] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  506.886876] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  506.886939] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  506.886948] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  506.887010] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  506.887064] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  506.887121] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  506.887172] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.887225] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  506.887297] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  506.887358] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  506.887409] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  506.887465] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  506.887514] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  506.887579] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  506.887645] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  506.887718] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  506.887841] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  506.887854] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  506.887929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  506.887944] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  506.888023] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  506.888096] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  506.888169] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  506.888231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.888280] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  506.888352] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  506.888406] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  506.888456] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  506.888504] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  506.888552] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  506.888608] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  506.888655] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  506.888705] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  506.888794] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  506.888805] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  506.888856] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  506.888866] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  506.888914] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  506.888967] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  506.889015] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  506.889068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  506.889115] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  506.889190] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  506.889245] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  506.889296] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  506.889345] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  506.889397] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  506.889465] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  506.889749] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  506.889960] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  506.890064] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  506.890161] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  506.890254] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  506.890328] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  506.890390] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  506.890448] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  506.890503] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  506.890620] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  506.890677] [drm:intel_power_well_disable [i915]] disabling DC off
>[  506.890737] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  506.890837] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  506.891327] [drm:intel_power_well_disable [i915]] disabling always-on
>[  506.891461] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/skl_huc_ver01_07_1398.bin
>[  506.891567] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  506.892226] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/skl_huc_ver01_07_1398.bin succeeded, fw ffff8804a4323cc8
>[  506.892298] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  506.893381] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880445d40040
>[  506.893948] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  506.894343] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  506.894626] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  506.898916] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  506.899128] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  506.899302] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  506.899469] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  506.899632] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  506.899761] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  506.899832] [drm] GuC firmware load skipped
>[  506.901194] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  506.901740] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  506.901912] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  506.901994] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  506.902068] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  506.906475] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-DP-1
>[  506.909164] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-2
>[  506.911151] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-3
>[  506.913539] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card0-DP-4
>[  506.915364] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  506.917170] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  506.948733] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  506.956932] [drm:asle_work [i915]] bclp = 0x80000002
>[  506.957101] [drm:asle_work [i915]] updating opregion backlight 2/255
>[  506.960292] [drm:asle_work [i915]] bclp = 0x800000ff
>[  506.960369] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  506.962046] acpi device:0f: registered as cooling_device13
>[  506.964258] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input39
>[  506.966023] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  506.966026] [drm] DRM_I915_DEBUG enabled
>[  506.966028] [drm] DRM_I915_DEBUG_GEM enabled
>[  506.966037] [drm:drm_setup_crtcs] 
>[  506.966046] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  506.966138] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  506.966239] [drm:intel_power_well_enable [i915]] enabling always-on
>[  506.966304] [drm:intel_power_well_enable [i915]] enabling DC off
>[  506.966659] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  506.975451] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  506.984091] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  506.992685] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.001265] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.009765] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.018210] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.026657] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.035088] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.043516] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.051943] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.060369] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.068794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.077220] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.085738] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.094164] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.102590] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.111016] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.119441] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.127866] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.136289] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.144714] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.153163] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.161588] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.170014] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.173570] [drm:asle_work [i915]] bclp = 0x800000ff
>[  507.173604] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  507.178471] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.186913] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.195344] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.203772] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.212203] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.220632] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.229060] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.237488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  507.237498] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  507.237522] [drm:intel_power_well_disable [i915]] disabling DC off
>[  507.237563] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  507.237582] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  507.238044] [drm:intel_power_well_disable [i915]] disabling always-on
>[  507.238049] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] status updated from unknown to disconnected
>[  507.238062] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  507.238065] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  507.238115] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  507.238142] [drm:intel_power_well_enable [i915]] enabling always-on
>[  507.238167] [drm:intel_power_well_enable [i915]] enabling DC off
>[  507.238658] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  507.239076] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  507.239120] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  507.240055] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  507.241619] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  507.241643] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  507.241664] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  507.241702] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  507.242574] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  507.243295] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  507.245560] [drm:drm_dp_i2c_do_msg] native defer
>[  507.246686] [drm:drm_dp_i2c_do_msg] native defer
>[  507.248100] [drm:drm_dp_i2c_do_msg] native defer
>[  507.249806] [drm:drm_dp_i2c_do_msg] native defer
>[  507.250933] [drm:drm_dp_i2c_do_msg] native defer
>[  507.252341] [drm:drm_dp_i2c_do_msg] native defer
>[  507.253421] [drm:drm_dp_i2c_do_msg] native defer
>[  507.254754] [drm:drm_dp_i2c_do_msg] native defer
>[  507.255897] [drm:drm_dp_i2c_do_msg] native defer
>[  507.257304] [drm:drm_dp_i2c_do_msg] native defer
>[  507.258364] [drm:drm_dp_i2c_do_msg] native defer
>[  507.259717] [drm:drm_dp_i2c_do_msg] native defer
>[  507.261417] [drm:drm_dp_i2c_do_msg] native defer
>[  507.262488] [drm:drm_dp_i2c_do_msg] native defer
>[  507.264317] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  507.264369] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  507.264387] [drm:intel_power_well_disable [i915]] disabling DC off
>[  507.264406] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  507.264422] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  507.264861] [drm:intel_power_well_disable [i915]] disabling always-on
>[  507.264864] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] status updated from unknown to connected
>[  507.264958] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  507.264963] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  507.264965] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.264968] [drm:drm_mode_debug_printmodeline] Modeline 70:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  507.264970] [drm:drm_mode_debug_printmodeline] Modeline 76:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  507.264972] [drm:drm_mode_debug_printmodeline] Modeline 71:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  507.264973] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  507.264975] [drm:drm_mode_debug_printmodeline] Modeline 75:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  507.264976] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  507.264978] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  507.264979] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  507.264982] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  507.264983] [drm:drm_mode_debug_printmodeline] Modeline 78:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  507.264985] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  507.264987] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  507.265013] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  507.265051] [drm:intel_power_well_enable [i915]] enabling always-on
>[  507.265068] [drm:intel_power_well_enable [i915]] enabling DC off
>[  507.265360] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  507.265380] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  507.265395] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  507.265457] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  507.265496] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  507.265511] [drm:intel_power_well_disable [i915]] disabling DC off
>[  507.265528] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  507.265541] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  507.265991] [drm:intel_power_well_disable [i915]] disabling always-on
>[  507.265993] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] status updated from unknown to disconnected
>[  507.265995] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  507.265997] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  507.266053] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  507.266074] [drm:intel_power_well_enable [i915]] enabling always-on
>[  507.268429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  507.268454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  507.270732] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  507.270750] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  507.273014] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  507.273038] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  507.275317] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  507.275321] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  507.275344] [drm:intel_power_well_disable [i915]] disabling always-on
>[  507.275346] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] status updated from unknown to disconnected
>[  507.275348] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  507.275350] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  507.275375] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  507.275396] [drm:intel_power_well_enable [i915]] enabling always-on
>[  507.275414] [drm:intel_power_well_enable [i915]] enabling DC off
>[  507.275705] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  507.275756] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  507.275780] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  507.276294] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  507.276636] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  507.276659] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  507.276696] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  507.276714] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  507.277151] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  507.277475] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  507.283746] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  507.284068] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  507.284096] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  507.284115] [drm:intel_power_well_disable [i915]] disabling DC off
>[  507.284134] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  507.284151] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  507.284572] [drm:intel_power_well_disable [i915]] disabling always-on
>[  507.284574] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] status updated from unknown to connected
>[  507.284750] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  507.284753] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  507.284810] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  507.284812] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  507.284818] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  507.284820] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  507.284825] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  507.284827] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  507.284835] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  507.284838] [drm:drm_mode_debug_printmodeline] Modeline 82:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  507.284840] [drm:drm_mode_debug_printmodeline] Modeline 83:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  507.284843] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  507.284845] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  507.284848] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  507.284851] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  507.284854] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  507.284856] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  507.284859] [drm:drm_mode_debug_printmodeline] Modeline 101:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  507.284861] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  507.284864] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  507.284867] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  507.284870] [drm:drm_mode_debug_printmodeline] Modeline 88:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  507.284873] [drm:drm_mode_debug_printmodeline] Modeline 87:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  507.284875] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  507.284878] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  507.284881] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  507.284883] [drm:drm_mode_debug_printmodeline] Modeline 91:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  507.284887] [drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  507.284889] [drm:drm_mode_debug_printmodeline] Modeline 116:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  507.284892] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  507.284894] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  507.284897] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  507.284900] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  507.284902] [drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  507.284905] [drm:drm_mode_debug_printmodeline] Modeline 107:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  507.284908] [drm:drm_mode_debug_printmodeline] Modeline 122:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  507.284911] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  507.284913] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  507.284916] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  507.284919] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  507.284922] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  507.284924] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  507.284957] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  507.284987] [drm:intel_power_well_enable [i915]] enabling always-on
>[  507.287245] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  507.287266] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  507.289540] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  507.289545] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  507.291826] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  507.291851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  507.294129] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  507.294133] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  507.294157] [drm:intel_power_well_disable [i915]] disabling always-on
>[  507.294159] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] status updated from unknown to disconnected
>[  507.294161] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  507.294171] [drm:drm_setup_crtcs] connector 47 enabled? no
>[  507.294172] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  507.294173] [drm:drm_setup_crtcs] connector 56 enabled? no
>[  507.294174] [drm:drm_setup_crtcs] connector 60 enabled? no
>[  507.294175] [drm:drm_setup_crtcs] connector 63 enabled? yes
>[  507.294176] [drm:drm_setup_crtcs] connector 67 enabled? no
>[  507.294204] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  507.294227] [drm:intel_fb_initial_config [i915]] connector DP-2 has no encoder or crtc, skipping
>[  507.294247] [drm:intel_fb_initial_config [i915]] connector DP-3 not enabled, skipping
>[  507.294266] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 not enabled, skipping
>[  507.294283] [drm:intel_fb_initial_config [i915]] connector DP-4 has no encoder or crtc, skipping
>[  507.294299] [drm:intel_fb_initial_config [i915]] connector HDMI-A-2 not enabled, skipping
>[  507.294315] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  507.294331] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  507.294346] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  507.294351] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  507.294352] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  507.294353] [drm:drm_setup_crtcs] found mode 1920x1200
>[  507.294354] [drm:drm_setup_crtcs] looking for cmdline mode on connector 63
>[  507.294355] [drm:drm_setup_crtcs] looking for preferred mode on connector 63 0
>[  507.294356] [drm:drm_setup_crtcs] found mode 3840x2160
>[  507.294357] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  507.294376] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 31 (0,0)
>[  507.294379] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 38 (0,0)
>[  507.294403] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  507.310374] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000
>[  507.310814] fbcon: inteldrmfb (fb0) is primary device
>[  507.311216] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  507.311239] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  507.311264] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  507.311288] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  507.311306] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  507.311329] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.311350] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  507.311369] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  507.311386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  507.311403] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  507.311419] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  507.311422] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.311437] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  507.311439] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  507.311455] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  507.311469] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  507.311483] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  507.311497] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.311511] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  507.311531] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  507.311546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  507.311561] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  507.311574] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  507.311588] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  507.311609] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  507.311626] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  507.311648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  507.311670] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  507.311688] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  507.311707] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  507.311736] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  507.311752] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  507.311767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  507.311781] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  507.311795] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  507.311797] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  507.311811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  507.311813] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  507.311827] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  507.311840] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  507.311853] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  507.311866] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  507.311879] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  507.311898] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  507.311912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  507.311926] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  507.311939] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  507.311952] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  507.311971] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  507.311994] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  507.312012] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  507.312028] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  507.312046] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  507.312064] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  507.312080] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  507.312253] [drm:intel_power_well_enable [i915]] enabling always-on
>[  507.312271] [drm:intel_power_well_enable [i915]] enabling DC off
>[  507.312568] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  507.312595] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  507.312613] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  507.312657] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  507.312674] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  507.312694] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  507.312710] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  507.312749] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  507.315045] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  507.315068] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  507.315097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  507.315121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  507.315142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  507.315161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  507.315179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  507.315196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  507.315214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  507.315230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  507.315246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  507.315261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  507.315277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  507.315292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  507.315307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  507.315326] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  507.315346] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  507.315366] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  507.315384] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  507.315443] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  507.315463] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  507.318762] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  507.320116] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  507.320137] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  507.320156] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  507.320176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  507.325336] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  507.325357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  507.330516] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  507.332926] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ede8008
>[  507.333529] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  507.333601] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  507.333623] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  507.333695] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  507.333715] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  507.336975] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  507.336999] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  507.337019] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  507.337039] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  507.337709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  507.337749] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  507.337767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  507.338425] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  507.338443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  507.338460] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  507.339118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  507.339137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  507.340104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  507.342377] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff88049ededd28
>[  507.342953] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  507.342984] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  507.343004] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  507.343062] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  507.359858] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  507.359892] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  507.359943] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  507.359998] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  507.360027] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  507.360073] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  507.360239] Console: switching to colour frame buffer device 240x75
>[  507.390083] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  507.411718] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  507.431419] [drm] RC6 on
>[  507.446674] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  507.446683] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  507.446689] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  507.446693] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  507.446698] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  507.446731] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[  507.801378] [IGT] drv_module_reload: exiting, ret=0
>[  507.980837] Console: switching to colour dummy device 80x25
>[  507.981136] [IGT] gvt_basic: executing
>[  508.520124] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  508.520141] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  508.520155] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  508.520170] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  508.520183] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  508.520195] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  508.520217] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  508.520229] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  508.529360] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input40
>[  508.531230] input: HDA Intel PCH Speaker as /devices/pci0000:00/0000:00:1f.3/sound/card0/input41
>[  508.531973] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input42
>[  508.532618] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input43
>[  508.533192] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input44
>[  508.534046] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input45
>[  508.534662] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input46
>[  508.655766] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  508.655802] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  508.655830] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  508.655852] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  508.655875] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  508.655896] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[  508.655922] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  508.655942] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[  508.701940] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  508.702132] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  508.720034] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  508.720242] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[  508.720343] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  508.720485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  508.720544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  508.720599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  508.720647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  508.720693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  508.720738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  508.720868] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  508.720922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  508.720974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  508.721022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  508.721069] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  508.721118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  508.721165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  508.721218] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  508.721279] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  508.721337] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  508.721391] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  508.721447] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  508.726591] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  508.726646] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  508.726736] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  508.726882] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  508.727393] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  508.727588] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[  508.727697] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  508.745089] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[  508.745183] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[  508.745350] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  508.746937] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  508.746997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  508.747059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  508.747115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  508.747166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  508.747215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  508.747260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  508.747307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  508.747349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  508.747392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  508.747434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  508.747483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  508.747525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  508.747567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  508.747616] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  508.747673] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  508.747726] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  508.747834] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  508.747891] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  508.747972] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  508.748025] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  508.748077] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  508.748159] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  508.748268] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  508.748354] [drm:intel_power_well_disable [i915]] disabling DC off
>[  508.748428] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  508.748493] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  508.749029] [drm:intel_power_well_disable [i915]] disabling always-on
>[  508.749962] [drm:intel_runtime_pm_get_noresume [i915]] RPM wakelock ref not held during HW access
>[  508.794974] [drm:intel_uncore_forcewake_get [i915]] RPM wakelock ref not held during HW access
>[  508.798001] [drm:intel_power_well_enable [i915]] enabling always-on
>[  508.798021] [drm:intel_power_well_enable [i915]] enabling DC off
>[  508.798312] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  508.798337] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  508.798356] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  508.798411] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  508.798430] [drm:skl_set_power_well [i915]] Enabling DDI A/E power well
>[  508.798448] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  508.798467] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  508.798484] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  508.798502] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[  508.798519] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  508.798537] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  508.946469] [drm:i915_driver_load [i915]] Found SunrisePoint PCH
>[  508.946496] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[  508.947773] [drm:intel_device_info_dump [i915]] i915 device info: platform=SKYLAKE gen=9 pciid=0x193b rev=0x09
>[  508.947793] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[  508.947811] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[  508.947827] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[  508.947844] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[  508.947859] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[  508.947875] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[  508.947890] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[  508.947905] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[  508.947921] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[  508.947935] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[  508.947950] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[  508.947964] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[  508.947978] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[  508.947992] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[  508.948006] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[  508.948020] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[  508.948034] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[  508.948048] [drm:intel_device_info_dump [i915]] i915 device info: has_hw_contexts: yes
>[  508.948062] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[  508.948076] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[  508.948089] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[  508.948103] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[  508.948117] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[  508.948130] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[  508.948144] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[  508.948157] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[  508.948171] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[  508.948184] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[  508.948198] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[  508.948214] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[  508.948235] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[  508.948274] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[  508.948294] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[  508.948313] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[  508.948344] [drm] Found 128MB of eDRAM
>[  508.950758] [drm:intel_device_info_runtime_init [i915]] slice mask: 0007
>[  508.950785] [drm:intel_device_info_runtime_init [i915]] slice total: 3
>[  508.950809] [drm:intel_device_info_runtime_init [i915]] subslice total: 9
>[  508.950833] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[  508.950856] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[  508.950880] [drm:intel_device_info_runtime_init [i915]] EU total: 72
>[  508.950902] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[  508.950925] [drm:intel_device_info_runtime_init [i915]] has slice power gating: y
>[  508.950946] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[  508.950967] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[  508.950993] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[  508.951017] [drm:i915_driver_load [i915]] use GPU sempahores? no
>[  508.951054] [drm] Memory usable by graphics device = 4096M
>[  508.951084] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[  508.951110] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[  508.951119] [drm] Replacing VGA console driver
>[  508.951198] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[  508.951324] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x3ae2b018
>[  508.951380] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[  508.951407] [drm:intel_opregion_setup [i915]] SWSCI supported
>[  508.956917] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[  508.956942] [drm:intel_opregion_setup [i915]] ASLE supported
>[  508.956963] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[  508.956982] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[  508.957168] [drm:intel_gvt_init [i915]] Not in host or MPT modules not found
>[  508.957174] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[  508.957174] [drm] Driver supports precise vblank timestamp query.
>[  508.957199] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[  508.957220] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 206
>[  508.957240] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[  508.957257] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[  508.959383] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[  508.959411] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[  508.959433] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[  508.959459] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[  508.959463] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  508.959482] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[  508.959501] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[  508.959518] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[  508.959535] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 206 not known; assuming 38
>[  508.959554] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[  508.959571] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  508.959587] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[  508.959602] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  508.959617] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[  508.959632] [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[  508.959647] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8
>[  508.959980] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[  508.960029] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[  508.960052] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  508.960105] [drm:intel_power_well_enable [i915]] enabling power well 1
>[  508.960129] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[  508.960154] [drm:skl_init_cdclk [i915]] Sanitizing cdclk programmed by pre-os
>[  508.962711] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[  508.962749] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[  508.964838] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  508.964874] [drm:intel_power_well_enable [i915]] enabling always-on
>[  508.964893] [drm:intel_power_well_enable [i915]] enabling DC off
>[  508.964911] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  508.964939] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  508.964960] [drm:intel_power_well_enable [i915]] enabling DDI A/E power well
>[  508.964977] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  508.964992] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[  508.965008] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  508.965024] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[  508.965059] [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_26.bin
>[  508.966382] [drm] Finished loading DMC firmware i915/skl_dmc_ver1_26.bin (v1.26)
>[  508.967380] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[  508.967415] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[  508.967442] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[  508.967466] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[  508.967489] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[  508.967512] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[  508.967534] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[  508.967555] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[  508.967577] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[  508.967612] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[  508.967985] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  508.968345] [drm:intel_dp_init_connector [i915]] Adding DP connector on port A
>[  508.968439] [drm:intel_dp_init_connector [i915]] using AUX A for port A (platform default)
>[  508.968534] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[  508.968579] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[  508.968640] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[  508.979294] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  508.987737] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  508.996170] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.004600] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.013029] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.021543] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.029972] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.038401] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.046829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.055257] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.063688] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.072144] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.080572] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.089093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.097522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.105949] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.114377] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.122805] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.131230] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7c1003ff
>[  509.131958] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  509.132772] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[  509.133460] [drm:drm_dp_dual_mode_detect] DP dual mode adaptor ID: a8 (err 0)
>[  509.133490] [drm:lspcon_init [i915]] LSPCON detected
>[  509.134216] [drm:lspcon_wait_mode [i915]] Waiting for LSPCON mode PCON to settle
>[  509.149814] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  509.150772] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  509.151751] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  509.151864] [drm:lspcon_init [i915]] Success: LSPCON init
>[  509.151930] [drm:intel_ddi_init [i915]] LSPCON init success on port B
>[  509.152053] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[  509.152179] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[  509.152306] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[  509.152391] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[  509.152495] [drm:intel_dp_init_connector [i915]] Adding DP connector on port D
>[  509.152572] [drm:intel_dp_init_connector [i915]] using AUX D for port D (VBT)
>[  509.152697] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port D
>[  509.152829] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT)
>[  509.153016] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:31:pipe A] hw state readout: disabled
>[  509.153111] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:38:pipe B] hw state readout: disabled
>[  509.153187] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe C] hw state readout: disabled
>[  509.153244] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[  509.153296] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[  509.153346] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[  509.153394] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[  509.153442] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:46:DDI A] hw state readout: disabled, pipe A
>[  509.153489] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DDI B] hw state readout: disabled, pipe A
>[  509.153530] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:52:DP-MST A] hw state readout: disabled, pipe A
>[  509.153572] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:53:DP-MST B] hw state readout: disabled, pipe B
>[  509.153612] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:54:DP-MST C] hw state readout: disabled, pipe C
>[  509.153656] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI C] hw state readout: disabled, pipe A
>[  509.153695] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[  509.153735] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[  509.153808] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST C] hw state readout: disabled, pipe C
>[  509.153857] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DDI D] hw state readout: disabled, pipe A
>[  509.153898] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:64:DP-MST A] hw state readout: disabled, pipe A
>[  509.153940] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:65:DP-MST B] hw state readout: disabled, pipe B
>[  509.153979] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DP-MST C] hw state readout: disabled, pipe C
>[  509.154026] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:47:DP-1] hw state readout: disabled
>[  509.154074] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:51:DP-2] hw state readout: disabled
>[  509.154122] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-3] hw state readout: disabled
>[  509.154170] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:HDMI-A-1] hw state readout: disabled
>[  509.154236] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:63:DP-4] hw state readout: disabled
>[  509.154306] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:HDMI-A-2] hw state readout: disabled
>[  509.154386] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][setup_hw_state]
>[  509.154456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[  509.154524] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  509.154587] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  509.154598] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  509.154641] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  509.154648] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  509.154690] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  509.154731] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  509.154805] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  509.154845] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.154888] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  509.154948] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  509.154992] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  509.155033] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  509.155074] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  509.155115] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  509.155158] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][setup_hw_state]
>[  509.155198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[  509.155238] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  509.155276] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  509.155284] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  509.155321] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  509.155333] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  509.155370] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  509.155411] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  509.155454] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  509.155507] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.155561] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  509.155637] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  509.155697] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  509.155770] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  509.155827] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  509.155887] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  509.155952] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][setup_hw_state]
>[  509.156007] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[  509.156061] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  509.156114] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  509.156122] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  509.156157] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  509.156163] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[  509.156199] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[  509.156235] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[  509.156271] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[  509.156307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.156342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  509.156396] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  509.156437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  509.156475] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[  509.156513] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[  509.156549] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[  509.156598] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[  509.156795] [drm:intel_power_well_disable [i915]] disabling DDI D power well
>[  509.156872] [drm:skl_set_power_well [i915]] Disabling DDI D power well
>[  509.156928] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[  509.156981] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[  509.157034] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[  509.157084] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[  509.157138] [drm:intel_power_well_disable [i915]] disabling DDI A/E power well
>[  509.157205] [drm:skl_set_power_well [i915]] Disabling DDI A/E power well
>[  509.157276] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  509.157410] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  509.157476] [drm:intel_power_well_disable [i915]] disabling DC off
>[  509.157547] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  509.157609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  509.158113] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.158189] [drm:intel_huc_init [i915]] HuC firmware pending, path i915/skl_huc_ver01_07_1398.bin
>[  509.158247] [drm:intel_uc_fw_fetch [i915]] before requesting firmware: uC fw fetch status PENDING
>[  509.158662] [drm:intel_uc_fw_fetch [i915]] fetch uC fw from i915/skl_huc_ver01_07_1398.bin succeeded, fw ffff8804a2c89428
>[  509.158713] [drm:intel_uc_fw_fetch [i915]] firmware version 1.7 OK (minimum 1.7)
>[  509.159502] [drm:intel_uc_fw_fetch [i915]] uC fw fetch status SUCCESS, obj ffff880446cd0040
>[  509.160010] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[  509.160315] [drm:i915_gem_context_init [i915]] LR context support initialized
>[  509.160528] [drm:intel_engine_create_scratch [i915]] render ring pipe control offset: 0xfffff000
>[  509.164289] [drm:gen8_init_common_ring [i915]] Execlists enabled for render ring
>[  509.164452] [drm:gen8_init_common_ring [i915]] Execlists enabled for blitter ring
>[  509.164587] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd ring
>[  509.164714] [drm:gen8_init_common_ring [i915]] Execlists enabled for bsd2 ring
>[  509.164900] [drm:gen8_init_common_ring [i915]] Execlists enabled for video enhancement ring
>[  509.165043] [drm:intel_guc_setup [i915]] GuC fw status: path i915/skl_guc_ver6_1.bin, fetch NONE, load NONE
>[  509.165064] [drm] GuC firmware load skipped
>[  509.166137] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  509.166661] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[  509.166728] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[  509.166830] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[  509.166887] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[  509.169950] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-DP-1
>[  509.172836] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-2
>[  509.175736] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-3
>[  509.178721] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card0-DP-4
>[  509.180625] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  509.182276] [drm:intel_opregion_register [i915]] 6 outputs detected
>[  509.205213] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[  509.210037] [drm:asle_work [i915]] bclp = 0x80000002
>[  509.210135] [drm:asle_work [i915]] updating opregion backlight 2/255
>[  509.211458] [drm:asle_work [i915]] bclp = 0x800000ff
>[  509.211496] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  509.212296] acpi device:0f: registered as cooling_device13
>[  509.213441] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input47
>[  509.214080] [drm] Initialized i915 1.6.0 20170206 for 0000:00:02.0 on minor 0
>[  509.214081] [drm] DRM_I915_DEBUG enabled
>[  509.214081] [drm] DRM_I915_DEBUG_GEM enabled
>[  509.214091] [drm:drm_setup_crtcs] 
>[  509.214095] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1]
>[  509.214139] [drm:intel_dp_detect [i915]] [CONNECTOR:47:DP-1]
>[  509.214189] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.214219] [drm:intel_power_well_enable [i915]] enabling DC off
>[  509.214525] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  509.223043] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.230199] [drm:asle_work [i915]] bclp = 0x800000ff
>[  509.230234] [drm:asle_work [i915]] updating opregion backlight 255/255
>[  509.231514] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.239963] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.248395] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.256820] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.265247] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.273672] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.282099] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.290525] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.298952] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.307376] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.315802] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.324227] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.332653] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.341092] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.349518] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.357944] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.366368] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.374794] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.383232] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.391669] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.400100] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.408530] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.416959] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.425387] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.433814] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.442242] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.450670] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.459096] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.467522] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.475954] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.484382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[  509.484392] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[  509.484416] [drm:intel_power_well_disable [i915]] disabling DC off
>[  509.484439] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  509.484458] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  509.484939] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.484944] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] status updated from unknown to disconnected
>[  509.484977] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:47:DP-1] disconnected
>[  509.484980] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2]
>[  509.485012] [drm:intel_dp_detect [i915]] [CONNECTOR:51:DP-2]
>[  509.485040] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.485058] [drm:intel_power_well_enable [i915]] enabling DC off
>[  509.485404] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  509.485425] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  509.485441] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  509.486363] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 02 01 04 01 0f 00 01
>[  509.487923] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  509.487947] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  509.487967] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  509.488004] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  509.488826] [drm:intel_dp_read_desc [i915]] DP branch: OUI 00-1c-f8 dev-ID 175IB0 HW-rev 1.0 SW-rev 7.32
>[  509.489563] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  509.491830] [drm:drm_dp_i2c_do_msg] native defer
>[  509.492932] [drm:drm_dp_i2c_do_msg] native defer
>[  509.494325] [drm:drm_dp_i2c_do_msg] native defer
>[  509.495406] [drm:drm_dp_i2c_do_msg] native defer
>[  509.496724] [drm:drm_dp_i2c_do_msg] native defer
>[  509.498436] [drm:drm_dp_i2c_do_msg] native defer
>[  509.499491] [drm:drm_dp_i2c_do_msg] native defer
>[  509.500826] [drm:drm_dp_i2c_do_msg] native defer
>[  509.501952] [drm:drm_dp_i2c_do_msg] native defer
>[  509.503364] [drm:drm_dp_i2c_do_msg] native defer
>[  509.504417] [drm:drm_dp_i2c_do_msg] native defer
>[  509.505734] [drm:drm_dp_i2c_do_msg] native defer
>[  509.506877] [drm:drm_dp_i2c_do_msg] native defer
>[  509.508290] [drm:drm_dp_i2c_do_msg] native defer
>[  509.510446] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  509.510481] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  509.510518] [drm:intel_power_well_disable [i915]] disabling DC off
>[  509.510536] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  509.510552] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  509.511053] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.511076] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] status updated from unknown to connected
>[  509.511119] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[  509.511144] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:51:DP-2] probed modes :
>[  509.511147] [drm:drm_mode_debug_printmodeline] Modeline 69:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.511148] [drm:drm_mode_debug_printmodeline] Modeline 70:"1920x1080" 60 140000 1920 2068 2100 2101 1080 1082 1087 1115 0x40 0x9
>[  509.511151] [drm:drm_mode_debug_printmodeline] Modeline 76:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  509.511153] [drm:drm_mode_debug_printmodeline] Modeline 71:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  509.511154] [drm:drm_mode_debug_printmodeline] Modeline 72:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  509.511156] [drm:drm_mode_debug_printmodeline] Modeline 75:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  509.511158] [drm:drm_mode_debug_printmodeline] Modeline 73:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  509.511159] [drm:drm_mode_debug_printmodeline] Modeline 74:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  509.511161] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  509.511162] [drm:drm_mode_debug_printmodeline] Modeline 77:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  509.511164] [drm:drm_mode_debug_printmodeline] Modeline 78:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  509.511165] [drm:drm_mode_debug_printmodeline] Modeline 79:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  509.511167] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3]
>[  509.511194] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-3]
>[  509.511214] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.511231] [drm:intel_power_well_enable [i915]] enabling DC off
>[  509.511539] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  509.511560] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  509.511575] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  509.511619] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  509.511641] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  509.511656] [drm:intel_power_well_disable [i915]] disabling DC off
>[  509.511673] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  509.511686] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  509.512180] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.512184] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] status updated from unknown to disconnected
>[  509.512187] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:56:DP-3] disconnected
>[  509.512189] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1]
>[  509.512215] [drm:intel_hdmi_detect [i915]] [CONNECTOR:60:HDMI-A-1]
>[  509.512234] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.514629] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  509.514652] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  509.515253] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  509.515257] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[  509.517556] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  509.517579] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  509.519917] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  509.519930] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  509.519952] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.519955] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] status updated from unknown to disconnected
>[  509.519956] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:HDMI-A-1] disconnected
>[  509.519958] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4]
>[  509.519981] [drm:intel_dp_detect [i915]] [CONNECTOR:63:DP-4]
>[  509.520001] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.520017] [drm:intel_power_well_enable [i915]] enabling DC off
>[  509.520308] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  509.520328] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  509.520344] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  509.520830] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 82 02 02 06 00 00 00 00
>[  509.521176] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[  509.521200] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  509.521220] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  509.521239] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  509.521654] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0
>[  509.522021] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  509.528303] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[  509.528625] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  509.528654] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  509.528674] [drm:intel_power_well_disable [i915]] disabling DC off
>[  509.528695] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  509.528712] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  509.529175] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.529179] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] status updated from unknown to connected
>[  509.529382] [drm:drm_edid_to_eld] ELD monitor DELL P2715Q
>[  509.529384] [drm:drm_edid_to_eld] ELD size 36, SAD count 1
>[  509.529422] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[  509.529423] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[  509.529426] [drm:drm_mode_debug_printmodeline] Modeline 113:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[  509.529428] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  509.529431] [drm:drm_mode_debug_printmodeline] Modeline 124:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[  509.529432] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[  509.529437] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:63:DP-4] probed modes :
>[  509.529439] [drm:drm_mode_debug_printmodeline] Modeline 82:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  509.529441] [drm:drm_mode_debug_printmodeline] Modeline 83:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  509.529442] [drm:drm_mode_debug_printmodeline] Modeline 86:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x40 0x6
>[  509.529444] [drm:drm_mode_debug_printmodeline] Modeline 84:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1082 1087 1125 0x40 0x5
>[  509.529446] [drm:drm_mode_debug_printmodeline] Modeline 100:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  509.529447] [drm:drm_mode_debug_printmodeline] Modeline 118:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  509.529449] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  509.529450] [drm:drm_mode_debug_printmodeline] Modeline 120:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  509.529452] [drm:drm_mode_debug_printmodeline] Modeline 101:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  509.529453] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  509.529455] [drm:drm_mode_debug_printmodeline] Modeline 102:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  509.529456] [drm:drm_mode_debug_printmodeline] Modeline 119:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  509.529458] [drm:drm_mode_debug_printmodeline] Modeline 88:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  509.529459] [drm:drm_mode_debug_printmodeline] Modeline 87:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  509.529461] [drm:drm_mode_debug_printmodeline] Modeline 96:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  509.529462] [drm:drm_mode_debug_printmodeline] Modeline 89:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  509.529464] [drm:drm_mode_debug_printmodeline] Modeline 90:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  509.529465] [drm:drm_mode_debug_printmodeline] Modeline 91:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  509.529467] [drm:drm_mode_debug_printmodeline] Modeline 85:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  509.529468] [drm:drm_mode_debug_printmodeline] Modeline 116:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  509.529470] [drm:drm_mode_debug_printmodeline] Modeline 106:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  509.529471] [drm:drm_mode_debug_printmodeline] Modeline 97:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  509.529473] [drm:drm_mode_debug_printmodeline] Modeline 98:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  509.529475] [drm:drm_mode_debug_printmodeline] Modeline 99:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  509.529476] [drm:drm_mode_debug_printmodeline] Modeline 92:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  509.529478] [drm:drm_mode_debug_printmodeline] Modeline 107:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  509.529479] [drm:drm_mode_debug_printmodeline] Modeline 122:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  509.529481] [drm:drm_mode_debug_printmodeline] Modeline 109:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  509.529482] [drm:drm_mode_debug_printmodeline] Modeline 93:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  509.529484] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  509.529485] [drm:drm_mode_debug_printmodeline] Modeline 94:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  509.529487] [drm:drm_mode_debug_printmodeline] Modeline 95:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  509.529488] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2]
>[  509.529515] [drm:intel_hdmi_detect [i915]] [CONNECTOR:67:HDMI-A-2]
>[  509.529535] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.531816] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  509.531838] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  509.534120] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  509.534124] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpd
>[  509.536404] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  509.536429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  509.538709] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  509.538726] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[  509.538750] [drm:intel_power_well_disable [i915]] disabling always-on
>[  509.538752] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] status updated from unknown to disconnected
>[  509.538754] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:67:HDMI-A-2] disconnected
>[  509.538765] [drm:drm_setup_crtcs] connector 47 enabled? no
>[  509.538766] [drm:drm_setup_crtcs] connector 51 enabled? yes
>[  509.538767] [drm:drm_setup_crtcs] connector 56 enabled? no
>[  509.538768] [drm:drm_setup_crtcs] connector 60 enabled? no
>[  509.538769] [drm:drm_setup_crtcs] connector 63 enabled? yes
>[  509.538770] [drm:drm_setup_crtcs] connector 67 enabled? no
>[  509.538799] [drm:intel_fb_initial_config [i915]] connector DP-1 not enabled, skipping
>[  509.538821] [drm:intel_fb_initial_config [i915]] connector DP-2 has no encoder or crtc, skipping
>[  509.538841] [drm:intel_fb_initial_config [i915]] connector DP-3 not enabled, skipping
>[  509.538860] [drm:intel_fb_initial_config [i915]] connector HDMI-A-1 not enabled, skipping
>[  509.538877] [drm:intel_fb_initial_config [i915]] connector DP-4 has no encoder or crtc, skipping
>[  509.538893] [drm:intel_fb_initial_config [i915]] connector HDMI-A-2 not enabled, skipping
>[  509.538909] [drm:intel_fb_initial_config [i915]] fallback: Not all outputs enabled
>[  509.538926] [drm:intel_fb_initial_config [i915]] Enabled: 0, detected: 2
>[  509.538941] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  509.538945] [drm:drm_setup_crtcs] looking for cmdline mode on connector 51
>[  509.538946] [drm:drm_setup_crtcs] looking for preferred mode on connector 51 0
>[  509.538947] [drm:drm_setup_crtcs] found mode 1920x1200
>[  509.538948] [drm:drm_setup_crtcs] looking for cmdline mode on connector 63
>[  509.538949] [drm:drm_setup_crtcs] looking for preferred mode on connector 63 0
>[  509.538950] [drm:drm_setup_crtcs] found mode 3840x2160
>[  509.538951] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[  509.538971] [drm:drm_setup_crtcs] desired mode 1920x1200 set on crtc 31 (0,0)
>[  509.538975] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 38 (0,0)
>[  509.539000] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[  509.554882] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000
>[  509.555373] fbcon: inteldrmfb (fb0) is primary device
>[  509.555771] [drm:intel_atomic_check [i915]] [CONNECTOR:51:DP-2] checking for sink bpp constrains
>[  509.555797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to default limit of 24
>[  509.555824] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 154000KHz
>[  509.555849] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  509.555870] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  509.555894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.555918] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[  509.555939] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  509.555959] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  509.555977] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  509.555994] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  509.555998] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.556016] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  509.556018] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  509.556035] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  509.556051] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  509.556067] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  509.556083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.556098] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  509.556120] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  509.556137] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  509.556154] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[  509.556170] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[  509.556184] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[  509.556207] [drm:intel_atomic_check [i915]] [CONNECTOR:63:DP-4] checking for sink bpp constrains
>[  509.556226] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  509.556250] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  509.556282] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  509.556308] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  509.556337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  509.556364] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[  509.556388] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  509.556410] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  509.556432] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  509.556453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  509.556457] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  509.556478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  509.556482] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  509.556503] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  509.556524] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  509.556545] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[  509.556567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  509.556588] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  509.556615] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[  509.556637] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  509.556659] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[  509.556680] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[  509.556700] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[  509.556742] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  509.556773] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[  509.556800] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  509.556826] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  509.556853] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[  509.556878] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[  509.556902] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>[  509.557135] [drm:intel_power_well_enable [i915]] enabling always-on
>[  509.557162] [drm:intel_power_well_enable [i915]] enabling DC off
>[  509.557470] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  509.557510] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  509.557537] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  509.557603] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[  509.557628] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[  509.557659] [drm:intel_power_well_enable [i915]] enabling DDI D power well
>[  509.557684] [drm:skl_set_power_well [i915]] Enabling DDI D power well
>[  509.557721] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  509.559951] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  509.559973] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  509.560001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI A]
>[  509.560025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DDI B]
>[  509.560045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:52:DP-MST A]
>[  509.560063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:53:DP-MST B]
>[  509.560080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:54:DP-MST C]
>[  509.560095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[  509.560112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[  509.560128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[  509.560143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST C]
>[  509.560157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DDI D]
>[  509.560172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:64:DP-MST A]
>[  509.560186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:65:DP-MST B]
>[  509.560200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DP-MST C]
>[  509.560218] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 0
>[  509.560237] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  509.560255] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  509.560272] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 3
>[  509.560329] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[  509.560347] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  509.563628] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  509.564987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  509.565009] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  509.565029] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  509.565049] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  509.570227] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  509.570248] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  509.575440] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  509.577932] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e412a8
>[  509.578536] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  509.578621] [drm:intel_fbc_enable [i915]] reserved 36864000 bytes of contiguous stolen space for FBC, threshold: 1
>[  509.578643] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  509.578714] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[  509.578748] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[  509.581978] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  509.582002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  509.582022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  509.582043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  509.582812] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[  509.582831] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  509.582849] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  509.583506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 08000000
>[  509.583524] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  509.583541] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  509.584199] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  509.584217] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  509.585186] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  509.587459] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8804a1e42548
>[  509.588033] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  509.588067] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:63:DP-4], [ENCODER:62:DDI D]
>[  509.588086] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[  509.588145] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  509.604942] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:51:DP-2]
>[  509.604976] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[  509.605028] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 1
>[  509.605083] [drm:verify_connector_state.isra.48 [i915]] [CONNECTOR:63:DP-4]
>[  509.605112] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[  509.605158] [drm:verify_single_dpll_state.isra.71 [i915]] DPLL 2
>[  509.605331] Console: switching to colour frame buffer device 240x75
>[  509.626823] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[  509.638475] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[  509.655156] [IGT] gvt_basic: exiting, ret=77
>[  509.665471] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC233: line_outs=1 (0x1b/0x0/0x0/0x0/0x0) type:speaker
>[  509.665476] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[  509.665479] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[  509.665481] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[  509.665483] snd_hda_codec_realtek hdaudioC0D0:    dig-out=0x1e/0x0
>[  509.665485] snd_hda_codec_realtek hdaudioC0D0:    inputs:

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Attachments on bug 99788: 129549 | 131119

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