Attachment 129839 Details for Bug 99912 – dmesg.log

dmesg.log

dmesg.log (text/plain), 32.86 KB, created by Luis Botello on 2017-02-22 19:03:08 UTC

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Creator: Luis Botello

Created: 2017-02-22 19:03:08 UTC

Size: 32.86 KB

patch

obsolete

>[ 1011.355459] Console: switching to colour dummy device 80x25
>[ 1011.355483] [IGT] kms_setmode: executing
>[ 1011.355659] [drm:intel_ring_workarounds_emit [i915]] Number of Workarounds emitted: 17
>[ 1011.409263] [IGT] kms_setmode: starting subtest basic
>[ 1011.409424] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1011.409519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1011.409668] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1011.427724] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1011.427788] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[ 1011.427842] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 1011.427925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1011.427980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1011.428027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1011.428072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1011.428116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1011.428168] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1011.428219] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1011.428267] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1011.428312] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1011.428358] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1011.441801] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[ 1011.441852] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[ 1011.441927] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1011.441984] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 1011.442060] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1011.442143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1011.442264] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1011.459197] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 38
>[ 1011.459263] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[ 1011.459353] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1011.459411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1011.459459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1011.459507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1011.459553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1011.459611] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:56:HDMI-A-2]
>[ 1011.459666] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1011.459718] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1011.459765] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1011.459810] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1011.459863] [drm:intel_power_well_disable [i915]] disabling DDI C power well
>[ 1011.459909] [drm:skl_set_power_well [i915]] Disabling DDI C power well
>[ 1011.459954] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1011.460007] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1011.460066] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[ 1011.460113] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1011.460159] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1011.460203] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1011.460652] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1011.460724] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1011.461310] [drm:drm_mode_addfb2 [drm]] [FB:57]
>[ 1011.510531] [drm:drm_mode_addfb2 [drm]] [FB:58]
>[ 1011.524720] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1011.524729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:DP-1]
>[ 1011.524770] [drm:intel_atomic_check [i915]] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[ 1011.524782] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1011.524794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 1011.524807] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1011.524825] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1011.524836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1011.524848] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[ 1011.524861] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1011.524873] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1011.524882] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1011.524893] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1011.524903] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1011.524913] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1011.524923] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1011.524938] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1011.524953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1011.524967] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1011.524980] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1011.524988] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1011.525000] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1011.525008] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1011.525017] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[ 1011.525025] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[ 1011.525033] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[ 1011.525044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1011.525058] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[ 1011.525068] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 1011.525367] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1011.525375] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1011.525643] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1011.525655] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1011.525664] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1011.525681] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[ 1011.525694] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[ 1011.525716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1011.525725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1011.525734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1011.525743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1011.525751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1011.525761] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1011.525772] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1011.525781] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1011.525790] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1011.525802] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[ 1011.525812] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 1011.529896] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1011.529908] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1011.529918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1011.529928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1011.532427] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1011.532438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1011.535230] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1011.537340] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff9f9b5eead000
>[ 1011.537626] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1011.537675] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1011.537685] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1011.554491] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1011.554508] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1011.554532] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1013.571348] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1013.571467] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1013.571624] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1013.588731] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1013.588795] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 31
>[ 1013.588848] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 1013.589035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1013.589117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1013.589185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1013.589255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1013.589309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1013.589385] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1013.589446] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1013.589516] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1013.589571] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1013.589636] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1013.589711] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[ 1013.589765] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[ 1013.589831] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1013.589905] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1013.589982] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1013.590053] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1013.590107] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1013.590172] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1013.590641] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1013.590732] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1013.591129] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1013.591202] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1013.591756] [drm:drm_mode_addfb2 [drm]] [FB:58]
>[ 1013.601845] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 1013.614520] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1013.614529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:DP-1]
>[ 1013.614570] [drm:intel_atomic_check [i915]] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[ 1013.614581] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1013.614594] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 1013.614606] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1013.614615] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1013.614626] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1013.614637] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[ 1013.614647] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1013.614657] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1013.614666] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1013.614675] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1013.614682] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1013.614691] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1013.614697] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1013.614706] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1013.614715] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1013.614723] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1013.614731] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1013.614739] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1013.614750] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x21, cfgcr1: 0x80400173, cfgcr2: 0x3a5
>[ 1013.614759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1013.614767] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[ 1013.614775] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[ 1013.614783] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[ 1013.614794] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1013.614808] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 1
>[ 1013.614818] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 1013.615137] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1013.615145] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1013.615414] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1013.615426] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1013.615435] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1013.615450] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[ 1013.615467] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[ 1013.615486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1013.615496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1013.615505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1013.615514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1013.615522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1013.615532] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1013.615542] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1013.615552] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1013.615561] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1013.615572] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 38
>[ 1013.615582] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 1013.618878] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1013.618890] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1013.618899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1013.618910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1013.621406] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1013.621417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1013.624210] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1013.626827] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff9f9b61d22000
>[ 1013.627120] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1013.643931] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1013.643947] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[ 1013.643971] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1015.660942] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1015.661088] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1015.661234] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1015.678653] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 38
>[ 1015.678713] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 1015.678797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1015.678853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1015.678901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1015.678945] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1015.678989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1015.679042] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1015.679093] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1015.679142] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1015.679187] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1015.679231] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1015.679283] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[ 1015.679326] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[ 1015.679368] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1015.679418] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1015.679474] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[ 1015.679519] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1015.679562] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1015.679603] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1015.680047] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1015.680122] [drm:drm_mode_setcrtc [drm]] [CRTC:31:pipe A]
>[ 1015.680544] [drm:drm_mode_setcrtc [drm]] [CRTC:38:pipe B]
>[ 1015.680594] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1015.681227] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 1015.691708] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[ 1015.704164] [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe C]
>[ 1015.704172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:47:DP-1]
>[ 1015.704213] [drm:intel_atomic_check [i915]] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[ 1015.704224] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1015.704237] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 1015.704249] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1015.704259] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1015.704270] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1015.704281] [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe C][modeset]
>[ 1015.704291] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 1015.704301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1015.704310] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1015.704319] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1015.704325] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1015.704334] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1015.704340] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1015.704350] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1015.704358] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1015.704367] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[ 1015.704375] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1015.704383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1015.704394] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1015.704403] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1015.704411] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 1C] disabled, scaler_id = -1
>[ 1015.704420] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2C] disabled, scaler_id = -1
>[ 1015.704428] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor C] disabled, scaler_id = -1
>[ 1015.704438] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1015.704453] [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe C] allocated DPLL 1
>[ 1015.704462] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe C
>[ 1015.704471] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0
>[ 1015.704792] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1015.704801] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1015.705076] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1015.705090] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1015.705103] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1015.705135] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[ 1015.705152] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[ 1015.705170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1015.705182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1015.705196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1015.705206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1015.705219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1015.705231] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1015.705245] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1015.705257] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1015.705270] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1015.705287] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 4, on? 0) for crtc 45
>[ 1015.705298] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 1015.709369] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1015.709380] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1015.709390] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1015.709400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1015.711893] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1015.711905] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1015.714700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1015.717350] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff9f9b61d27800
>[ 1015.717578] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 1015.734412] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1015.734429] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[ 1015.734453] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1017.757270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1017.757406] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 1017.769451] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 4, on? 1) for crtc 45
>[ 1017.769513] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 1017.769598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1017.769654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1017.769702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1017.769745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1017.769789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1017.769841] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1017.769892] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1017.769939] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1017.769985] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1017.770028] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1017.770080] [drm:intel_power_well_disable [i915]] disabling DDI B power well
>[ 1017.770124] [drm:skl_set_power_well [i915]] Disabling DDI B power well
>[ 1017.770166] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1017.770216] [drm:skl_set_power_well [i915]] Disabling power well 2
>[ 1017.770272] [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe C]
>[ 1017.770316] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1017.770359] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1017.770400] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1017.770844] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1017.771026] [IGT] kms_setmode: exiting, ret=99
>[ 1017.771344] [drm:intel_ring_workarounds_emit [i915]] Number of Workarounds emitted: 17
>[ 1017.793283] [drm:intel_atomic_check [i915]] [CONNECTOR:47:DP-1] checking for sink bpp constrains
>[ 1017.793337] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1017.793392] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 1017.793443] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1017.793486] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1017.793533] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1017.793585] [drm:intel_dump_pipe_config [i915]] [CRTC:31:pipe A][modeset]
>[ 1017.793630] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 1017.793674] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1017.793715] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1017.793756] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1017.793790] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1017.793832] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1017.793860] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1017.793904] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1017.793944] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1017.793982] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1017.794021] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1017.794058] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1017.794107] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1017.794144] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1017.794182] [drm:intel_dump_pipe_config [i915]] [PLANE:25:plane 1A] disabled, scaler_id = -1
>[ 1017.794219] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 2A] disabled, scaler_id = -1
>[ 1017.794255] [drm:intel_dump_pipe_config [i915]] [PLANE:29:cursor A] disabled, scaler_id = -1
>[ 1017.794304] [drm:intel_atomic_check [i915]] [CONNECTOR:56:HDMI-A-2] checking for sink bpp constrains
>[ 1017.794346] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1017.794394] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[ 1017.794438] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[ 1017.794482] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1017.794523] [drm:intel_dump_pipe_config [i915]] [CRTC:38:pipe B][modeset]
>[ 1017.794561] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1017.794599] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[ 1017.794636] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1017.794666] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1017.794706] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1017.794732] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1017.794774] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1017.794812] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[ 1017.794849] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1017.794885] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1017.794921] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1017.794968] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1017.795005] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1017.795042] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 1B] disabled, scaler_id = -1
>[ 1017.795078] [drm:intel_dump_pipe_config [i915]] [PLANE:34:plane 2B] disabled, scaler_id = -1
>[ 1017.795113] [drm:intel_dump_pipe_config [i915]] [PLANE:36:cursor B] disabled, scaler_id = -1
>[ 1017.795161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1017.795216] [drm:intel_find_shared_dpll [i915]] [CRTC:31:pipe A] allocated DPLL 1
>[ 1017.795260] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 1017.795308] [drm:intel_find_shared_dpll [i915]] [CRTC:38:pipe B] allocated DPLL 2
>[ 1017.795348] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[ 1017.795424] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1017.795462] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1017.795760] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1017.795806] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1017.795854] [drm:skl_set_power_well [i915]] Enabling power well 2
>[ 1017.795920] [drm:intel_power_well_enable [i915]] enabling DDI B power well
>[ 1017.795955] [drm:skl_set_power_well [i915]] Enabling DDI B power well
>[ 1017.795992] [drm:intel_power_well_enable [i915]] enabling DDI C power well
>[ 1017.796026] [drm:skl_set_power_well [i915]] Enabling DDI C power well
>[ 1017.796064] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 1017.796120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:46:DDI B]
>[ 1017.796162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DP-MST A]
>[ 1017.796201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST B]
>[ 1017.796238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST C]
>[ 1017.796274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI C]
>[ 1017.796317] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 0
>[ 1017.796360] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1017.796400] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1017.796437] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 3
>[ 1017.796485] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 31
>[ 1017.796526] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 1017.800536] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1017.800599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1017.800658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1017.800717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1017.803160] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1017.803175] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1017.805890] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1017.808488] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff9f9b625d8800
>[ 1017.808707] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1017.808738] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1017.808749] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1017.808776] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 38
>[ 1017.808785] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 1017.810895] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff9f9b625db000
>[ 1017.811118] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1017.828297] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:47:DP-1]
>[ 1017.828316] [drm:intel_atomic_commit_tail [i915]] [CRTC:31:pipe A]
>[ 1017.828340] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 1
>[ 1017.828363] [drm:verify_connector_state.isra.79 [i915]] [CONNECTOR:56:HDMI-A-2]
>[ 1017.828378] [drm:intel_atomic_commit_tail [i915]] [CRTC:38:pipe B]
>[ 1017.828397] [drm:verify_single_dpll_state.isra.105 [i915]] DPLL 2
>[ 1017.845066] Console: switching to colour frame buffer device 240x67
>

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