Attachment 130344 Details for Bug 100300 – dmesgGPUhang

dmesgGPUhang

dmesgGPUhang (text/plain), 251.47 KB, created by cprigent on 2017-03-21 14:25:07 UTC

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Creator: cprigent

Created: 2017-03-21 14:25:07 UTC

Size: 251.47 KB

patch

obsolete

>[  711.268216] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.268276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.268343] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.268408] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.268470] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.285024] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.285111] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.285188] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.285265] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.285415] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.285476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.285549] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.285610] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.285676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.285741] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.285805] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.285863] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.285920] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.285966] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.286024] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.286060] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.286122] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.286180] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.286239] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.286297] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.286354] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.286425] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.286483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.286547] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.286606] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.286664] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.286722] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.286780] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.286840] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.286905] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.286990] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.287051] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.287174] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.302925] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.302995] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.303082] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.303179] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.303274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.303340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.303406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.303466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.303526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.303585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.303653] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.303715] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.303776] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.303854] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.303918] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.303989] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.304057] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.304119] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.304182] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.304249] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.304318] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.304384] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.304449] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.304696] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.304762] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.304833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.304919] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.304982] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.305049] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.305115] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.305181] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.305248] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.305312] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.305375] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.305424] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.305487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.305528] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.305594] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.305657] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.305721] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.305786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.305849] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.305923] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.305986] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.306058] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.306124] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.306186] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.306249] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.306313] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.306376] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.306443] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.306522] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.306588] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.306720] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.306800] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.306871] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.306956] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.307028] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.307115] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.307437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.307503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.307568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.307633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.307696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.307759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.307825] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.307893] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.307957] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.308058] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.308121] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.308302] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.308371] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.308441] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.308509] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.308749] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.308816] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.309488] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.309560] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.309774] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.309841] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.309908] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.309970] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.310184] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.310252] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.310333] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.310394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.310462] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.310527] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.310591] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.310827] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.310892] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.311059] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.311123] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.311327] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.311392] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.311459] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.311520] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.311766] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.311831] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.311897] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.311959] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.312025] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.312087] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.312324] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.312389] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.312856] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.312926] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.313134] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.313203] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.313273] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.313337] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.313585] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.313654] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.313723] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.315808] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.315870] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.316074] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.316136] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.316204] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3293800
>[  711.316591] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.316763] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.316834] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.316949] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.333553] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.333621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.333701] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.333767] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.333836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.333905] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.333971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.334039] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.334103] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.334147] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.334213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.334255] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.334324] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.334390] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.334455] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.334520] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.334584] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.334659] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.334726] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.334795] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.334862] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.334927] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.334992] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.335056] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.335122] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.335193] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.335280] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.335349] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.335466] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.335752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.335820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.335886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.335951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.336016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.336081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.336148] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.336215] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.336297] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.350321] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  711.350391] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  711.350574] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  711.350640] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  711.350747] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3291000
>[  711.351134] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  711.352060] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.352137] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.352300] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.352475] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.352536] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.352662] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.352753] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.352825] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.352897] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.352964] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.353027] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.353099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.353165] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.353225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.353275] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.353335] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.353376] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.353440] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.353501] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.353565] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.353626] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.353689] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.353761] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.353823] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.353888] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.353952] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.354013] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.354076] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.354137] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.354200] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.354270] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.354349] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.354413] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.354542] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  711.367196] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.367264] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.367482] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.367545] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.367610] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  711.367672] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  711.367750] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  711.367846] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  711.367940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.368005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.368071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.368131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.368190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.368249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.368315] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.368379] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.368440] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.385543] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.385628] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.385704] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.385781] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.385933] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.385995] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.386067] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.386128] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.386193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.386258] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.386323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.386381] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.386438] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.386485] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.386543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.386580] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.386641] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.386700] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.386758] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.386816] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.386873] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.386941] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.386999] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.387064] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.387123] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.387181] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.387240] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.387298] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.387358] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.387422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.387508] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.387570] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.387689] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.402862] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.402931] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.403016] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.403111] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.403206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.403272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.403338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.403398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.403458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.403516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.403583] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.403646] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.403707] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.403784] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.403854] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.403926] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.403994] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.404059] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.404120] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.404186] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.404256] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.404322] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.404387] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.404674] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.404739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.404813] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.404895] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.404958] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.405025] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.405090] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.405156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.405223] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.405287] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.405351] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.405399] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.405462] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.405503] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.405569] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.405631] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.405695] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.405761] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.405823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.405896] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.405961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.406028] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.406093] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.406155] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.406220] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.406282] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.406345] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.406414] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.406492] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.406558] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.406692] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.406769] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.406841] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.406926] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.406999] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.407085] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.407395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.407460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.407525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.407590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.407654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.407717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.407783] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.407849] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.407915] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.408024] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.408092] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.408271] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.408340] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.408410] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.408477] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.408719] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.408785] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.409452] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.409522] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.409738] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.409803] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.409870] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.409937] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.410151] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.410216] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.410297] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.410357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.410423] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.410489] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.410553] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.410790] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.410856] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.411023] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.411087] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.411292] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.411355] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.411421] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.411482] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.411728] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.411793] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.411859] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.411920] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.411988] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.412053] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.412291] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.412356] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.412823] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.412888] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.413095] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.413163] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.413231] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.413296] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.413546] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.413615] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.413684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.415777] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.415833] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.416030] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.416086] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.416147] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3297000
>[  711.416512] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.416719] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.416785] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.416891] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.433444] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.433495] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.433552] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.433601] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.433652] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.433702] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.433751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.433798] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.433845] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.433877] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.433925] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.433955] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.434005] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.434053] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.434101] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.434148] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.434195] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.434248] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.434296] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.434346] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.434394] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.434441] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.434489] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.434536] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.434585] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.434637] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.434700] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.434749] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.434834] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.435174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.435224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.435273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.435320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.435368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.435415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.435464] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.435513] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.435576] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.450235] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  711.450293] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  711.450458] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  711.450512] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  711.450605] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3291000
>[  711.450982] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  711.451851] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.451916] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.452013] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.452163] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.452212] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.452270] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.452332] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.452380] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.452435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.452489] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.452587] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.452648] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.452706] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.452758] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.452804] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.452863] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.452902] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.452963] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.453019] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.453076] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.453127] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.453178] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.453242] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.453296] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.453350] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.453402] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.453454] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.453504] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.453556] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.453606] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.453663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.453728] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.453783] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.453888] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  711.466835] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.466904] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.467122] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.467185] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.467250] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  711.467312] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  711.467390] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  711.467485] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  711.467580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.467646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.467713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.467775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.467835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.467895] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.467961] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.468026] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.468088] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.468656] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.468746] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.468823] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.468902] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.469039] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.469103] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.469180] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.469243] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.469313] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.469378] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.469446] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.469507] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.469567] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.469615] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.469678] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.469718] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.469787] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.469849] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.469913] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.469976] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.470039] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.470109] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.470172] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.470240] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.470304] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.470366] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.470431] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.470494] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.470557] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.470626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.470714] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.470781] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.470919] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.485513] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.485581] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.485665] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.485761] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.485856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.485924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.485987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.486047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.486106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.486164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.486232] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.486295] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.486355] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.486433] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.486502] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.486575] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.486643] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.486705] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.486768] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.486834] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.486904] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.486969] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.487034] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.487243] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.487303] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.487374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.487451] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.487512] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.487577] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.487639] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.487703] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.487764] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.487822] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.487880] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.487926] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.487984] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.488021] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.488083] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.488141] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.488200] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.488257] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.488315] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.488387] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.488444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.488508] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.488638] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.488710] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.488779] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.488844] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.488908] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.488983] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.489064] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.489132] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.489256] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.489319] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.489387] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.489458] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.489526] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.489606] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.492293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.492369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.492433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.492499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.492608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.492665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.492724] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.492784] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.492842] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.492937] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.492994] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.493185] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.493244] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.493309] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.493369] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.493578] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.493640] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.494302] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.494360] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.494572] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.494629] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.494687] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.494742] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.494950] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.495006] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.495080] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.495135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.495193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.495252] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.495308] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.495542] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.495598] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.495758] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.495814] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.496014] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.496072] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.496130] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.496185] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.496427] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.496483] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.496569] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.496634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.496706] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.496770] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.497017] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.497079] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.497540] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.497602] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.497801] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.497863] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.497925] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.497983] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.498227] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.498288] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.498351] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.500499] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.500582] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.500799] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.500857] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.500926] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3294000
>[  711.501297] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.501480] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.501544] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.501650] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.518406] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.518475] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.518551] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.518612] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.518679] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.518747] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.518815] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.518874] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.518932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.518978] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.519037] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.519074] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.519135] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.519194] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.519253] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.519313] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.519371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.519444] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.519502] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.519569] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.519629] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.519688] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.519746] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.519804] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.519864] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.519933] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.520017] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.520078] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.520220] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.520504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.520786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.520849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.520915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.520977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.521048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.521121] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.521191] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.521273] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.535032] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  711.535108] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  711.535308] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  711.535381] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  711.535499] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b66de000
>[  711.535894] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  711.537177] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.537263] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.537385] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.553715] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.553795] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.553878] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.553964] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.554030] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.554105] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.554179] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.554254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.554324] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.554390] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.554456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.554507] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.554573] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.554615] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.554684] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.554751] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.554817] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.554882] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.554947] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.555026] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.555091] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.555164] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.555231] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.555297] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.555362] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.555428] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.555495] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.555568] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.555650] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.555719] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.555874] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  711.569362] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.569430] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.569661] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.569724] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.569789] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  711.569852] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  711.569930] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  711.570023] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  711.570139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.570206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.570273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.570333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.570393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.570453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.570519] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.570582] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.570644] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.586964] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.587050] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.587125] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.587202] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.587358] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.587419] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.587491] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.587551] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.587615] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.587680] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.587743] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.587801] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.587859] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.587906] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.587964] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.588001] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.588062] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.588121] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.588180] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.588238] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.588296] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.588364] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.588422] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.588487] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.588649] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.588720] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.588788] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.588853] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.588923] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.588996] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.589088] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.589151] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.589261] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.605350] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.605427] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.605522] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.605627] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.605732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.605806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.605881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.605948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.606018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.606083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.606159] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.606229] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.606297] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.606383] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.606460] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.606541] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.606616] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.606687] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.606758] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.606833] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.606907] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.606981] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.607054] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.607285] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.607353] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.607431] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.607517] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.607583] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.607657] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.607727] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.607800] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.607868] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.607934] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.608001] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.608050] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.608116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.608158] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.608227] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.608294] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.608360] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.608425] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.608489] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.608646] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.608722] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.608809] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.608888] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.608964] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.609044] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.609119] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.609199] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.609284] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.609379] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.609457] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.609624] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.609690] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.609763] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.609839] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.609904] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.609985] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.610267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.610334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.610398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.610459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.610522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.610585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.610650] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.610714] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.610778] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.610880] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.610943] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.611123] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.611192] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.611262] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.611329] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.611550] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.611616] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.612286] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.612357] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.612656] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.612723] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.612802] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.612870] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.613090] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.613158] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.613242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.613306] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.613372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.613439] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.613506] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.613749] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.613817] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.613987] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.614054] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.614263] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.614331] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.614399] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.614465] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.614716] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.614781] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.614847] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.614910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.614977] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.615044] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.615283] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.615347] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.615814] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.615878] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.616084] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.616147] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.616213] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.616275] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.616521] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.616612] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.616692] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.618782] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.618844] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.619075] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.619141] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.619219] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b6dce800
>[  711.619598] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.619791] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.619861] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.619974] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.636688] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.636752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.636819] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.636874] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.636935] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.636997] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.637054] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.637107] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.637159] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.637200] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.637253] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.637286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.637342] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.637395] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.637448] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.637500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.637552] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.637618] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.637670] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.637729] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.637782] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.637835] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.637889] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.637943] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.637995] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.638053] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.638130] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.638188] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.638307] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.638585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.638642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.638695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.638749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.638801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.638853] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.638912] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.638968] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.639036] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.653289] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  711.653352] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  711.653527] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  711.653586] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  711.653685] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3292800
>[  711.654067] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  711.654926] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.654996] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.655099] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.655262] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.655317] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.655381] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.655449] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.655502] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.655563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.655621] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.655677] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.655732] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.655784] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.655835] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.655876] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.655929] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.655962] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.656017] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.656070] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.656122] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.656174] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.656226] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.656291] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.656343] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.656401] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.656454] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.656507] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.656614] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.656680] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.656738] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.656806] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.656880] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.656943] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.658592] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  711.671598] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.671667] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.671937] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.672004] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.672071] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  711.672134] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  711.672212] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  711.672307] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  711.672402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.672469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.672531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.672642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.672705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.672774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.672849] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.672920] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.672990] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.688422] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.688493] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.688628] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.688692] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.688826] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.688879] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.688943] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.688995] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.689052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.689107] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.689163] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.689215] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.689266] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.689308] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.689361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.689393] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.689448] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.689500] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.689552] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.689606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.689658] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.689721] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.689774] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.689825] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.689878] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.689930] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.689982] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.690032] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.690084] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.690144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.690218] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.690273] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.690376] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.705770] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.705799] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.705839] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.705893] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.705940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.705966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.705994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.706018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.706043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.706065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.706093] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.706120] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.706144] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.706180] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.706211] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.706244] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.706273] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.706298] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.706324] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.706352] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.706384] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.706412] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.706439] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.706559] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.706582] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.706613] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.706645] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.706668] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.706698] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.706722] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.706751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.706776] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.706799] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.706822] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.706842] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.706865] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.706879] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.706904] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.706927] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.706951] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.706974] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.706997] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.707028] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.707051] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.707080] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.707103] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.707129] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.707154] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.707179] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.707205] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.707232] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.707266] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.707289] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.707347] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.707371] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.707396] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.707430] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.707455] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.707491] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.707734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.707758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.707781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.707804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.707827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.707849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.707873] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.707897] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.707921] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.707969] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.707992] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.708115] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.708140] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.708166] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.708194] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.708362] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.708388] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.709017] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.709047] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.709218] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.709246] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.709275] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.709303] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.709476] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.709505] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.709548] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.709575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.709603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.709632] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.709660] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.709856] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.709885] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.710014] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.710041] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.710204] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.710232] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.710261] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.710289] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.710492] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.710520] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.710547] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.710572] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.710600] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.710626] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.710820] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.710847] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.711272] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.711298] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.711458] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.711485] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.711514] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.711540] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.711741] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.711767] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.711797] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.713838] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.713864] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.714025] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.714051] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.714080] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3296800
>[  711.714411] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.714521] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.714550] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.714617] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.731283] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.731311] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.731345] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.731370] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.731396] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.731423] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.731448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.731472] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.731495] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.731511] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.731536] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.731553] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.731579] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.731603] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.731627] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.731651] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.731674] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.731702] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.731726] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.731751] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.731775] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.731801] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.731827] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.731850] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.731877] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.731902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.731935] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.731960] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.732005] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.732259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.732284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.732309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.732333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.732357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.732381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.732405] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.732430] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.732469] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.747941] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  711.747965] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  711.748083] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  711.748109] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  711.748161] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3292800
>[  711.748515] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  711.749309] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.749336] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.749395] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.749456] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.749479] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.749504] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.749533] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.749556] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.749580] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.749604] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.749626] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.749650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.749672] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.749694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.749709] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.749732] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.749746] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.749770] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.749793] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.749815] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.749838] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.749860] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.749886] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.749908] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.749932] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.749955] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.749977] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.750000] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.750022] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.750045] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.750069] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.750095] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.750119] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.750163] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  711.764952] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.764980] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.765151] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.765191] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.765218] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  711.765243] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  711.765278] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  711.765331] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  711.765377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.765403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.765433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.765457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.765482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.765507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.765537] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.765562] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.765589] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.766125] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.766164] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.766197] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.766231] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.766311] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.766338] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.766369] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.766392] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.766421] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.766449] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.766475] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.766498] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.766521] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.766541] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.766564] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.766579] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.766603] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.766626] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.766649] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.766674] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.766697] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.766728] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.766751] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.766779] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.766802] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.766827] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.766851] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.766878] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.766901] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.766928] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.766968] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.766992] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.767055] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.783952] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.783981] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.784022] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.784076] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.784122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.784148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.784178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.784202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.784227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.784252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.784281] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.784307] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.784331] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.784367] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.784398] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.784431] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.784460] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.784485] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.784587] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.784619] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.784653] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.784684] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.784718] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.784822] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.784848] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.784879] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.784913] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.784939] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.784967] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.784994] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.785022] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.785048] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.785075] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.785100] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.785123] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.785149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.785168] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.785195] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.785221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.785247] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.785273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.785298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.785328] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.785354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.785383] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.785409] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.785436] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.785461] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.785487] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.785513] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.785542] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.785576] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.785603] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.785659] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.785688] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.785716] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.785751] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.785780] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.785817] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.786055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.786082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.786110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.786135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.786162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.786187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.786215] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.786243] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.786270] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.786319] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.786345] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.786471] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.786499] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.786527] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.786554] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.786722] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.786749] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.787377] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.787405] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.787574] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.787601] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.787628] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.787654] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.787822] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.787848] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.787889] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.787913] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.787942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.787970] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.787996] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.788189] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.788216] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.788345] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.788371] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.788534] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.788566] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.788598] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.788628] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.788834] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.788862] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.788891] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.788917] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.788949] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.788976] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.789171] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.789199] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.789626] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.789652] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.789812] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.789838] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.789866] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.789892] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.790093] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.790120] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.790149] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.792189] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.792215] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.792377] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.792403] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.792432] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3290800
>[  711.792781] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.792927] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.792955] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.793019] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.809689] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.809716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.809747] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.809771] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.809796] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.809822] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.809846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.809869] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.809891] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.809907] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.809932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.809947] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.809971] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.809994] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.810017] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.810039] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.810062] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.810091] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.810114] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.810140] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.810163] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.810185] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.810208] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.810230] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.810255] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.810280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.810310] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.810334] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.810376] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.810628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.810652] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.810675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.810698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.810721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.810743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.810766] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.810790] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.810828] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.826349] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  711.826372] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  711.826491] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  711.826517] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  711.826569] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3292800
>[  711.826906] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  711.827679] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.827706] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.827765] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.827826] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.827849] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.827876] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.827905] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.827929] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.827955] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.827979] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.828001] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.828025] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.828047] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.828069] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.828084] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.828108] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.828122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.828146] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.828169] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.828192] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.828214] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.828236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.828262] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.828284] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.828308] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.828331] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.828354] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.828376] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.828399] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.828421] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.828445] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.828471] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.828511] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.828578] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  711.843281] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.843309] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.843481] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.843521] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.843548] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  711.843574] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  711.843608] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  711.843661] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  711.843707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.843733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.843764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.843788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.843813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.843838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.843868] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.843893] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.843917] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.844406] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.844440] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.844468] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.844517] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.844628] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.844659] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.844693] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.844722] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.844750] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.844778] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.844809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.844836] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.844861] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.844883] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.844909] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.844927] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.844954] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.844981] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.845006] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.845035] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.845060] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.845091] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.845116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.845144] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.845170] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.845196] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.845221] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.845247] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.845272] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.845301] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.845340] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.845369] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.845430] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.862924] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.862953] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.862994] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.863048] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.863094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.863121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.863149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.863172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.863195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.863218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.863248] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.863272] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.863299] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.863334] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.863365] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.863398] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.863427] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.863451] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.863478] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.863505] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.863537] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.863565] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.863595] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.863713] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.863737] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.863768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.863801] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.863826] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.863854] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.863879] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.863907] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.863931] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.863954] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.863977] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.863999] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.864022] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.864037] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.864061] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.864084] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.864109] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.864132] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.864155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.864185] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.864208] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.864238] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.864263] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.864287] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.864312] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.864337] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.864361] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.864389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.864422] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.864449] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.864585] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.864618] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.864649] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.864684] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.864715] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.864755] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.865002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.865030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.865057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.865082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.865108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.865133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.865160] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.865188] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.865215] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.865262] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.865288] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.865413] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.865442] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.865471] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.865500] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.865667] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.865695] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.866337] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.866364] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.866556] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.866581] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.866607] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.866632] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.866817] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.866842] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.866881] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.866907] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.866932] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.866958] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.866983] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.867177] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.867204] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.867333] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.867359] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.867519] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.867545] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.867572] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.867598] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.867798] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.867824] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.867852] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.867878] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.867906] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.867932] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.868123] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.868150] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.868575] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.868608] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.868772] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.868801] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.868831] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.868858] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.869065] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.869093] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.869124] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.871163] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.871188] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.871369] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.871395] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.871422] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3293000
>[  711.871752] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.871849] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.871876] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.871941] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.888778] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.888809] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.888841] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.888865] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.888895] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.888924] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.888953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.888976] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.888999] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.889022] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.889045] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.889059] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.889083] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.889106] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.889131] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.889154] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.889177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.889208] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.889231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.889260] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.889283] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.889308] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.889333] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.889358] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.889383] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.889411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.889448] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.889474] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.889535] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.889793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.889818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.889841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.889864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.889887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.889910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.889936] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.889960] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.889998] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.905435] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  711.905505] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  711.905688] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  711.905753] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  711.905861] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3292800
>[  711.906248] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  711.907206] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.907283] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.907446] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.907621] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.907682] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.907752] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.907827] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.907886] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.907951] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.908016] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.908078] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.908139] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.908200] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.908257] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.908302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.908361] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.908397] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.908458] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.908517] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.908628] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.908692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.908763] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.908842] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.908910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.908983] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.909057] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.909124] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.909196] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.909267] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.909337] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.909416] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.909498] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.909578] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.909721] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  711.922769] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.922838] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.923066] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.923129] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.923194] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  711.923256] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  711.923334] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  711.923430] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  711.923524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.923590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.923657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.923717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.923776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.923835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.923904] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.923967] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.924028] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.940684] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  711.940769] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.940846] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.940923] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.941075] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.941136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.941209] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.941270] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.941335] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.941400] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.941462] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.941520] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.941578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.941624] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.941683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.941719] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.941780] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.941839] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.941898] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.941956] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.942014] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.942081] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.942139] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.942206] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.942265] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.942324] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.942383] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.942441] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.942502] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.942567] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.942653] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.942719] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.942842] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  711.957560] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  711.957629] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  711.957714] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  711.957811] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  711.957904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.957970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.958036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.958096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.958158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.958217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.958284] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.958347] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.958408] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.958484] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  711.958553] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  711.958626] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  711.958693] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  711.958755] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  711.958819] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.958885] [drm:intel_power_well_disable [i915]] disabling DC off
>[  711.958955] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  711.959021] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  711.959086] [drm:intel_power_well_disable [i915]] disabling always-on
>[  711.959293] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  711.959354] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.959424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  711.959501] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  711.959560] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  711.959627] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.959689] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  711.959754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  711.959816] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  711.959875] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  711.959932] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.959977] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.960036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.960073] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  711.960135] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  711.960194] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  711.960252] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  711.960311] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.960368] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.960440] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.960498] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.960624] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.960696] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.960767] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  711.960835] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  711.960903] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  711.960972] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  711.961050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.961135] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  711.961205] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  711.961341] [drm:intel_power_well_enable [i915]] enabling always-on
>[  711.961408] [drm:intel_power_well_enable [i915]] enabling DC off
>[  711.961476] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  711.961557] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  711.961623] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  711.961703] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  711.962006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.962073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.962138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.962199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.962262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.962326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.962394] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.962457] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.962522] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  711.962630] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  711.962695] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  711.962873] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  711.962942] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  711.963014] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.963082] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.963298] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.963366] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.964036] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.964106] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.964323] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.964390] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.964459] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.964526] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.964842] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.964909] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.964993] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  711.965056] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  711.965124] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  711.965194] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.965261] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.965503] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.965571] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.965742] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.965807] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.966013] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.966081] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.966147] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.966209] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.966454] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.966519] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.966585] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  711.966646] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  711.966715] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.966777] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.967015] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.967080] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.967546] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.967611] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.967814] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.967879] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.967945] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.968007] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.968252] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.968317] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.968384] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  711.970468] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  711.970530] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  711.970733] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  711.970796] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  711.970864] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3296800
>[  711.971238] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  711.971421] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  711.971489] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  711.971600] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.988359] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  711.988431] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  711.988505] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  711.988649] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  711.988727] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  711.988809] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  711.988876] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  711.988940] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  711.989005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  711.989053] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.989118] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  711.989157] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  711.989224] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  711.989287] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  711.989351] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  711.989416] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  711.989479] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  711.989554] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  711.989617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  711.989685] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  711.989749] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  711.989813] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  711.989872] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  711.989935] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  711.989999] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  711.990072] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  711.990162] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  711.990226] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  711.990398] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  711.990680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  711.990743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  711.990806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  711.990867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  711.990928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  711.990989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  711.991054] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  711.991117] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  711.991195] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.004966] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  712.005035] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  712.005219] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  712.005284] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  712.005392] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3292800
>[  712.005778] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  712.006720] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  712.006796] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  712.006960] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.007136] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  712.007197] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.007268] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  712.007343] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  712.007402] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  712.007467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.007531] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  712.007594] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  712.007655] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  712.007713] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  712.007770] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.007816] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  712.007874] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.007911] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  712.007972] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  712.008030] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  712.008089] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  712.008146] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.008204] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.008275] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.008333] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.008398] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  712.008457] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  712.008516] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  712.008608] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  712.008682] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  712.008751] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  712.008827] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.008913] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  712.008984] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  712.009128] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  712.021527] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.021596] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.021819] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.021882] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.021948] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  712.022010] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  712.022089] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  712.022184] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  712.022278] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.022344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.022410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.022470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.022530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.022589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.022657] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.022721] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.022782] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.023522] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  712.023608] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  712.023684] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  712.023761] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.023917] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  712.023978] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.024049] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  712.024109] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  712.024174] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.024239] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  712.024303] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  712.024361] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  712.024419] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.024466] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.024524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.024661] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.024734] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  712.024798] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  712.024863] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  712.024933] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.025001] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.025082] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.025147] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.025220] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  712.025287] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  712.025356] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  712.025421] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  712.025485] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  712.025543] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  712.025610] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.025695] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  712.025758] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  712.025884] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  712.041075] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  712.041144] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  712.041229] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  712.041324] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  712.041419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.041485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.041549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.041609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.041669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.041728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.041797] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.041862] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.041923] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.042000] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  712.042070] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  712.042143] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  712.042211] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  712.042273] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  712.042337] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.042404] [drm:intel_power_well_disable [i915]] disabling DC off
>[  712.042470] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  712.042536] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  712.042601] [drm:intel_power_well_disable [i915]] disabling always-on
>[  712.042815] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  712.042875] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.042946] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  712.043023] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  712.043083] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  712.043149] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.043212] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  712.043277] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  712.043339] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  712.043399] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  712.043456] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.043501] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  712.043560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.043598] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  712.043660] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  712.043719] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  712.043778] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  712.043836] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.043894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.043966] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.044024] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.044090] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  712.044150] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  712.044209] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  712.044269] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  712.044329] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  712.044388] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  712.044454] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.044528] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  712.044649] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  712.044779] [drm:intel_power_well_enable [i915]] enabling always-on
>[  712.044851] [drm:intel_power_well_enable [i915]] enabling DC off
>[  712.044926] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  712.045011] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  712.045082] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  712.045170] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  712.045456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.045522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.045593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.045655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.045719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.045782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.045848] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.045914] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.045979] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.046080] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  712.046146] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  712.046326] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  712.046395] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  712.046465] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.046530] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.046750] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.046822] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.047491] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.047562] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.047781] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.047848] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.047918] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.047982] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.048199] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.048267] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.048351] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  712.048414] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  712.048479] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  712.048573] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.048651] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.048897] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.048966] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.049136] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.049203] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.049412] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.049480] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.049549] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.049613] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.049862] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.049930] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.049999] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  712.050062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  712.050130] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.050199] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.050441] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.050509] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.050975] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.051041] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.051237] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.051295] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.051352] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.051406] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.051642] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.051699] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.051756] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  712.053829] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.053881] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.054077] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.054129] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.054185] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b66de800
>[  712.054547] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  712.054723] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  712.054778] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  712.054876] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.071641] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  712.071701] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.071763] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  712.071813] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  712.071869] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.071927] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  712.071983] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  712.072032] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  712.072080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.072120] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.072171] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.072201] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.072252] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  712.072301] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  712.072350] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  712.072398] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.072445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.072507] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.072646] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.072705] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  712.072769] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  712.072824] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  712.072880] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  712.072935] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  712.072986] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  712.073044] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.073118] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  712.073172] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  712.073294] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  712.073566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.073620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.073673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.073725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.073775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.073826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.073881] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.073936] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.074005] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.088253] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  712.088311] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  712.088481] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  712.088611] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  712.088711] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b66de000
>[  712.089085] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  712.089994] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  712.090056] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  712.090153] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.106798] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  712.106866] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.106939] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[  712.107016] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  712.107075] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  712.107142] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.107209] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  712.107276] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  712.107337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  712.107396] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  712.107453] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.107499] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  712.107558] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.107595] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  712.107657] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0xa
>[  712.107716] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  712.107774] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  712.107832] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.107889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.107959] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.108017] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.108083] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  712.108142] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  712.108201] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  712.108259] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  712.108316] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  712.108375] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  712.108441] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.108515] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  712.108619] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  712.108783] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  712.123236] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.123309] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.123614] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.123689] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.123764] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  712.123835] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  712.123923] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  712.124027] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  712.124132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.124207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.124281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.124349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.124415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.124482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.124627] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.124753] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.124827] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.140193] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  712.140289] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  712.140375] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  712.140461] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.140750] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  712.140825] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.140909] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  712.140981] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  712.141058] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.141133] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  712.141208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  712.141280] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  712.141350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.141404] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.141476] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.141522] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.141596] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  712.141667] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  712.141738] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  712.141809] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.141880] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.141962] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.142034] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.142112] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  712.142183] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  712.142254] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  712.142321] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  712.142391] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  712.142462] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  712.142540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.142639] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  712.142713] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  712.142851] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  712.156844] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  712.156913] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  712.156999] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  712.157094] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  712.157188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.157253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.157316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.157376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.157435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.157493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.157559] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.157624] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.157685] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.157764] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  712.157832] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  712.157904] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  712.157971] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  712.158034] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  712.158097] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.158164] [drm:intel_power_well_disable [i915]] disabling DC off
>[  712.158234] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  712.158300] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  712.158365] [drm:intel_power_well_disable [i915]] disabling always-on
>[  712.158593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.158684] [drm:intel_power_well_enable [i915]] enabling always-on
>[  712.158745] [drm:intel_power_well_enable [i915]] enabling DC off
>[  712.158807] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  712.158880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.158940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.158999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.159057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.159115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.159172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.159233] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  712.159293] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  712.159351] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.159411] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.159469] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.159533] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  712.159593] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  712.159658] [drm:intel_power_well_disable [i915]] disabling DC off
>[  712.159723] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  712.159788] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  712.159853] [drm:intel_power_well_disable [i915]] disabling always-on
>[  712.161673] [IGT] kms_flip: exiting, ret=0
>[  712.213279] [drm:intel_atomic_check [i915]] [CONNECTOR:60:eDP-1] checking for sink bpp constrains
>[  712.213356] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.213439] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[  712.213524] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  712.213590] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[  712.213666] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.213740] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[  712.213813] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  712.213883] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[  712.213950] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  712.214015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.214063] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  712.214130] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.214171] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  712.214240] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[  712.214308] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[  712.214376] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  712.214442] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.214506] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.214587] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.214652] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.214721] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  712.214786] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  712.214851] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1
>[  712.214916] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 4A] disabled, scaler_id = -1
>[  712.214980] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  712.215052] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>[  712.215120] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.215192] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[  712.215270] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  712.215335] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[  712.215403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.215470] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  712.215535] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  712.215602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[  712.215666] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  712.215730] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.215772] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  712.215837] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.215877] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  712.215945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[  712.216010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[  712.216077] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  712.216141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.216221] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.216295] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.216360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.216425] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] disabled, scaler_id = -1
>[  712.216490] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>[  712.216626] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>[  712.216691] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>[  712.216756] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>[  712.216830] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>[  712.216898] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  712.216976] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>[  712.217044] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpc to 24 for HDMI
>[  712.217112] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  712.217179] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>[  712.217243] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[  712.217307] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>[  712.217371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  712.217412] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.217476] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  712.217517] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.217584] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  712.217650] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>[  712.217715] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[  712.217779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  712.217843] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  712.217917] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  712.217981] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  712.218045] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] disabled, scaler_id = -1
>[  712.218109] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[  712.218173] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>[  712.218237] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>[  712.218301] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>[  712.218375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.218464] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe A] using pre-allocated PORT PLL A
>[  712.218535] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  712.218604] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>[  712.218671] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>[  712.218751] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>[  712.218816] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>[  712.218975] [drm:intel_power_well_enable [i915]] enabling always-on
>[  712.219032] [drm:intel_power_well_enable [i915]] enabling DC off
>[  712.219095] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  712.219161] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  712.219317] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  712.219375] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  712.219445] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  712.219626] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>[  712.219803] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  712.219858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  712.219912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  712.219966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  712.220018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  712.220070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  712.220130] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.220185] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.220239] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.220328] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 36
>[  712.220382] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  712.220594] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  712.220654] [drm:skl_set_power_well [i915]] Enabling AUX A
>[  712.220714] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  712.220769] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  712.220832] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  712.220885] [drm:wait_panel_status [i915]] Wait complete
>[  712.220938] [drm:edp_panel_on [i915]] Wait for panel power on
>[  712.220993] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  712.323124] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  712.323203] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  712.323277] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  712.323388] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  712.423083] [drm:wait_panel_status [i915]] Wait complete
>[  712.423164] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  712.423238] [drm:skl_set_power_well [i915]] Disabling AUX A
>[  712.423315] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  712.423384] [drm:skl_set_power_well [i915]] Enabling DDI A IO power well
>[  712.423458] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  712.423526] [drm:skl_set_power_well [i915]] Enabling AUX A
>[  712.423608] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  712.423684] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  712.424914] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  712.424986] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  712.425057] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  712.425715] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  712.425781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  712.426727] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  712.426955] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b6e45000
>[  712.427379] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  712.427461] [drm:intel_edp_backlight_on.part.24 [i915]] 
>[  712.427528] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  712.427599] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 67764
>[  712.432661] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  712.432728] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  712.432895] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>[  712.432959] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>[  712.433132] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  712.433195] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  712.433261] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.433323] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.433530] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.433593] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.434256] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.434318] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.434529] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.434594] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.434657] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.434719] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.434931] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.434993] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.435069] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  712.435127] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  712.435186] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  712.435250] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.435313] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.435547] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.435609] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.435772] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.435834] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.436034] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.436096] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.436160] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.436221] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.436463] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.436525] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.436620] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  712.436678] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  712.436772] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.436834] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.437074] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.437136] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.437597] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.437658] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.437862] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.437924] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.437987] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.438049] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.438294] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.438356] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.438418] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  712.440517] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.440597] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.440800] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.440862] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.440933] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b6e44000
>[  712.441302] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  712.441485] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>[  712.441546] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>[  712.441715] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[  712.441777] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[  712.441877] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b6e44800
>[  712.442255] [drm:intel_enable_pipe [i915]] enabling pipe C
>[  712.459952] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:60:eDP-1]
>[  712.460042] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[  712.460220] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  712.460392] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  712.460468] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  712.460722] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  712.460916] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  712.460990] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  712.461099] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  712.461622] Console: switching to colour frame buffer device 240x67
>[  712.615282] Console: switching to colour dummy device 80x25
>[  712.615333] [IGT] kms_flip: executing
>[  712.653002] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:eDP-1]
>[  712.653090] [drm:intel_dp_detect [i915]] [CONNECTOR:60:eDP-1]
>[  712.653172] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  712.653246] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  712.653314] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  712.653380] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  712.653850] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41
>[  712.654370] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  712.654394] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:60:eDP-1] probed modes :
>[  712.654441] [drm:drm_mode_debug_printmodeline [drm]] Modeline 61:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  712.654476] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:68:DP-1]
>[  712.654545] [drm:intel_dp_detect [i915]] [CONNECTOR:68:DP-1]
>[  712.654618] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  712.654728] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  712.655209] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[  712.655598] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>[  712.655665] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>[  712.655729] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  712.655793] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  712.656242] [drm:intel_dp_read_desc [i915]] DP sink: OUI 00-00-00(NS) dev-ID  HW-rev 0.0 SW-rev 0.0
>[  712.656309] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  712.657266] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  712.657344] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  712.657425] [drm:drm_edid_to_eld [drm]] ELD: no CEA Extension found
>[  712.657463] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:68:DP-1] probed modes :
>[  712.657506] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[  712.657545] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[  712.657585] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[  712.657621] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  712.657657] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  712.657696] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  712.657731] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  712.657770] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[  712.657808] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  712.657843] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  712.657880] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  712.657919] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  712.657961] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:72:HDMI-A-1]
>[  712.658031] [drm:intel_hdmi_detect [i915]] [CONNECTOR:72:HDMI-A-1]
>[  712.660204] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  712.660269] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  712.662522] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[  712.662570] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[  712.664964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  712.665031] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[  712.667392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[  712.667420] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  712.667442] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:72:HDMI-A-1] disconnected
>[  712.667498] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:75:HDMI-A-2]
>[  712.667566] [drm:intel_hdmi_detect [i915]] [CONNECTOR:75:HDMI-A-2]
>[  712.745828] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  712.745901] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  712.748265] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  712.748296] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  712.748345] [drm:drm_rgb_quant_range_selectable [drm]] CEA VCDB 0x2b
>[  712.748654] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[  712.748693] [drm:drm_edid_to_eld [drm]] ELD monitor HP E232
>[  712.748734] [drm:drm_edid_to_eld [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  712.748774] [drm:drm_edid_to_eld [drm]] ELD size 28, SAD count 0
>[  712.748833] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:75:HDMI-A-2] probed modes :
>[  712.748876] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  712.748917] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  712.748954] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  712.748993] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  712.749029] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  712.749067] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  712.749107] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  712.749145] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  712.749180] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  712.749218] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  712.749254] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  712.749294] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  712.749329] [drm:drm_mode_debug_printmodeline [drm]] Modeline 102:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  712.749368] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  712.749406] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  712.749444] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  712.749480] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  712.749521] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  712.749944] [IGT] kms_flip: starting subtest blt-wf_vblank-vs-dpms
>[  712.750456] [drm:drm_mode_addfb2 [drm]] [FB:62]
>[  712.750526] [drm:drm_mode_addfb2 [drm]] [FB:108]
>[  712.823122] [drm:drm_mode_setcrtc [drm]] [CRTC:36:pipe A]
>[  712.823181] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  712.823254] [drm:intel_edp_backlight_off.part.25 [i915]] 
>[  713.028785] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  713.028889] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  713.044437] [drm:intel_edp_panel_off.part.23 [i915]] Turn eDP port A panel power off
>[  713.044513] [drm:intel_edp_panel_off.part.23 [i915]] Wait for panel power off time
>[  713.044687] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  713.096520] [drm:wait_panel_status [i915]] Wait complete
>[  713.096654] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  713.096730] [drm:skl_set_power_well [i915]] Disabling AUX A
>[  713.096804] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  713.096875] [drm:skl_set_power_well [i915]] Disabling DDI A IO power well
>[  713.096961] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 36
>[  713.097064] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  713.097168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  713.097243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  713.097312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  713.097379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  713.097445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  713.097511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  713.097587] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  713.097668] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  713.097739] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:60:eDP-1]
>[  713.097817] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  713.097886] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  713.097957] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  713.098033] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  713.098594] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  713.109790] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  713.109883] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[  713.109983] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  713.110090] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  713.110228] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  713.127476] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  713.127553] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  713.127792] [drm:intel_power_well_disable [i915]] disabling AUX B
>[  713.127863] [drm:skl_set_power_well [i915]] Disabling AUX B
>[  713.127936] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  713.128005] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  713.128104] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>[  713.128207] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>[  713.128312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  713.128386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  713.128459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  713.128527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  713.128679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  713.128751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  713.128838] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:68:DP-1]
>[  713.128925] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  713.129005] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  713.129084] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  713.143279] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>[  713.143377] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  713.143483] [drm:drm_mode_setcrtc [drm]] [CRTC:58:pipe C]
>[  713.143594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  713.143727] [drm:intel_disable_pipe [i915]] disabling pipe C
>[  713.160938] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[  713.161016] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[  713.161111] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>[  713.161215] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>[  713.161318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  713.161392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  713.161466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  713.161533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  713.161599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  713.161664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  713.161739] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:75:HDMI-A-2]
>[  713.161811] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  713.161879] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  713.161947] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  713.162033] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>[  713.162110] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  713.162192] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  713.162268] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>[  713.162343] [drm:intel_power_well_disable [i915]] disabling DC off
>[  713.162421] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  713.162494] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  713.162566] [drm:intel_power_well_disable [i915]] disabling always-on
>[  713.162658] [drm:drm_mode_setcrtc [drm]] [CRTC:36:pipe A]
>[  713.162704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:60:eDP-1]
>[  713.162808] [drm:intel_atomic_check [i915]] [CONNECTOR:60:eDP-1] checking for sink bpp constrains
>[  713.162876] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  713.162954] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[  713.163039] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  713.163106] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[  713.163179] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  713.163250] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[  713.163323] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  713.163392] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[  713.163458] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  713.163522] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  713.163568] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  713.163634] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  713.163675] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  713.163745] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[  713.163811] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[  713.163880] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  713.163947] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  713.164012] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  713.164091] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  713.164156] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  713.164227] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  713.164293] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  713.164360] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1
>[  713.164428] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 4A] disabled, scaler_id = -1
>[  713.164495] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  713.164642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  713.164736] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe A] using pre-allocated PORT PLL A
>[  713.164821] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  713.165231] [drm:intel_power_well_enable [i915]] enabling always-on
>[  713.165296] [drm:intel_power_well_enable [i915]] enabling DC off
>[  713.165365] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  713.165441] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>[  713.165605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  713.165669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  713.165734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  713.165797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  713.165859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  713.165920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  713.165986] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  713.166052] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  713.166116] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  713.166216] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 36
>[  713.166280] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>[  713.166541] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  713.166610] [drm:skl_set_power_well [i915]] Enabling AUX A
>[  713.166679] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  713.166747] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  713.572854] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>[  713.624152] [drm:wait_panel_status [i915]] Wait complete
>[  713.624231] [drm:edp_panel_on [i915]] Wait for panel power on
>[  713.624309] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  713.726339] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  713.726424] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  713.726499] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  713.726919] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  713.824788] [drm:wait_panel_status [i915]] Wait complete
>[  713.824868] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  713.824943] [drm:skl_set_power_well [i915]] Disabling AUX A
>[  713.825019] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  713.825089] [drm:skl_set_power_well [i915]] Enabling DDI A IO power well
>[  713.825162] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  713.825231] [drm:skl_set_power_well [i915]] Enabling AUX A
>[  713.825313] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  713.825390] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  713.826590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  713.826658] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  713.826727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  713.827387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  713.827453] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  713.828408] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  713.828786] [drm:skylake_pfit_enable [i915]] for crtc_state = ffff8c69b3292000
>[  713.829213] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  713.829299] [drm:intel_edp_backlight_on.part.24 [i915]] 
>[  713.829373] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  713.829443] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 67764
>[  713.836676] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>[  713.836744] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[  713.846241] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:60:eDP-1]
>[  713.846323] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[  713.846464] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  713.879748] [drm:intel_atomic_check [i915]] [CONNECTOR:60:eDP-1] checking for sink bpp constrains
>[  713.879827] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  713.879911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[  713.879996] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  713.880063] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[  713.880138] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  713.880212] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[  713.880285] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  713.880355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[  713.880422] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  713.880488] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  713.880625] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  713.880705] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  713.880760] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  713.880839] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[  713.880915] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[  713.880995] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  713.881070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  713.881144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  713.881224] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  713.881301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  713.881372] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  713.881443] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  713.881511] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  713.881582] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1
>[  713.881654] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 4A] disabled, scaler_id = -1
>[  713.881723] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  713.881802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  713.881889] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe A] using pre-allocated PORT PLL A
>[  713.881962] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  713.882102] [drm:intel_edp_backlight_off.part.25 [i915]] 
>[  714.088802] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  714.088905] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  714.097244] [drm:intel_edp_panel_off.part.23 [i915]] Turn eDP port A panel power off
>[  714.097321] [drm:intel_edp_panel_off.part.23 [i915]] Wait for panel power off time
>[  714.097397] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>[  714.149184] [drm:wait_panel_status [i915]] Wait complete
>[  714.149267] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  714.149342] [drm:skl_set_power_well [i915]] Disabling AUX A
>[  714.149416] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  714.149486] [drm:skl_set_power_well [i915]] Disabling DDI A IO power well
>[  714.149580] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 36
>[  714.149681] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>[  714.149785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>[  714.149859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>[  714.149931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>[  714.149998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>[  714.150066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>[  714.150133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>[  714.150210] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  714.150281] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL B
>[  714.150365] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>[  714.150436] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  714.150506] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  714.150602] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  714.150681] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL C
>[  714.150767] [drm:intel_power_well_disable [i915]] disabling dpio-common-a
>[  714.150846] [drm:verify_connector_state.isra.78 [i915]] [CONNECTOR:60:eDP-1]
>[  714.150916] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[  714.150992] [drm:verify_single_dpll_state.isra.106 [i915]] PORT PLL A
>[  714.151067] [drm:intel_power_well_disable [i915]] disabling DC off
>[  714.151146] [drm:gen9_enable_dc5 [i915]] Enabling DC5
>[  714.151219] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 01
>[  714.151292] [drm:intel_power_well_disable [i915]] disabling always-on
>[  714.151939] [drm:intel_atomic_check [i915]] [CONNECTOR:60:eDP-1] checking for sink bpp constrains
>[  714.152009] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  714.152085] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>[  714.152169] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  714.152235] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>[  714.152306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  714.152376] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[  714.152444] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  714.152512] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>[  714.152656] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  714.152723] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  714.152780] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  714.152849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  714.152895] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[  714.152970] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>[  714.153040] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>[  714.153112] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  714.153181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  714.153251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  714.153330] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>[  714.153400] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  714.153473] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:108, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  714.153546] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  714.153615] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  714.153685] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1
>[  714.153754] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 4A] disabled, scaler_id = -1
>[  714.153828] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  714.153906] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>[  714.153991] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe A] using pre-allocated PORT PLL A
>[  714.154063] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>[  714.643013] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000010, dig 0x18001819, pins 0x00000020
>[  714.643096] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  714.643247] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  714.643329] [drm:intel_power_well_enable [i915]] enabling always-on
>[  714.643404] [drm:intel_power_well_enable [i915]] enabling DC off
>[  714.643480] [drm:gen9_set_dc_state [i915]] Setting DC state from 01 to 00
>[  714.643561] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  714.643635] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  714.643723] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>[  714.644258] [drm:intel_power_well_enable [i915]] enabling AUX B
>[  714.644329] [drm:skl_set_power_well [i915]] Enabling AUX B
>[  714.644922] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 03 00 00 00
>[  717.828787] [drm:missed_breadcrumb [i915]] blitter ring missed breadcrumb at intel_breadcrumbs_hangcheck+0x61/0x80 [i915], irq posted? yes
>[  723.823486] [drm] GPU HANG: ecode 9:1:0xe77ffef6, in kms_flip [1783], reason: Hang on blitter ring, action: reset
>[  723.823490] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
>[  723.823491] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
>[  723.823493] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
>[  723.823494] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
>[  723.823496] [drm] GPU crash dump saved to /sys/class/drm/card0/error
>[  723.823683] [drm:i915_reset_and_wakeup [i915]] resetting chip
>[  724.964587] asynchronous wait on fence i915:kms_flip[1783]/0:a timed out
>[  733.775052] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  733.775137] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  733.972483] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  733.972567] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  737.791425] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  737.791508] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 0
>[  737.988540] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000020, dig 0x18001a18, pins 0x00000040
>[  737.988625] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 6 - cnt: 1
>[  846.820617] INFO: task kworker/u8:0:5 blocked for more than 120 seconds.
>[  846.820630]       Tainted: G     U          4.10.0-drm-tip-28b9323-glk-dmc-104+ #1
>[  846.820634] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
>[  846.820639] kworker/u8:0    D    0     5      2 0x00000000
>[  846.820738] Workqueue: i915-dp i915_digport_work_func [i915]
>[  846.820742] Call Trace:
>[  846.820759]  __schedule+0x28c/0x8f0
>[  846.820766]  schedule+0x36/0x80
>[  846.820771]  schedule_preempt_disabled+0xe/0x10
>[  846.820777]  __ww_mutex_lock.isra.6+0x3c7/0x6a0
>[  846.820784]  __ww_mutex_lock_slowpath+0x16/0x20
>[  846.820787]  ww_mutex_lock+0x37/0x70
>[  846.820832]  drm_modeset_lock+0x91/0xd0 [drm]
>[  846.820907]  intel_dp_hpd_pulse+0x1f6/0x310 [i915]
>[  846.820980]  i915_digport_work_func+0x95/0x110 [i915]
>[  846.820988]  process_one_work+0x16b/0x480
>[  846.820993]  worker_thread+0x4b/0x500
>[  846.821000]  kthread+0x101/0x140
>[  846.821005]  ? process_one_work+0x480/0x480
>[  846.821010]  ? kthread_create_on_node+0x60/0x60
>[  846.821015]  ret_from_fork+0x2c/0x40
>[  846.821026] INFO: task kworker/2:0:23 blocked for more than 120 seconds.
>[  846.821031]       Tainted: G     U          4.10.0-drm-tip-28b9323-glk-dmc-104+ #1
>[  846.821034] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
>[  846.821038] kworker/2:0     D    0    23      2 0x00000000
>[  846.821119] Workqueue: events_long i915_hangcheck_elapsed [i915]
>[  846.821122] Call Trace:
>[  846.821129]  __schedule+0x28c/0x8f0
>[  846.821136]  schedule+0x36/0x80
>[  846.821141]  schedule_preempt_disabled+0xe/0x10
>[  846.821146]  __mutex_lock.isra.5+0x266/0x4e0
>[  846.821154]  __mutex_lock_slowpath+0x13/0x20
>[  846.821159]  mutex_lock+0x2f/0x40
>[  846.821235]  intel_prepare_reset+0x24/0x120 [i915]
>[  846.821303]  i915_reset_and_wakeup+0xb7/0x190 [i915]
>[  846.821373]  i915_handle_error+0x1b0/0x230 [i915]
>[  846.821381]  ? scnprintf+0x4d/0x90
>[  846.821456]  hangcheck_declare_hang+0xda/0x110 [i915]
>[  846.821528]  i915_hangcheck_elapsed+0x2a9/0x2d0 [i915]
>[  846.821534]  process_one_work+0x16b/0x480
>[  846.821539]  worker_thread+0x4b/0x500
>[  846.821545]  kthread+0x101/0x140
>[  846.821549]  ? process_one_work+0x480/0x480
>[  846.821554]  ? kthread_create_on_node+0x60/0x60
>[  846.821559]  ret_from_fork+0x2c/0x40
>[  846.821619] INFO: task kms_flip:1783 blocked for more than 120 seconds.
>[  846.821624]       Tainted: G     U          4.10.0-drm-tip-28b9323-glk-dmc-104+ #1
>[  846.821627] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
>[  846.821631] kms_flip        D    0  1783      1 0x00000004
>[  846.821636] Call Trace:
>[  846.821643]  __schedule+0x28c/0x8f0
>[  846.821716]  ? intel_prepare_plane_fb+0x237/0x290 [i915]
>[  846.821723]  schedule+0x36/0x80
>[  846.821795]  intel_atomic_commit+0x3d8/0x510 [i915]
>[  846.821832]  ? drm_property_free_blob+0x70/0x80 [drm]
>[  846.821838]  ? wake_atomic_t_function+0x60/0x60
>[  846.821877]  drm_atomic_commit+0x4b/0x50 [drm]
>[  846.821899]  drm_atomic_helper_connector_dpms+0xfd/0x1d0 [drm_kms_helper]
>[  846.821937]  drm_mode_connector_set_obj_prop+0x62/0x70 [drm]
>[  846.821972]  drm_mode_obj_set_property_ioctl+0x11b/0x160 [drm]
>[  846.822006]  drm_mode_connector_property_set_ioctl+0x3f/0x60 [drm]
>[  846.822042]  drm_ioctl+0x1ff/0x460 [drm]
>[  846.822076]  ? drm_mode_connector_set_obj_prop+0x70/0x70 [drm]
>[  846.822085]  ? hrtimer_start_range_ns+0x1bf/0x390
>[  846.822093]  do_vfs_ioctl+0xa1/0x5d0
>[  846.822099]  ? SyS_timer_settime+0x14f/0x1e0
>[  846.822104]  SyS_ioctl+0x79/0x90
>[  846.822110]  entry_SYSCALL_64_fastpath+0x1e/0xad
>[  846.822115] RIP: 0033:0x7f614d6658b7
>[  846.822117] RSP: 002b:00007fff29174be8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
>[  846.822122] RAX: ffffffffffffffda RBX: 0000000000000003 RCX: 00007f614d6658b7
>[  846.822124] RDX: 00007fff29174c20 RSI: 00000000c01064ab RDI: 0000000000000003
>[  846.822127] RBP: 00007fff29174b30 R08: 00007fff29174c10 R09: 0000000000000000
>[  846.822129] R10: 0000000000000000 R11: 0000000000000246 R12: 0000000040406469
>[  846.822131] R13: 0000000000000003 R14: 0000000000000003 R15: 0000000000000009

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