Attachment 130650 Details for Bug 100531 – possible fix

[patch] possible fix

0001-radeonsi-fix-broken-texture-filtering-on-SIK-CIK-sin.patch (text/plain), 1.95 KB, created by Marek Olšák on 2017-04-02 22:34:03 UTC

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Creator: Marek Olšák

Created: 2017-04-02 22:34:03 UTC

Size: 1.95 KB

patch

obsolete

>From aa50c311072ea121f21ba21ec38dbacef11be441 Mon Sep 17 00:00:00 2001
>From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= <marek.olsak@amd.com>
>Date: Mon, 3 Apr 2017 00:22:16 +0200
>Subject: [PATCH] radeonsi: fix broken texture filtering on SIK-CIK since GFX9
> changes
>
>Don't clear state[7] on SI-CIK, and only do the meta stuff on VI+.
>---
> src/gallium/drivers/radeonsi/si_descriptors.c | 32 ++++++++++++++-------------
> 1 file changed, 17 insertions(+), 15 deletions(-)
>
>diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
>index 2b91158..8f5a16b 100644
>--- a/src/gallium/drivers/radeonsi/si_descriptors.c
>+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
>@@ -404,26 +404,28 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
> 		va += base_level_info->offset;
> 	}
> 
>-	if (vi_dcc_enabled(tex, first_level)) {
>-		meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
>-			  tex->dcc_offset;
>-
>-		if (sscreen->b.chip_class <= VI)
>-			meta_va += base_level_info->dcc_offset;
>-	} else if (tex->tc_compatible_htile && !is_stencil) {
>-		meta_va = tex->htile_buffer->gpu_address;
>-	}
>-
> 	state[0] = va >> 8;
> 	state[1] &= C_008F14_BASE_ADDRESS_HI;
> 	state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
> 
>-	state[6] &= C_008F28_COMPRESSION_EN;
>-	state[7] = 0;
>+	if (sscreen->b.chip_class >= VI) {
>+		state[6] &= C_008F28_COMPRESSION_EN;
>+		state[7] = 0;
> 
>-	if (meta_va) {
>-		state[6] |= S_008F28_COMPRESSION_EN(1);
>-		state[7] = meta_va >> 8;
>+		if (vi_dcc_enabled(tex, first_level)) {
>+			meta_va = (!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
>+				  tex->dcc_offset;
>+
>+			if (sscreen->b.chip_class <= VI)
>+				meta_va += base_level_info->dcc_offset;
>+		} else if (tex->tc_compatible_htile && !is_stencil) {
>+			meta_va = tex->htile_buffer->gpu_address;
>+		}
>+
>+		if (meta_va) {
>+			state[6] |= S_008F28_COMPRESSION_EN(1);
>+			state[7] = meta_va >> 8;
>+		}
> 	}
> 
> 	if (sscreen->b.chip_class >= GFX9) {
>-- 
>2.7.4
>

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Attachments on bug 100531: 130639 | 130640 | 130641 | 130649 | 130650

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