Attachment 130972 Details for Bug 100755 – next-20170324 with fastboot=1, shows suspend/resume, works fine

next-20170324 with fastboot=1, shows suspend/resume, works fine

dmesg.good.format (text/plain), 79.27 KB, created by Rafael Ristovski on 2017-04-21 19:09:42 UTC

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Creator: Rafael Ristovski

Created: 2017-04-21 19:09:42 UTC

Size: 79.27 KB

patch

obsolete

>[drm:i915_driver_load] Found LynxPoint LP PCH [drm:i915_driver_load] Found LynxPoint LP PCH
>[drm:intel_power_domains_init] Allowed DC state mask 00 [drm:intel_power_domains_init] Allowed DC state mask 00
>[drm:intel_device_info_dump] i915 device info: platform=HASWELL gen=7 pciid=0x0a16 rev=0x09 [drm:intel_device_info_dump] i915 device info: platform=HASWELL gen=7 pciid=0x0a16 rev=0x09
>[drm:intel_device_info_dump] i915 device info: is_mobile: no [drm:intel_device_info_dump] i915 device info: is_mobile: no
>[drm:intel_device_info_dump] i915 device info: is_lp: no [drm:intel_device_info_dump] i915 device info: is_lp: no
>[drm:intel_device_info_dump] i915 device info: is_alpha_support: no [drm:intel_device_info_dump] i915 device info: is_alpha_support: no
>[drm:intel_device_info_dump] i915 device info: has_64bit_reloc: no [drm:intel_device_info_dump] i915 device info: has_64bit_reloc: no
>[drm:intel_device_info_dump] i915 device info: has_aliasing_ppgtt: yes [drm:intel_device_info_dump] i915 device info: has_aliasing_ppgtt: yes
>[drm:intel_device_info_dump] i915 device info: has_csr: no [drm:intel_device_info_dump] i915 device info: has_csr: no
>[drm:intel_device_info_dump] i915 device info: has_ddi: yes [drm:intel_device_info_dump] i915 device info: has_ddi: yes
>[drm:intel_device_info_dump] i915 device info: has_decoupled_mmio: no [drm:intel_device_info_dump] i915 device info: has_decoupled_mmio: no
>[drm:intel_device_info_dump] i915 device info: has_dp_mst: yes [drm:intel_device_info_dump] i915 device info: has_dp_mst: yes
>[drm:intel_device_info_dump] i915 device info: has_fbc: yes [drm:intel_device_info_dump] i915 device info: has_fbc: yes
>[drm:intel_device_info_dump] i915 device info: has_fpga_dbg: yes [drm:intel_device_info_dump] i915 device info: has_fpga_dbg: yes
>[drm:intel_device_info_dump] i915 device info: has_full_ppgtt: yes [drm:intel_device_info_dump] i915 device info: has_full_ppgtt: yes
>[drm:intel_device_info_dump] i915 device info: has_full_48bit_ppgtt: no [drm:intel_device_info_dump] i915 device info: has_full_48bit_ppgtt: no
>[drm:intel_device_info_dump] i915 device info: has_gmbus_irq: yes [drm:intel_device_info_dump] i915 device info: has_gmbus_irq: yes
>[drm:intel_device_info_dump] i915 device info: has_gmch_display: no [drm:intel_device_info_dump] i915 device info: has_gmch_display: no
>[drm:intel_device_info_dump] i915 device info: has_guc: no [drm:intel_device_info_dump] i915 device info: has_guc: no
>[drm:intel_device_info_dump] i915 device info: has_hotplug: yes [drm:intel_device_info_dump] i915 device info: has_hotplug: yes
>[drm:intel_device_info_dump] i915 device info: has_hw_contexts: yes [drm:intel_device_info_dump] i915 device info: has_hw_contexts: yes
>[drm:intel_device_info_dump] i915 device info: has_l3_dpf: yes [drm:intel_device_info_dump] i915 device info: has_l3_dpf: yes
>[drm:intel_device_info_dump] i915 device info: has_llc: yes [drm:intel_device_info_dump] i915 device info: has_llc: yes
>[drm:intel_device_info_dump] i915 device info: has_logical_ring_contexts: no [drm:intel_device_info_dump] i915 device info: has_logical_ring_contexts: no
>[drm:intel_device_info_dump] i915 device info: has_overlay: no [drm:intel_device_info_dump] i915 device info: has_overlay: no
>[drm:intel_device_info_dump] i915 device info: has_pipe_cxsr: no [drm:intel_device_info_dump] i915 device info: has_pipe_cxsr: no
>[drm:intel_device_info_dump] i915 device info: has_pooled_eu: no [drm:intel_device_info_dump] i915 device info: has_pooled_eu: no
>[drm:intel_device_info_dump] i915 device info: has_psr: yes [drm:intel_device_info_dump] i915 device info: has_psr: yes
>[drm:intel_device_info_dump] i915 device info: has_rc6: yes [drm:intel_device_info_dump] i915 device info: has_rc6: yes
>[drm:intel_device_info_dump] i915 device info: has_rc6p: no [drm:intel_device_info_dump] i915 device info: has_rc6p: no
>[drm:intel_device_info_dump] i915 device info: has_resource_streamer: yes [drm:intel_device_info_dump] i915 device info: has_resource_streamer: yes
>[drm:intel_device_info_dump] i915 device info: has_runtime_pm: yes [drm:intel_device_info_dump] i915 device info: has_runtime_pm: yes
>[drm:intel_device_info_dump] i915 device info: has_snoop: no [drm:intel_device_info_dump] i915 device info: has_snoop: no
>[drm:intel_device_info_dump] i915 device info: cursor_needs_physical: no [drm:intel_device_info_dump] i915 device info: cursor_needs_physical: no
>[drm:intel_device_info_dump] i915 device info: hws_needs_physical: no [drm:intel_device_info_dump] i915 device info: hws_needs_physical: no
>[drm:intel_device_info_dump] i915 device info: overlay_needs_physical: no [drm:intel_device_info_dump] i915 device info: overlay_needs_physical: no
>[drm:intel_device_info_dump] i915 device info: supports_tv: no [drm:intel_device_info_dump] i915 device info: supports_tv: no
>[drm:intel_device_info_runtime_init] slice mask: 0000 [drm:intel_device_info_runtime_init] slice mask: 0000
>[drm:intel_device_info_runtime_init] slice total: 0 [drm:intel_device_info_runtime_init] slice total: 0
>[drm:intel_device_info_runtime_init] subslice total: 0 [drm:intel_device_info_runtime_init] subslice total: 0
>[drm:intel_device_info_runtime_init] subslice mask 0000 [drm:intel_device_info_runtime_init] subslice mask 0000
>[drm:intel_device_info_runtime_init] subslice per slice: 0 [drm:intel_device_info_runtime_init] subslice per slice: 0
>[drm:intel_device_info_runtime_init] EU total: 0 [drm:intel_device_info_runtime_init] EU total: 0
>[drm:intel_device_info_runtime_init] EU per subslice: 0 [drm:intel_device_info_runtime_init] EU per subslice: 0
>[drm:intel_device_info_runtime_init] has slice power gating: n [drm:intel_device_info_runtime_init] has slice power gating: n
>[drm:intel_device_info_runtime_init] has subslice power gating: n [drm:intel_device_info_runtime_init] has subslice power gating: n
>[drm:intel_device_info_runtime_init] has EU power gating: n [drm:intel_device_info_runtime_init] has EU power gating: n
>[drm:i915_driver_load] ppgtt mode: 1 [drm:i915_driver_load] ppgtt mode: 1
>[drm:i915_driver_load] use GPU semaphores? yes [drm:i915_driver_load] use GPU semaphores? yes
>[drm:i915_ggtt_probe_hw] GMADR size = 256M [drm:i915_ggtt_probe_hw] GMADR size = 256M
>[drm:i915_ggtt_probe_hw] GTT stolen size = 64M [drm:i915_ggtt_probe_hw] GTT stolen size = 64M
>[drm:i915_gem_init_stolen] Memory reserved for graphics device: 65536K, usable: 64512K [drm:i915_gem_init_stolen] Memory reserved for graphics device: 65536K, usable: 64512K
>[drm:intel_opregion_setup] graphic opregion physical addr: 0x9afb2018 [drm:intel_opregion_setup] graphic opregion physical addr: 0x9afb2018
>[drm:intel_opregion_setup] Public ACPI methods supported [drm:intel_opregion_setup] Public ACPI methods supported
>[drm:intel_opregion_setup] SWSCI supported [drm:intel_opregion_setup] SWSCI supported
>[drm:intel_opregion_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483 [drm:intel_opregion_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[drm:intel_opregion_setup] ASLE supported [drm:intel_opregion_setup] ASLE supported
>[drm:intel_opregion_setup] ASLE extension supported [drm:intel_opregion_setup] ASLE extension supported
>[drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (Mailbox #4) [drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[drm:intel_bios_init] Set default to SSC at 120000 kHz [drm:intel_bios_init] Set default to SSC at 120000 kHz
>[drm:intel_bios_init] VBT signature "$VBT HASWELL        ", BDB version 176 [drm:intel_bios_init] VBT signature "$VBT HASWELL        ", BDB version 176
>[drm:intel_bios_init] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 1 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0 [drm:intel_bios_init] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 1 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>[drm:intel_bios_init] crt_ddc_bus_pin: 2 [drm:intel_bios_init] crt_ddc_bus_pin: 2
>[drm:intel_opregion_get_panel_type] Ignoring OpRegion panel type (0) [drm:intel_opregion_get_panel_type] Ignoring OpRegion panel type (0)
>[drm:intel_bios_init] Panel type: 2 (VBT) [drm:intel_bios_init] Panel type: 2 (VBT)
>[drm:intel_bios_init] DRRS supported mode is seamless [drm:intel_bios_init] DRRS supported mode is seamless
>[drm:intel_bios_init] Found panel mode in BIOS VBT tables: [drm:intel_bios_init] Found panel mode in BIOS VBT tables:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 0 69300 1366 1374 1384 1462 768 771 772 790 0x8 0xa [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 0 69300 1366 1374 1384 1462 768 771 772 790 0x8 0xa
>[drm:intel_bios_init] VBT initial LVDS value 200300 [drm:intel_bios_init] VBT initial LVDS value 200300
>[drm:intel_bios_init] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 13, level 255, controller 0 [drm:intel_bios_init] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 13, level 255, controller 0
>[drm:intel_bios_init] Found SDVO panel mode in BIOS VBT tables: [drm:intel_bios_init] Found SDVO panel mode in BIOS VBT tables:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa [drm:drm_mode_debug_printmodeline] Modeline 0:"1600x1200" 0 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x8 0xa
>[drm:intel_bios_init] No SDVO device info is found in VBT [drm:intel_bios_init] No SDVO device info is found in VBT
>[drm:intel_bios_init] DRRS State Enabled:0 [drm:intel_bios_init] DRRS State Enabled:0
>[drm:intel_bios_init] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0 [drm:intel_bios_init] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[drm:intel_bios_init] VBT HDMI level shift for port A: 0 [drm:intel_bios_init] VBT HDMI level shift for port A: 0
>[drm:intel_bios_init] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0 [drm:intel_bios_init] Port B VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[drm:intel_bios_init] VBT HDMI level shift for port B: 7 [drm:intel_bios_init] VBT HDMI level shift for port B: 7
>[drm:intel_dsm_detect] no _DSM method for intel device [drm:intel_dsm_detect] no _DSM method for intel device
>[drm:intel_dsm_detect] no _DSM method for intel device [drm:intel_dsm_detect] no _DSM method for intel device
>[drm:intel_update_rawclk] rawclk rate: 24000 kHz [drm:intel_update_rawclk] rawclk rate: 24000 kHz
>[drm:intel_power_well_enable] enabling always-on [drm:intel_power_well_enable] enabling always-on
>[drm:intel_power_well_enable] enabling display [drm:intel_power_well_enable] enabling display
>[drm:intel_fbc_init] Sanitized enable_fbc value: 0 [drm:intel_fbc_init] Sanitized enable_fbc value: 0
>[drm:intel_print_wm_latency] Primary WM0 latency 20 (2.0 usec) [drm:intel_print_wm_latency] Primary WM0 latency 20 (2.0 usec)
>[drm:intel_print_wm_latency] Primary WM1 latency 4 (2.0 usec) [drm:intel_print_wm_latency] Primary WM1 latency 4 (2.0 usec)
>[drm:intel_print_wm_latency] Primary WM2 latency 36 (18.0 usec) [drm:intel_print_wm_latency] Primary WM2 latency 36 (18.0 usec)
>[drm:intel_print_wm_latency] Primary WM3 latency 90 (45.0 usec) [drm:intel_print_wm_latency] Primary WM3 latency 90 (45.0 usec)
>[drm:intel_print_wm_latency] Primary WM4 latency 160 (80.0 usec) [drm:intel_print_wm_latency] Primary WM4 latency 160 (80.0 usec)
>[drm:intel_print_wm_latency] Sprite WM0 latency 20 (2.0 usec) [drm:intel_print_wm_latency] Sprite WM0 latency 20 (2.0 usec)
>[drm:intel_print_wm_latency] Sprite WM1 latency 4 (2.0 usec) [drm:intel_print_wm_latency] Sprite WM1 latency 4 (2.0 usec)
>[drm:intel_print_wm_latency] Sprite WM2 latency 36 (18.0 usec) [drm:intel_print_wm_latency] Sprite WM2 latency 36 (18.0 usec)
>[drm:intel_print_wm_latency] Sprite WM3 latency 90 (45.0 usec) [drm:intel_print_wm_latency] Sprite WM3 latency 90 (45.0 usec)
>[drm:intel_print_wm_latency] Sprite WM4 latency 160 (80.0 usec) [drm:intel_print_wm_latency] Sprite WM4 latency 160 (80.0 usec)
>[drm:intel_print_wm_latency] Cursor WM0 latency 20 (2.0 usec) [drm:intel_print_wm_latency] Cursor WM0 latency 20 (2.0 usec)
>[drm:intel_print_wm_latency] Cursor WM1 latency 4 (2.0 usec) [drm:intel_print_wm_latency] Cursor WM1 latency 4 (2.0 usec)
>[drm:intel_print_wm_latency] Cursor WM2 latency 36 (18.0 usec) [drm:intel_print_wm_latency] Cursor WM2 latency 36 (18.0 usec)
>[drm:intel_print_wm_latency] Cursor WM3 latency 90 (45.0 usec) [drm:intel_print_wm_latency] Cursor WM3 latency 90 (45.0 usec)
>[drm:intel_print_wm_latency] Cursor WM4 latency 160 (80.0 usec) [drm:intel_print_wm_latency] Cursor WM4 latency 160 (80.0 usec)
>[drm:intel_modeset_init] 3 display pipes available. [drm:intel_modeset_init] 3 display pipes available.
>[drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 0 kHz, ref: 0 kHz [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 0 kHz, ref: 0 kHz
>[drm:intel_update_max_cdclk] Max CD clock rate: 450000 kHz [drm:intel_update_max_cdclk] Max CD clock rate: 450000 kHz
>[drm:intel_update_max_cdclk] Max dotclock rate: 450000 kHz [drm:intel_update_max_cdclk] Max dotclock rate: 450000 kHz
>[drm:intel_dp_init_connector] Adding eDP connector on port A [drm:intel_dp_init_connector] Adding eDP connector on port A
>[drm:intel_dp_init_connector] using AUX A for port A (VBT) [drm:intel_dp_init_connector] using AUX A for port A (VBT)
>[drm:intel_pps_dump_state] cur t1_t3 2000 t8 0 t9 2000 t10 500 t11_t12 6000 [drm:intel_pps_dump_state] cur t1_t3 2000 t8 0 t9 2000 t10 500 t11_t12 6000
>[drm:intel_pps_dump_state] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000 [drm:intel_pps_dump_state] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[drm:intel_dp_init_panel_power_sequencer.part.17] panel power up delay 200, power down delay 50, power cycle delay 600 [drm:intel_dp_init_panel_power_sequencer.part.17] panel power up delay 200, power down delay 50, power cycle delay 600
>[drm:intel_dp_init_panel_power_sequencer.part.17] backlight on delay 1, off delay 200 [drm:intel_dp_init_panel_power_sequencer.part.17] backlight on delay 1, off delay 200
>[drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af06 [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af06
>[drm:edp_panel_vdd_on] Turning eDP port A VDD on [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>[drm:intel_dp_read_dpcd] DPCD: 11 0a 82 01 00 00 01 80 02 00 00 00 00 01 00 [drm:intel_dp_read_dpcd] DPCD: 11 0a 82 01 00 00 01 80 02 00 00 00 00 01 00
>[drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 [drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0
>[drm:drm_edid_to_eld] ELD: no CEA Extension found [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[drm:intel_dp_init_connector] VBT doesn't support DRRS [drm:intel_dp_init_connector] VBT doesn't support DRRS
>[drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, enabled, brightness 937/937 [drm:intel_panel_setup_backlight] Connector eDP-1 backlight initialized, enabled, brightness 937/937
>[drm:intel_hdmi_init_connector] Adding HDMI connector on port B [drm:intel_hdmi_init_connector] Adding HDMI connector on port B
>[drm:intel_hdmi_init_connector] Using DDC pin 0x5 for port B (VBT) [drm:intel_hdmi_init_connector] Using DDC pin 0x5 for port B (VBT)
>[drm:intel_ddi_init] VBT says port C is not DVI/HDMI/DP compatible, respect it [drm:intel_ddi_init] VBT says port C is not DVI/HDMI/DP compatible, respect it
>[drm:intel_set_plane_visible] pipe A active planes 0x0 [drm:intel_set_plane_visible] pipe A active planes 0x0
>[drm:intel_modeset_setup_hw_state] [CRTC:32:pipe A] hw state readout: enabled [drm:intel_modeset_setup_hw_state] [CRTC:32:pipe A] hw state readout: enabled
>[drm:intel_set_plane_visible] pipe B active planes 0x0 [drm:intel_set_plane_visible] pipe B active planes 0x0
>[drm:intel_modeset_setup_hw_state] [CRTC:39:pipe B] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CRTC:39:pipe B] hw state readout: disabled
>[drm:intel_set_plane_visible] pipe C active planes 0x0 [drm:intel_set_plane_visible] pipe C active planes 0x0
>[drm:intel_modeset_setup_hw_state] [CRTC:46:pipe C] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CRTC:46:pipe C] hw state readout: disabled
>[drm:intel_modeset_setup_hw_state] WRPLL 1 hw state readout: crtc_mask 0x00000001, on 1 [drm:intel_modeset_setup_hw_state] WRPLL 1 hw state readout: crtc_mask 0x00000001, on 1
>[drm:intel_modeset_setup_hw_state] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0 [drm:intel_modeset_setup_hw_state] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[drm:intel_modeset_setup_hw_state] SPLL hw state readout: crtc_mask 0x00000000, on 0 [drm:intel_modeset_setup_hw_state] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[drm:intel_modeset_setup_hw_state] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1 [drm:intel_modeset_setup_hw_state] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[drm:intel_modeset_setup_hw_state] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1 [drm:intel_modeset_setup_hw_state] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[drm:intel_modeset_setup_hw_state] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1 [drm:intel_modeset_setup_hw_state] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[drm:intel_modeset_setup_hw_state] [ENCODER:47:DDI A] hw state readout: enabled, pipe A [drm:intel_modeset_setup_hw_state] [ENCODER:47:DDI A] hw state readout: enabled, pipe A
>[drm:intel_modeset_setup_hw_state] [ENCODER:56:DDI B] hw state readout: disabled, pipe A [drm:intel_modeset_setup_hw_state] [ENCODER:56:DDI B] hw state readout: disabled, pipe A
>[drm:intel_modeset_setup_hw_state] [CONNECTOR:48:eDP-1] hw state readout: enabled [drm:intel_modeset_setup_hw_state] [CONNECTOR:48:eDP-1] hw state readout: enabled
>[drm:intel_modeset_setup_hw_state] [CONNECTOR:57:HDMI-A-1] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CONNECTOR:57:HDMI-A-1] hw state readout: disabled
>[drm:intel_dump_pipe_config] [CRTC:32:pipe A][setup_hw_state] [drm:intel_dump_pipe_config] [CRTC:32:pipe A][setup_hw_state]
>[drm:intel_dump_pipe_config] cpu_transcoder: EDP, pipe bpp: 18, dithering: 0 [drm:intel_dump_pipe_config] cpu_transcoder: EDP, pipe bpp: 18, dithering: 0
>[drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2428257, gmch_n: 8388608, link_m: 134903, link_n: 524288, tu: 64 [drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2428257, gmch_n: 8388608, link_m: 134903, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69472 1366 1374 1384 1462 768 771 772 790 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69472 1366 1374 1384 1462 768 771 772 790 0x40 0x9
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69472 1366 1374 1384 1462 768 771 772 790 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69472 1366 1374 1384 1462 768 771 772 790 0x40 0x9
>[drm:intel_dump_pipe_config] crtc timings: 69472 1366 1374 1384 1462 768 771 772 790, type: 0x40 flags: 0x9 [drm:intel_dump_pipe_config] crtc timings: 69472 1366 1374 1384 1462 768 771 772 790, type: 0x40 flags: 0x9
>[drm:intel_dump_pipe_config] port clock: 270000, pipe src size: 720x400, pixel rate 69472 [drm:intel_dump_pipe_config] port clock: 270000, pipe src size: 720x400, pixel rate 69472
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x05560300, enabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x05560300, enabled
>[drm:intel_dump_pipe_config] ips: 0, double wide: 0 [drm:intel_dump_pipe_config] ips: 0, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x90280202 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x90280202 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [CRTC:39:pipe B][setup_hw_state] [drm:intel_dump_pipe_config] [CRTC:39:pipe B][setup_hw_state]
>[drm:intel_dump_pipe_config] cpu_transcoder: B, pipe bpp: 0, dithering: 0 [drm:intel_dump_pipe_config] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0 [drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0, double wide: 0 [drm:intel_dump_pipe_config] ips: 0, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:33:primary B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:33:primary B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:35:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:35:sprite B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:37:cursor B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:37:cursor B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [CRTC:46:pipe C][setup_hw_state] [drm:intel_dump_pipe_config] [CRTC:46:pipe C][setup_hw_state]
>[drm:intel_dump_pipe_config] cpu_transcoder: C, pipe bpp: 0, dithering: 0 [drm:intel_dump_pipe_config] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0 [drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0, double wide: 0 [drm:intel_dump_pipe_config] ips: 0, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:40:primary C] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:40:primary C] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:42:sprite C] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:42:sprite C] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:44:cursor C] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:44:cursor C] disabled, scaler_id = 0
>[drm:intel_modeset_setup_hw_state] LCPLL 810 enabled but not in use, disabling [drm:intel_modeset_setup_hw_state] LCPLL 810 enabled but not in use, disabling
>[drm:intel_modeset_setup_hw_state] LCPLL 1350 enabled but not in use, disabling [drm:intel_modeset_setup_hw_state] LCPLL 1350 enabled but not in use, disabling
>[drm:intel_modeset_setup_hw_state] LCPLL 2700 enabled but not in use, disabling [drm:intel_modeset_setup_hw_state] LCPLL 2700 enabled but not in use, disabling
>[drm:i915_gem_init_ggtt] clearing unused GTT space: [1000, 80000000] [drm:i915_gem_init_ggtt] clearing unused GTT space: [1000, 80000000]
>[drm:i915_ppgtt_create] Allocated pde space (2M) at GTT entry: 7fe00 [drm:i915_ppgtt_create] Allocated pde space (2M) at GTT entry: 7fe00
>[drm:i915_ppgtt_create] Adding PPGTT at offset 7fe00000 [drm:i915_ppgtt_create] Adding PPGTT at offset 7fe00000
>[drm:i915_gem_context_init] HW context support initialized [drm:i915_gem_context_init] HW context support initialized
>[drm:intel_init_ring_buffer] render ring hws offset: 0x00001000 [drm:intel_init_ring_buffer] render ring hws offset: 0x00001000
>[drm:intel_engine_create_scratch] render ring pipe control offset: 0x7fdee000 [drm:intel_engine_create_scratch] render ring pipe control offset: 0x7fdee000
>[drm:intel_init_ring_buffer] blitter ring hws offset: 0x00022000 [drm:intel_init_ring_buffer] blitter ring hws offset: 0x00022000
>[drm:intel_init_ring_buffer] bsd ring hws offset: 0x00043000 [drm:intel_init_ring_buffer] bsd ring hws offset: 0x00043000
>[drm:intel_init_ring_buffer] video enhancement ring hws offset: 0x00064000 [drm:intel_init_ring_buffer] video enhancement ring hws offset: 0x00064000
>[drm:init_workarounds_ring] render ring: Number of context specific w/a: 0 [drm:init_workarounds_ring] render ring: Number of context specific w/a: 0
>[drm:intel_init_gt_powersave] Overclocking supported, max: 1100MHz, overclock: 1100MHz [drm:intel_init_gt_powersave] Overclocking supported, max: 1100MHz, overclock: 1100MHz
>[drm:intel_fbdev_init] pipe A not active or no fb, skipping [drm:intel_fbdev_init] pipe A not active or no fb, skipping
>[drm:intel_fbdev_init] pipe B not active or no fb, skipping [drm:intel_fbdev_init] pipe B not active or no fb, skipping
>[drm:intel_fbdev_init] pipe C not active or no fb, skipping [drm:intel_fbdev_init] pipe C not active or no fb, skipping
>[drm:intel_fbdev_init] no active fbs found, not using BIOS config [drm:intel_fbdev_init] no active fbs found, not using BIOS config
>[drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered [drm:intel_backlight_device_register] Connector eDP-1 backlight sysfs interface registered
>[drm:intel_dp_connector_register] registering DPDDC-A bus for card0-eDP-1 [drm:intel_dp_connector_register] registering DPDDC-A bus for card0-eDP-1
>[drm:intel_opregion_register] 2 outputs detected [drm:intel_opregion_register] 2 outputs detected
>[drm:drm_setup_crtcs]  [drm:drm_setup_crtcs] 
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1]
>[drm:intel_dp_detect] [CONNECTOR:48:eDP-1] [drm:intel_dp_detect] [CONNECTOR:48:eDP-1]
>[drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no
>[drm:intel_dp_print_rates] source rates: 162000, 270000, 540000 [drm:intel_dp_print_rates] source rates: 162000, 270000, 540000
>[drm:intel_dp_print_rates] sink rates: 162000, 270000 [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[drm:intel_dp_print_rates] common rates: 162000, 270000 [drm:intel_dp_print_rates] common rates: 162000, 270000
>[drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 [drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] status updated from unknown to connected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] status updated from unknown to connected
>[drm:drm_edid_to_eld] ELD: no CEA Extension found [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] probed modes : [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] probed modes :
>[drm:drm_mode_debug_printmodeline] Modeline 49:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 49:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9
>[drm:drm_mode_debug_printmodeline] Modeline 50:"1366x768" 40 69300 1366 1374 1384 1786 768 771 772 968 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 50:"1366x768" 40 69300 1366 1374 1384 1786 768 771 772 968 0x40 0x9
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1]
>[drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-1] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-1]
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] status updated from unknown to disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] status updated from unknown to disconnected
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] disconnected
>[drm:drm_setup_crtcs] connector 48 enabled? yes [drm:drm_setup_crtcs] connector 48 enabled? yes
>[drm:drm_setup_crtcs] connector 57 enabled? no [drm:drm_setup_crtcs] connector 57 enabled? no
>[drm:intel_fb_initial_config] Not using firmware configuration [drm:intel_fb_initial_config] Not using firmware configuration
>[drm:drm_setup_crtcs] looking for cmdline mode on connector 48 [drm:drm_setup_crtcs] looking for cmdline mode on connector 48
>[drm:drm_setup_crtcs] looking for preferred mode on connector 48 0 [drm:drm_setup_crtcs] looking for preferred mode on connector 48 0
>[drm:drm_setup_crtcs] found mode 1366x768 [drm:drm_setup_crtcs] found mode 1366x768
>[drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[drm:drm_setup_crtcs] desired mode 1366x768 set on crtc 32 (0,0) [drm:drm_setup_crtcs] desired mode 1366x768 set on crtc 32 (0,0)
>[drm:intelfb_create] no BIOS fb, allocating a new one [drm:intelfb_create] no BIOS fb, allocating a new one
>[drm:intelfb_create] allocated 1366x768 fb: 0x00085000 [drm:intelfb_create] allocated 1366x768 fb: 0x00085000
>[drm:intel_atomic_check] [CONNECTOR:48:eDP-1] checking for sink bpp constrains [drm:intel_atomic_check] [CONNECTOR:48:eDP-1] checking for sink bpp constrains
>[drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 18 [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 18
>[drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 69300KHz [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 69300KHz
>[drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18 [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[drm:intel_dp_compute_config] DP link bw required 155925 available 540000 [drm:intel_dp_compute_config] DP link bw required 155925 available 540000
>[drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 18, dithering: 1 [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[drm:pipe_config_err] mismatch in ips_enabled (expected 0, found 1) [drm:pipe_config_err] mismatch in ips_enabled (expected 0, found 1)
>[drm:intel_dump_pipe_config] [CRTC:32:pipe A][modeset] [drm:intel_dump_pipe_config] [CRTC:32:pipe A][modeset]
>[drm:intel_dump_pipe_config] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1 [drm:intel_dump_pipe_config] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2428257, gmch_n: 8388608, link_m: 134903, link_n: 524288, tu: 64 [drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2428257, gmch_n: 8388608, link_m: 134903, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9
>[drm:intel_dump_pipe_config] crtc timings: 69300 1366 1374 1384 1462 768 771 772 790, type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config] crtc timings: 69300 1366 1374 1384 1462 768 771 772 790, type: 0x48 flags: 0x9
>[drm:intel_dump_pipe_config] port clock: 270000, pipe src size: 1366x768, pixel rate 69300 [drm:intel_dump_pipe_config] port clock: 270000, pipe src size: 1366x768, pixel rate 69300
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 1, double wide: 0 [drm:intel_dump_pipe_config] ips: 1, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x90280202 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x90280202 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0
>[drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A [drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A
>[drm:intel_edp_backlight_off.part.28]  [drm:intel_edp_backlight_off.part.28] 
>[drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[drm:lpt_disable_backlight] cpu backlight was enabled, disabling [drm:lpt_disable_backlight] cpu backlight was enabled, disabling
>[drm:intel_disable_pipe] disabling pipe A [drm:intel_disable_pipe] disabling pipe A
>[drm:intel_edp_panel_off.part.26] Turn eDP port A panel power off [drm:intel_edp_panel_off.part.26] Turn eDP port A panel power off
>[drm:intel_edp_panel_off.part.26] Wait for panel power off time [drm:intel_edp_panel_off.part.26] Wait for panel power off time
>[drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000 [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000
>[drm:wait_panel_status] Wait complete [drm:wait_panel_status] Wait complete
>[drm:intel_disable_shared_dpll] disable WRPLL 1 (active 1, on? 1) for crtc 32 [drm:intel_disable_shared_dpll] disable WRPLL 1 (active 1, on? 1) for crtc 32
>[drm:intel_disable_shared_dpll] disabling WRPLL 1 [drm:intel_disable_shared_dpll] disabling WRPLL 1
>[drm:intel_atomic_commit_tail] [ENCODER:47:DDI A] [drm:intel_atomic_commit_tail] [ENCODER:47:DDI A]
>[drm:intel_atomic_commit_tail] [ENCODER:56:DDI B] [drm:intel_atomic_commit_tail] [ENCODER:56:DDI B]
>[drm:verify_single_dpll_state.isra.114] WRPLL 1 [drm:verify_single_dpll_state.isra.114] WRPLL 1
>[drm:verify_single_dpll_state.isra.114] WRPLL 2 [drm:verify_single_dpll_state.isra.114] WRPLL 2
>[drm:verify_single_dpll_state.isra.114] SPLL [drm:verify_single_dpll_state.isra.114] SPLL
>[drm:verify_single_dpll_state.isra.114] LCPLL 810 [drm:verify_single_dpll_state.isra.114] LCPLL 810
>[drm:verify_single_dpll_state.isra.114] LCPLL 1350 [drm:verify_single_dpll_state.isra.114] LCPLL 1350
>[drm:verify_single_dpll_state.isra.114] LCPLL 2700 [drm:verify_single_dpll_state.isra.114] LCPLL 2700
>[drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 32 [drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 32
>[drm:intel_enable_shared_dpll] enabling LCPLL 1350 [drm:intel_enable_shared_dpll] enabling LCPLL 1350
>[drm:edp_panel_on] Turn eDP port A panel power on [drm:edp_panel_on] Turn eDP port A panel power on
>[drm:wait_panel_power_cycle] Wait for panel power cycle [drm:wait_panel_power_cycle] Wait for panel power cycle
>[drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000 [drm:wait_panel_status] mask b800000f value 00000000 status 08000001 control 00000000
>[drm:wait_panel_status] Wait complete [drm:wait_panel_status] Wait complete
>[drm:edp_panel_on] Wait for panel power on [drm:edp_panel_on] Wait for panel power on
>[drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000003 [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000003
>[drm:wait_panel_status] Wait complete [drm:wait_panel_status] Wait complete
>[drm:edp_panel_vdd_on] Turning eDP port A VDD on [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[drm:intel_dp_set_signal_levels] Using signal levels 00000000 [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[drm:intel_dp_set_signal_levels] Using vswing level 0 [drm:intel_dp_set_signal_levels] Using vswing level 0
>[drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[drm:intel_dp_start_link_train] clock recovery OK [drm:intel_dp_start_link_train] clock recovery OK
>[drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[drm:intel_enable_pipe] enabling pipe A [drm:intel_enable_pipe] enabling pipe A
>[drm:intel_edp_backlight_on.part.27]  [drm:intel_edp_backlight_on.part.27] 
>[drm:intel_panel_enable_backlight] pipe A [drm:intel_panel_enable_backlight] pipe A
>[drm:intel_panel_actually_set_backlight] set backlight PWM = 937 [drm:intel_panel_actually_set_backlight] set backlight PWM = 937
>[drm:intel_psr_enable] PSR not supported by this panel [drm:intel_psr_enable] PSR not supported by this panel
>[drm:intel_edp_drrs_enable] Panel doesn't support DRRS [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[drm:intel_power_well_disable] disabling display [drm:intel_power_well_disable] disabling display
>[drm:hsw_set_power_well.constprop.16] Requesting to disable the power well [drm:hsw_set_power_well.constprop.16] Requesting to disable the power well
>[drm:verify_connector_state.isra.83] [CONNECTOR:48:eDP-1] [drm:verify_connector_state.isra.83] [CONNECTOR:48:eDP-1]
>[drm:intel_atomic_commit_tail] [CRTC:32:pipe A] [drm:intel_atomic_commit_tail] [CRTC:32:pipe A]
>[drm:verify_single_dpll_state.isra.114] LCPLL 1350 [drm:verify_single_dpll_state.isra.114] LCPLL 1350
>[drm:intel_print_rc6_info] Enabling RC6 states: RC6 on [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[drm:sandybridge_pcode_read] warning: pcode (read) mailbox access failed: -6 [drm:sandybridge_pcode_read] warning: pcode (read) mailbox access failed: -6
>[drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[drm:intel_power_well_enable] enabling display [drm:intel_power_well_enable] enabling display
>[drm:hsw_set_power_well.constprop.16] Enabling power well [drm:hsw_set_power_well.constprop.16] Enabling power well
>[drm:i915_audio_component_get_eld] Not valid for port B [drm:i915_audio_component_get_eld] Not valid for port B
>[drm:i915_audio_component_get_eld] Not valid for port B [drm:i915_audio_component_get_eld] Not valid for port B
>[drm:i915_audio_component_get_eld] Not valid for port B [drm:i915_audio_component_get_eld] Not valid for port B
>[drm:i915_audio_component_get_eld] Not valid for port C [drm:i915_audio_component_get_eld] Not valid for port C
>[drm:i915_audio_component_get_eld] Not valid for port C [drm:i915_audio_component_get_eld] Not valid for port C
>[drm:i915_audio_component_get_eld] Not valid for port C [drm:i915_audio_component_get_eld] Not valid for port C
>[drm:i915_audio_component_get_eld] Not valid for port D [drm:i915_audio_component_get_eld] Not valid for port D
>[drm:i915_audio_component_get_eld] Not valid for port D [drm:i915_audio_component_get_eld] Not valid for port D
>[drm:i915_audio_component_get_eld] Not valid for port D [drm:i915_audio_component_get_eld] Not valid for port D
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:drm_fb_helper_hotplug_event]  [drm:drm_fb_helper_hotplug_event] 
>[drm:drm_setup_crtcs]  [drm:drm_setup_crtcs] 
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1]
>[drm:intel_dp_detect] [CONNECTOR:48:eDP-1] [drm:intel_dp_detect] [CONNECTOR:48:eDP-1]
>[drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no
>[drm:intel_dp_print_rates] source rates: 162000, 270000, 540000 [drm:intel_dp_print_rates] source rates: 162000, 270000, 540000
>[drm:intel_dp_print_rates] sink rates: 162000, 270000 [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[drm:intel_dp_print_rates] common rates: 162000, 270000 [drm:intel_dp_print_rates] common rates: 162000, 270000
>[drm:edp_panel_vdd_on] Turning eDP port A VDD on [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>[drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 [drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0
>[drm:drm_edid_to_eld] ELD: no CEA Extension found [drm:drm_edid_to_eld] ELD: no CEA Extension found
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] probed modes : [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:eDP-1] probed modes :
>[drm:drm_mode_debug_printmodeline] Modeline 49:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 49:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9
>[drm:drm_mode_debug_printmodeline] Modeline 50:"1366x768" 40 69300 1366 1374 1384 1786 768 771 772 968 0x40 0x9 [drm:drm_mode_debug_printmodeline] Modeline 50:"1366x768" 40 69300 1366 1374 1384 1786 768 771 772 968 0x40 0x9
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1]
>[drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-1] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-1]
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] disconnected [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-1] disconnected
>[drm:drm_setup_crtcs] connector 48 enabled? yes [drm:drm_setup_crtcs] connector 48 enabled? yes
>[drm:drm_setup_crtcs] connector 57 enabled? no [drm:drm_setup_crtcs] connector 57 enabled? no
>[drm:intel_fb_initial_config] Not using firmware configuration [drm:intel_fb_initial_config] Not using firmware configuration
>[drm:drm_setup_crtcs] looking for cmdline mode on connector 48 [drm:drm_setup_crtcs] looking for cmdline mode on connector 48
>[drm:drm_setup_crtcs] looking for preferred mode on connector 48 0 [drm:drm_setup_crtcs] looking for preferred mode on connector 48 0
>[drm:drm_setup_crtcs] found mode 1366x768 [drm:drm_setup_crtcs] found mode 1366x768
>[drm:drm_setup_crtcs] picking CRTCs for 1366x768 config [drm:drm_setup_crtcs] picking CRTCs for 1366x768 config
>[drm:drm_setup_crtcs] desired mode 1366x768 set on crtc 32 (0,0) [drm:drm_setup_crtcs] desired mode 1366x768 set on crtc 32 (0,0)
>[drm:amdgpu_acpi_init [amdgpu]] Call to ATCS verify_interface failed: -5 [drm:amdgpu_acpi_init [amdgpu]] Call to ATCS verify_interface failed: -5
>[drm:amdgpu_acpi_init [amdgpu]] Call to ATIF verify_interface failed: -5 [drm:amdgpu_acpi_init [amdgpu]] Call to ATIF verify_interface failed: -5
>[drm:intel_backlight_device_update_status] updating intel_backlight, brightness=153/937 [drm:intel_backlight_device_update_status] updating intel_backlight, brightness=153/937
>[drm:intel_panel_actually_set_backlight] set backlight PWM = 193 [drm:intel_panel_actually_set_backlight] set backlight PWM = 193
>[drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>[drm:intel_edp_backlight_off.part.28]  [drm:intel_edp_backlight_off.part.28] 
>[drm:intel_panel_actually_set_backlight] set backlight PWM = 0 [drm:intel_panel_actually_set_backlight] set backlight PWM = 0
>[drm:intel_disable_pipe] disabling pipe A [drm:intel_disable_pipe] disabling pipe A
>[drm:edp_panel_vdd_on] Turning eDP port A VDD on [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[drm:intel_edp_panel_off.part.26] Turn eDP port A panel power off [drm:intel_edp_panel_off.part.26] Turn eDP port A panel power off
>[drm:intel_edp_panel_off.part.26] Wait for panel power off time [drm:intel_edp_panel_off.part.26] Wait for panel power off time
>[drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000 [drm:wait_panel_status] mask b0000000 value 00000000 status 80000008 control 00000000
>[drm:wait_panel_status] Wait complete [drm:wait_panel_status] Wait complete
>[drm:intel_disable_shared_dpll] disable LCPLL 1350 (active 1, on? 1) for crtc 32 [drm:intel_disable_shared_dpll] disable LCPLL 1350 (active 1, on? 1) for crtc 32
>[drm:intel_disable_shared_dpll] disabling LCPLL 1350 [drm:intel_disable_shared_dpll] disabling LCPLL 1350
>[drm:intel_atomic_commit_tail] [ENCODER:47:DDI A] [drm:intel_atomic_commit_tail] [ENCODER:47:DDI A]
>[drm:intel_atomic_commit_tail] [ENCODER:56:DDI B] [drm:intel_atomic_commit_tail] [ENCODER:56:DDI B]
>[drm:verify_connector_state.isra.83] [CONNECTOR:48:eDP-1] [drm:verify_connector_state.isra.83] [CONNECTOR:48:eDP-1]
>[drm:verify_single_dpll_state.isra.114] WRPLL 1 [drm:verify_single_dpll_state.isra.114] WRPLL 1
>[drm:verify_single_dpll_state.isra.114] WRPLL 2 [drm:verify_single_dpll_state.isra.114] WRPLL 2
>[drm:verify_single_dpll_state.isra.114] SPLL [drm:verify_single_dpll_state.isra.114] SPLL
>[drm:verify_single_dpll_state.isra.114] LCPLL 810 [drm:verify_single_dpll_state.isra.114] LCPLL 810
>[drm:verify_single_dpll_state.isra.114] LCPLL 1350 [drm:verify_single_dpll_state.isra.114] LCPLL 1350
>[drm:verify_single_dpll_state.isra.114] LCPLL 2700 [drm:verify_single_dpll_state.isra.114] LCPLL 2700
>[drm:intel_atomic_commit_tail] [CRTC:32:pipe A] [drm:intel_atomic_commit_tail] [CRTC:32:pipe A]
>[drm:i915_check_and_clear_faults.part.48] Unexpected fault [drm:i915_check_and_clear_faults.part.48] Unexpected fault
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:intel_power_well_disable] disabling display [drm:intel_power_well_disable] disabling display
>[drm:hsw_set_power_well.constprop.16] Requesting to disable the power well [drm:hsw_set_power_well.constprop.16] Requesting to disable the power well
>[drm:intel_power_well_disable] disabling always-on [drm:intel_power_well_disable] disabling always-on
>[drm:hsw_enable_pc8] Enabling package C8+ [drm:hsw_enable_pc8] Enabling package C8+
>[drm:hsw_disable_pc8] Disabling package C8+ [drm:hsw_disable_pc8] Disabling package C8+
>[drm:intel_power_well_enable] enabling always-on [drm:intel_power_well_enable] enabling always-on
>[drm:intel_power_well_enable] enabling display [drm:intel_power_well_enable] enabling display
>[drm:intel_opregion_setup] graphic opregion physical addr: 0x9afb2018 [drm:intel_opregion_setup] graphic opregion physical addr: 0x9afb2018
>[drm:intel_opregion_setup] Public ACPI methods supported [drm:intel_opregion_setup] Public ACPI methods supported
>[drm:intel_opregion_setup] SWSCI supported [drm:intel_opregion_setup] SWSCI supported
>[drm:intel_opregion_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483 [drm:intel_opregion_setup] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[drm:intel_opregion_setup] ASLE supported [drm:intel_opregion_setup] ASLE supported
>[drm:intel_opregion_setup] ASLE extension supported [drm:intel_opregion_setup] ASLE extension supported
>[drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (Mailbox #4) [drm:intel_opregion_setup] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af06 [drm:intel_dp_init_panel_power_sequencer_registers] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af06
>[drm:init_workarounds_ring] render ring: Number of context specific w/a: 0 [drm:init_workarounds_ring] render ring: Number of context specific w/a: 0
>[drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 0 kHz, ref: 0 kHz [drm:intel_update_cdclk] Current CD clock rate: 450000 kHz, VCO: 0 kHz, ref: 0 kHz
>[drm:intel_set_plane_visible] pipe A active planes 0x0 [drm:intel_set_plane_visible] pipe A active planes 0x0
>[drm:intel_modeset_setup_hw_state] [CRTC:32:pipe A] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CRTC:32:pipe A] hw state readout: disabled
>[drm:intel_set_plane_visible] pipe B active planes 0x0 [drm:intel_set_plane_visible] pipe B active planes 0x0
>[drm:intel_modeset_setup_hw_state] [CRTC:39:pipe B] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CRTC:39:pipe B] hw state readout: disabled
>[drm:intel_set_plane_visible] pipe C active planes 0x0 [drm:intel_set_plane_visible] pipe C active planes 0x0
>[drm:intel_modeset_setup_hw_state] [CRTC:46:pipe C] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CRTC:46:pipe C] hw state readout: disabled
>[drm:intel_modeset_setup_hw_state] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0 [drm:intel_modeset_setup_hw_state] WRPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[drm:intel_modeset_setup_hw_state] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0 [drm:intel_modeset_setup_hw_state] WRPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[drm:intel_modeset_setup_hw_state] SPLL hw state readout: crtc_mask 0x00000000, on 0 [drm:intel_modeset_setup_hw_state] SPLL hw state readout: crtc_mask 0x00000000, on 0
>[drm:intel_modeset_setup_hw_state] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1 [drm:intel_modeset_setup_hw_state] LCPLL 810 hw state readout: crtc_mask 0x00000000, on 1
>[drm:intel_modeset_setup_hw_state] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1 [drm:intel_modeset_setup_hw_state] LCPLL 1350 hw state readout: crtc_mask 0x00000000, on 1
>[drm:intel_modeset_setup_hw_state] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1 [drm:intel_modeset_setup_hw_state] LCPLL 2700 hw state readout: crtc_mask 0x00000000, on 1
>[drm:intel_modeset_setup_hw_state] [ENCODER:47:DDI A] hw state readout: disabled, pipe A [drm:intel_modeset_setup_hw_state] [ENCODER:47:DDI A] hw state readout: disabled, pipe A
>[drm:intel_modeset_setup_hw_state] [ENCODER:56:DDI B] hw state readout: disabled, pipe A [drm:intel_modeset_setup_hw_state] [ENCODER:56:DDI B] hw state readout: disabled, pipe A
>[drm:intel_modeset_setup_hw_state] [CONNECTOR:48:eDP-1] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CONNECTOR:48:eDP-1] hw state readout: disabled
>[drm:intel_modeset_setup_hw_state] [CONNECTOR:57:HDMI-A-1] hw state readout: disabled [drm:intel_modeset_setup_hw_state] [CONNECTOR:57:HDMI-A-1] hw state readout: disabled
>[drm:intel_dump_pipe_config] [CRTC:32:pipe A][setup_hw_state] [drm:intel_dump_pipe_config] [CRTC:32:pipe A][setup_hw_state]
>[drm:intel_dump_pipe_config] cpu_transcoder: A, pipe bpp: 0, dithering: 0 [drm:intel_dump_pipe_config] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0 [drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0, double wide: 0 [drm:intel_dump_pipe_config] ips: 0, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [CRTC:39:pipe B][setup_hw_state] [drm:intel_dump_pipe_config] [CRTC:39:pipe B][setup_hw_state]
>[drm:intel_dump_pipe_config] cpu_transcoder: B, pipe bpp: 0, dithering: 0 [drm:intel_dump_pipe_config] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0 [drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0, double wide: 0 [drm:intel_dump_pipe_config] ips: 0, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:33:primary B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:33:primary B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:35:sprite B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:35:sprite B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:37:cursor B] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:37:cursor B] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [CRTC:46:pipe C][setup_hw_state] [drm:intel_dump_pipe_config] [CRTC:46:pipe C][setup_hw_state]
>[drm:intel_dump_pipe_config] cpu_transcoder: C, pipe bpp: 0, dithering: 0 [drm:intel_dump_pipe_config] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 [drm:intel_dump_pipe_config] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0 [drm:intel_dump_pipe_config] port clock: 0, pipe src size: 0x0, pixel rate 0
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 0, double wide: 0 [drm:intel_dump_pipe_config] ips: 0, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:40:primary C] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:40:primary C] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:42:sprite C] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:42:sprite C] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:44:cursor C] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:44:cursor C] disabled, scaler_id = 0
>[drm:intel_modeset_setup_hw_state] LCPLL 810 enabled but not in use, disabling [drm:intel_modeset_setup_hw_state] LCPLL 810 enabled but not in use, disabling
>[drm:intel_modeset_setup_hw_state] LCPLL 1350 enabled but not in use, disabling [drm:intel_modeset_setup_hw_state] LCPLL 1350 enabled but not in use, disabling
>[drm:intel_modeset_setup_hw_state] LCPLL 2700 enabled but not in use, disabling [drm:intel_modeset_setup_hw_state] LCPLL 2700 enabled but not in use, disabling
>[drm:intel_atomic_check] [CONNECTOR:48:eDP-1] checking for sink bpp constrains [drm:intel_atomic_check] [CONNECTOR:48:eDP-1] checking for sink bpp constrains
>[drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 18 [drm:intel_atomic_check] clamping display bpp (was 36) to EDID reported max of 18
>[drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 69300KHz [drm:intel_dp_compute_config] DP link computation with max lane count 2 max bw 270000 pixel clock 69300KHz
>[drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18 [drm:intel_dp_compute_config] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 18
>[drm:intel_dp_compute_config] DP link bw required 155925 available 540000 [drm:intel_dp_compute_config] DP link bw required 155925 available 540000
>[drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 18, dithering: 1 [drm:intel_atomic_check] hw max bpp: 36, pipe bpp: 18, dithering: 1
>[drm:pipe_config_err] mismatch in cpu_transcoder (expected 0, found 3) [drm:pipe_config_err] mismatch in cpu_transcoder (expected 0, found 3)
>[drm:pipe_config_err] mismatch in lane_count (expected 0, found 2) [drm:pipe_config_err] mismatch in lane_count (expected 0, found 2)
>[drm:pipe_config_err] mismatch in dp_m_n (expected tu 0 gmch 0/0 link 0/0, found tu 64, gmch 2422210/8388608 link 134567/524288) [drm:pipe_config_err] mismatch in dp_m_n (expected tu 0 gmch 0/0 link 0/0, found tu 64, gmch 2422210/8388608 link 134567/524288)
>[drm:pipe_config_err] mismatch in output_types (expected 0x00000000, found 0x00000100) [drm:pipe_config_err] mismatch in output_types (expected 0x00000000, found 0x00000100)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hdisplay (expected 0, found 1366) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hdisplay (expected 0, found 1366)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_htotal (expected 0, found 1462) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_htotal (expected 0, found 1462)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hblank_start (expected 0, found 1366) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hblank_start (expected 0, found 1366)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hblank_end (expected 0, found 1462) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hblank_end (expected 0, found 1462)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hsync_start (expected 0, found 1374) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hsync_start (expected 0, found 1374)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hsync_end (expected 0, found 1384) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_hsync_end (expected 0, found 1384)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vdisplay (expected 0, found 768) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vdisplay (expected 0, found 768)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vtotal (expected 0, found 790) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vtotal (expected 0, found 790)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vblank_start (expected 0, found 768) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vblank_start (expected 0, found 768)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vblank_end (expected 0, found 790) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vblank_end (expected 0, found 790)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vsync_start (expected 0, found 771) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vsync_start (expected 0, found 771)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vsync_end (expected 0, found 772) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_vsync_end (expected 0, found 772)
>[drm:pipe_config_err] mismatch in pixel_multiplier (expected 0, found 1) [drm:pipe_config_err] mismatch in pixel_multiplier (expected 0, found 1)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.flags (1) (expected 0, found 1) [drm:pipe_config_err] mismatch in base.adjusted_mode.flags (1) (expected 0, found 1)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.flags (8) (expected 0, found 8) [drm:pipe_config_err] mismatch in base.adjusted_mode.flags (8) (expected 0, found 8)
>[drm:pipe_config_err] mismatch in ips_enabled (expected 0, found 1) [drm:pipe_config_err] mismatch in ips_enabled (expected 0, found 1)
>[drm:pipe_config_err] mismatch in shared_dpll (expected           (null), found ffff8802543746b8) [drm:pipe_config_err] mismatch in shared_dpll (expected           (null), found ffff8802543746b8)
>[drm:pipe_config_err] mismatch in pipe_bpp (expected 0, found 18) [drm:pipe_config_err] mismatch in pipe_bpp (expected 0, found 18)
>[drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_clock (expected 0, found 69300) [drm:pipe_config_err] mismatch in base.adjusted_mode.crtc_clock (expected 0, found 69300)
>[drm:pipe_config_err] mismatch in port_clock (expected 0, found 270000) [drm:pipe_config_err] mismatch in port_clock (expected 0, found 270000)
>[drm:intel_dump_pipe_config] [CRTC:32:pipe A][modeset] [drm:intel_dump_pipe_config] [CRTC:32:pipe A][modeset]
>[drm:intel_dump_pipe_config] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1 [drm:intel_dump_pipe_config] cpu_transcoder: EDP, pipe bpp: 18, dithering: 1
>[drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2422210, gmch_n: 8388608, link_m: 134567, link_n: 524288, tu: 64 [drm:intel_dump_pipe_config] dp m_n: lanes: 2; gmch_m: 2422210, gmch_n: 8388608, link_m: 134567, link_n: 524288, tu: 64
>[drm:intel_dump_pipe_config] audio: 0, infoframes: 0 [drm:intel_dump_pipe_config] audio: 0, infoframes: 0
>[drm:intel_dump_pipe_config] requested mode: [drm:intel_dump_pipe_config] requested mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9
>[drm:intel_dump_pipe_config] adjusted mode: [drm:intel_dump_pipe_config] adjusted mode:
>[drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9 [drm:drm_mode_debug_printmodeline] Modeline 0:"1366x768" 60 69300 1366 1374 1384 1462 768 771 772 790 0x48 0x9
>[drm:intel_dump_pipe_config] crtc timings: 69300 1366 1374 1384 1462 768 771 772 790, type: 0x48 flags: 0x9 [drm:intel_dump_pipe_config] crtc timings: 69300 1366 1374 1384 1462 768 771 772 790, type: 0x48 flags: 0x9
>[drm:intel_dump_pipe_config] port clock: 270000, pipe src size: 1366x768, pixel rate 69300 [drm:intel_dump_pipe_config] port clock: 270000, pipe src size: 1366x768, pixel rate 69300
>[drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled [drm:intel_dump_pipe_config] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[drm:intel_dump_pipe_config] ips: 1, double wide: 0 [drm:intel_dump_pipe_config] ips: 1, double wide: 0
>[drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0 [drm:hsw_dump_hw_state] dpll_hw_state: wrpll: 0x0 spll: 0x0
>[drm:intel_dump_pipe_config] planes on this crtc [drm:intel_dump_pipe_config] planes on this crtc
>[drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:26:primary A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:28:sprite A] disabled, scaler_id = 0
>[drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0 [drm:intel_dump_pipe_config] [PLANE:30:cursor A] disabled, scaler_id = 0
>[drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A [drm:intel_reference_shared_dpll] using LCPLL 1350 for pipe A
>[drm:intel_atomic_commit_tail] [ENCODER:47:DDI A] [drm:intel_atomic_commit_tail] [ENCODER:47:DDI A]
>[drm:intel_atomic_commit_tail] [ENCODER:56:DDI B] [drm:intel_atomic_commit_tail] [ENCODER:56:DDI B]
>[drm:verify_connector_state.isra.83] [CONNECTOR:57:HDMI-A-1] [drm:verify_connector_state.isra.83] [CONNECTOR:57:HDMI-A-1]
>[drm:verify_single_dpll_state.isra.114] WRPLL 1 [drm:verify_single_dpll_state.isra.114] WRPLL 1
>[drm:verify_single_dpll_state.isra.114] WRPLL 2 [drm:verify_single_dpll_state.isra.114] WRPLL 2
>[drm:verify_single_dpll_state.isra.114] SPLL [drm:verify_single_dpll_state.isra.114] SPLL
>[drm:verify_single_dpll_state.isra.114] LCPLL 810 [drm:verify_single_dpll_state.isra.114] LCPLL 810
>[drm:verify_single_dpll_state.isra.114] LCPLL 1350 [drm:verify_single_dpll_state.isra.114] LCPLL 1350
>[drm:verify_single_dpll_state.isra.114] LCPLL 2700 [drm:verify_single_dpll_state.isra.114] LCPLL 2700
>[drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 32 [drm:intel_enable_shared_dpll] enable LCPLL 1350 (active 1, on? 0) for crtc 32
>[drm:intel_enable_shared_dpll] enabling LCPLL 1350 [drm:intel_enable_shared_dpll] enabling LCPLL 1350
>[drm:edp_panel_on] Turn eDP port A panel power on [drm:edp_panel_on] Turn eDP port A panel power on
>[drm:wait_panel_power_cycle] Wait for panel power cycle [drm:wait_panel_power_cycle] Wait for panel power cycle
>[drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000 [drm:wait_panel_status] mask b800000f value 00000000 status 00000000 control 00000000
>[drm:wait_panel_status] Wait complete [drm:wait_panel_status] Wait complete
>[drm:edp_panel_on] Wait for panel power on [drm:edp_panel_on] Wait for panel power on
>[drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000003 [drm:wait_panel_status] mask b000000f value 80000008 status 0000000a control 00000003
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2) [drm:dce_v6_0_pageflip_irq [amdgpu]] amdgpu_crtc->pflip_status = 0 != AMDGPU_FLIP_SUBMITTED(2)
>[drm:wait_panel_status] Wait complete [drm:wait_panel_status] Wait complete
>[drm:edp_panel_vdd_on] Turning eDP port A VDD on [drm:edp_panel_vdd_on] Turning eDP port A VDD on
>[drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b [drm:edp_panel_vdd_on] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>[drm:intel_dp_set_signal_levels] Using signal levels 00000000 [drm:intel_dp_set_signal_levels] Using signal levels 00000000
>[drm:intel_dp_set_signal_levels] Using vswing level 0 [drm:intel_dp_set_signal_levels] Using vswing level 0
>[drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0
>[drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1 [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS1
>[drm:intel_dp_start_link_train] clock recovery OK [drm:intel_dp_start_link_train] clock recovery OK
>[drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2 [drm:intel_dp_program_link_training_pattern] Using DP training pattern TPS2
>[drm:intel_dp_start_link_train] Channel EQ done. DP Training successful [drm:intel_dp_start_link_train] Channel EQ done. DP Training successful
>[drm:intel_enable_pipe] enabling pipe A [drm:intel_enable_pipe] enabling pipe A
>[drm:intel_edp_backlight_on.part.27]  [drm:intel_edp_backlight_on.part.27] 
>[drm:intel_panel_enable_backlight] pipe A [drm:intel_panel_enable_backlight] pipe A
>[drm:intel_panel_actually_set_backlight] set backlight PWM = 193 [drm:intel_panel_actually_set_backlight] set backlight PWM = 193
>[drm:intel_psr_enable] PSR not supported by this panel [drm:intel_psr_enable] PSR not supported by this panel
>[drm:intel_edp_drrs_enable] Panel doesn't support DRRS [drm:intel_edp_drrs_enable] Panel doesn't support DRRS
>[drm:verify_connector_state.isra.83] [CONNECTOR:48:eDP-1] [drm:verify_connector_state.isra.83] [CONNECTOR:48:eDP-1]
>[drm:intel_atomic_commit_tail] [CRTC:32:pipe A] [drm:intel_atomic_commit_tail] [CRTC:32:pipe A]
>[drm:verify_single_dpll_state.isra.114] LCPLL 1350 [drm:verify_single_dpll_state.isra.114] LCPLL 1350
>[drm:intel_atomic_commit_tail] [CRTC:39:pipe B] [drm:intel_atomic_commit_tail] [CRTC:39:pipe B]
>[drm:intel_atomic_commit_tail] [CRTC:46:pipe C] [drm:intel_atomic_commit_tail] [CRTC:46:pipe C]
>[drm:intel_opregion_register] 2 outputs detected [drm:intel_opregion_register] 2 outputs detected
>[drm:intel_dp_detect] [CONNECTOR:48:eDP-1] [drm:intel_dp_detect] [CONNECTOR:48:eDP-1]
>[drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no [drm:intel_dp_detect] Display Port TPS3 support: source yes, sink no
>[drm:intel_dp_print_rates] source rates: 162000, 270000, 540000 [drm:intel_dp_print_rates] source rates: 162000, 270000, 540000
>[drm:intel_dp_print_rates] sink rates: 162000, 270000 [drm:intel_dp_print_rates] sink rates: 162000, 270000
>[drm:intel_dp_print_rates] common rates: 162000, 270000 [drm:intel_dp_print_rates] common rates: 162000, 270000
>[drm:amdgpu_atif_handler [amdgpu]] event, device_class = video, type = 0x80 [drm:amdgpu_atif_handler [amdgpu]] event, device_class = video, type = 0x80
>[drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 [drm:intel_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0
>[drm:drm_helper_hpd_irq_event] [CONNECTOR:48:eDP-1] status updated from connected to connected [drm:drm_helper_hpd_irq_event] [CONNECTOR:48:eDP-1] status updated from connected to connected
>[drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-1] [drm:intel_hdmi_detect] [CONNECTOR:57:HDMI-A-1]
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1) [drm:gmbus_xfer] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6) [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-1] status updated from disconnected to disconnected [drm:drm_helper_hpd_irq_event] [CONNECTOR:57:HDMI-A-1] status updated from disconnected to disconnected
>[drm:intel_print_rc6_info] Enabling RC6 states: RC6 on [drm:intel_print_rc6_info] Enabling RC6 states: RC6 on
>[drm:sandybridge_pcode_read] warning: pcode (read) mailbox access failed: -6 [drm:sandybridge_pcode_read] warning: pcode (read) mailbox access failed: -6
>[drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off [drm:edp_panel_vdd_off_sync] Turning eDP port A VDD off
>[drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007 [drm:edp_panel_vdd_off_sync] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007

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Attachments on bug 100755: 130972 | 130973 | 130979 | 130986 | 131053 | 131054 | 131098

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