Attachment 131058 Details for Bug 100240 – late guc loading

[patch] late guc loading

0001-drm-i915-Allow-late-GuC-HuC-loading.patch (text/plain), 7.88 KB, created by Michel Thierry on 2017-04-26 22:39:18 UTC

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Creator: Michel Thierry

Created: 2017-04-26 22:39:18 UTC

Size: 7.88 KB

patch

obsolete

>From f5c0b83d931d2e46d550ae127a2694845a193c6b Mon Sep 17 00:00:00 2001
>From: Michel Thierry <michel.thierry@intel.com>
>Date: Wed, 26 Apr 2017 12:05:33 -0700
>Subject: [PATCH] !UPSTREAM: drm/i915: Allow late GuC/HuC loading
>
>This patch allows for the GuC and HuC to be loaded until the first
>device is open (instead of during the driver initialisation).
>
>Delaying the fw load prevents a load failure when the partition that the
>firmware is supposed to be on has not been mounted yet, as is the case
>in Android.
>
>Since the GuC won't exist until later on, a couple of functions with
>need of it have to also be delayed (i915_guc_log_register &
>__intel_autoenable_gt_powersave).
>
>There was a collection of patches in 4.1/4.4 to do more less the same,
>but they were obsolete for 4.11 and it made more sense to rewrite it
>from scratch.
>
>!UPSTREAM: The hw_late code is part of a solution for loading firmware
>of a file system that has not been mounted yet. Only a problem
>on Android.
>
>Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>---
> drivers/gpu/drm/i915/i915_drv.c         | 11 ++++++--
> drivers/gpu/drm/i915/i915_drv.h         |  3 +++
> drivers/gpu/drm/i915/i915_gem.c         | 38 +++++++++++++++++++++++++---
> drivers/gpu/drm/i915/i915_gem_context.c | 45 ++++++++++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_guc_log.c    |  2 --
> drivers/gpu/drm/i915/intel_pm.c         |  7 +++++
> 6 files changed, 91 insertions(+), 15 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index df8e2e8e3b7f..d23988940aa4 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -607,7 +607,12 @@ static int i915_load_modeset_init(struct drm_device *dev)
> 	if (ret)
> 		goto cleanup_irq;
> 
>-	intel_uc_init_fw(dev_priv);
>+	/*
>+	 * ANDROID: we cannot attempt to load the fw here, the filesystem
>+	 * where our bin files are located won't be mounted until much
>+	 * later.
>+	 * intel_uc_init_fw(dev_priv);
>+	 */
> 
> 	ret = i915_gem_init(dev_priv);
> 	if (ret)
>@@ -1146,7 +1151,9 @@ static void i915_driver_register(struct drm_i915_private *dev_priv)
> 	/* Reveal our presence to userspace */
> 	if (drm_dev_register(dev, 0) == 0) {
> 		i915_debugfs_register(dev_priv);
>-		i915_guc_log_register(dev_priv);
>+		/* ANDROID: we defered the guc log registration */
>+		if (dev_priv->contexts_ready)
>+			i915_guc_log_register(dev_priv);
> 		i915_setup_sysfs(dev_priv);
> 
> 		/* Depends on sysfs having been initialized */
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index a985547a8b21..c38fb7b6004e 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -2555,6 +2555,8 @@ struct drm_i915_private {
> 	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
> 	 * will be rejected. Instead look for a better place.
> 	 */
>+
>+	bool contexts_ready; /* for deferred initialization */
> };
> 
> static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
>@@ -3477,6 +3479,7 @@ void i915_gem_reset_engine(struct intel_engine_cs *engine,
> void i915_gem_init_mmio(struct drm_i915_private *i915);
> int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
> int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
>+int __must_check i915_gem_init_hw_late(struct drm_i915_private *dev_priv);
> void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
> void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
> int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
>diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
>index 4e357d333cc2..53da392a7517 100644
>--- a/drivers/gpu/drm/i915/i915_gem.c
>+++ b/drivers/gpu/drm/i915/i915_gem.c
>@@ -4682,6 +4682,28 @@ static int __i915_gem_restart_engines(void *data)
> 	return 0;
> }
> 
>+int i915_gem_init_hw_late(struct drm_i915_private *dev_priv)
>+{
>+	int ret;
>+
>+	/*
>+	 * Place for things that can be delayed until the first context
>+	 * is open. For example, fw loading in android.
>+	 */
>+
>+	/* fetch firmware */
>+	intel_uc_init_fw(dev_priv);
>+
>+	/* We can't enable contexts until all firmware is loaded */
>+	ret = intel_uc_init_hw(dev_priv);
>+	if (ret)
>+		return ret;
>+
>+	i915_guc_log_register(dev_priv);
>+
>+	return 0;
>+}
>+
> int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> {
> 	int ret;
>@@ -4735,10 +4757,18 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv)
> 
> 	intel_mocs_init_l3cc_table(dev_priv);
> 
>-	/* We can't enable contexts until all firmware is loaded */
>-	ret = intel_uc_init_hw(dev_priv);
>-	if (ret)
>-		goto out;
>+	/*
>+	 * Don't call i915_gem_init_hw_late() the very first time (during
>+	 * driver load); it will get called during first open instead.
>+	 * It should only be called on subsequent (re-initialization) passes.
>+	 */
>+	if (dev_priv->contexts_ready) {
>+		ret = i915_gem_init_hw_late(dev_priv);
>+		if (ret)
>+			goto out;
>+	} else {
>+		DRM_DEBUG_DRIVER("deferring late initialization\n");
>+	}
> 
> out:
> 	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
>index a1c04e17fac1..0c4181de53aa 100644
>--- a/drivers/gpu/drm/i915/i915_gem_context.c
>+++ b/drivers/gpu/drm/i915/i915_gem_context.c
>@@ -642,25 +642,56 @@ static int context_idr_cleanup(int id, void *p, void *data)
> 	return 0;
> }
> 
>+int i915_gem_context_first_open(struct drm_i915_private *dev_priv)
>+{
>+	int ret;
>+
>+	lockdep_assert_held(&dev_priv->drm.struct_mutex);
>+
>+	DRM_DEBUG_DRIVER("late initialization starting\n");
>+
>+	intel_runtime_pm_get(dev_priv);
>+	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>+
>+	ret = i915_gem_init_hw_late(dev_priv);
>+	if (ret == 0)
>+		dev_priv->contexts_ready = true;
>+	else
>+		DRM_ERROR("late initialization failed: %d\n", ret);
>+
>+	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
>+	intel_runtime_pm_put(dev_priv);
>+
>+	return ret;
>+}
>+
> int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
> {
> 	struct drm_i915_file_private *file_priv = file->driver_priv;
> 	struct i915_gem_context *ctx;
>+	int ret = 0;
> 
> 	idr_init(&file_priv->context_idr);
> 
> 	mutex_lock(&dev->struct_mutex);
>-	ctx = i915_gem_create_context(to_i915(dev), file_priv);
>-	mutex_unlock(&dev->struct_mutex);
> 
>-	GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
>+	if (!to_i915(dev)->contexts_ready)
>+		ret = i915_gem_context_first_open(to_i915(dev));
> 
>-	if (IS_ERR(ctx)) {
>-		idr_destroy(&file_priv->context_idr);
>-		return PTR_ERR(ctx);
>+	if (ret == 0) {
>+		ctx = i915_gem_create_context(to_i915(dev), file_priv);
>+		if (IS_ERR(ctx))
>+			ret = PTR_ERR(ctx);
>+
>+		GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
> 	}
> 
>-	return 0;
>+	mutex_unlock(&dev->struct_mutex);
>+
>+	if (ret)
>+		idr_destroy(&file_priv->context_idr);
>+
>+	return ret;
> }
> 
> void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
>diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c
>index 16d3b8719cab..8ef0d5c1c382 100644
>--- a/drivers/gpu/drm/i915/intel_guc_log.c
>+++ b/drivers/gpu/drm/i915/intel_guc_log.c
>@@ -644,9 +644,7 @@ void i915_guc_log_register(struct drm_i915_private *dev_priv)
> 	if (!i915.enable_guc_submission || i915.guc_log_level < 0)
> 		return;
> 
>-	mutex_lock(&dev_priv->drm.struct_mutex);
> 	guc_log_late_setup(&dev_priv->guc);
>-	mutex_unlock(&dev_priv->drm.struct_mutex);
> }
> 
> void i915_guc_log_unregister(struct drm_i915_private *dev_priv)
>diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>index cacb65fa2dd5..bb2107ba0c31 100644
>--- a/drivers/gpu/drm/i915/intel_pm.c
>+++ b/drivers/gpu/drm/i915/intel_pm.c
>@@ -7099,6 +7099,13 @@ static void __intel_autoenable_gt_powersave(struct work_struct *work)
> 	struct intel_engine_cs *rcs;
> 	struct drm_i915_gem_request *req;
> 
>+	/*
>+	 * ANDROID: In deferred fw mode, we can't submit anything until we know
>+	 * we loaded and setup the guc and we're ready to handle submissions.
>+	 */
>+	if (!dev_priv->contexts_ready)
>+		goto out;
>+
> 	if (READ_ONCE(dev_priv->rps.enabled))
> 		goto out;
> 
>-- 
>2.11.0
>

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Attachments on bug 100240: 130272 | 130273 | 131058

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