Attachment 131741 Details for Bug 101321 – dmesg.log

dmesg.log

dmesg.log (text/plain), 329.49 KB, created by maria guadalupe on 2017-06-06 20:23:40 UTC

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Creator: maria guadalupe

Created: 2017-06-06 20:23:40 UTC

Size: 329.49 KB

patch

obsolete

>[    0.000000] Linux version 4.12.0-rc3-drm-tip-ww22-commit-187376e+ (gfx@bifrost) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4) ) #1 SMP PREEMPT Mon May 29 08:19:27 CDT 2017
>[    0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc3-drm-tip-ww22-commit-187376e+ root=UUID=f869e850-fa74-451a-a1a4-4b76793f1022 ro quiet splash fastboot drm.debug=0xe vt.handoff=7
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
>[    0.000000] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
>[    0.000000] x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
>[    0.000000] x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
>[    0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format.
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000059000-0x000000000009dfff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000804c7fff] usable
>[    0.000000] BIOS-e820: [mem 0x00000000804c8000-0x00000000804c8fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x00000000804c9000-0x00000000804c9fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000804ca000-0x0000000089994fff] usable
>[    0.000000] BIOS-e820: [mem 0x0000000089995000-0x000000008a91bfff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000008a91c000-0x000000008a9f9fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000008a9fa000-0x000000008ad7dfff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x000000008ad7e000-0x000000008b299fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000008b29a000-0x000000008b2fdfff] type 20
>[    0.000000] BIOS-e820: [mem 0x000000008b2fe000-0x000000008b2fefff] usable
>[    0.000000] BIOS-e820: [mem 0x000000008b2ff000-0x000000008fffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000ff000000-0x00000000ffffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000026effffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] efi: EFI v2.50 by American Megatrends
>[    0.000000] efi:  ESRT=0x8b1cde58  ACPI=0x8acfa000  ACPI 2.0=0x8acfa000  SMBIOS=0x8b1cc000 
>[    0.000000] SMBIOS 3.0 present.
>[    0.000000] DMI: Micro-Star International Co., Ltd. MS-B142/MS-B1421, BIOS 8.10 09/12/2016
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] e820: last_pfn = 0x26f000 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: write-back
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 00C0000000 mask 7FC0000000 uncachable
>[    0.000000]   1 base 00A0000000 mask 7FE0000000 uncachable
>[    0.000000]   2 base 0090000000 mask 7FF0000000 uncachable
>[    0.000000]   3 base 008C000000 mask 7FFC000000 uncachable
>[    0.000000]   4 base 008B800000 mask 7FFF800000 uncachable
>[    0.000000]   5 disabled
>[    0.000000]   6 disabled
>[    0.000000]   7 disabled
>[    0.000000]   8 disabled
>[    0.000000]   9 disabled
>[    0.000000] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- WT  
>[    0.000000] e820: last_pfn = 0x8b2ff max_arch_pfn = 0x400000000
>[    0.000000] esrt: Reserving ESRT space from 0x000000008b1cde58 to 0x000000008b1cde90.
>[    0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576
>[    0.000000] Using GB pages for direct mapping
>[    0.000000] BRK [0x056c2000, 0x056c2fff] PGTABLE
>[    0.000000] BRK [0x056c3000, 0x056c3fff] PGTABLE
>[    0.000000] BRK [0x056c4000, 0x056c4fff] PGTABLE
>[    0.000000] BRK [0x056c5000, 0x056c5fff] PGTABLE
>[    0.000000] BRK [0x056c6000, 0x056c6fff] PGTABLE
>[    0.000000] BRK [0x056c7000, 0x056c7fff] PGTABLE
>[    0.000000] Secure boot could not be determined
>[    0.000000] RAMDISK: [mem 0x36975000-0x374b1fff]
>[    0.000000] ACPI: Early table checksum verification disabled
>[    0.000000] ACPI: RSDP 0x000000008ACFA000 000024 (v02 MSI_NB)
>[    0.000000] ACPI: XSDT 0x000000008ACFA0A0 0000C4 (v01 MSI_NB MEGABOOK 01072009 AMI  00010013)
>[    0.000000] ACPI: FACP 0x000000008AD1E7C0 000114 (v06 MSI_NB MEGABOOK 01072009 AMI  00010013)
>[    0.000000] ACPI: DSDT 0x000000008ACFA200 0245BD (v02 MSI_NB MEGABOOK 01072009 INTL 20160422)
>[    0.000000] ACPI: FACS 0x000000008AD65C40 000040
>[    0.000000] ACPI: APIC 0x000000008AD1E8D8 000084 (v03 MSI_NB MEGABOOK 01072009 AMI  00010013)
>[    0.000000] ACPI: FPDT 0x000000008AD1E960 000044 (v01 MSI_NB MEGABOOK 01072009 AMI  00010013)
>[    0.000000] ACPI: MCFG 0x000000008AD1E9A8 00003C (v01 MSI_NB MEGABOOK 01072009 MSFT 00000097)
>[    0.000000] ACPI: FIDT 0x000000008AD1E9E8 00009C (v01 MSI_NB MEGABOOK 01072009 AMI  00010013)
>[    0.000000] ACPI: SSDT 0x000000008AD1EA88 003154 (v02 SaSsdt SaSsdt   00003000 INTL 20160422)
>[    0.000000] ACPI: HPET 0x000000008AD21BE0 000038 (v01 INTEL  KBL-ULT  00000001 MSFT 0000005F)
>[    0.000000] ACPI: SSDT 0x000000008AD21C18 000E3B (v02 INTEL  Ther_Rvp 00001000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008AD22A58 000909 (v02 INTEL  xh_rvp07 00000000 INTL 20160422)
>[    0.000000] ACPI: UEFI 0x000000008AD23368 000042 (v01 INTEL  EDK2     00000002      01000013)
>[    0.000000] ACPI: SSDT 0x000000008AD233B0 000EDE (v02 CpuRef CpuSsdt  00003000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008AD24290 000553 (v02 CtdpB  CtdpB    00001000 INTL 20160422)
>[    0.000000] ACPI: LPIT 0x000000008AD247E8 000094 (v01 INTEL  KBL-ULT  00000000 MSFT 0000005F)
>[    0.000000] ACPI: WSMT 0x000000008AD24880 000028 (v01 INTEL  KBL-ULT  00000000 MSFT 0000005F)
>[    0.000000] ACPI: SSDT 0x000000008AD248A8 00029F (v02 INTEL  sensrhub 00000000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008AD24B48 003002 (v02 INTEL  PtidDevc 00001000 INTL 20160422)
>[    0.000000] ACPI: DBGP 0x000000008AD27B50 000034 (v01 INTEL           00000002 MSFT 0000005F)
>[    0.000000] ACPI: DBG2 0x000000008AD27B88 000054 (v00 INTEL           00000002 MSFT 0000005F)
>[    0.000000] ACPI: TPM2 0x000000008AD27BE0 000034 (v03        Tpm2Tabl 00000001 AMI  00000000)
>[    0.000000] ACPI: BGRT 0x000000008AD27C18 000038 (v01 MSI_NB MEGABOOK 01072009 AMI  00010013)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>[    0.000000]   Normal   [mem 0x0000000100000000-0x000000026effffff]
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x0000000000001000-0x0000000000057fff]
>[    0.000000]   node   0: [mem 0x0000000000059000-0x000000000009dfff]
>[    0.000000]   node   0: [mem 0x0000000000100000-0x00000000804c7fff]
>[    0.000000]   node   0: [mem 0x00000000804ca000-0x0000000089994fff]
>[    0.000000]   node   0: [mem 0x000000008a91c000-0x000000008a9f9fff]
>[    0.000000]   node   0: [mem 0x000000008b2fe000-0x000000008b2fefff]
>[    0.000000]   node   0: [mem 0x0000000100000000-0x000000026effffff]
>[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000026effffff]
>[    0.000000] On node 0 totalpages: 2066958
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 22 pages reserved
>[    0.000000]   DMA zone: 3996 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 8746 pages used for memmap
>[    0.000000]   DMA32 zone: 559730 pages, LIFO batch:31
>[    0.000000]   Normal zone: 23488 pages used for memmap
>[    0.000000]   Normal zone: 1503232 pages, LIFO batch:31
>[    0.000000] Reserving Intel graphics memory at 0x000000008c000000-0x000000008fffffff
>[    0.000000] ACPI: PM-Timer IO Port: 0x1808
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
>[    0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
>[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x804c8000-0x804c8fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x804c9000-0x804c9fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x89995000-0x8a91bfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8a9fa000-0x8ad7dfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8ad7e000-0x8b299fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8b29a000-0x8b2fdfff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8b2ff000-0x8fffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x90000000-0xdfffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xefffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xfdffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe000000-0xfe010fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe011000-0xfebfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec00000-0xfec00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfec01000-0xfedfffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee00000-0xfee00fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfee01000-0xfeffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xff000000-0xffffffff]
>[    0.000000] e820: [mem 0x90000000-0xdfffffff] available for PCI devices
>[    0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
>[    0.000000] setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1
>[    0.000000] percpu: Embedded 37 pages/cpu @ffff88026ec00000 s114376 r8192 d28984 u524288
>[    0.000000] pcpu-alloc: s114376 r8192 d28984 u524288 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 0 1 2 3 
>[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 2034638
>[    0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc3-drm-tip-ww22-commit-187376e+ root=UUID=f869e850-fa74-451a-a1a4-4b76793f1022 ro quiet splash fastboot drm.debug=0xe vt.handoff=7
>[    0.000000] log_buf_len individual max cpu contribution: 262144 bytes
>[    0.000000] log_buf_len total cpu_extra contributions: 786432 bytes
>[    0.000000] log_buf_len min size: 262144 bytes
>[    0.000000] log_buf_len: 1048576 bytes
>[    0.000000] early log buf free: 250008(95%)
>[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
>[    0.000000] Memory: 7898000K/8267832K available (8664K kernel code, 1377K rwdata, 3444K rodata, 1200K init, 22640K bss, 369832K reserved, 0K cma-reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
>[    0.000000] Running RCU self tests
>[    0.000000] Preemptible hierarchical RCU implementation.
>[    0.000000] 	RCU lockdep checking is enabled.
>[    0.000000] 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=4.
>[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
>[    0.000000] kmemleak: Kernel memory leak detector disabled
>[    0.000000] NR_IRQS:4352 nr_irqs:1024 16
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
>[    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
>[    0.000000] ... MAX_LOCK_DEPTH:          48
>[    0.000000] ... MAX_LOCKDEP_KEYS:        8191
>[    0.000000] ... CLASSHASH_SIZE:          4096
>[    0.000000] ... MAX_LOCKDEP_ENTRIES:     32768
>[    0.000000] ... MAX_LOCKDEP_CHAINS:      65536
>[    0.000000] ... CHAINHASH_SIZE:          32768
>[    0.000000]  memory used by lock dependency info: 8159 kB
>[    0.000000]  per task-struct memory footprint: 1920 bytes
>[    0.000000] kmemleak: Early log buffer exceeded (2883), please increase DEBUG_KMEMLEAK_EARLY_LOG_SIZE
>[    0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns
>[    0.000000] hpet clockevent registered
>[    0.001000] tsc: Detected 2900.000 MHz processor
>[    0.001000] Calibrating delay loop (skipped), value calculated using timer frequency.. 5808.00 BogoMIPS (lpj=2904000)
>[    0.001000] pid_max: default: 32768 minimum: 301
>[    0.001000] ACPI: Core revision 20170303
>[    0.248644] ACPI: 8 ACPI AML tables successfully acquired and loaded
>[    0.249102] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
>[    0.249104] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
>[    0.250109] CPU: Physical Processor ID: 0
>[    0.250110] CPU: Processor Core ID: 0
>[    0.250115] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
>[    0.250116] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
>[    0.250121] mce: CPU supports 8 MCE banks
>[    0.250139] CPU0: Thermal monitoring enabled (TM1)
>[    0.250156] process: using mwait in idle threads
>[    0.250159] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
>[    0.250161] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
>[    0.250337] Freeing SMP alternatives memory: 32K
>[    0.256008] random: fast init done
>[    0.260812] smpboot: Max logical packages: 2
>[    0.262074] x2apic: IRQ remapping doesn't support X2APIC mode
>[    0.266572] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.276611] TSC deadline timer enabled
>[    0.276618] smpboot: CPU0: Intel(R) Core(TM) i7-7500U CPU @ 2.70GHz (family: 0x6, model: 0x8e, stepping: 0x9)
>[    0.280056] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver.
>[    0.280093] ... version:                4
>[    0.280094] ... bit width:              48
>[    0.280095] ... generic registers:      4
>[    0.280097] ... value mask:             0000ffffffffffff
>[    0.280098] ... max period:             00007fffffffffff
>[    0.280099] ... fixed-purpose events:   3
>[    0.280100] ... event mask:             000000070000000f
>[    0.286259] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
>[    0.288037] smp: Bringing up secondary CPUs ...
>[    0.296097] x86: Booting SMP configuration:
>[    0.296101] .... node  #0, CPUs:      #1 #2 #3
>[    0.492170] smp: Brought up 1 node, 4 CPUs
>[    0.492170] smpboot: Total of 4 processors activated (23294.31 BogoMIPS)
>[    0.493248] sched_clock: Marking stable (493000000, 0)->(497139625, -4139625)
>[    0.493786] devtmpfs: initialized
>[    0.494539] PM: Registering ACPI NVS region [mem 0x804c8000-0x804c8fff] (4096 bytes)
>[    0.494544] PM: Registering ACPI NVS region [mem 0x8a9fa000-0x8ad7dfff] (3686400 bytes)
>[    0.496628] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
>[    0.496632] futex hash table entries: 1024 (order: 5, 131072 bytes)
>[    0.496788] xor: automatically using best checksumming function   avx       
>[    0.496794] pinctrl core: initialized pinctrl subsystem
>[    0.497291] NET: Registered protocol family 16
>[    0.498154] cpuidle: using governor menu
>[    0.498158] PCCT header not found.
>[    0.498255] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
>[    0.498260] ACPI: bus type PCI registered
>[    0.498451] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>[    0.498454] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
>[    0.498472] PCI: Using configuration type 1 for base access
>[    0.506747] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>[    0.524142] raid6: sse2x1   gen()  8976 MB/s
>[    0.541217] raid6: sse2x1   xor()  6363 MB/s
>[    0.558289] raid6: sse2x2   gen() 10792 MB/s
>[    0.575358] raid6: sse2x2   xor()  7248 MB/s
>[    0.592426] raid6: sse2x4   gen() 12082 MB/s
>[    0.609502] raid6: sse2x4   xor()  8857 MB/s
>[    0.626576] raid6: avx2x1   gen() 17648 MB/s
>[    0.643653] raid6: avx2x1   xor() 12865 MB/s
>[    0.660728] raid6: avx2x2   gen() 20648 MB/s
>[    0.677804] raid6: avx2x2   xor() 13378 MB/s
>[    0.694880] raid6: avx2x4   gen() 21984 MB/s
>[    0.711963] raid6: avx2x4   xor() 15408 MB/s
>[    0.711965] raid6: using algorithm avx2x4 gen() 21984 MB/s
>[    0.711967] raid6: .... xor() 15408 MB/s, rmw enabled
>[    0.711968] raid6: using avx2x2 recovery algorithm
>[    0.712095] ACPI: Added _OSI(Module Device)
>[    0.712097] ACPI: Added _OSI(Processor Device)
>[    0.712098] ACPI: Added _OSI(3.0 _SCP Extensions)
>[    0.712100] ACPI: Added _OSI(Processor Aggregator Device)
>[    0.724296] ACPI: Executed 30 blocks of module-level executable AML code
>[    0.829093] ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
>[    0.849259] ACPI: Dynamic OEM Table Load:
>[    0.849275] ACPI: SSDT 0xFFFF880264D62548 0006F6 (v02 PmRef  Cpu0Ist  00003000 INTL 20160422)
>[    0.850162] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.850844] ACPI: \_PR_.CPU0: _OSC native thermal LVT Acked
>[    0.863775] ACPI: Dynamic OEM Table Load:
>[    0.863790] ACPI: SSDT 0xFFFF880264D6B528 0003FF (v02 PmRef  Cpu0Cst  00003001 INTL 20160422)
>[    0.864489] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.865440] ACPI: Dynamic OEM Table Load:
>[    0.865454] ACPI: SSDT 0xFFFF88026482B858 000115 (v02 PmRef  Cpu0Hwp  00003000 INTL 20160422)
>[    0.865757] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.866126] ACPI: Dynamic OEM Table Load:
>[    0.866139] ACPI: SSDT 0xFFFF8802648286A8 0001A4 (v02 PmRef  HwpLvt   00003000 INTL 20160422)
>[    0.866374] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.869410] ACPI: Dynamic OEM Table Load:
>[    0.869429] ACPI: SSDT 0xFFFF880264D64A88 00065C (v02 PmRef  ApIst    00003000 INTL 20160422)
>[    0.873683] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.874522] ACPI: Dynamic OEM Table Load:
>[    0.874536] ACPI: SSDT 0xFFFF88026482B508 000197 (v02 PmRef  ApHwp    00003000 INTL 20160422)
>[    0.875300] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.876109] ACPI: Dynamic OEM Table Load:
>[    0.876123] ACPI: SSDT 0xFFFF8802648289F8 00018A (v02 PmRef  ApCst    00003000 INTL 20160422)
>[    0.876893] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.901822] ACPI: Interpreter enabled
>[    0.902006] ACPI: (supports S0 S3 S4 S5)
>[    0.902008] ACPI: Using IOAPIC for interrupt routing
>[    0.902214] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[    0.940089] ACPI: Power Resource [WRST] (on)
>[    0.943362] ACPI: Power Resource [WRST] (on)
>[    0.946710] ACPI: Power Resource [WRST] (on)
>[    0.950069] ACPI: Power Resource [WRST] (on)
>[    0.953389] ACPI: Power Resource [WRST] (on)
>[    0.956685] ACPI: Power Resource [WRST] (on)
>[    0.959967] ACPI: Power Resource [WRST] (on)
>[    0.963312] ACPI: Power Resource [WRST] (on)
>[    0.966634] ACPI: Power Resource [WRST] (on)
>[    0.969937] ACPI: Power Resource [WRST] (on)
>[    0.973227] ACPI: Power Resource [WRST] (on)
>[    0.976546] ACPI: Power Resource [WRST] (on)
>[    0.979831] ACPI: Power Resource [WRST] (on)
>[    0.983074] ACPI: Power Resource [WRST] (on)
>[    0.986309] ACPI: Power Resource [WRST] (on)
>[    0.989584] ACPI: Power Resource [WRST] (on)
>[    0.992822] ACPI: Power Resource [WRST] (on)
>[    1.005465] ACPI: Power Resource [WRST] (on)
>[    1.008730] ACPI: Power Resource [WRST] (on)
>[    1.011954] ACPI: Power Resource [WRST] (on)
>[    1.086875] ACPI: Power Resource [FN00] (off)
>[    1.087928] ACPI: Power Resource [FN01] (off)
>[    1.089026] ACPI: Power Resource [FN02] (off)
>[    1.090117] ACPI: Power Resource [FN03] (off)
>[    1.091184] ACPI: Power Resource [FN04] (off)
>[    1.099973] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
>[    1.099987] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
>[    1.101846] acpi PNP0A08:00: _OSC: platform does not support [PME AER]
>[    1.103615] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PCIeCapability]
>[    1.103617] acpi PNP0A08:00: FADT indicates ASPM is unsupported, using BIOS configuration
>[    1.106029] PCI host bridge to bus 0000:00
>[    1.106034] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
>[    1.106040] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>[    1.106045] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>[    1.106048] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window]
>[    1.106052] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window]
>[    1.106055] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window]
>[    1.106058] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window]
>[    1.106062] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window]
>[    1.106065] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window]
>[    1.106068] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window]
>[    1.106071] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window]
>[    1.106074] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window]
>[    1.106078] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window]
>[    1.106081] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window]
>[    1.106084] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window]
>[    1.106087] pci_bus 0000:00: root bus resource [mem 0x90000000-0xdfffffff window]
>[    1.106090] pci_bus 0000:00: root bus resource [mem 0xfd000000-0xfe7fffff window]
>[    1.106094] pci_bus 0000:00: root bus resource [bus 00-fe]
>[    1.106126] pci 0000:00:00.0: [8086:5904] type 00 class 0x060000
>[    1.108733] pci 0000:00:02.0: [8086:5916] type 00 class 0x030000
>[    1.108749] pci 0000:00:02.0: reg 0x10: [mem 0xde000000-0xdeffffff 64bit]
>[    1.108759] pci 0000:00:02.0: reg 0x18: [mem 0xc0000000-0xcfffffff 64bit pref]
>[    1.108766] pci 0000:00:02.0: reg 0x20: [io  0xf000-0xf03f]
>[    1.109991] pci 0000:00:08.0: [8086:1911] type 00 class 0x088000
>[    1.110008] pci 0000:00:08.0: reg 0x10: [mem 0xdf22f000-0xdf22ffff 64bit]
>[    1.111012] pci 0000:00:14.0: [8086:9d2f] type 00 class 0x0c0330
>[    1.111037] pci 0000:00:14.0: reg 0x10: [mem 0xdf210000-0xdf21ffff 64bit]
>[    1.111162] pci 0000:00:14.0: PME# supported from D3hot D3cold
>[    1.112855] pci 0000:00:14.0: System wakeup disabled by ACPI
>[    1.113006] pci 0000:00:14.2: [8086:9d31] type 00 class 0x118000
>[    1.113030] pci 0000:00:14.2: reg 0x10: [mem 0xdf22e000-0xdf22efff 64bit]
>[    1.114051] pci 0000:00:16.0: [8086:9d3a] type 00 class 0x078000
>[    1.114092] pci 0000:00:16.0: reg 0x10: [mem 0xdf22d000-0xdf22dfff 64bit]
>[    1.114256] pci 0000:00:16.0: PME# supported from D3hot
>[    1.115492] pci 0000:00:17.0: [8086:9d03] type 00 class 0x010601
>[    1.115513] pci 0000:00:17.0: reg 0x10: [mem 0xdf228000-0xdf229fff]
>[    1.115523] pci 0000:00:17.0: reg 0x14: [mem 0xdf22c000-0xdf22c0ff]
>[    1.115534] pci 0000:00:17.0: reg 0x18: [io  0xf090-0xf097]
>[    1.115544] pci 0000:00:17.0: reg 0x1c: [io  0xf080-0xf083]
>[    1.115555] pci 0000:00:17.0: reg 0x20: [io  0xf060-0xf07f]
>[    1.115565] pci 0000:00:17.0: reg 0x24: [mem 0xdf22b000-0xdf22b7ff]
>[    1.115643] pci 0000:00:17.0: PME# supported from D3hot
>[    1.116906] pci 0000:00:1c.0: [8086:9d12] type 01 class 0x060400
>[    1.117023] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[    1.118484] pci 0000:00:1c.0: System wakeup disabled by ACPI
>[    1.118629] pci 0000:00:1c.3: [8086:9d13] type 01 class 0x060400
>[    1.118742] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
>[    1.120201] pci 0000:00:1c.3: System wakeup disabled by ACPI
>[    1.120358] pci 0000:00:1f.0: [8086:9d58] type 00 class 0x060100
>[    1.121684] pci 0000:00:1f.2: [8086:9d21] type 00 class 0x058000
>[    1.121697] pci 0000:00:1f.2: reg 0x10: [mem 0xdf224000-0xdf227fff]
>[    1.122948] pci 0000:00:1f.3: [8086:9d71] type 00 class 0x040300
>[    1.122975] pci 0000:00:1f.3: reg 0x10: [mem 0xdf220000-0xdf223fff 64bit]
>[    1.123008] pci 0000:00:1f.3: reg 0x20: [mem 0xdf200000-0xdf20ffff 64bit]
>[    1.123089] pci 0000:00:1f.3: PME# supported from D3hot D3cold
>[    1.124642] pci 0000:00:1f.3: System wakeup disabled by ACPI
>[    1.124784] pci 0000:00:1f.4: [8086:9d23] type 00 class 0x0c0500
>[    1.124831] pci 0000:00:1f.4: reg 0x10: [mem 0xdf22a000-0xdf22a0ff 64bit]
>[    1.124901] pci 0000:00:1f.4: reg 0x20: [io  0xf040-0xf05f]
>[    1.126276] pci 0000:01:00.0: [10ec:8168] type 00 class 0x020000
>[    1.126307] pci 0000:01:00.0: reg 0x10: [io  0xe000-0xe0ff]
>[    1.126341] pci 0000:01:00.0: reg 0x18: [mem 0xdf104000-0xdf104fff 64bit]
>[    1.126362] pci 0000:01:00.0: reg 0x20: [mem 0xdf100000-0xdf103fff 64bit]
>[    1.126512] pci 0000:01:00.0: supports D1 D2
>[    1.126513] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    1.127104] pci 0000:01:00.0: System wakeup disabled by ACPI
>[    1.127280] pci 0000:00:1c.0: PCI bridge to [bus 01]
>[    1.127285] pci 0000:00:1c.0:   bridge window [io  0xe000-0xefff]
>[    1.127289] pci 0000:00:1c.0:   bridge window [mem 0xdf100000-0xdf1fffff]
>[    1.127429] pci 0000:02:00.0: [8086:24fb] type 00 class 0x028000
>[    1.127477] pci 0000:02:00.0: reg 0x10: [mem 0xdf000000-0xdf001fff 64bit]
>[    1.127702] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
>[    1.128325] pci 0000:02:00.0: System wakeup disabled by ACPI
>[    1.128486] pci 0000:00:1c.3: PCI bridge to [bus 02]
>[    1.128492] pci 0000:00:1c.3:   bridge window [mem 0xdf000000-0xdf0fffff]
>[    1.128511] pci_bus 0000:00: on NUMA node 0
>[    1.143405] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.143993] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 *10 11 12 14 15)
>[    1.144581] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.145159] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.145761] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.146362] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.146953] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.147546] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15)
>[    1.152479] ACPI: Enabled 4 GPEs in block 00 to 7F
>[    1.152917] pci 0000:00:02.0: vgaarb: setting as boot VGA device
>[    1.152921] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
>[    1.152928] pci 0000:00:02.0: vgaarb: bridge control possible
>[    1.152930] vgaarb: loaded
>[    1.153446] SCSI subsystem initialized
>[    1.153608] libata version 3.00 loaded.
>[    1.153706] ACPI: bus type USB registered
>[    1.153799] usbcore: registered new interface driver usbfs
>[    1.153843] usbcore: registered new interface driver hub
>[    1.153902] usbcore: registered new device driver usb
>[    1.154211] Registered efivars operations
>[    1.174055] Advanced Linux Sound Architecture Driver Initialized.
>[    1.174092] PCI: Using ACPI for IRQ routing
>[    1.202314] PCI: pci_cache_line_size set to 64 bytes
>[    1.202381] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>[    1.202390] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
>[    1.202394] e820: reserve RAM buffer [mem 0x804c8000-0x83ffffff]
>[    1.202399] e820: reserve RAM buffer [mem 0x89995000-0x8bffffff]
>[    1.202404] e820: reserve RAM buffer [mem 0x8a9fa000-0x8bffffff]
>[    1.202408] e820: reserve RAM buffer [mem 0x8b2ff000-0x8bffffff]
>[    1.202413] e820: reserve RAM buffer [mem 0x26f000000-0x26fffffff]
>[    1.203093] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>[    1.203105] hpet0: 8 comparators, 64-bit 24.000000 MHz counter
>[    1.205179] clocksource: Switched to clocksource hpet
>[    1.266751] pnp: PnP ACPI init
>[    1.268479] system 00:00: [io  0x0680-0x069f] has been reserved
>[    1.268486] system 00:00: [io  0xffff] has been reserved
>[    1.268491] system 00:00: [io  0xffff] has been reserved
>[    1.268496] system 00:00: [io  0xffff] has been reserved
>[    1.268501] system 00:00: [io  0x1800-0x18fe] has been reserved
>[    1.268509] system 00:00: [io  0x164e-0x164f] has been reserved
>[    1.268529] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.269092] pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    1.269387] system 00:02: [io  0x1854-0x1857] has been reserved
>[    1.269392] system 00:02: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
>[    1.271613] system 00:03: [mem 0xfed10000-0xfed17fff] has been reserved
>[    1.271619] system 00:03: [mem 0xfed18000-0xfed18fff] has been reserved
>[    1.271624] system 00:03: [mem 0xfed19000-0xfed19fff] has been reserved
>[    1.271632] system 00:03: [mem 0xe0000000-0xefffffff] has been reserved
>[    1.271638] system 00:03: [mem 0xfed20000-0xfed3ffff] has been reserved
>[    1.271643] system 00:03: [mem 0xfed90000-0xfed93fff] has been reserved
>[    1.271649] system 00:03: [mem 0xfed45000-0xfed8ffff] has been reserved
>[    1.271654] system 00:03: [mem 0xff000000-0xffffffff] has been reserved
>[    1.271664] system 00:03: [mem 0xfee00000-0xfeefffff] could not be reserved
>[    1.271670] system 00:03: [mem 0xdffc0000-0xdffdffff] has been reserved
>[    1.271675] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.271963] system 00:04: [mem 0xfd000000-0xfdabffff] has been reserved
>[    1.271968] system 00:04: [mem 0xfdad0000-0xfdadffff] has been reserved
>[    1.271973] system 00:04: [mem 0xfdb00000-0xfdffffff] has been reserved
>[    1.271981] system 00:04: [mem 0xfe000000-0xfe01ffff] could not be reserved
>[    1.271986] system 00:04: [mem 0xfe036000-0xfe03bfff] has been reserved
>[    1.271991] system 00:04: [mem 0xfe03d000-0xfe3fffff] has been reserved
>[    1.271996] system 00:04: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.273966] system 00:05: [io  0xff00-0xfffe] has been reserved
>[    1.273971] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.284222] system 00:06: [mem 0xfe029000-0xfe029fff] has been reserved
>[    1.284227] system 00:06: [mem 0xfe028000-0xfe028fff] has been reserved
>[    1.284232] system 00:06: [mem 0xfdaf0000-0xfdafffff] has been reserved
>[    1.284237] system 00:06: [mem 0xfdae0000-0xfdaeffff] has been reserved
>[    1.284242] system 00:06: [mem 0xfdac0000-0xfdacffff] has been reserved
>[    1.284248] system 00:06: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    1.291996] pnp: PnP ACPI: found 7 devices
>[    1.306062] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
>[    1.306086] pci 0000:00:1c.0: PCI bridge to [bus 01]
>[    1.306089] pci 0000:00:1c.0:   bridge window [io  0xe000-0xefff]
>[    1.306095] pci 0000:00:1c.0:   bridge window [mem 0xdf100000-0xdf1fffff]
>[    1.306104] pci 0000:00:1c.3: PCI bridge to [bus 02]
>[    1.306108] pci 0000:00:1c.3:   bridge window [mem 0xdf000000-0xdf0fffff]
>[    1.306117] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
>[    1.306119] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
>[    1.306121] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
>[    1.306123] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window]
>[    1.306124] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window]
>[    1.306126] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window]
>[    1.306127] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window]
>[    1.306129] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window]
>[    1.306131] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window]
>[    1.306132] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window]
>[    1.306134] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window]
>[    1.306136] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window]
>[    1.306137] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window]
>[    1.306139] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window]
>[    1.306140] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window]
>[    1.306142] pci_bus 0000:00: resource 19 [mem 0x90000000-0xdfffffff window]
>[    1.306144] pci_bus 0000:00: resource 20 [mem 0xfd000000-0xfe7fffff window]
>[    1.306146] pci_bus 0000:01: resource 0 [io  0xe000-0xefff]
>[    1.306147] pci_bus 0000:01: resource 1 [mem 0xdf100000-0xdf1fffff]
>[    1.306149] pci_bus 0000:02: resource 1 [mem 0xdf000000-0xdf0fffff]
>[    1.307148] NET: Registered protocol family 2
>[    1.307681] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
>[    1.307772] TCP bind hash table entries: 65536 (order: 10, 4194304 bytes)
>[    1.310708] TCP: Hash tables configured (established 65536 bind 65536)
>[    1.310853] UDP hash table entries: 4096 (order: 7, 655360 bytes)
>[    1.311302] UDP-Lite hash table entries: 4096 (order: 7, 655360 bytes)
>[    1.311917] NET: Registered protocol family 1
>[    1.311941] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>[    1.313950] PCI: CLS 0 bytes, default 64
>[    1.314242] Unpacking initramfs...
>[    1.516723] Freeing initrd memory: 11508K
>[    1.516728] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[    1.516731] software IO TLB [mem 0x7c10c000-0x8010c000] (64MB) mapped at [ffff88007c10c000-ffff88008010bfff]
>[    1.516929] RAPL PMU: API unit is 2^-32 Joules, 5 fixed counters, 655360 ms ovfl timer
>[    1.516931] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules
>[    1.516932] RAPL PMU: hw unit of domain package 2^-14 Joules
>[    1.516933] RAPL PMU: hw unit of domain dram 2^-14 Joules
>[    1.516934] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules
>[    1.516936] RAPL PMU: hw unit of domain psys 2^-14 Joules
>[    1.517288] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x29dc05e54fc, max_idle_ns: 440795291716 ns
>[    1.521920] workingset: timestamp_bits=46 max_order=21 bucket_order=0
>[    1.535039] ntfs: driver 2.1.32 [Flags: R/O].
>[    1.545671] NET: Registered protocol family 38
>[    1.545829] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
>[    1.545837] io scheduler noop registered
>[    1.546042] io scheduler cfq registered (default)
>[    1.546043] io scheduler mq-deadline registered
>[    1.546045] io scheduler kyber registered
>[    1.546046] start plist test
>[    1.547264] end plist test
>[    1.550902] uvesafb: failed to execute /sbin/v86d
>[    1.550920] uvesafb: make sure that the v86d helper is installed and executable
>[    1.550937] uvesafb: Getting VBE info block failed (eax=0x4f00, err=-2)
>[    1.550952] uvesafb: vbe_init() failed with -22
>[    1.550979] uvesafb: probe of uvesafb.0 failed with error -22
>[    1.551038] intel_idle: MWAIT substates: 0x11142120
>[    1.551039] intel_idle: v0.4.1 model 0x8E
>[    1.552383] intel_idle: lapic_timer_reliable_states 0xffffffff
>[    1.552826] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input0
>[    1.552879] ACPI: Sleep Button [SLPB]
>[    1.553042] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
>[    1.553081] ACPI: Power Button [PWRB]
>[    1.553291] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
>[    1.553364] ACPI: Power Button [PWRF]
>[    1.601918] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info().
>[    1.643785] thermal LNXTHERM:00: registered as thermal_zone0
>[    1.643789] ACPI: Thermal Zone [TZ00] (28 C)
>[    1.645557] thermal LNXTHERM:01: registered as thermal_zone1
>[    1.645559] ACPI: Thermal Zone [TZ01] (30 C)
>[    1.645965] GHES: HEST is not enabled!
>[    1.646287] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
>[    1.667328] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>[    1.688545] serial8250: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A
>[    1.690718] Non-volatile memory driver v1.3
>[    1.690960] Linux agpgart interface v0.103
>[    1.692826] loop: module loaded
>[    1.693467] ahci 0000:00:17.0: version 3.0
>[    1.694600] ahci 0000:00:17.0: AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
>[    1.694603] ahci 0000:00:17.0: flags: 64bit ncq pm led clo only pio slum part deso sadm sds apst 
>[    1.696412] scsi host0: ahci
>[    1.697160] scsi host1: ahci
>[    1.697389] ata1: SATA max UDMA/133 abar m2048@0xdf22b000 port 0xdf22b100 irq 120
>[    1.697392] ata2: SATA max UDMA/133 abar m2048@0xdf22b000 port 0xdf22b180 irq 120
>[    1.697557] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[    1.697571] ehci-pci: EHCI PCI platform driver
>[    1.697618] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[    1.697626] ohci-pci: OHCI PCI platform driver
>[    1.697658] uhci_hcd: USB Universal Host Controller Interface driver
>[    1.698861] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.698917] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
>[    1.700131] xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00109810
>[    1.700137] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
>[    1.700557] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.700561] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.700563] usb usb1: Product: xHCI Host Controller
>[    1.700565] usb usb1: Manufacturer: Linux 4.12.0-rc3-drm-tip-ww22-commit-187376e+ xhci-hcd
>[    1.700566] usb usb1: SerialNumber: 0000:00:14.0
>[    1.701244] hub 1-0:1.0: USB hub found
>[    1.701326] hub 1-0:1.0: 12 ports detected
>[    1.768336] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.768351] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>[    1.768607] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[    1.768610] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.768612] usb usb2: Product: xHCI Host Controller
>[    1.768614] usb usb2: Manufacturer: Linux 4.12.0-rc3-drm-tip-ww22-commit-187376e+ xhci-hcd
>[    1.768615] usb usb2: SerialNumber: 0000:00:14.0
>[    1.769236] hub 2-0:1.0: USB hub found
>[    1.769302] hub 2-0:1.0: 6 ports detected
>[    1.802419] usb: port power management may be unreliable
>[    1.803930] usbcore: registered new interface driver usb-storage
>[    1.804122] i8042: PNP: No PS/2 controller found.
>[    1.804341] mousedev: PS/2 mouse device common for all mice
>[    1.805019] rtc_cmos 00:01: RTC can wake from S4
>[    1.805612] rtc_cmos 00:01: rtc core: registered rtc_cmos as rtc0
>[    1.805703] rtc_cmos 00:01: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[    1.806070] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0)
>[    1.806495] device-mapper: uevent: version 1.0.3
>[    1.806885] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
>[    1.806887] intel_pstate: Intel P-state driver initializing
>[    1.807813] intel_pstate: HWP enabled
>[    1.809361] EFI Variables Facility v0.08 2004-May-17
>[    1.833502] hidraw: raw HID events driver (C) Jiri Kosina
>[    1.833764] usbcore: registered new interface driver usbhid
>[    1.833765] usbhid: USB HID core driver
>[    1.833990] intel_rapl: Found RAPL domain package
>[    1.833991] intel_rapl: Found RAPL domain core
>[    1.833993] intel_rapl: Found RAPL domain uncore
>[    1.833994] intel_rapl: Found RAPL domain dram
>[    1.835021] Initializing XFRM netlink socket
>[    1.835614] NET: Registered protocol family 10
>[    1.836471] Segment Routing with IPv6
>[    1.836499] mip6: Mobile IPv6
>[    1.836507] NET: Registered protocol family 17
>[    1.836515] NET: Registered protocol family 15
>[    1.837249] AVX2 version of gcm_enc/dec engaged.
>[    1.837250] AES CTR mode by8 optimization enabled
>[    1.861943] alg: No test for pcbc(aes) (pcbc-aes-aesni)
>[    1.862415] registered taskstats version 1
>[    1.864195] Btrfs loaded, crc32c=crc32c-generic
>[    1.869821] rtc_cmos 00:01: setting system clock to 2017-06-06 17:30:21 UTC (1496770221)
>[    1.870051] PM: Hibernation image not present or could not be loaded.
>[    1.870057] ALSA device list:
>[    1.870058]   No soundcards found.
>[    2.005158] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[    2.005260] ata2: SATA link down (SStatus 4 SControl 300)
>[    2.008377] ata1.00: ATA-10: INTEL SSDSC2BW120H6, RG20, max UDMA/133
>[    2.008384] ata1.00: 234441648 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>[    2.021623] ata1.00: configured for UDMA/133
>[    2.023984] scsi 0:0:0:0: Direct-Access     ATA      INTEL SSDSC2BW12 RG20 PQ: 0 ANSI: 5
>[    2.027623] sd 0:0:0:0: Attached scsi generic sg0 type 0
>[    2.028018] sd 0:0:0:0: [sda] 234441648 512-byte logical blocks: (120 GB/112 GiB)
>[    2.028221] sd 0:0:0:0: [sda] Write Protect is off
>[    2.028227] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[    2.028528] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    2.033598]  sda: sda1 sda2 sda3
>[    2.037106] sd 0:0:0:0: [sda] Attached SCSI disk
>[    2.040404] Freeing unused kernel memory: 1200K
>[    2.040409] Write protecting the kernel read-only data: 14336k
>[    2.042673] Freeing unused kernel memory: 1556K
>[    2.045934] Freeing unused kernel memory: 652K
>[    2.131234] usb 1-3: new low-speed USB device number 2 using xhci_hcd
>[    2.263646] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
>[    2.263662] r8169 0000:01:00.0: can't disable ASPM; OS doesn't have ASPM control
>[    2.266120] [drm:i915_driver_load [i915]] Found SunrisePoint LP PCH
>[    2.266151] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[    2.267150] [drm:intel_device_info_dump [i915]] i915 device info: platform=KABYLAKE gen=9 pciid=0x5916 rev=0x02
>[    2.267181] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[    2.267945] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[    2.267968] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[    2.267990] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[    2.268010] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[    2.268030] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[    2.268056] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[    2.268078] [drm:intel_device_info_dump [i915]] i915 device info: has_decoupled_mmio: no
>[    2.268095] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[    2.268112] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[    2.268134] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[    2.268159] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[    2.268183] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[    2.268245] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>[    2.268271] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[    2.268295] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[    2.268320] [drm:intel_device_info_dump [i915]] i915 device info: has_guc_ct: no
>[    2.268345] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[    2.268370] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[    2.268394] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[    2.268419] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[    2.268444] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[    2.268462] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>[    2.268479] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[    2.268495] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[    2.268512] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[    2.268534] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[    2.268558] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[    2.268583] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[    2.268608] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[    2.268629] [drm:intel_device_info_dump [i915]] i915 device info: unfenced_needs_alignment: no
>[    2.268654] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[    2.268677] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[    2.268701] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[    2.268725] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[    2.270389] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[    2.270421] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[    2.270452] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[    2.270480] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[    2.270509] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[    2.270537] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[    2.270564] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[    2.270590] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[    2.270616] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[    2.270640] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[    2.270692] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[    2.270720] [drm:i915_driver_load [i915]] use GPU semaphores? no
>[    2.270753] [drm] Memory usable by graphics device = 4096M
>[    2.270787] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[    2.270819] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>[    2.270840] [drm] Replacing VGA console driver
>[    2.270916] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>[    2.271001] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8ad61018
>[    2.271060] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[    2.271095] [drm:intel_opregion_setup [i915]] SWSCI supported
>[    2.274613] r8169 0000:01:00.0 eth0: RTL8168h/8111h at 0xffffc9000002d000, 4c:cc:6a:6a:00:26, XID 14100880 IRQ 122
>[    2.274616] r8169 0000:01:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko]
>[    2.280321] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[    2.280362] [drm:intel_opregion_setup [i915]] ASLE supported
>[    2.280395] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[    2.280426] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[    2.280596] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[    2.280602] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[    2.280603] [drm] Driver supports precise vblank timestamp query.
>[    2.280633] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[    2.280660] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 207
>[    2.280684] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[    2.280707] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[    2.284251] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[    2.284290] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[    2.284324] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[    2.284359] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[    2.284364] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    2.284393] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[    2.284420] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[    2.284448] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>[    2.284472] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 207 not known; assuming 38
>[    2.284502] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[    2.284539] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[    2.284562] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[    2.284586] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    2.284606] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[    2.284630] [drm:intel_bios_init [i915]] Port C VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>[    2.284652] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[    2.284989] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[    2.285036] [drm:intel_update_rawclk [i915]] rawclk rate: 24000 kHz
>[    2.285069] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[    2.285139] [drm:intel_power_well_enable [i915]] enabling power well 1
>[    2.285175] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[    2.285239] [drm:intel_update_cdclk [i915]] Current CD clock rate: 675000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    2.285278] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[    2.285307] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 675000 kHz
>[    2.285350] [drm:intel_power_well_enable [i915]] enabling always-on
>[    2.285378] [drm:intel_power_well_enable [i915]] enabling DC off
>[    2.285405] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[    2.285437] [drm:intel_power_well_enable [i915]] enabling power well 2
>[    2.285463] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[    2.285488] [drm:skl_set_power_well [i915]] Enabling DDI A/E IO power well
>[    2.285527] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[    2.285556] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[    2.285582] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>[    2.285609] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[    2.285636] [drm:skl_set_power_well [i915]] Enabling DDI D IO power well
>[    2.285683] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_01.bin
>[    2.287298] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_01.bin (v1.1)
>[    2.289315] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[    2.289357] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[    2.289388] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[    2.289418] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[    2.289445] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[    2.289473] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[    2.289500] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[    2.289523] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[    2.289545] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[    2.289601] [drm:intel_modeset_init [i915]] 3 display pipes available.
>[    2.290836] [drm:intel_update_cdclk [i915]] Current CD clock rate: 675000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    2.290854] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem
>[    2.291452] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[    2.291529] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[    2.291655] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0
>[    2.291691] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 5000
>[    2.291723] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 500
>[    2.291755] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[    2.291841] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x4af05
>[    2.291879] [drm:intel_edp_panel_vdd_sanitize [i915]] VDD left on by BIOS, adjusting state tracking
>[    2.302924] usb 1-3: New USB device found, idVendor=046d, idProduct=c077
>[    2.302931] usb 1-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[    2.302934] usb 1-3: Product: USB Optical Mouse
>[    2.302936] usb 1-3: Manufacturer: Logitech
>[    2.303585] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.306434] input: Logitech USB Optical Mouse as /devices/pci0000:00/0000:00:14.0/usb1/1-3/1-3:1.0/0003:046D:C077.0001/input/input3
>[    2.307335] hid-generic 0003:046D:C077.0001: input,hidraw0: USB HID v1.11 Mouse [Logitech USB Optical Mouse] on usb-0000:00:14.0-3/input0
>[    2.312513] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.314842] r8169 0000:01:00.0 enp1s0: renamed from eth0
>[    2.321093] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.329692] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.338272] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.346852] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.355432] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.364042] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.372623] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.381229] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.389807] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.398382] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.406958] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.415529] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.424105] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.432680] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.441254] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.449829] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.458404] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.463220] usb 1-4: new low-speed USB device number 3 using xhci_hcd
>[    2.466978] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.475553] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.484128] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.492731] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.501336] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.509916] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.518488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.527059] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.533470] clocksource: Switched to clocksource tsc
>[    2.535592] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.544040] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.552488] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.560934] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.569381] [drm:intel_dp_aux_ch [i915]] dp_aux_ch timeout status 0x7d4003ff
>[    2.569391] [drm:drm_dp_dpcd_access] Too many retries, giving up. First error: -110
>[    2.569395] [drm] failed to retrieve link info, disabling eDP
>[    2.569434] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[    2.569489] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000000
>[    2.569549] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[    2.569574] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[    2.569641] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>[    2.569664] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x5 for port B (platform default)
>[    2.569701] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[    2.569723] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>[    2.569822] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x1
>[    2.569848] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:32:pipe A] hw state readout: enabled
>[    2.569873] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>[    2.569896] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:39:pipe B] hw state readout: disabled
>[    2.569919] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>[    2.569940] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:46:pipe C] hw state readout: disabled
>[    2.569961] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[    2.569981] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000001, on 1
>[    2.570000] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[    2.570019] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[    2.570043] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:47:DDI B] hw state readout: enabled, pipe A
>[    2.570060] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:49:DP-MST A] hw state readout: disabled, pipe A
>[    2.570077] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:50:DP-MST B] hw state readout: disabled, pipe B
>[    2.570094] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:51:DP-MST C] hw state readout: disabled, pipe C
>[    2.570111] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI C] hw state readout: disabled, pipe A
>[    2.570143] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:48:DP-1] hw state readout: enabled
>[    2.570164] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:54:HDMI-A-1] hw state readout: disabled
>[    2.570181] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:HDMI-A-2] hw state readout: disabled
>[    2.570282] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][setup_hw_state]
>[    2.570302] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[    2.570321] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    2.570339] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.570342] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 61 540000 3840 3888 3920 4000 2160 2163 2168 2222 0x40 0x9
>[    2.570360] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.570363] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 61 540000 3840 3888 3920 4000 2160 2163 2168 2222 0x40 0x9
>[    2.570380] [drm:intel_dump_pipe_config [i915]] crtc timings: 540000 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x40 flags: 0x9
>[    2.570397] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 1024x768, pixel rate 540000
>[    2.570414] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
>[    2.570431] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0f000870, enabled
>[    2.570447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.570469] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.570487] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.570504] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[    2.570520] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[    2.570536] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[    2.570553] [drm:intel_dump_pipe_config [i915]] [CRTC:39:pipe B][setup_hw_state]
>[    2.570569] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[    2.570584] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    2.570599] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.570602] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.570617] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.570619] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.570635] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    2.570650] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[    2.570665] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>[    2.570680] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.570695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.570716] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.570732] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.570748] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 1B] disabled, scaler_id = -1
>[    2.570764] [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2B] disabled, scaler_id = -1
>[    2.570779] [drm:intel_dump_pipe_config [i915]] [PLANE:37:cursor B] disabled, scaler_id = -1
>[    2.570795] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe C][setup_hw_state]
>[    2.570811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>[    2.570825] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    2.570840] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.570843] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.570857] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.570859] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.570874] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    2.570889] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[    2.570905] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>[    2.570920] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.570935] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.570955] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.570971] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.570987] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 1C] disabled, scaler_id = -1
>[    2.571003] [drm:intel_dump_pipe_config [i915]] [PLANE:42:plane 2C] disabled, scaler_id = -1
>[    2.571018] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor C] disabled, scaler_id = -1
>[    2.571038] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[    2.571103] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[    2.571126] [drm:skl_set_power_well [i915]] Disabling DDI D IO power well
>[    2.571147] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[    2.571167] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>[    2.571186] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[    2.571212] [drm:skl_set_power_well [i915]] Disabling DDI A/E IO power well
>[    2.571250] [drm:skylake_get_initial_plane_config [i915]] pipe A with fb: size=1024x768@32, offset=0, pitch 4096, size 0x300000
>[    2.571274] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=300000
>[    2.571312] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] failed to allocate stolen space
>[    2.571340] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>[    2.571626] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, 100000000]
>[    2.571672] [drm:i915_gem_context_init [i915]] logical context support initialized
>[    2.571752] [drm:intel_engine_create_scratch [i915]] rcs0 pipe control offset: 0xfffff000
>[    2.572579] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0
>[    2.572618] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 17
>[    2.572687] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0
>[    2.572756] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0
>[    2.572822] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0
>[    2.572946] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[    2.572970] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[    2.572992] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>[    2.573014] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[    2.573973] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[    2.574463] [drm] Initialized i915 1.6.0 20170529 for 0000:00:02.0 on minor 0
>[    2.574986] [drm:intel_opregion_register [i915]] 3 outputs detected
>[    2.582790] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[    2.585693] [drm:asle_work [i915]] bclp = 0x80000002
>[    2.585730] [drm:asle_work [i915]] updating opregion backlight 2/255
>[    2.586544] [drm:asle_work [i915]] bclp = 0x800000ff
>[    2.586572] [drm:asle_work [i915]] updating opregion backlight 255/255
>[    2.587038] acpi device:0f: registered as cooling_device9
>[    2.587561] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input4
>[    2.588251] [drm] DRM_I915_DEBUG enabled
>[    2.588253] [drm] DRM_I915_DEBUG_GEM enabled
>[    2.588265] [drm:drm_setup_crtcs] 
>[    2.588276] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[    2.588322] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[    2.589339] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 80 02 00 06 00 00 00 00
>[    2.590187] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[    2.590225] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    2.590251] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    2.590275] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    2.591174] [drm:drm_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[    2.592009] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    2.605090] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    2.605896] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] status updated from unknown to connected
>[    2.606117] [drm:drm_edid_to_eld] ELD monitor S277HK
>[    2.606119] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[    2.606167] [drm:drm_mode_debug_printmodeline] Modeline 92:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[    2.606168] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    2.606173] [drm:drm_mode_debug_printmodeline] Modeline 93:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[    2.606185] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[    2.606189] [drm:drm_mode_debug_printmodeline] Modeline 112:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[    2.606190] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    2.606197] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] probed modes :
>[    2.606199] [drm:drm_mode_debug_printmodeline] Modeline 60:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[    2.606202] [drm:drm_mode_debug_printmodeline] Modeline 63:"3840x2160" 30 262790 3840 3888 3920 4000 2160 2165 2170 2191 0x40 0x5
>[    2.606204] [drm:drm_mode_debug_printmodeline] Modeline 64:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[    2.606206] [drm:drm_mode_debug_printmodeline] Modeline 65:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[    2.606208] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    2.606210] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    2.606212] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    2.606214] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    2.606216] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    2.606218] [drm:drm_mode_debug_printmodeline] Modeline 98:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    2.606220] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[    2.606222] [drm:drm_mode_debug_printmodeline] Modeline 114:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[    2.606224] [drm:drm_mode_debug_printmodeline] Modeline 71:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[    2.606227] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    2.606229] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    2.606231] [drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[    2.606233] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    2.606235] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    2.606237] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.606239] [drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.606241] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    2.606243] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    2.606245] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    2.606247] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    2.606249] [drm:drm_mode_debug_printmodeline] Modeline 83:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    2.606251] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    2.606253] [drm:drm_mode_debug_printmodeline] Modeline 85:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    2.606255] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    2.606257] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    2.606259] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    2.606262] [drm:drm_mode_debug_printmodeline] Modeline 110:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.606264] [drm:drm_mode_debug_printmodeline] Modeline 90:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.606266] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    2.606268] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[    2.606270] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    2.606272] [drm:drm_mode_debug_printmodeline] Modeline 106:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.606274] [drm:drm_mode_debug_printmodeline] Modeline 77:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.606276] [drm:drm_mode_debug_printmodeline] Modeline 78:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    2.606279] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[    2.606308] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[    2.608544] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    2.608574] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    2.610790] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    2.610794] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    2.613011] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    2.613038] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    2.615267] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    2.615271] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[    2.615274] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] status updated from unknown to disconnected
>[    2.615276] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[    2.615279] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[    2.615307] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[    2.617527] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    2.617554] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    2.619766] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    2.619770] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[    2.621986] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    2.622012] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    2.624236] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    2.624240] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[    2.624244] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] status updated from unknown to disconnected
>[    2.624246] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[    2.624256] [drm:drm_setup_crtcs] connector 48 enabled? yes
>[    2.624258] [drm:drm_setup_crtcs] connector 54 enabled? no
>[    2.624260] [drm:drm_setup_crtcs] connector 57 enabled? no
>[    2.624289] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[    2.624294] [drm:drm_setup_crtcs] looking for cmdline mode on connector 48
>[    2.624296] [drm:drm_setup_crtcs] looking for preferred mode on connector 48 0
>[    2.624298] [drm:drm_setup_crtcs] found mode 3840x2160
>[    2.624299] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>[    2.624306] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 32 (0,0)
>[    2.624338] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[    2.636906] [drm:intelfb_create [i915]] allocated 3840x2160 fb: 0x00040000
>[    2.637238] fbcon: inteldrmfb (fb0) is primary device
>[    2.637716] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[    2.637742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[    2.637768] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[    2.637794] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[    2.637815] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[    2.637840] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    2.637863] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[    2.637883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[    2.637904] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[    2.637922] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[    2.637940] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.637944] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[    2.637961] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.637964] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[    2.637981] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[    2.637998] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[    2.638014] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
>[    2.638031] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.638046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.638068] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.638085] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.638102] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[    2.638118] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[    2.638134] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[    2.638155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[    2.638179] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[    2.638207] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[    2.638226] [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>[    2.638476] [drm:intel_disable_pipe [i915]] disabling pipe A
>[    2.641121] usb 1-4: New USB device found, idVendor=03f0, idProduct=0024
>[    2.641123] usb 1-4: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>[    2.641123] usb 1-4: Product: HP Basic USB Keyboard
>[    2.641124] usb 1-4: Manufacturer: CHICONY
>[    2.647637] input: CHICONY HP Basic USB Keyboard as /devices/pci0000:00/0000:00:14.0/usb1/1-4/1-4:1.0/0003:03F0:0024.0002/input/input5
>[    2.651162] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[    2.651189] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[    2.651280] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[    2.651316] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[    2.651348] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[    2.651378] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[    2.651402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[    2.651423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[    2.651442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[    2.651461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[    2.651479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[    2.651499] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[    2.651519] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[    2.651538] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[    2.651556] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[    2.651581] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[    2.651601] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[    2.653844] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[    2.653870] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[    2.656853] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[    2.656878] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[    2.656901] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[    2.656923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[    2.660529] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[    2.660554] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[    2.660576] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[    2.664154] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[    2.664179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[    2.664212] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[    2.667790] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[    2.667816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[    2.670618] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[    2.672742] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4
>[    2.673686] [drm:intel_enable_pipe [i915]] enabling pipe A
>[    2.673725] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[    2.673748] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[    2.673793] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[    2.673834] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[    2.673858] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[    2.700197] hid-generic 0003:03F0:0024.0002: input,hidraw1: USB HID v1.10 Keyboard [CHICONY HP Basic USB Keyboard] on usb-0000:00:14.0-4/input0
>[    2.707293] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[    2.707341] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[    2.707395] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[    2.707431] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[    2.707521] Console: switching to colour frame buffer device 480x135
>[    2.747008] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[    2.856293] usb 1-5: new full-speed USB device number 4 using xhci_hcd
>[    3.026688] usb 1-5: New USB device found, idVendor=8087, idProduct=0aa7
>[    3.026696] usb 1-5: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    3.235008] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null)
>[    3.406349] systemd[1]: systemd 232 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN)
>[    3.406702] systemd[1]: Detected architecture x86-64.
>[    3.406984] systemd[1]: Set hostname to <gfx-desktop>.
>[    3.502779] systemd[1]: Listening on udev Kernel Socket.
>[    3.503325] systemd[1]: Created slice User and Session Slice.
>[    3.503488] systemd[1]: Listening on Journal Socket.
>[    3.503596] systemd[1]: Listening on /dev/initctl Compatibility Named Pipe.
>[    3.503871] systemd[1]: Created slice System Slice.
>[    3.505264] systemd[1]: Starting Uncomplicated firewall...
>[    3.505560] systemd[1]: Created slice system-systemd\x2dfsck.slice.
>[    3.655619] EXT4-fs (sda3): re-mounted. Opts: errors=remount-ro
>[    3.704082] systemd-journald[247]: Received request to flush runtime journal from PID 1
>[    3.750016] [drm] RC6 on
>[    4.237894] mei_me 0000:00:16.0: enabling device (0000 -> 0002)
>[    4.241432] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[    4.241503] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[    4.244748] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 80 02 00 06 00 00 00 00
>[    4.246164] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[    4.246194] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    4.246238] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    4.246264] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    4.247613] [drm:drm_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[    4.248522] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    4.251120] [drm:asle_work [i915]] bclp = 0x800000ff
>[    4.269676] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[    4.270884] [drm:drm_edid_to_eld] ELD monitor S277HK
>[    4.270889] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[    4.271073] [drm:drm_mode_debug_printmodeline] Modeline 132:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[    4.271077] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    4.271084] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[    4.271087] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[    4.271094] [drm:drm_mode_debug_printmodeline] Modeline 152:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[    4.271097] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[    4.271316] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] probed modes :
>[    4.271328] [drm:drm_mode_debug_printmodeline] Modeline 60:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[    4.271332] [drm:drm_mode_debug_printmodeline] Modeline 63:"3840x2160" 30 262790 3840 3888 3920 4000 2160 2165 2170 2191 0x40 0x5
>[    4.271336] [drm:drm_mode_debug_printmodeline] Modeline 64:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[    4.271340] [drm:drm_mode_debug_printmodeline] Modeline 65:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[    4.271344] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    4.271347] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    4.271351] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    4.271355] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[    4.271359] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    4.271363] [drm:drm_mode_debug_printmodeline] Modeline 98:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[    4.271366] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[    4.271370] [drm:drm_mode_debug_printmodeline] Modeline 114:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[    4.271374] [drm:drm_mode_debug_printmodeline] Modeline 71:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[    4.271377] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    4.271381] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    4.271385] [drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[    4.271389] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[    4.271392] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[    4.271396] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.271400] [drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.271403] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    4.271407] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[    4.271411] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[    4.271415] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    4.271419] [drm:drm_mode_debug_printmodeline] Modeline 83:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[    4.271423] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[    4.271427] [drm:drm_mode_debug_printmodeline] Modeline 85:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[    4.271430] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    4.271450] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[    4.271454] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    4.271458] [drm:drm_mode_debug_printmodeline] Modeline 110:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.271461] [drm:drm_mode_debug_printmodeline] Modeline 90:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.271465] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[    4.271469] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[    4.271473] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[    4.271476] [drm:drm_mode_debug_printmodeline] Modeline 106:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.271480] [drm:drm_mode_debug_printmodeline] Modeline 77:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.271484] [drm:drm_mode_debug_printmodeline] Modeline 78:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[    4.273702] [drm:asle_work [i915]] updating opregion backlight 255/255
>[    4.302147] snd_hda_intel 0000:00:1f.3: enabling device (0000 -> 0002)
>[    4.306399] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[    4.311671] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[    4.311712] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[    4.313789] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    4.313817] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    4.315341] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[    4.315348] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[    4.317307] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    4.317438] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[    4.319283] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[    4.319291] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[    4.319297] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[    4.319320] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[    4.319348] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[    4.321290] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    4.321320] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    4.323290] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    4.323298] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[    4.325373] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    4.325403] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    4.327283] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    4.327290] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[    4.327296] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[    4.327475] [drm:drm_mode_addfb2] [FB:59]
>[    4.362472] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC887-VD: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:hp
>[    4.362477] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[    4.362480] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=0 (0x0/0x0/0x0/0x0/0x0)
>[    4.362482] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[    4.362484] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[    4.362487] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>[    4.380879] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    4.380923] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    4.380955] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    4.380982] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    4.381008] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    4.381034] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    4.381061] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    4.381083] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    4.386317] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input6
>[    4.387097] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input7
>[    4.387526] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input8
>[    4.387865] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input9
>[    4.388300] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input10
>[    4.388765] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input11
>[    4.389237] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input12
>[    4.518793] [drm:drm_mode_addfb2] [FB:59]
>[    4.518862] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[    4.518907] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[    4.565025] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[    4.565058] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[    4.666323] Adding 8787964k swap on /dev/sda2.  Priority:-1 extents:1 across:8787964k SSFS
>[    4.703499] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
>[    5.381078] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready
>[    5.400080] r8169 0000:01:00.0 enp1s0: link down
>[    5.400093] r8169 0000:01:00.0 enp1s0: link down
>[    5.400359] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready
>[    8.844759] random: crng init done
>[    9.390174] r8169 0000:01:00.0 enp1s0: link up
>[    9.390268] IPv6: ADDRCONF(NETDEV_CHANGE): enp1s0: link becomes ready
>[   12.773783] [drm:drm_fb_helper_hotplug_event] 
>[   12.773796] [drm:drm_setup_crtcs] 
>[   12.773818] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1]
>[   12.773903] [drm:intel_dp_detect [i915]] [CONNECTOR:48:DP-1]
>[   12.774960] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 00 01 80 02 00 06 00 00 00 00
>[   12.775835] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink yes
>[   12.775867] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[   12.775896] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[   12.775924] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[   12.776844] [drm:drm_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID Dp1.2 HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[   12.777781] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[   12.794986] [drm:drm_detect_monitor_audio] Monitor has basic audio support
>[   12.795966] [drm:drm_edid_to_eld] ELD monitor S277HK
>[   12.795969] [drm:drm_edid_to_eld] ELD size 32, SAD count 1
>[   12.796092] [drm:drm_mode_debug_printmodeline] Modeline 132:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[   12.796094] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[   12.796098] [drm:drm_mode_debug_printmodeline] Modeline 133:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[   12.796100] [drm:drm_mode_prune_invalid] Not using 720x576i mode: H_ILLEGAL
>[   12.796104] [drm:drm_mode_debug_printmodeline] Modeline 152:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[   12.796105] [drm:drm_mode_prune_invalid] Not using 720x480i mode: H_ILLEGAL
>[   12.796284] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:48:DP-1] probed modes :
>[   12.796288] [drm:drm_mode_debug_printmodeline] Modeline 60:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[   12.796291] [drm:drm_mode_debug_printmodeline] Modeline 63:"3840x2160" 30 262790 3840 3888 3920 4000 2160 2165 2170 2191 0x40 0x5
>[   12.796293] [drm:drm_mode_debug_printmodeline] Modeline 64:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[   12.796295] [drm:drm_mode_debug_printmodeline] Modeline 65:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[   12.796297] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   12.796300] [drm:drm_mode_debug_printmodeline] Modeline 103:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[   12.796302] [drm:drm_mode_debug_printmodeline] Modeline 62:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   12.796306] [drm:drm_mode_debug_printmodeline] Modeline 104:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[   12.796309] [drm:drm_mode_debug_printmodeline] Modeline 95:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[   12.796312] [drm:drm_mode_debug_printmodeline] Modeline 98:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[   12.796316] [drm:drm_mode_debug_printmodeline] Modeline 99:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   12.796320] [drm:drm_mode_debug_printmodeline] Modeline 114:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[   12.796325] [drm:drm_mode_debug_printmodeline] Modeline 71:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[   12.796330] [drm:drm_mode_debug_printmodeline] Modeline 79:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   12.796335] [drm:drm_mode_debug_printmodeline] Modeline 68:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[   12.796339] [drm:drm_mode_debug_printmodeline] Modeline 70:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[   12.796343] [drm:drm_mode_debug_printmodeline] Modeline 67:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[   12.796347] [drm:drm_mode_debug_printmodeline] Modeline 66:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[   12.796350] [drm:drm_mode_debug_printmodeline] Modeline 69:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   12.796354] [drm:drm_mode_debug_printmodeline] Modeline 105:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[   12.796357] [drm:drm_mode_debug_printmodeline] Modeline 97:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[   12.796360] [drm:drm_mode_debug_printmodeline] Modeline 80:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[   12.796363] [drm:drm_mode_debug_printmodeline] Modeline 81:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[   12.796366] [drm:drm_mode_debug_printmodeline] Modeline 82:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[   12.796370] [drm:drm_mode_debug_printmodeline] Modeline 83:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[   12.796375] [drm:drm_mode_debug_printmodeline] Modeline 84:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[   12.796379] [drm:drm_mode_debug_printmodeline] Modeline 85:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[   12.796383] [drm:drm_mode_debug_printmodeline] Modeline 72:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[   12.796387] [drm:drm_mode_debug_printmodeline] Modeline 73:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[   12.796392] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[   12.796396] [drm:drm_mode_debug_printmodeline] Modeline 110:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[   12.796399] [drm:drm_mode_debug_printmodeline] Modeline 90:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[   12.796403] [drm:drm_mode_debug_printmodeline] Modeline 74:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[   12.796406] [drm:drm_mode_debug_printmodeline] Modeline 75:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[   12.796408] [drm:drm_mode_debug_printmodeline] Modeline 76:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[   12.796412] [drm:drm_mode_debug_printmodeline] Modeline 106:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[   12.796417] [drm:drm_mode_debug_printmodeline] Modeline 77:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[   12.796422] [drm:drm_mode_debug_printmodeline] Modeline 78:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[   12.796427] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1]
>[   12.796489] [drm:intel_hdmi_detect [i915]] [CONNECTOR:54:HDMI-A-1]
>[   12.798267] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   12.798291] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   12.800333] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[   12.800346] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>[   12.802325] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   12.802344] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[   12.804324] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[   12.804328] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   12.804332] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:54:HDMI-A-1] disconnected
>[   12.804335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2]
>[   12.804354] [drm:intel_hdmi_detect [i915]] [CONNECTOR:57:HDMI-A-2]
>[   12.806333] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   12.806351] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   12.808332] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[   12.808339] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpc
>[   12.810336] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   12.810354] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[   12.812484] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[   12.812488] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>[   12.812491] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:57:HDMI-A-2] disconnected
>[   12.812547] [drm:drm_setup_crtcs] connector 48 enabled? yes
>[   12.812549] [drm:drm_setup_crtcs] connector 54 enabled? no
>[   12.812551] [drm:drm_setup_crtcs] connector 57 enabled? no
>[   12.812570] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[   12.812576] [drm:drm_setup_crtcs] looking for cmdline mode on connector 48
>[   12.812578] [drm:drm_setup_crtcs] looking for preferred mode on connector 48 0
>[   12.812580] [drm:drm_setup_crtcs] found mode 3840x2160
>[   12.812581] [drm:drm_setup_crtcs] picking CRTCs for 3840x2160 config
>[   12.812591] [drm:drm_setup_crtcs] desired mode 3840x2160 set on crtc 32 (0,0)
>[  137.858898] [drm:drm_mode_addfb2] [FB:88]
>[  137.970628] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  137.970652] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  142.982130] [drm:drm_mode_addfb2] [FB:86]
>[  143.065139] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  143.065169] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  143.065318] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  143.065345] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  143.065373] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 262790KHz
>[  143.065400] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  143.065419] [drm:intel_dp_compute_config [i915]] DP link bw required 788370 available 1080000
>[  143.065439] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  143.065463] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  143.065486] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  143.065515] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6123450, gmch_n: 8388608, link_m: 510287, link_n: 524288, tu: 64
>[  143.065532] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  143.065553] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  143.065558] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262790 3840 3888 3920 4000 2160 2165 2170 2191 0x40 0x5
>[  143.065579] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  143.065583] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 30 262790 3840 3888 3920 4000 2160 2165 2170 2191 0x40 0x5
>[  143.065603] [drm:intel_dump_pipe_config [i915]] crtc timings: 262790 3840 3888 3920 4000 2160 2165 2170 2191, type: 0x40 flags: 0x5
>[  143.065621] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 262790
>[  143.065637] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  143.065657] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  143.065677] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  143.065702] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x1, cfgcr1: 0x0, cfgcr2: 0x0
>[  143.065720] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  143.065770] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  143.065786] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  143.065806] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  143.065827] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  143.065858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  143.065885] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  143.065908] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  143.066933] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  143.067021] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  143.067304] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  143.082221] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  143.082247] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  143.082281] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  143.082325] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  143.082354] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  143.082379] [drm:intel_set_cdclk [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  143.082786] [drm:intel_update_cdclk [i915]] Current CD clock rate: 337500 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  143.082807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  143.082824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  143.082841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  143.082857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  143.082873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  143.082889] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  143.082907] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  143.082923] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  143.082939] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  143.082958] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  143.082974] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  143.085097] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  143.085114] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  143.088078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  143.088096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  143.088112] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  143.088129] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  143.090612] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  143.090631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  143.093452] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  143.095561] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 4
>[  143.096444] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  143.096471] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  143.096487] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  143.096513] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  143.096576] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  143.096592] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  143.130089] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  143.130123] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  143.130163] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  148.130821] [drm:drm_mode_addfb2] [FB:88]
>[  148.208453] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  148.208485] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  148.208623] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  148.208643] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  148.208663] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 209800KHz
>[  148.208685] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  148.208701] [drm:intel_dp_compute_config [i915]] DP link bw required 629400 available 648000
>[  148.208718] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  148.208735] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  148.208751] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  148.208767] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 8147823, gmch_n: 8388608, link_m: 339492, link_n: 262144, tu: 64
>[  148.208782] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  148.208796] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  148.208800] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[  148.208814] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  148.208817] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 24 209800 3840 3888 3920 4000 2160 2163 2168 2185 0x40 0x5
>[  148.208832] [drm:intel_dump_pipe_config [i915]] crtc timings: 209800 3840 3888 3920 4000 2160 2163 2168 2185, type: 0x40 flags: 0x5
>[  148.208856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 3840x2160, pixel rate 209800
>[  148.208869] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  148.208883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  148.208896] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  148.208912] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  148.208926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  148.208941] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  148.208954] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  148.208967] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  148.208981] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  148.208998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  148.209055] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  148.209071] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  148.210126] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  148.210155] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  148.210211] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  148.233862] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  148.233879] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  148.233901] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  148.233921] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  148.233939] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  148.233961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  148.233978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  148.233994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  148.234010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  148.234025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  148.234041] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  148.234058] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  148.234074] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  148.234089] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  148.234108] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  148.234123] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  148.236248] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  148.236264] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  148.239227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  148.239245] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  148.239261] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  148.239279] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  148.241827] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  148.241846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  148.244879] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  148.246401] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  148.248468] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  148.248571] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  148.248644] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  148.248732] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  148.248879] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  148.248952] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  148.290520] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  148.290637] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  148.290775] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  153.291408] [drm:drm_mode_addfb2] [FB:86]
>[  153.352588] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  153.352619] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  153.352719] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  153.352738] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  153.352759] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 241500KHz
>[  153.352780] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  153.352796] [drm:intel_dp_compute_config [i915]] DP link bw required 724500 available 1080000
>[  153.352813] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  153.352829] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  153.352846] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  153.352861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5627357, gmch_n: 8388608, link_m: 468946, link_n: 524288, tu: 64
>[  153.352876] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  153.352890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  153.352893] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  153.352908] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  153.352920] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x9
>[  153.352935] [drm:intel_dump_pipe_config [i915]] crtc timings: 241500 2560 2608 2640 2720 1440 1443 1448 1481, type: 0x40 flags: 0x9
>[  153.352949] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2560x1440, pixel rate 241500
>[  153.352963] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  153.352976] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  153.352989] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  153.353006] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  153.353020] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  153.353034] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[  153.353048] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[  153.353061] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  153.353074] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  153.353092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  153.353148] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  153.353164] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  153.353776] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  153.353806] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  153.353848] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  153.373264] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  153.373282] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  153.373305] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  153.373326] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  153.373345] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  153.373369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  153.373386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  153.373402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  153.373418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  153.373433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  153.373448] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  153.373465] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  153.373481] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  153.373497] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  153.373515] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  153.373530] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  153.375677] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  153.375696] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  153.378687] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  153.378706] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  153.378722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  153.378739] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  153.381157] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  153.381176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  153.383990] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  153.386131] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 4
>[  153.386998] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  153.387025] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  153.387041] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  153.387064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  153.387106] [drm:intel_fbc_enable [i915]] reserved 29491200 bytes of contiguous stolen space for FBC, threshold: 1
>[  153.387122] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  153.404012] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  153.404130] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  153.404355] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  158.405050] [drm:drm_mode_addfb2] [FB:88]
>[  158.458508] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  158.458531] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  158.458613] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  158.458631] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  158.458651] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  158.458670] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  158.458686] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  158.458703] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  158.458720] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  158.458736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  158.458751] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  158.458766] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  158.458780] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  158.458783] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  158.458797] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  158.458800] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  158.458814] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  158.458852] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  158.458867] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  158.458881] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  158.458894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  158.458911] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  158.458925] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  158.458940] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 2560x1440 format = XR24 little-endian (0x34325258)
>[  158.458953] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+2560+1440 dst 0x0+2560+1440
>[  158.458967] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  158.458981] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  158.458998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  158.459019] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  158.459034] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  158.459524] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  158.459545] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  158.459586] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  158.477074] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  158.477091] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  158.477114] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  158.477135] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  158.477153] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  158.477176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  158.477237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  158.477261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  158.477284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  158.477306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  158.477332] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  158.477363] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  158.477389] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  158.477416] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  158.477447] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  158.477471] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  158.479596] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  158.479611] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  158.482565] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  158.482582] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  158.482599] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  158.482616] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  158.485115] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  158.485133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  158.487924] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  158.490024] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  158.490888] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  158.490914] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  158.490931] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  158.490953] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  158.490999] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  158.491021] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  158.507719] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  158.507747] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  158.507783] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  163.508383] [drm:drm_mode_addfb2] [FB:86]
>[  163.561974] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  163.561995] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  163.562086] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  163.562105] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  163.562125] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148352KHz
>[  163.562143] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  163.562159] [drm:intel_dp_compute_config [i915]] DP link bw required 445056 available 648000
>[  163.562177] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  163.562213] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  163.562232] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  163.562254] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5761420, gmch_n: 8388608, link_m: 240059, link_n: 262144, tu: 64
>[  163.562275] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  163.562295] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  163.562310] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  163.562329] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  163.562333] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  163.562352] [drm:intel_dump_pipe_config [i915]] crtc timings: 148352 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  163.562370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148352
>[  163.562392] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  163.562413] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  163.562433] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  163.562454] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  163.562470] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  163.562492] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  163.562512] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  163.562532] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  163.562549] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  163.562575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  163.562602] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  163.562624] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  163.563045] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  163.563072] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  163.563118] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  163.575769] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  163.575786] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  163.575809] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  163.575831] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  163.575850] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  163.575874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  163.575891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  163.575907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  163.575923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  163.575938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  163.575954] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  163.575971] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  163.575987] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  163.576003] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  163.576021] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  163.576036] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  163.577243] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  163.577259] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  163.580214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  163.580231] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  163.580248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  163.580265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  163.582749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  163.582768] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  163.585547] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  163.587268] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  163.588130] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  163.588157] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  163.588174] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  163.588226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  163.588281] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  163.588301] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  163.605062] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  163.605095] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  163.605132] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  168.605577] [drm:drm_mode_addfb2] [FB:88]
>[  168.659218] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  168.659235] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  168.659319] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  168.659343] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  168.659368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz
>[  168.659391] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  168.659409] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  168.659427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  168.659444] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  168.659459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  168.659475] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  168.659489] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  168.659503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  168.659506] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  168.659521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  168.659523] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  168.659538] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  168.659552] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  168.659566] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  168.659579] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  168.659593] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  168.659609] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  168.659623] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  168.659638] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  168.659652] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  168.659666] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  168.659679] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  168.659697] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  168.659718] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  168.659734] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  168.660136] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  168.660157] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  168.660190] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  168.677162] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  168.677179] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  168.677245] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  168.677275] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  168.677302] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  168.677325] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  168.677352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  168.677373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  168.677393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  168.677414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  168.677432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  168.677451] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  168.677472] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  168.677490] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  168.677508] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  168.677529] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  168.677545] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  168.679658] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  168.679672] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  168.682621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  168.682638] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  168.682654] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  168.682672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  168.685110] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  168.685128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  168.687888] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  168.689265] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  168.690054] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  168.690079] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  168.690095] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  168.690116] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  168.690154] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  168.690171] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  168.706994] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  168.707024] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  168.707059] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  173.707519] [drm:drm_mode_addfb2] [FB:86]
>[  173.757166] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  173.757205] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  173.757297] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  173.757322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  173.757346] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74176KHz
>[  173.757366] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  173.757389] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  173.757414] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  173.757438] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  173.757456] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  173.757488] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  173.757510] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  173.757529] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  173.757533] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  173.757554] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  173.757558] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[  173.757579] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2008 2052 2200 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  173.757600] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  173.757617] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  173.757637] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  173.757657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  173.757681] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  173.757698] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  173.757715] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  173.757735] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  173.757755] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  173.757775] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  173.757796] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  173.757822] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  173.757845] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  173.758213] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  173.758241] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  173.758287] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  173.775400] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  173.775417] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  173.775439] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  173.775460] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  173.775478] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  173.775500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  173.775517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  173.775533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  173.775549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  173.775564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  173.775580] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  173.775597] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  173.775612] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  173.775628] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  173.775646] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  173.775661] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  173.777778] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  173.777794] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  173.780695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  173.780714] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  173.780730] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  173.780747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  173.783129] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  173.783146] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  173.785881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  173.787972] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  173.788764] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  173.788789] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  173.788805] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  173.788827] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  173.788871] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  173.788893] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  173.805662] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  173.805691] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  173.805724] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  178.806178] [drm:drm_mode_addfb2] [FB:88]
>[  178.856018] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  178.856040] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  178.856112] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  178.856136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  178.856160] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  178.856181] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  178.856217] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  178.856237] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  178.856261] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  178.856283] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  178.856307] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  178.856328] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  178.856347] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  178.856352] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  178.856369] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  178.856373] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  178.856394] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2448 2492 2640 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  178.856415] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  178.856437] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  178.856455] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  178.856476] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  178.856500] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  178.856520] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  178.856538] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  178.856554] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  178.856574] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  178.856594] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  178.856627] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  178.856653] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  178.856676] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  178.857031] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  178.857060] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  178.857103] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  178.861690] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  178.861707] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  178.861728] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  178.861748] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  178.861767] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  178.861788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  178.861805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  178.861821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  178.861837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  178.861852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  178.861868] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  178.861885] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  178.861901] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  178.861916] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  178.861934] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  178.861949] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  178.863278] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  178.863294] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  178.866245] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  178.866263] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  178.866279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  178.866296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  178.868761] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  178.868779] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  178.871543] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  178.873637] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  178.874444] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  178.874468] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  178.874484] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  178.874506] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  178.874540] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  178.874556] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  178.894606] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  178.894633] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  178.894666] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  178.894682] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  183.895187] [drm:drm_mode_addfb2] [FB:86]
>[  183.948856] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  183.948882] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  183.948974] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  183.948992] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  183.949015] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz
>[  183.949056] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  183.949072] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  183.949089] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  183.949106] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  183.949122] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  183.949138] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  183.949153] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  183.949176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  183.949179] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  183.949209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  183.949212] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[  183.949227] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2448 2492 2640 1080 1084 1094 1125, type: 0x40 flags: 0x15
>[  183.949241] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  183.949257] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  183.949273] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  183.949287] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  183.949305] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  183.949320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  183.949335] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  183.949350] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  183.949365] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  183.949381] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  183.949400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  183.949421] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  183.949440] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  183.949834] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  183.949856] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  183.949888] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  183.955684] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  183.955702] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  183.955723] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  183.955743] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  183.955761] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  183.955777] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  183.955798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  183.955814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  183.955830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  183.955845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  183.955860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  183.955875] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  183.955892] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  183.955908] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  183.955923] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  183.955941] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  183.955956] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  183.957215] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  183.957229] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  183.960174] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  183.960198] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  183.960234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  183.960259] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  183.962718] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  183.962736] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  183.965494] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  183.967598] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  183.968408] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  183.968432] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  183.968449] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  183.968470] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  183.968503] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  183.968519] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  183.988573] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  183.988601] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  183.988634] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  188.989085] [drm:drm_mode_addfb2] [FB:88]
>[  189.039180] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  189.039215] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  189.039286] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  189.039304] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  189.039323] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz
>[  189.039342] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  189.039357] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  189.039374] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  189.039391] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  189.039407] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  189.039423] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  189.039438] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  189.039452] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  189.039455] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  189.039478] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  189.039481] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  189.039495] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  189.039509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74250
>[  189.039523] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  189.039537] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  189.039550] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  189.039572] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  189.039585] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  189.039600] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  189.039614] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  189.039628] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  189.039641] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  189.039659] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  189.039678] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  189.039694] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  189.040003] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  189.040023] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  189.040055] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  189.050805] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  189.050821] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  189.050842] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  189.050862] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  189.050881] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  189.050902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  189.050918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  189.050934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  189.050950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  189.050965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  189.050981] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  189.050998] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  189.051014] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  189.051030] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  189.051049] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  189.051065] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  189.053178] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  189.053206] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  189.056189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  189.056218] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  189.056234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  189.056251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  189.058736] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  189.058755] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  189.061548] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  189.063681] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  189.064488] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  189.064512] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  189.064529] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  189.064550] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  189.064584] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  189.064601] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  189.106334] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  189.106366] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  189.106406] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  189.106425] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  194.106932] [drm:drm_mode_addfb2] [FB:86]
>[  194.158772] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  194.158801] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  194.158891] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  194.158910] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  194.158930] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74176KHz
>[  194.158949] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  194.158965] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  194.158983] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  194.159000] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  194.159016] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  194.159031] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  194.159046] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  194.159060] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  194.159063] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  194.159077] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  194.159079] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[  194.159094] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1920 2558 2602 2750 1080 1084 1089 1125, type: 0x40 flags: 0x5
>[  194.159117] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 74176
>[  194.159131] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  194.159144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  194.159158] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  194.159174] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  194.159188] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  194.159218] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  194.159232] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  194.159246] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  194.159261] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  194.159283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  194.159307] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  194.159324] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  194.159755] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  194.159776] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  194.159808] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  194.190549] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  194.190567] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  194.190590] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  194.190612] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  194.190631] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  194.190654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  194.190671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  194.190687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  194.190703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  194.190718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  194.190734] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  194.190751] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  194.190767] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  194.190783] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  194.190802] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  194.190817] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  194.193049] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  194.193067] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  194.196059] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  194.196077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  194.196094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  194.196111] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  194.198587] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  194.198606] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  194.201380] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  194.203455] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  194.204334] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  194.204360] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  194.204377] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  194.204399] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  194.204440] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  194.204457] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  194.246242] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  194.246276] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  194.246318] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  199.246672] [drm:drm_mode_addfb2] [FB:88]
>[  199.296845] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  199.296873] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  199.296959] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  199.296977] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  199.296998] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 146250KHz
>[  199.297018] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  199.297034] [drm:intel_dp_compute_config [i915]] DP link bw required 438750 available 648000
>[  199.297051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  199.297068] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  199.297084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  199.297099] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5679786, gmch_n: 8388608, link_m: 236657, link_n: 262144, tu: 64
>[  199.297114] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  199.297128] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  199.297131] [drm:drm_mode_debug_printmodeline] Modeline 0:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  199.297145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  199.297158] [drm:drm_mode_debug_printmodeline] Modeline 0:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[  199.297173] [drm:intel_dump_pipe_config [i915]] crtc timings: 146250 1680 1784 1960 2240 1050 1053 1059 1089, type: 0x40 flags: 0x6
>[  199.297187] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1680x1050, pixel rate 146250
>[  199.297217] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  199.297231] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  199.297244] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  199.297262] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  199.297279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  199.297294] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[  199.297309] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[  199.297323] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  199.297338] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  199.297358] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  199.297380] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  199.297396] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  199.297786] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  199.297807] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  199.297840] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  199.336342] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  199.336362] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  199.336389] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  199.336414] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  199.336437] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  199.336464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  199.336485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  199.336504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  199.336522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  199.336541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  199.336560] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  199.336580] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  199.336599] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  199.336618] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  199.336640] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  199.336659] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  199.338806] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  199.338830] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  199.341844] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  199.341870] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  199.341892] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  199.341914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  199.344437] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  199.344465] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  199.347303] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  199.349400] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  199.350426] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  199.350464] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  199.350490] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  199.350522] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  199.350579] [drm:intel_fbc_enable [i915]] reserved 14112000 bytes of contiguous stolen space for FBC, threshold: 1
>[  199.350604] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  199.367295] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  199.367349] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  199.367416] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  204.367933] [drm:drm_mode_addfb2] [FB:86]
>[  204.417763] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  204.417791] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  204.417871] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  204.417889] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  204.417911] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 135000KHz
>[  204.417932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  204.417948] [drm:intel_dp_compute_config [i915]] DP link bw required 405000 available 648000
>[  204.417965] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  204.417981] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  204.417997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  204.418012] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5242880, gmch_n: 8388608, link_m: 218453, link_n: 262144, tu: 64
>[  204.418027] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  204.418041] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  204.418044] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  204.418058] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  204.418069] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  204.418084] [drm:intel_dump_pipe_config [i915]] crtc timings: 135000 1280 1296 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  204.418098] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 135000
>[  204.418111] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  204.418125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  204.418138] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  204.418154] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  204.418168] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  204.418182] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1680x1050 format = XR24 little-endian (0x34325258)
>[  204.418212] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1680+1050 dst 0x0+1680+1050
>[  204.418226] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  204.418239] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  204.418259] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  204.418284] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  204.418301] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  204.418568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  204.418590] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  204.418650] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  204.423249] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  204.423265] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  204.423287] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  204.423307] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  204.423326] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  204.423346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  204.423363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  204.423379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  204.423395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  204.423411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  204.423427] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  204.423444] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  204.423460] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  204.423475] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  204.423493] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  204.423509] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  204.425623] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  204.425639] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  204.428591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  204.428609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  204.428625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  204.428643] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  204.431119] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  204.431137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  204.433904] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  204.435283] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  204.436148] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  204.436173] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  204.436189] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  204.436233] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  204.436275] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1
>[  204.436298] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  204.449631] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  204.449656] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  204.449690] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  209.450046] [drm:drm_mode_addfb2] [FB:88]
>[  209.499554] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  209.499582] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  209.499662] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  209.499681] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  209.499701] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 108000KHz
>[  209.499722] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  209.499738] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000
>[  209.499755] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  209.499772] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  209.499788] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  209.499803] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  209.499818] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  209.499832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  209.499835] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  209.499849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  209.499861] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  209.499875] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1280 1328 1440 1688 1024 1025 1028 1066, type: 0x40 flags: 0x5
>[  209.499889] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x1024, pixel rate 108000
>[  209.499903] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  209.499916] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  209.499930] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  209.499946] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  209.499959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  209.499974] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1280x1024 format = XR24 little-endian (0x34325258)
>[  209.499987] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1280+1024 dst 0x0+1280+1024
>[  209.500001] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  209.500014] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  209.500032] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  209.500051] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  209.500067] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  209.500427] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  209.500448] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  209.500487] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  209.502998] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  209.503013] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  209.503033] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  209.503053] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  209.503071] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  209.503091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  209.503107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  209.503123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  209.503138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  209.503152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  209.503168] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  209.503186] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  209.503219] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  209.503237] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  209.503257] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  209.503274] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  209.505315] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  209.505329] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  209.508260] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  209.508278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  209.508294] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  209.508311] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  209.510768] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  209.510786] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  209.513545] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  209.515646] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  209.516518] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  209.516543] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  209.516560] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  209.516581] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  209.516615] [drm:intel_fbc_enable [i915]] reserved 10485760 bytes of contiguous stolen space for FBC, threshold: 1
>[  209.516632] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  209.533363] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  209.533391] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  209.533426] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  214.533939] [drm:drm_mode_addfb2] [FB:86]
>[  214.583989] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  214.584013] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  214.584099] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  214.584122] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  214.584147] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 106500KHz
>[  214.584170] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  214.584186] [drm:intel_dp_compute_config [i915]] DP link bw required 319500 available 324000
>[  214.584223] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  214.584244] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  214.584266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  214.584288] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4136049, gmch_n: 4194304, link_m: 172335, link_n: 262144, tu: 64
>[  214.584309] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  214.584330] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  214.584336] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  214.584354] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  214.584358] [drm:drm_mode_debug_printmodeline] Modeline 0:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[  214.584376] [drm:intel_dump_pipe_config [i915]] crtc timings: 106500 1440 1520 1672 1904 900 903 909 934, type: 0x40 flags: 0x6
>[  214.584393] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1440x900, pixel rate 106500
>[  214.584415] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  214.584436] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  214.584456] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  214.584476] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  214.584493] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  214.584514] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1280x1024 format = XR24 little-endian (0x34325258)
>[  214.584535] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1280+1024 dst 0x0+1280+1024
>[  214.584555] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  214.584571] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  214.584597] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  214.584625] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  214.584646] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  214.584928] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  214.584999] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  214.585039] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  214.600242] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  214.600259] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  214.600282] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  214.600303] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  214.600322] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  214.600345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  214.600363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  214.600379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  214.600394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  214.600410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  214.600426] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  214.600443] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  214.600459] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  214.600474] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  214.600493] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  214.600508] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  214.602617] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  214.602631] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  214.605573] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  214.605590] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  214.605606] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  214.605623] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  214.608075] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  214.608093] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  214.610844] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  214.612940] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  214.613801] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  214.613827] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  214.613843] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  214.613865] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  214.613910] [drm:intel_fbc_enable [i915]] reserved 10368000 bytes of contiguous stolen space for FBC, threshold: 1
>[  214.613932] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  214.630810] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  214.630841] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  214.630879] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  219.631308] [drm:drm_mode_addfb2] [FB:88]
>[  219.680199] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  219.680225] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  219.680307] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  219.680325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  219.680345] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 108000KHz
>[  219.680365] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  219.680381] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000
>[  219.680398] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  219.680415] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  219.680431] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  219.680447] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  219.680462] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  219.680476] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  219.680479] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  219.680498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  219.680514] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[  219.680530] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1280 1376 1488 1800 960 961 964 1000, type: 0x40 flags: 0x5
>[  219.680545] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x960, pixel rate 108000
>[  219.680559] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  219.680572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  219.680586] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  219.680602] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  219.680616] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  219.680630] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1440x900 format = XR24 little-endian (0x34325258)
>[  219.680643] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1440+900 dst 0x0+1440+900
>[  219.680657] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  219.680670] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  219.680688] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  219.680707] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  219.680722] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  219.680982] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  219.681003] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  219.681041] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  219.691719] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  219.691736] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  219.691760] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  219.691782] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  219.691800] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  219.691824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  219.691841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  219.691857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  219.691873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  219.691889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  219.691905] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  219.691922] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  219.691938] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  219.691953] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  219.691972] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  219.691987] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  219.693293] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  219.693312] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  219.696296] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  219.696314] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  219.696331] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  219.696348] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  219.698817] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  219.698836] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  219.701606] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  219.703287] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  219.704152] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  219.704178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  219.704198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  219.704258] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  219.704345] [drm:intel_fbc_enable [i915]] reserved 9830400 bytes of contiguous stolen space for FBC, threshold: 1
>[  219.704368] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  219.721192] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  219.721371] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  219.721508] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  224.722104] [drm:drm_mode_addfb2] [FB:86]
>[  224.769826] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  224.769855] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  224.769936] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  224.769955] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  224.769974] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 108000KHz
>[  224.769995] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  224.770011] [drm:intel_dp_compute_config [i915]] DP link bw required 324000 available 324000
>[  224.770029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  224.770046] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  224.770062] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  224.770078] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 4194304, gmch_n: 4194304, link_m: 174762, link_n: 262144, tu: 64
>[  224.770092] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  224.770107] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  224.770110] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  224.770124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  224.770127] [drm:drm_mode_debug_printmodeline] Modeline 0:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[  224.770141] [drm:intel_dump_pipe_config [i915]] crtc timings: 108000 1152 1216 1344 1600 864 865 868 900, type: 0x40 flags: 0x5
>[  224.770164] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1152x864, pixel rate 108000
>[  224.770177] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  224.770191] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  224.770219] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  224.770236] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  224.770250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  224.770266] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1280x960 format = XR24 little-endian (0x34325258)
>[  224.770282] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1280+960 dst 0x0+1280+960
>[  224.770297] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  224.770311] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  224.770331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  224.770351] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  224.770367] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  224.770604] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  224.770625] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  224.770659] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  224.773180] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  224.773209] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  224.773231] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  224.773251] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  224.773269] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  224.773290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  224.773306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  224.773322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  224.773338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  224.773354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  224.773370] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  224.773387] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  224.773403] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  224.773419] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  224.773437] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  224.773453] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  224.775571] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  224.775587] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  224.778567] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  224.778585] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  224.778601] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  224.778618] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  224.781108] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  224.781127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  224.783902] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  224.786047] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  224.786913] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  224.786938] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  224.786955] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  224.786977] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  224.787010] [drm:intel_fbc_enable [i915]] reserved 7962624 bytes of contiguous stolen space for FBC, threshold: 1
>[  224.787027] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  224.800570] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  224.800684] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  224.800818] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  229.801444] [drm:drm_mode_addfb2] [FB:88]
>[  229.850009] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  229.850038] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  229.850116] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  229.850136] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  229.850155] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz
>[  229.850173] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  229.850189] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  229.850221] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  229.850238] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  229.850254] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  229.850271] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  229.850289] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  229.850313] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  229.850317] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  229.850337] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  229.850341] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  229.850362] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  229.850383] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250
>[  229.850404] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  229.850424] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  229.850445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  229.850468] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  229.850483] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  229.850498] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1152x864 format = XR24 little-endian (0x34325258)
>[  229.850512] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1152+864 dst 0x0+1152+864
>[  229.850526] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  229.850539] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  229.850557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  229.850577] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  229.850593] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  229.850798] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  229.850819] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  229.850852] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  229.855468] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  229.855485] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  229.855514] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  229.855535] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  229.855554] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  229.855574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  229.855591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  229.855607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  229.855622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  229.855637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  229.855653] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  229.855670] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  229.855686] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  229.855702] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  229.855720] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  229.855735] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  229.857220] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  229.857236] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  229.860198] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  229.860225] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  229.860242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  229.860258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  229.862649] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  229.862667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  229.865413] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  229.867292] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  229.868155] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  229.868180] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  229.868440] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  229.868473] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  229.868518] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  229.868537] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  229.884998] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  229.885025] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  229.885061] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  234.885568] [drm:drm_mode_addfb2] [FB:86]
>[  234.933518] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  234.933547] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  234.933628] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  234.933647] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  234.933667] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74176KHz
>[  234.933686] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  234.933702] [drm:intel_dp_compute_config [i915]] DP link bw required 222528 available 324000
>[  234.933720] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  234.933737] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  234.933753] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  234.933769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2880710, gmch_n: 4194304, link_m: 120029, link_n: 262144, tu: 64
>[  234.933783] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  234.933798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  234.933801] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  234.933815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  234.933827] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  234.933842] [drm:intel_dump_pipe_config [i915]] crtc timings: 74176 1280 1390 1430 1650 720 725 730 750, type: 0x40 flags: 0x5
>[  234.933856] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74176
>[  234.933870] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  234.933884] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  234.933897] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  234.933914] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  234.933928] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  234.933942] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  234.933956] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1280+720 dst 0x0+1280+720
>[  234.933970] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  234.933984] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  234.934002] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  234.934022] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  234.934038] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  234.934276] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  234.934297] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  234.934338] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  234.936786] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  234.936801] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  234.936821] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  234.936840] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  234.936858] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  234.936878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  234.936894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  234.936909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  234.936925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  234.936939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  234.936955] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  234.936972] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  234.936988] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  234.937003] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  234.937021] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  234.937036] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  234.939140] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  234.939154] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  234.942134] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  234.942152] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  234.942168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  234.942184] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  234.944661] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  234.944680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  234.947491] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  234.949299] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  234.950162] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  234.950187] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  234.950221] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  234.950252] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  234.950299] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  234.950319] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  234.967382] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  234.967502] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  234.967640] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  239.968320] [drm:drm_mode_addfb2] [FB:88]
>[  240.015469] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  240.015489] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  240.015561] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  240.015580] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  240.015599] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 74250KHz
>[  240.015621] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  240.015638] [drm:intel_dp_compute_config [i915]] DP link bw required 222750 available 324000
>[  240.015662] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  240.015679] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  240.015695] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  240.015711] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2883584, gmch_n: 4194304, link_m: 120149, link_n: 262144, tu: 64
>[  240.015727] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  240.015741] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  240.015744] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  240.015758] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  240.015761] [drm:drm_mode_debug_printmodeline] Modeline 0:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  240.015775] [drm:intel_dump_pipe_config [i915]] crtc timings: 74250 1280 1720 1760 1980 720 725 730 750, type: 0x40 flags: 0x5
>[  240.015795] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1280x720, pixel rate 74250
>[  240.015809] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  240.015823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  240.015837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  240.015853] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  240.015867] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  240.015882] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  240.015896] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1280+720 dst 0x0+1280+720
>[  240.015909] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  240.015923] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  240.015941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  240.015961] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  240.015976] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  240.016192] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  240.016226] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  240.016267] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  240.022744] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  240.022760] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  240.022781] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  240.022801] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  240.022819] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  240.022840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  240.022856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  240.022872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  240.022888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  240.022903] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  240.022919] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  240.022936] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  240.022952] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  240.022967] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  240.022985] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  240.023000] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  240.025113] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  240.025129] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  240.028122] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  240.028140] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  240.028157] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  240.028174] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  240.030694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  240.030713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  240.033517] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  240.035589] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  240.036467] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  240.036492] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  240.036508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  240.036531] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  240.036573] [drm:intel_fbc_enable [i915]] reserved 7372800 bytes of contiguous stolen space for FBC, threshold: 1
>[  240.036596] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  240.056644] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  240.056672] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  240.056707] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  245.057175] [drm:drm_mode_addfb2] [FB:86]
>[  245.103717] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  245.103736] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  245.103812] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  245.103831] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  245.103851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 78750KHz
>[  245.103872] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  245.103888] [drm:intel_dp_compute_config [i915]] DP link bw required 236250 available 324000
>[  245.103905] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  245.103922] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  245.103938] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  245.103953] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 3058346, gmch_n: 4194304, link_m: 127431, link_n: 262144, tu: 64
>[  245.103968] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  245.103983] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  245.103986] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  245.104000] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  245.104002] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[  245.104017] [drm:intel_dump_pipe_config [i915]] crtc timings: 78750 1024 1040 1136 1312 768 769 772 800, type: 0x40 flags: 0x5
>[  245.104040] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 78750
>[  245.104055] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  245.104068] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  245.104082] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  245.104098] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  245.104112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  245.104126] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1280x720 format = XR24 little-endian (0x34325258)
>[  245.104140] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1280+720 dst 0x0+1280+720
>[  245.104154] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  245.104167] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  245.104184] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  245.104218] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  245.104233] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  245.104494] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  245.104523] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  245.104563] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  245.117644] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  245.117661] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  245.117684] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  245.117706] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  245.117725] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  245.117748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  245.117765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  245.117781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  245.117797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  245.117812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  245.117828] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  245.117845] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  245.117861] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  245.117877] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  245.117895] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  245.117910] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  245.120143] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  245.120161] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  245.123193] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  245.123224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  245.123241] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  245.123258] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  245.125758] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  245.125777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  245.128586] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  245.130728] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  245.131606] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  245.131633] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  245.131650] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  245.131672] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  245.131715] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  245.131732] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  245.145265] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  245.145443] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  245.145576] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  250.146313] [drm:drm_mode_addfb2] [FB:88]
>[  250.194574] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  250.194591] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  250.194663] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  250.194687] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  250.194712] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 75000KHz
>[  250.194738] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  250.194754] [drm:intel_dp_compute_config [i915]] DP link bw required 225000 available 324000
>[  250.194772] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  250.194789] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  250.194804] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  250.194820] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2912711, gmch_n: 4194304, link_m: 121362, link_n: 262144, tu: 64
>[  250.194834] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  250.194849] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  250.194852] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  250.194866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  250.194869] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[  250.194886] [drm:intel_dump_pipe_config [i915]] crtc timings: 75000 1024 1048 1184 1328 768 771 777 806, type: 0x40 flags: 0xa
>[  250.194900] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 75000
>[  250.194914] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  250.194928] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  250.194942] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  250.194958] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  250.194972] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  250.194987] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1024x768 format = XR24 little-endian (0x34325258)
>[  250.195001] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1024+768 dst 0x0+1024+768
>[  250.195015] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  250.195029] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  250.195047] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  250.195067] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  250.195082] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  250.195321] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  250.195347] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  250.195391] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  250.197844] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  250.197860] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  250.197882] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  250.197902] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  250.197921] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  250.197942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  250.197958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  250.197974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  250.197990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  250.198005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  250.198021] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  250.198038] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  250.198054] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  250.198070] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  250.198088] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  250.198103] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  250.200246] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  250.200261] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  250.203201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  250.203226] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  250.203243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  250.203260] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  250.205714] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  250.205734] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  250.208499] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  250.210285] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  250.211148] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  250.211172] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  250.211191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  250.211488] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  250.211535] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  250.211558] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  250.225736] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  250.225767] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  250.225805] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  255.226177] [drm:drm_mode_addfb2] [FB:86]
>[  255.272927] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  255.272949] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  255.273022] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  255.273041] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  255.273060] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 65000KHz
>[  255.273081] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  255.273096] [drm:intel_dp_compute_config [i915]] DP link bw required 195000 available 324000
>[  255.273114] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  255.273130] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  255.273146] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  255.273162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2524349, gmch_n: 4194304, link_m: 105181, link_n: 262144, tu: 64
>[  255.273177] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  255.273191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  255.273210] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  255.273228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  255.273241] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  255.273262] [drm:intel_dump_pipe_config [i915]] crtc timings: 65000 1024 1048 1184 1344 768 771 777 806, type: 0x40 flags: 0xa
>[  255.273285] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1024x768, pixel rate 65000
>[  255.273306] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  255.273325] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  255.273342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  255.273366] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  255.273387] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  255.273410] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 1024x768 format = XR24 little-endian (0x34325258)
>[  255.273426] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1024+768 dst 0x0+1024+768
>[  255.273443] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  255.273466] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  255.273492] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  255.273518] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  255.273536] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  255.273790] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  255.273819] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  255.273863] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  255.278477] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  255.278494] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  255.278516] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  255.278536] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  255.278555] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  255.278576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  255.278593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  255.278609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  255.278624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  255.278639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  255.278655] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  255.278672] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  255.278688] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  255.278703] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  255.278721] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  255.278737] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  255.280228] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  255.280243] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  255.283207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  255.283244] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  255.283268] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  255.283291] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  255.285763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  255.285782] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  255.288553] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  255.290286] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  255.291149] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  255.291174] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  255.291194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  255.291454] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  255.291500] [drm:intel_fbc_enable [i915]] reserved 6291456 bytes of contiguous stolen space for FBC, threshold: 1
>[  255.291524] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  255.308135] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  255.308166] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  255.308252] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  260.308780] [drm:drm_mode_addfb2] [FB:88]
>[  260.352268] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  260.352294] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  260.352364] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  260.352383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  260.352402] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 57284KHz
>[  260.352422] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 2 clock 162000 bpp 24
>[  260.352438] [drm:intel_dp_compute_config [i915]] DP link bw required 171852 available 324000
>[  260.352455] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  260.352472] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  260.352488] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  260.352503] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 2224689, gmch_n: 4194304, link_m: 92695, link_n: 262144, tu: 64
>[  260.352518] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  260.352532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  260.352535] [drm:drm_mode_debug_printmodeline] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  260.352549] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  260.352552] [drm:drm_mode_debug_printmodeline] Modeline 0:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[  260.352575] [drm:intel_dump_pipe_config [i915]] crtc timings: 57284 832 864 928 1152 624 625 628 667, type: 0x40 flags: 0xa
>[  260.352589] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 832x624, pixel rate 57284
>[  260.352603] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  260.352617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  260.352630] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  260.352646] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  260.352660] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  260.352675] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 1024x768 format = XR24 little-endian (0x34325258)
>[  260.352688] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1024+768 dst 0x0+1024+768
>[  260.352702] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  260.352715] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  260.352733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  260.352752] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  260.352768] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  260.352976] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  260.352997] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  260.353029] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  260.359710] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  260.359726] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  260.359748] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  260.359768] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  260.359786] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  260.359807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  260.359824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  260.359840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  260.359855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  260.359871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  260.359887] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  260.359904] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  260.359919] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  260.359935] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  260.359953] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  260.359969] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  260.362092] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  260.362108] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  260.365075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  260.365094] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  260.365110] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  260.365127] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  260.367626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  260.367645] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  260.370378] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  260.372290] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 2
>[  260.373153] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  260.373178] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  260.373198] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  260.373243] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  260.373290] [drm:intel_fbc_enable [i915]] reserved 4153344 bytes of contiguous stolen space for FBC, threshold: 1
>[  260.373310] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  260.386825] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  260.386856] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  260.386893] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  265.387473] [drm:drm_mode_addfb2] [FB:86]
>[  265.427911] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  265.427936] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  265.428007] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  265.428025] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  265.428045] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 49500KHz
>[  265.428066] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  265.428082] [drm:intel_dp_compute_config [i915]] DP link bw required 148500 available 162000
>[  265.428100] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  265.428117] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  265.428133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  265.428149] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1922389, gmch_n: 2097152, link_m: 80099, link_n: 262144, tu: 64
>[  265.428164] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  265.428178] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  265.428181] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  265.428213] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  265.428226] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[  265.428247] [drm:intel_dump_pipe_config [i915]] crtc timings: 49500 800 816 896 1056 600 601 604 625, type: 0x40 flags: 0x5
>[  265.428268] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 49500
>[  265.428290] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  265.428310] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  265.428326] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  265.428351] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  265.428372] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  265.428395] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 832x624 format = XR24 little-endian (0x34325258)
>[  265.428412] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+832+624 dst 0x0+832+624
>[  265.428432] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  265.428454] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  265.428480] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  265.428507] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  265.428530] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  265.428709] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  265.428739] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  265.428782] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  265.431310] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  265.431326] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  265.431348] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  265.431368] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  265.431386] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  265.431408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  265.431424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  265.431440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  265.431455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  265.431470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  265.431486] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  265.431503] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  265.431519] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  265.431534] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  265.431552] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  265.431568] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  265.433693] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  265.433710] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  265.436680] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  265.436698] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  265.436715] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  265.436732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  265.439137] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  265.439156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  265.441923] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  265.444034] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  265.444899] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  265.444924] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  265.444941] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  265.444963] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  265.444997] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  265.445013] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  265.458533] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  265.458647] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  265.458783] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  270.459380] [drm:drm_mode_addfb2] [FB:88]
>[  270.498932] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  270.498958] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  270.499026] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  270.499045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  270.499064] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 50000KHz
>[  270.499085] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  270.499100] [drm:intel_dp_compute_config [i915]] DP link bw required 150000 available 162000
>[  270.499118] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  270.499135] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  270.499151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  270.499167] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1941807, gmch_n: 2097152, link_m: 80908, link_n: 262144, tu: 64
>[  270.499182] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  270.499213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  270.499217] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  270.499246] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  270.499251] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[  270.499273] [drm:intel_dump_pipe_config [i915]] crtc timings: 50000 800 856 976 1040 600 637 643 666, type: 0x40 flags: 0x5
>[  270.499295] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 50000
>[  270.499315] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  270.499333] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  270.499354] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  270.499378] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  270.499398] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  270.499417] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  270.499433] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+800+600 dst 0x0+800+600
>[  270.499454] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  270.499473] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  270.499499] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  270.499521] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  270.499543] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  270.499731] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  270.499760] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  270.499804] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  270.512892] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  270.512910] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  270.512934] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  270.512956] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  270.512975] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  270.512998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  270.513015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  270.513031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  270.513047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  270.513062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  270.513079] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  270.513096] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  270.513112] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  270.513128] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  270.513146] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  270.513162] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  270.515304] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  270.515320] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  270.518291] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  270.518310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  270.518326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  270.518343] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  270.520805] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  270.520824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  270.523613] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  270.525310] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  270.526174] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  270.526220] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  270.526244] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  270.526276] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  270.526329] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  270.526353] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  270.540433] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  270.540549] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  270.540685] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  275.541356] [drm:drm_mode_addfb2] [FB:86]
>[  275.581099] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  275.581125] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  275.581193] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  275.581235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  275.581259] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 40000KHz
>[  275.581286] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  275.581309] [drm:intel_dp_compute_config [i915]] DP link bw required 120000 available 162000
>[  275.581333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  275.581356] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  275.581375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  275.581393] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1553445, gmch_n: 2097152, link_m: 64726, link_n: 262144, tu: 64
>[  275.581414] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  275.581443] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  275.581447] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  275.581466] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  275.581470] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  275.581491] [drm:intel_dump_pipe_config [i915]] crtc timings: 40000 800 840 968 1056 600 601 605 628, type: 0x40 flags: 0x5
>[  275.581512] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 40000
>[  275.581533] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  275.581549] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  275.581566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  275.581589] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  275.581610] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  275.581631] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  275.581649] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+800+600 dst 0x0+800+600
>[  275.581666] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  275.581686] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  275.581711] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  275.581737] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  275.581756] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  275.581932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  275.581960] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  275.582004] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  275.584532] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  275.584549] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  275.584571] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  275.584590] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  275.584609] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  275.584630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  275.584646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  275.584662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  275.584678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  275.584693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  275.584709] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  275.584726] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  275.584742] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  275.584757] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  275.584775] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  275.584791] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  275.586919] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  275.586935] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  275.589903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  275.589921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  275.589937] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  275.589954] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  275.592423] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  275.592442] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  275.595170] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  275.597284] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  275.598151] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  275.598175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  275.598191] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  275.598240] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  275.598585] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  275.598609] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  275.615020] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  275.615051] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  275.615089] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  280.615578] [drm:drm_mode_addfb2] [FB:88]
>[  280.655698] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  280.655725] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  280.655793] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  280.655812] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  280.655831] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 36000KHz
>[  280.655851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  280.655867] [drm:intel_dp_compute_config [i915]] DP link bw required 108000 available 162000
>[  280.655885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  280.655901] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  280.655917] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  280.655933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1398101, gmch_n: 2097152, link_m: 58254, link_n: 262144, tu: 64
>[  280.655948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  280.655962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  280.655965] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  280.655979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  280.655989] [drm:drm_mode_debug_printmodeline] Modeline 0:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[  280.656004] [drm:intel_dump_pipe_config [i915]] crtc timings: 36000 800 824 896 1024 600 601 603 625, type: 0x40 flags: 0x5
>[  280.656018] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 800x600, pixel rate 36000
>[  280.656032] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  280.656045] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  280.656059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  280.656075] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  280.656089] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  280.656103] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  280.656117] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+800+600 dst 0x0+800+600
>[  280.656130] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  280.656144] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  280.656161] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  280.656180] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  280.656196] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  280.656414] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  280.656444] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  280.656489] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  280.674064] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  280.674081] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  280.674104] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  280.674126] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  280.674144] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  280.674168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  280.674185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  280.674244] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  280.674269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  280.674291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  280.674313] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  280.674341] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  280.674368] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  280.674393] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  280.674421] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  280.674445] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  280.676528] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  280.676545] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  280.679532] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  280.679550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  280.679567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  280.679584] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  280.682067] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  280.682086] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  280.684840] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  280.686285] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  280.687148] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  280.687175] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  280.687194] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  280.687239] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  280.687421] [drm:intel_fbc_enable [i915]] reserved 3840000 bytes of contiguous stolen space for FBC, threshold: 1
>[  280.687443] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  280.705257] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  280.705289] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  280.705326] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  285.705707] [drm:drm_mode_addfb2] [FB:86]
>[  285.742406] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  285.742433] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  285.742498] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  285.742516] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  285.742536] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 27000KHz
>[  285.742555] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  285.742571] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000
>[  285.742589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  285.742606] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  285.742622] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  285.742638] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  285.742653] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  285.742667] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  285.742670] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  285.742684] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  285.742695] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  285.742710] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 732 796 864 576 581 586 625, type: 0x40 flags: 0xa
>[  285.742724] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x576, pixel rate 27000
>[  285.742738] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  285.742751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  285.742765] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  285.742781] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  285.742795] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  285.742810] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 800x600 format = XR24 little-endian (0x34325258)
>[  285.742824] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+800+600 dst 0x0+800+600
>[  285.742837] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  285.742851] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  285.742868] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  285.742888] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  285.742903] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  285.743054] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  285.743075] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  285.743109] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  285.754769] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  285.754786] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  285.754808] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  285.754828] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  285.754847] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  285.754869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  285.754886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  285.754902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  285.754917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  285.754932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  285.754948] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  285.754965] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  285.754981] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  285.754997] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  285.755015] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  285.755031] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  285.757156] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  285.757172] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  285.760137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  285.760155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  285.760171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  285.760191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  285.762654] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  285.762671] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  285.765355] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  285.767385] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  285.768254] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  285.768278] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  285.768295] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  285.768317] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  285.768351] [drm:intel_fbc_enable [i915]] reserved 3317760 bytes of contiguous stolen space for FBC, threshold: 1
>[  285.768367] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  285.788480] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  285.788512] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  285.788563] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  290.788940] [drm:drm_mode_addfb2] [FB:88]
>[  290.819690] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  290.819713] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  290.819781] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  290.819805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  290.819830] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 27027KHz
>[  290.819852] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  290.819868] [drm:intel_dp_compute_config [i915]] DP link bw required 81081 available 162000
>[  290.819885] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  290.819902] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  290.819918] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  290.819933] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1049624, gmch_n: 2097152, link_m: 43734, link_n: 262144, tu: 64
>[  290.819948] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  290.819962] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  290.819965] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  290.819979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  290.819982] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  290.819996] [drm:intel_dump_pipe_config [i915]] crtc timings: 27027 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  290.820010] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27027
>[  290.820024] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  290.820038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  290.820051] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  290.820068] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  290.820082] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  290.820097] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 720x576 format = XR24 little-endian (0x34325258)
>[  290.820111] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+720+576 dst 0x0+720+576
>[  290.820125] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  290.820139] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  290.820156] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  290.820175] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  290.820191] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  290.820392] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  290.820417] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  290.820461] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  290.829294] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  290.829312] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  290.829335] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  290.829357] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  290.829376] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  290.829399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  290.829417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  290.829432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  290.829448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  290.829463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  290.829478] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  290.829495] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  290.829511] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  290.829526] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  290.829544] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  290.829560] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  290.831227] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  290.831242] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  290.834313] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  290.834390] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  290.834463] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  290.834537] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  290.837243] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  290.837347] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  290.840815] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  290.842967] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  290.844802] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  290.844903] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  290.844975] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  290.845063] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  290.845235] [drm:intel_fbc_enable [i915]] reserved 2764800 bytes of contiguous stolen space for FBC, threshold: 1
>[  290.845415] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  290.861747] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  290.861853] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  290.861982] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  295.862464] [drm:drm_mode_addfb2] [FB:86]
>[  295.892537] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  295.892565] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  295.892632] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  295.892650] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.892670] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 27000KHz
>[  295.892688] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  295.892704] [drm:intel_dp_compute_config [i915]] DP link bw required 81000 available 162000
>[  295.892721] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.892738] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  295.892754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  295.892769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1048576, gmch_n: 2097152, link_m: 43690, link_n: 262144, tu: 64
>[  295.892784] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  295.892798] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.892801] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  295.892815] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.892818] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  295.892832] [drm:intel_dump_pipe_config [i915]] crtc timings: 27000 720 736 798 858 480 489 495 525, type: 0x40 flags: 0xa
>[  295.892855] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x480, pixel rate 27000
>[  295.892869] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  295.892883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.892896] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.892913] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  295.892926] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.892940] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 720x480 format = XR24 little-endian (0x34325258)
>[  295.892954] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+720+480 dst 0x0+720+480
>[  295.892967] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  295.892981] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  295.892999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.893018] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  295.893033] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  295.893172] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  295.893193] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  295.893244] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  295.895697] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  295.895712] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  295.895733] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  295.895752] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  295.895770] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  295.895791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  295.895807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  295.895823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  295.895838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  295.895852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  295.895868] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  295.895884] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  295.895900] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  295.895915] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  295.895933] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  295.895948] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  295.898059] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  295.898074] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  295.901043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  295.901062] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  295.901078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  295.901096] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  295.903581] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  295.903600] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  295.906276] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  295.908279] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  295.909140] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  295.909164] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  295.909181] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  295.909226] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  295.909273] [drm:intel_fbc_enable [i915]] reserved 2764800 bytes of contiguous stolen space for FBC, threshold: 1
>[  295.909292] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  295.925979] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  295.926006] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  295.926042] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  300.926513] [drm:drm_mode_addfb2] [FB:88]
>[  300.955985] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  300.956007] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  300.956068] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  300.956087] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  300.956107] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 31500KHz
>[  300.956128] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  300.956144] [drm:intel_dp_compute_config [i915]] DP link bw required 94500 available 162000
>[  300.956161] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  300.956178] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  300.956194] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  300.956228] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1223338, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64
>[  300.956247] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  300.956269] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  300.956273] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  300.956294] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  300.956298] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[  300.956320] [drm:intel_dump_pipe_config [i915]] crtc timings: 31500 640 656 720 840 480 481 484 500, type: 0x40 flags: 0xa
>[  300.956340] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 31500
>[  300.956357] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  300.956378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  300.956399] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  300.956422] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  300.956440] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  300.956457] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 720x480 format = XR24 little-endian (0x34325258)
>[  300.956478] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+720+480 dst 0x0+720+480
>[  300.956497] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  300.956517] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  300.956540] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  300.956567] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  300.956589] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  300.956751] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  300.956780] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  300.956838] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  300.965630] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  300.965646] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  300.965668] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  300.965689] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  300.965708] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  300.965729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  300.965746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  300.965762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  300.965777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  300.965792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  300.965808] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  300.965825] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  300.965841] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  300.965857] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  300.965875] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  300.965890] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  300.967228] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  300.967243] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  300.970205] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  300.970233] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  300.970251] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  300.970270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  300.972651] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  300.972668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  300.975411] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  300.977447] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  300.978322] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  300.978347] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  300.978364] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  300.978386] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  300.978420] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  300.978436] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  300.991927] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  300.991959] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  300.991996] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  305.992373] [drm:drm_mode_addfb2] [FB:86]
>[  306.022021] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  306.022043] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  306.022111] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  306.022129] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  306.022149] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 31500KHz
>[  306.022168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  306.022184] [drm:intel_dp_compute_config [i915]] DP link bw required 94500 available 162000
>[  306.022220] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  306.022242] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  306.022266] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  306.022289] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1223338, gmch_n: 2097152, link_m: 50972, link_n: 262144, tu: 64
>[  306.022310] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  306.022328] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  306.022333] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  306.022353] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  306.022358] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[  306.022379] [drm:intel_dump_pipe_config [i915]] crtc timings: 31500 640 664 704 832 480 489 492 520, type: 0x40 flags: 0xa
>[  306.022400] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 31500
>[  306.022418] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  306.022438] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  306.022458] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  306.022481] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  306.022498] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  306.022516] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  306.022536] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+640+480 dst 0x0+640+480
>[  306.022556] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  306.022576] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  306.022598] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  306.022624] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  306.022647] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  306.022806] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  306.022835] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  306.022879] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  306.033751] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  306.033768] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  306.033790] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  306.033810] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  306.033829] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  306.033850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  306.033866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  306.033882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  306.033897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  306.033912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  306.033928] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  306.033945] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  306.033961] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  306.033977] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  306.033995] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  306.034010] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  306.036139] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  306.036155] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  306.039136] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  306.039155] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  306.039171] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  306.039190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  306.041675] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  306.041694] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  306.044460] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  306.046575] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  306.047450] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  306.047475] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  306.047491] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  306.047513] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  306.047546] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  306.047562] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  306.061533] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  306.061648] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  306.061783] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  311.062349] [drm:drm_mode_addfb2] [FB:88]
>[  311.091964] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  311.091988] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  311.092054] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  311.092073] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.092093] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 30240KHz
>[  311.092113] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  311.092128] [drm:intel_dp_compute_config [i915]] DP link bw required 90720 available 162000
>[  311.092145] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.092161] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  311.092177] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  311.092193] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1174405, gmch_n: 2097152, link_m: 48933, link_n: 262144, tu: 64
>[  311.092225] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  311.092242] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.092246] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  311.092263] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.092268] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[  311.092286] [drm:intel_dump_pipe_config [i915]] crtc timings: 30240 640 704 768 864 480 483 486 525, type: 0x40 flags: 0xa
>[  311.092303] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 30240
>[  311.092320] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  311.092339] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.092356] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  311.092379] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  311.092393] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.092407] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  311.092421] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+640+480 dst 0x0+640+480
>[  311.092434] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  311.092448] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  311.092466] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.092485] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  311.092501] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  311.092627] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  311.092648] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  311.092682] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.102664] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  311.102680] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  311.102703] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.102725] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  311.102743] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  311.102766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  311.102783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  311.102799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  311.102815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  311.102830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  311.102846] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  311.102863] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  311.102879] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  311.102894] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  311.102912] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  311.102928] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  311.105127] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  311.105144] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  311.108139] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.108158] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.108174] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.108191] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.110673] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.110692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  311.113459] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.115571] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  311.116451] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  311.116477] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  311.116494] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  311.116516] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  311.116558] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  311.116574] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  311.131635] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  311.131664] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  311.131700] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  316.132188] [drm:drm_mode_addfb2] [FB:86]
>[  316.161910] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  316.161934] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  316.162003] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  316.162021] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  316.162040] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 25200KHz
>[  316.162059] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  316.162075] [drm:intel_dp_compute_config [i915]] DP link bw required 75600 available 162000
>[  316.162092] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  316.162109] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  316.162125] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  316.162141] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 978670, gmch_n: 2097152, link_m: 40777, link_n: 262144, tu: 64
>[  316.162156] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  316.162170] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  316.162173] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  316.162187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  316.162202] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  316.162217] [drm:intel_dump_pipe_config [i915]] crtc timings: 25200 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  316.162232] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25200
>[  316.162248] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  316.162263] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  316.162278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  316.162295] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  316.162310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  316.162326] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  316.162342] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+640+480 dst 0x0+640+480
>[  316.162356] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  316.162371] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  316.162389] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  316.162410] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  316.162427] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  316.162588] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  316.162616] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  316.162655] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  316.173654] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  316.173671] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  316.173694] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  316.173716] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  316.173735] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  316.173759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  316.173776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  316.173792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  316.173808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  316.173823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  316.173839] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  316.173856] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  316.173872] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  316.173888] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  316.173906] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  316.173922] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  316.176158] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  316.176175] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  316.179207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  316.179240] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  316.179256] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  316.179273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  316.181656] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  316.181673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  316.184437] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  316.186546] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  316.187423] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  316.187451] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  316.187467] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  316.187489] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  316.187531] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  316.187548] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  316.204424] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  316.204455] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  316.204493] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  321.204983] [drm:drm_mode_addfb2] [FB:88]
>[  321.235171] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  321.235204] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  321.235288] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  321.235313] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.235335] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 25175KHz
>[  321.235356] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  321.235378] [drm:intel_dp_compute_config [i915]] DP link bw required 75525 available 162000
>[  321.235403] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.235427] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  321.235445] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  321.235468] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 977700, gmch_n: 2097152, link_m: 40737, link_n: 262144, tu: 64
>[  321.235490] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  321.235511] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.235515] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  321.235532] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.235536] [drm:drm_mode_debug_printmodeline] Modeline 0:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  321.235557] [drm:intel_dump_pipe_config [i915]] crtc timings: 25175 640 656 752 800 480 490 492 525, type: 0x40 flags: 0xa
>[  321.235579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 640x480, pixel rate 25175
>[  321.235599] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.235617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.235637] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.235661] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.235682] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.235700] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:86, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  321.235717] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+640+480 dst 0x0+640+480
>[  321.235737] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  321.235757] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  321.235783] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.235809] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  321.235832] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  321.235996] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  321.236023] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  321.236068] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  321.238643] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  321.238659] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  321.238681] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  321.238702] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  321.238720] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  321.238742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  321.238758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  321.238774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  321.238790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  321.238805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  321.238821] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  321.238838] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  321.238854] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  321.238869] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  321.238887] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  321.238903] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  321.241063] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  321.241079] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  321.244047] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.244065] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.244082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.244099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.246563] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.246582] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  321.249275] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.251313] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  321.252180] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  321.252234] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  321.252260] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  321.252291] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  321.252336] [drm:intel_fbc_enable [i915]] reserved 2457600 bytes of contiguous stolen space for FBC, threshold: 1
>[  321.252360] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  321.269036] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  321.269064] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  321.269099] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  326.269460] [drm:drm_mode_addfb2] [FB:86]
>[  326.295827] [drm:drm_mode_setcrtc] [CRTC:32:pipe A]
>[  326.295844] [drm:drm_mode_setcrtc] [CONNECTOR:48:DP-1]
>[  326.295908] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  326.295927] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.295947] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 28320KHz
>[  326.295968] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 1 clock 162000 bpp 24
>[  326.295984] [drm:intel_dp_compute_config [i915]] DP link bw required 84960 available 162000
>[  326.296001] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.296018] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  326.296034] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  326.296050] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 1; gmch_m: 1099839, gmch_n: 2097152, link_m: 45826, link_n: 262144, tu: 64
>[  326.296065] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  326.296080] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.296083] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  326.296097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.296099] [drm:drm_mode_debug_printmodeline] Modeline 0:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[  326.296114] [drm:intel_dump_pipe_config [i915]] crtc timings: 28320 720 738 846 900 400 412 414 449, type: 0x40 flags: 0x6
>[  326.296128] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 720x400, pixel rate 28320
>[  326.296142] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  326.296156] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.296169] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.296186] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.296214] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.296229] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:88, fb = 640x480 format = XR24 little-endian (0x34325258)
>[  326.296243] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+640+480 dst 0x0+640+480
>[  326.296258] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  326.296275] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  326.296294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.296314] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  326.296332] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  326.296465] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  326.296486] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  326.296520] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  326.309762] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  326.309779] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  326.309802] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  326.309823] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  326.309842] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  326.309866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  326.309883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  326.309899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  326.309915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  326.309930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  326.309946] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  326.309962] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  326.309978] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  326.309994] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  326.310013] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  326.310028] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  326.312165] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  326.312182] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  326.315177] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  326.315196] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  326.315229] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  326.315246] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  326.317707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  326.317726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  326.320489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  326.322601] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 1
>[  326.323481] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  326.323507] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  326.323524] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  326.323546] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  326.323586] [drm:intel_fbc_enable [i915]] reserved 2304000 bytes of contiguous stolen space for FBC, threshold: 1
>[  326.323603] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  326.337932] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  326.337961] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  326.337997] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  331.338802] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  331.339845] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[  331.340066] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[  331.340832] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  331.348090] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  331.348195] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>[  331.348432] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  331.348679] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 32
>[  331.348808] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  331.348972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.349051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  331.349122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  331.349192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  331.349320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  331.349397] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  331.349483] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  331.349558] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  331.349642] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  331.349744] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  331.349911] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  331.350111] [drm:skl_set_power_well [i915]] Disabling power well 2
>[  331.350242] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.350398] [drm:intel_power_well_disable [i915]] disabling DC off
>[  331.350493] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  331.350581] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  331.351051] [drm:intel_power_well_disable [i915]] disabling always-on
>[  331.353032] [drm:intel_atomic_check [i915]] [CONNECTOR:48:DP-1] checking for sink bpp constrains
>[  331.353162] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  331.353254] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 533250KHz
>[  331.353417] [drm:intel_dp_compute_config [i915]] DP link bw 14 rate select 00 lane count 4 clock 540000 bpp 24
>[  331.353516] [drm:intel_dp_compute_config [i915]] DP link bw required 1599750 available 2160000
>[  331.353592] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  331.353611] [drm:intel_dump_pipe_config [i915]] [CRTC:32:pipe A][modeset]
>[  331.353634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  331.353656] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6212812, gmch_n: 8388608, link_m: 1035468, link_n: 1048576, tu: 64
>[  331.353677] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[  331.353694] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  331.353699] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.353719] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  331.353722] [drm:drm_mode_debug_printmodeline] Modeline 0:"3840x2160" 60 533250 3840 3888 3920 4000 2160 2163 2168 2222 0x48 0x9
>[  331.353743] [drm:intel_dump_pipe_config [i915]] crtc timings: 533250 3840 3888 3920 4000 2160 2163 2168 2222, type: 0x48 flags: 0x9
>[  331.353763] [drm:intel_dump_pipe_config [i915]] port clock: 540000, pipe src size: 3840x2160, pixel rate 533250
>[  331.353779] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  331.353798] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  331.353818] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  331.353841] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  331.353858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  331.353874] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>[  331.353894] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>[  331.353913] [drm:intel_dump_pipe_config [i915]] [PLANE:30:cursor A] disabled, scaler_id = -1
>[  331.353937] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 540000 kHz, actual 540000 kHz
>[  331.353958] [drm:intel_find_shared_dpll [i915]] [CRTC:32:pipe A] allocated DPLL 1
>[  331.353975] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  331.354045] [drm:intel_power_well_enable [i915]] enabling always-on
>[  331.354067] [drm:intel_power_well_enable [i915]] enabling DC off
>[  331.354361] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  331.354389] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  331.354408] [drm:skl_set_power_well [i915]] Enabling power well 2
>[  331.354470] [drm:intel_set_cdclk [i915]] Changing CDCLK to 540000 kHz, VCO 8100000 kHz, ref 24000 kHz
>[  331.354936] [drm:intel_update_cdclk [i915]] Current CD clock rate: 540000 kHz, VCO: 8100000 kHz, ref: 24000 kHz
>[  331.354956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:47:DDI B]
>[  331.354974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:49:DP-MST A]
>[  331.354991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:50:DP-MST B]
>[  331.355007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:51:DP-MST C]
>[  331.355022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI C]
>[  331.355039] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 0
>[  331.355057] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1
>[  331.355073] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 2
>[  331.355089] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 3
>[  331.355115] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 32
>[  331.355134] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  331.357271] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  331.357286] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>[  331.360300] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  331.360319] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  331.360337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.360355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  331.364007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[  331.364026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[  331.364043] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.367667] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 07000000
>[  331.367686] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 2
>[  331.367703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  331.371230] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  331.371249] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  331.374090] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  331.376202] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 540000, Lane count = 4
>[  331.377108] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  331.377149] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:48:DP-1], [ENCODER:47:DDI B]
>[  331.377166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 32 bytes ELD
>[  331.377197] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[  331.377376] [drm:intel_fbc_enable [i915]] reserved 33177600 bytes of contiguous stolen space for FBC, threshold: 1
>[  331.377411] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.394127] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:48:DP-1]
>[  331.394223] [drm:intel_atomic_commit_tail [i915]] [CRTC:32:pipe A]
>[  331.394420] [drm:verify_single_dpll_state.isra.76 [i915]] DPLL 1

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