Attachment 131897 Details for Bug 101384 – R600_DEBUG="vs,tcs,tes,gs,ps,cs" ./runner

R600_DEBUG="vs,tcs,tes,gs,ps,cs" ./runner

HeroSiegeLog_new (text/plain), 348.04 KB, created by Christian Lanig on 2017-06-12 19:24:02 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Christian Lanig

Created: 2017-06-12 19:24:02 UTC

Size: 348.04 KB

patch

obsolete

>***************************************
>*     YoYo Games Linux Runner V1.3    *
>***************************************	 
>CommandLine: -game game.unx
>ExeName= /home/user/.steam/steam/steamapps/common/HeroSiege/linux/runner
>MemoryManager allocated: 1722124
>
>***************************************
>*     YoYo Games Runner v1.0(999)[r32908]    *
>***************************************	 
>RunnerLoadGame: game.unx
>RunnerLoadGame() - assets/game.unx
>Checking if INIFile assets/options.ini Exists
>assets/options.ini file contents: [Linux]
>DisplayName="Hero Siege"
>NewDebugger=0
>
>INI DisplayName=Hero Siege
>Reading File assets/game.unx
>Loaded File assets/game.unx(244535986)
>IFF wad found
>Get Resolution
>Get Header Information
>InitGMLFunctions
>HighScore..SavePrePend /home/user/.config/Hero_Siege/ 
>Game..Math..Graphic..Action..File..Resource..Interaction..3D..Particle..Misc..DS..Sound..Physics..Gamepad..GAMEPAD: Initialising Ubuntu support
>GAMEPAD: 4 axis values (last) at 0xf6af6580
>GAMEPAD: Enumerating 3
>GAMEPAD: device name Wacom Intuos PT S Pad
>GAMEPAD: buttons - 5, axes - 2
>GAMEPAD: 4 axis values (last) at 0xf6af64c0
>GAMEPAD: 4 axis values (last) at 0xf6af64a0
>GAMEPAD: 4 axis values (last) at 0xf6af6480
>Buffers..Networking..Shaders..Steam being initialised with appId 269210
>Steam_Init
>Error: Failed to load libsteam_api.so: libsteam_api.so: cannot open shared object file: No such file or directory
>Failed LoadSteamLib() call: Error loading libsteam_api.so
>SteamInit failed: Error loading libsteam_api.so
>InitPushFunctions...YoYo..Fini
>Code_Load()
>VARI_Load()
>got 539 global variables
>got 1814 instance variables
>got 441 local variables
>ID_STRG
>Create Window
>Display Size(Pixels): 2560,1440
>GameDisplayName=Hero Siege
>Win #1
>XF86VidModeExtension-Version 2.2
>Got Doublebuffered Visual!
>glX-Version 1.4
>Icon: w=64 h=64
>sw=2560 wh=1440
>WindowCentre: 797,448
>Depth 24
>Congrats, you have Direct Rendering!
>Set Fullscreen 1
>sync = 0
>**** GLX Extensions ***
>GLX_ARB_create_context GLX_ARB_create_context_profile GLX_ARB_create_context_robustness GLX_ARB_fbconfig_float GLX_ARB_framebuffer_sRGB GLX_ARB_get_proc_address GLX_ARB_multisample GLX_EXT_import_context GLX_EXT_visual_info GLX_EXT_visual_rating GLX_EXT_fbconfig_packed_float GLX_EXT_framebuffer_sRGB GLX_EXT_create_context_es2_profile GLX_EXT_create_context_es_profile GLX_MESA_copy_sub_buffer GLX_MESA_multithread_makecurrent GLX_MESA_query_renderer GLX_MESA_swap_control GLX_OML_swap_method GLX_OML_sync_control GLX_SGI_make_current_read GLX_SGI_swap_control GLX_SGI_video_sync GLX_SGIS_multisample GLX_SGIX_fbconfig GLX_SGIX_pbuffer GLX_SGIX_visual_select_group GLX_EXT_texture_from_pixmap GLX_INTEL_swap_event GLX_EXT_buffer_age 
>Checking for GLX_EXT_swap_control
>Checking for GLX_SGI_swap_control
>Vsync: GLX_SGI
>DOUBLE BUFFERED
>Init Graphics
>GR_D3D_Init()
>OpenGL: version string 3.0 Mesa 17.2.0-devel - padoka PPA
>OpenGL: vendor string X.Org
>OpenGL GLSL: version string 1.30
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], COLOR, COLOR
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>radeonsi: Compiling shader 1
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32, float, float, float, float) #0 {
>main_body:
>  %25 = bitcast float %3 to i32
>  %26 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %25, 6
>  %27 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %26, float %21, 7
>  %28 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %27, float %22, 8
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %28, float %23, 9
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %29, float %24, 10
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %30, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %31
>}
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], COLOR
>DCL CONST[0..3]
>DCL TEMP[0]
>  0: MUL TEMP[0], IN[0].xxxx, CONST[0]
>  1: MAD TEMP[0], IN[0].yyyy, CONST[1], TEMP[0]
>  2: MAD TEMP[0], IN[0].zzzz, CONST[2], TEMP[0]
>  3: MAD OUT[0], IN[0].wwww, CONST[3], TEMP[0]
>  4: MOV OUT[1], IN[1]
>  5: END
>radeonsi: Compiling shader 2
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %14 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %15 = load <4 x i32>, <4 x i32> addrspace(2)* %14, align 16, !invariant.load !0
>  %16 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %15, i32 %12, i32 0, i1 false, i1 false) #2
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = extractelement <4 x float> %16, i32 1
>  %19 = extractelement <4 x float> %16, i32 2
>  %20 = extractelement <4 x float> %16, i32 3
>  %21 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %22, i32 %13, i32 0, i1 false, i1 false) #2
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = extractelement <4 x float> %23, i32 2
>  %27 = extractelement <4 x float> %23, i32 3
>  %28 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 0)
>  %31 = fmul nsz float %17, %30
>  %32 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 4)
>  %33 = fmul nsz float %17, %32
>  %34 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 8)
>  %35 = fmul nsz float %17, %34
>  %36 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 12)
>  %37 = fmul nsz float %17, %36
>  %38 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 16)
>  %39 = fmul nsz float %18, %38
>  %40 = fadd nsz float %39, %31
>  %41 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 20)
>  %42 = fmul nsz float %18, %41
>  %43 = fadd nsz float %42, %33
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 24)
>  %45 = fmul nsz float %18, %44
>  %46 = fadd nsz float %45, %35
>  %47 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 28)
>  %48 = fmul nsz float %18, %47
>  %49 = fadd nsz float %48, %37
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 32)
>  %51 = fmul nsz float %19, %50
>  %52 = fadd nsz float %51, %40
>  %53 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 36)
>  %54 = fmul nsz float %19, %53
>  %55 = fadd nsz float %54, %43
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 40)
>  %57 = fmul nsz float %19, %56
>  %58 = fadd nsz float %57, %46
>  %59 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 44)
>  %60 = fmul nsz float %19, %59
>  %61 = fadd nsz float %60, %49
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 48)
>  %63 = fmul nsz float %20, %62
>  %64 = fadd nsz float %63, %52
>  %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 52)
>  %66 = fmul nsz float %20, %65
>  %67 = fadd nsz float %66, %55
>  %68 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 56)
>  %69 = fmul nsz float %20, %68
>  %70 = fadd nsz float %69, %58
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 60)
>  %72 = fmul nsz float %20, %71
>  %73 = fadd nsz float %72, %61
>  %74 = and i32 %7, 1
>  %75 = icmp eq i32 %74, 0
>  br i1 %75, label %endif-block, label %if-true-block
>
>if-true-block:                                    ; preds = %main_body
>  %76 = call nsz float @llvm.maxnum.f32(float %24, float 0.000000e+00) #2
>  %77 = call nsz float @llvm.minnum.f32(float %76, float 1.000000e+00) #2
>  %78 = call nsz float @llvm.maxnum.f32(float %25, float 0.000000e+00) #2
>  %79 = call nsz float @llvm.minnum.f32(float %78, float 1.000000e+00) #2
>  %80 = call nsz float @llvm.maxnum.f32(float %26, float 0.000000e+00) #2
>  %81 = call nsz float @llvm.minnum.f32(float %80, float 1.000000e+00) #2
>  %82 = call nsz float @llvm.maxnum.f32(float %27, float 0.000000e+00) #2
>  %83 = call nsz float @llvm.minnum.f32(float %82, float 1.000000e+00) #2
>  br label %endif-block
>
>endif-block:                                      ; preds = %main_body, %if-true-block
>  %.03 = phi float [ %83, %if-true-block ], [ %27, %main_body ]
>  %.02 = phi float [ %81, %if-true-block ], [ %26, %main_body ]
>  %.01 = phi float [ %79, %if-true-block ], [ %25, %main_body ]
>  %.0 = phi float [ %77, %if-true-block ], [ %24, %main_body ]
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %.0, float %.01, float %.02, float %.03, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %64, float %67, float %70, float %73, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>radeonsi: Compiling shader 3
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %4) #2
>  %22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 1, i32 0, i32 %4) #2
>  %23 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 2, i32 0, i32 %4) #2
>  %24 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 3, i32 0, i32 %4) #2
>  %25 = bitcast float %3 to i32
>  %26 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %25, 6
>  %27 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %26, float %21, 7
>  %28 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %27, float %22, 8
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %28, float %23, 9
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %29, float %24, 10
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %30, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %31
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readnone }
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>radeonsi: Compiling shader 4
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %14 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %15 = load <4 x i32>, <4 x i32> addrspace(2)* %14, align 16, !invariant.load !0
>  %16 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %15, i32 %12, i32 0, i1 false, i1 false) #3
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = extractelement <4 x float> %16, i32 1
>  %19 = extractelement <4 x float> %16, i32 2
>  %20 = extractelement <4 x float> %16, i32 3
>  %21 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %22, i32 %13, i32 0, i1 false, i1 false) #3
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = extractelement <4 x float> %23, i32 2
>  %27 = extractelement <4 x float> %23, i32 3
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %24, float %25, float %26, float %27, i1 false, i1 false) #2
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %17, float %18, float %19, float %20, i1 true, i1 false) #2
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #2
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind }
>attributes #3 = { nounwind readnone }
>
>!0 = !{}
>
>radeonsi: Compiling shader 5
>Vertex Shader Prolog LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> @vs_prolog(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> undef, i32 %0, 0
>  %17 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %16, i32 %1, 1
>  %18 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %17, i32 %2, 2
>  %19 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %18, i32 %3, 3
>  %20 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %19, i32 %4, 4
>  %21 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %20, i32 %5, 5
>  %22 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %21, i32 %6, 6
>  %23 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %22, i32 %7, 7
>  %24 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %23, i32 %8, 8
>  %25 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %24, i32 %9, 9
>  %26 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %25, i32 %10, 10
>  %27 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %26, i32 %11, 11
>  %28 = bitcast i32 %12 to float
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %27, float %28, 12
>  %30 = bitcast i32 %13 to float
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %29, float %30, 13
>  %32 = bitcast i32 %14 to float
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %31, float %32, 14
>  %34 = bitcast i32 %15 to float
>  %35 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %33, float %34, 15
>  %36 = add i32 %12, %8
>  %37 = bitcast i32 %36 to float
>  %38 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %35, float %37, 16
>  %39 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %38, float %37, 17
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float }> %39
>}
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>
>SHADER KEY
>  part.vs.prolog.instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  mono.u.vs_export_prim_id = 0
>  opt.hw_vs.kill_outputs = 0x0
>  opt.hw_vs.clip_disable = 0
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s8, v0 ; 32080008
>	v_mov_b32_e32 v5, v4          ; 7E0A0304
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[6:7], 0x0                  ; C00A0003 00000000
>	s_load_dwordx4 s[4:7], s[6:7], 0x10                 ; C00A0103 00000010
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	buffer_load_format_xyzw v[0:3], v5, s[4:7], 0 idxen ; E00C2000 80010005
>	buffer_load_format_xyzw v[4:7], v4, s[0:3], 0 idxen ; E00C2000 80000404
>	s_waitcnt vmcnt(1)                                  ; BF8C0F71
>	exp param0 v0, v1, v2, v3                           ; C400020F 03020100
>	s_waitcnt vmcnt(0)                                  ; BF8C0F70
>	exp pos0 v4, v5, v6, v7 done                        ; C40008CF 07060504
>	s_endpgm                                            ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 16
>VGPRS: 8
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 72 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>radeonsi: Compiling shader 6
>Fragment Shader Epilog LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps void @ps_epilog(i64 inreg, i64 inreg, i64 inreg, float inreg, float, float, float, float, float, float, float, float, float, float, float, float, float, float) #0 {
>main_body:
>  %18 = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %4, float %5) #3
>  %19 = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %6, float %7) #3
>  %20 = bitcast <2 x half> %18 to <2 x i16>
>  %21 = bitcast <2 x half> %19 to <2 x i16>
>  call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> %20, <2 x i16> %21, i1 true, i1 true) #2
>  ret void
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #2
>
>attributes #0 = { "InitialPSInputAddr"="16777215" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind }
>attributes #3 = { nounwind readnone }
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>	s_mov_b32 m0, s7                 ; BEFC0007
>	v_interp_mov_f32 v0, p0, attr0.x ; D4020002
>	v_interp_mov_f32 v1, p0, attr0.y ; D4060102
>	v_interp_mov_f32 v2, p0, attr0.z ; D40A0202
>	v_interp_mov_f32 v3, p0, attr0.w ; D40E0302
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32 v0, v0, v1        ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32 v1, v2, v3        ; D2960001 00020702
>	exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100
>	s_endpgm                              ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0020
>*** SHADER STATS ***
>SGPRS: 10
>VGPRS: 16
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 48 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>Check TextureID
>finished(2)!!
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xy, GENERIC[1]
>DCL CONST[0..19]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1].x, IMM[0].xxxx
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3].xy, IN[1].xyxx
>  7: END
>radeonsi: Compiling shader 7
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %15 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <4 x i32>, <4 x i32> addrspace(2)* %15, align 16, !invariant.load !0
>  %17 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %16, i32 %12, i32 0, i1 false, i1 false) #2
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = extractelement <4 x float> %17, i32 1
>  %20 = extractelement <4 x float> %17, i32 2
>  %21 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %22, i32 %13, i32 0, i1 false, i1 false) #2
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %27 = load <4 x i32>, <4 x i32> addrspace(2)* %26, align 16, !invariant.load !0
>  %28 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %27, i32 %14, i32 0, i1 false, i1 false) #2
>  %29 = extractelement <4 x float> %28, i32 0
>  %30 = extractelement <4 x float> %28, i32 1
>  %31 = extractelement <4 x float> %28, i32 2
>  %32 = extractelement <4 x float> %28, i32 3
>  %33 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 256)
>  %36 = fmul nsz float %35, %18
>  %37 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 260)
>  %38 = fmul nsz float %37, %18
>  %39 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 264)
>  %40 = fmul nsz float %39, %18
>  %41 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 268)
>  %42 = fmul nsz float %41, %18
>  %43 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 272)
>  %44 = fmul nsz float %43, %19
>  %45 = fadd nsz float %44, %36
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 276)
>  %47 = fmul nsz float %46, %19
>  %48 = fadd nsz float %47, %38
>  %49 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 280)
>  %50 = fmul nsz float %49, %19
>  %51 = fadd nsz float %50, %40
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 284)
>  %53 = fmul nsz float %52, %19
>  %54 = fadd nsz float %53, %42
>  %55 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 288)
>  %56 = fmul nsz float %55, %20
>  %57 = fadd nsz float %56, %45
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 292)
>  %59 = fmul nsz float %58, %20
>  %60 = fadd nsz float %59, %48
>  %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 296)
>  %62 = fmul nsz float %61, %20
>  %63 = fadd nsz float %62, %51
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 300)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %54
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 304)
>  %68 = fadd nsz float %57, %67
>  %69 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 308)
>  %70 = fadd nsz float %60, %69
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 312)
>  %72 = fadd nsz float %63, %71
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 316)
>  %74 = fadd nsz float %66, %73
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %29, float %30, float %31, float %32, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %24, float %25, float undef, float undef, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %68, float %70, float %72, float %74, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #3
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #3
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1].xy, GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL TEMP[0..1], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[1], TEMP[0], SAMP[0], 2D
>  2: MUL OUT[0], IN[0], TEMP[1]
>  3: END
>radeonsi: Compiling shader 8
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %6 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 1, i32 %4) #3
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 1, i32 %4) #3
>  %26 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 1, i32 %4) #3
>  %27 = call nsz float @llvm.amdgcn.interp.p2(float %26, float %23, i32 1, i32 1, i32 %4) #3
>  %28 = getelementptr [80 x <8 x i32>], [80 x <8 x i32>] addrspace(2)* %2, i64 0, i64 16, !amdgpu.uniform !0
>  %29 = load <8 x i32>, <8 x i32> addrspace(2)* %28, align 32, !invariant.load !0
>  %30 = bitcast [80 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %31 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %30, i64 0, i64 35, !amdgpu.uniform !0
>  %32 = load <4 x i32>, <4 x i32> addrspace(2)* %31, align 16, !invariant.load !0
>  %33 = bitcast float %25 to i32
>  %34 = bitcast float %27 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = bitcast <2 x i32> %36 to <2 x float>
>  %38 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %37, <8 x i32> %29, <4 x i32> %32, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3
>  %39 = extractelement <4 x float> %38, i32 0
>  %40 = extractelement <4 x float> %38, i32 1
>  %41 = extractelement <4 x float> %38, i32 2
>  %42 = extractelement <4 x float> %38, i32 3
>  %43 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #3
>  %44 = call nsz float @llvm.amdgcn.interp.p2(float %43, float %23, i32 0, i32 0, i32 %4) #3
>  %45 = fmul nsz float %44, %39
>  %46 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #3
>  %47 = call nsz float @llvm.amdgcn.interp.p2(float %46, float %23, i32 1, i32 0, i32 %4) #3
>  %48 = fmul nsz float %47, %40
>  %49 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 0, i32 %4) #3
>  %50 = call nsz float @llvm.amdgcn.interp.p2(float %49, float %23, i32 2, i32 0, i32 %4) #3
>  %51 = fmul nsz float %50, %41
>  %52 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 3, i32 0, i32 %4) #3
>  %53 = call nsz float @llvm.amdgcn.interp.p2(float %52, float %23, i32 3, i32 0, i32 %4) #3
>  %54 = fmul nsz float %53, %42
>  %55 = bitcast float %3 to i32
>  %56 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %55, 6
>  %57 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %56, float %45, 7
>  %58 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %57, float %48, 8
>  %59 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %58, float %51, 9
>  %60 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %59, float %54, 10
>  %61 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %60, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %61
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readonly }
>attributes #3 = { nounwind readnone }
>
>!0 = !{}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xyz, GENERIC[1]
>DCL CONST[0..21]
>DCL TEMP[0..8], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1].x, IMM[0].xxxx
>  5: MOV OUT[2], IN[2]
>  6: MOV OUT[3].xy, IN[1].xyxx
>  7: MUL TEMP[3], CONST[12], IN[0].xxxx
>  8: MAD TEMP[4], CONST[13], IN[0].yyyy, TEMP[3]
>  9: MAD TEMP[5], CONST[14], IN[0].zzzz, TEMP[4]
> 10: ADD TEMP[6].z, TEMP[5], CONST[15]
> 11: ADD TEMP[7].x, TEMP[6].zzzz, -CONST[20].xxxx
> 12: MUL TEMP[8].x, TEMP[7].xxxx, CONST[21].xxxx
> 13: MOV OUT[3].z, TEMP[8].xxxx
> 14: END
>radeonsi: Compiling shader 9
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %15 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <4 x i32>, <4 x i32> addrspace(2)* %15, align 16, !invariant.load !0
>  %17 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %16, i32 %12, i32 0, i1 false, i1 false) #2
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = extractelement <4 x float> %17, i32 1
>  %20 = extractelement <4 x float> %17, i32 2
>  %21 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %22, i32 %13, i32 0, i1 false, i1 false) #2
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %27 = load <4 x i32>, <4 x i32> addrspace(2)* %26, align 16, !invariant.load !0
>  %28 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %27, i32 %14, i32 0, i1 false, i1 false) #2
>  %29 = extractelement <4 x float> %28, i32 0
>  %30 = extractelement <4 x float> %28, i32 1
>  %31 = extractelement <4 x float> %28, i32 2
>  %32 = extractelement <4 x float> %28, i32 3
>  %33 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 256)
>  %36 = fmul nsz float %35, %18
>  %37 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 260)
>  %38 = fmul nsz float %37, %18
>  %39 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 264)
>  %40 = fmul nsz float %39, %18
>  %41 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 268)
>  %42 = fmul nsz float %41, %18
>  %43 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 272)
>  %44 = fmul nsz float %43, %19
>  %45 = fadd nsz float %44, %36
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 276)
>  %47 = fmul nsz float %46, %19
>  %48 = fadd nsz float %47, %38
>  %49 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 280)
>  %50 = fmul nsz float %49, %19
>  %51 = fadd nsz float %50, %40
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 284)
>  %53 = fmul nsz float %52, %19
>  %54 = fadd nsz float %53, %42
>  %55 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 288)
>  %56 = fmul nsz float %55, %20
>  %57 = fadd nsz float %56, %45
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 292)
>  %59 = fmul nsz float %58, %20
>  %60 = fadd nsz float %59, %48
>  %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 296)
>  %62 = fmul nsz float %61, %20
>  %63 = fadd nsz float %62, %51
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 300)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %54
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 304)
>  %68 = fadd nsz float %57, %67
>  %69 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 308)
>  %70 = fadd nsz float %60, %69
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 312)
>  %72 = fadd nsz float %63, %71
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 316)
>  %74 = fadd nsz float %66, %73
>  %75 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 200)
>  %76 = fmul nsz float %75, %18
>  %77 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 216)
>  %78 = fmul nsz float %77, %19
>  %79 = fadd nsz float %78, %76
>  %80 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 232)
>  %81 = fmul nsz float %80, %20
>  %82 = fadd nsz float %81, %79
>  %83 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 248)
>  %84 = fadd nsz float %82, %83
>  %85 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 320)
>  %86 = fsub nsz float %84, %85
>  %87 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 336)
>  %88 = fmul nsz float %86, %87
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %29, float %30, float %31, float %32, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %24, float %25, float %88, float undef, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %68, float %70, float %72, float %74, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #3
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #3
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1].xyz, GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL CONST[1]
>DCL TEMP[0..4], LOCAL
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[1], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[2], IN[0], TEMP[1]
>  3: MOV_SAT TEMP[3].x, IN[1].zzzz
>  4: LRP TEMP[4].xyz, TEMP[3].xxxx, CONST[1].xyzz, TEMP[2].xyzz
>  5: MOV TEMP[4].w, TEMP[2].wwww
>  6: MOV OUT[0], TEMP[4]
>  7: END
>radeonsi: Compiling shader 10
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %6 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 1, i32 %4) #3
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 1, i32 %4) #3
>  %26 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 1, i32 %4) #3
>  %27 = call nsz float @llvm.amdgcn.interp.p2(float %26, float %23, i32 1, i32 1, i32 %4) #3
>  %28 = getelementptr [80 x <8 x i32>], [80 x <8 x i32>] addrspace(2)* %2, i64 0, i64 16, !amdgpu.uniform !0
>  %29 = load <8 x i32>, <8 x i32> addrspace(2)* %28, align 32, !invariant.load !0
>  %30 = bitcast [80 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %31 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %30, i64 0, i64 35, !amdgpu.uniform !0
>  %32 = load <4 x i32>, <4 x i32> addrspace(2)* %31, align 16, !invariant.load !0
>  %33 = bitcast float %25 to i32
>  %34 = bitcast float %27 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = bitcast <2 x i32> %36 to <2 x float>
>  %38 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %37, <8 x i32> %29, <4 x i32> %32, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3
>  %39 = extractelement <4 x float> %38, i32 0
>  %40 = extractelement <4 x float> %38, i32 1
>  %41 = extractelement <4 x float> %38, i32 2
>  %42 = extractelement <4 x float> %38, i32 3
>  %43 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #3
>  %44 = call nsz float @llvm.amdgcn.interp.p2(float %43, float %23, i32 0, i32 0, i32 %4) #3
>  %45 = fmul nsz float %44, %39
>  %46 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #3
>  %47 = call nsz float @llvm.amdgcn.interp.p2(float %46, float %23, i32 1, i32 0, i32 %4) #3
>  %48 = fmul nsz float %47, %40
>  %49 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 0, i32 %4) #3
>  %50 = call nsz float @llvm.amdgcn.interp.p2(float %49, float %23, i32 2, i32 0, i32 %4) #3
>  %51 = fmul nsz float %50, %41
>  %52 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 3, i32 0, i32 %4) #3
>  %53 = call nsz float @llvm.amdgcn.interp.p2(float %52, float %23, i32 3, i32 0, i32 %4) #3
>  %54 = fmul nsz float %53, %42
>  %55 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 1, i32 %4) #3
>  %56 = call nsz float @llvm.amdgcn.interp.p2(float %55, float %23, i32 2, i32 1, i32 %4) #3
>  %57 = call nsz float @llvm.maxnum.f32(float %56, float 0.000000e+00) #3
>  %58 = call nsz float @llvm.minnum.f32(float %57, float 1.000000e+00) #3
>  %59 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %60 = load <4 x i32>, <4 x i32> addrspace(2)* %59, align 16, !invariant.load !0
>  %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %60, i32 16)
>  %62 = fsub nsz float 1.000000e+00, %58
>  %63 = fmul nsz float %61, %58
>  %64 = fmul nsz float %45, %62
>  %65 = fadd nsz float %63, %64
>  %66 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %60, i32 20)
>  %67 = fmul nsz float %66, %58
>  %68 = fmul nsz float %48, %62
>  %69 = fadd nsz float %67, %68
>  %70 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %60, i32 24)
>  %71 = fmul nsz float %70, %58
>  %72 = fmul nsz float %51, %62
>  %73 = fadd nsz float %71, %72
>  %74 = bitcast float %3 to i32
>  %75 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %74, 6
>  %76 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %75, float %65, 7
>  %77 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %76, float %69, 8
>  %78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %77, float %73, 9
>  %79 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %78, float %54, 10
>  %80 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %79, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %80
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #3
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readonly }
>attributes #3 = { nounwind readnone }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1].xy, GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL CONST[1]
>DCL TEMP[0..4], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[1], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[2], IN[0], TEMP[1]
>  3: FSGE TEMP[3].x, CONST[1].xxxx, TEMP[2].wwww
>  4: AND TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx
>  5: KILL_IF -TEMP[4].xxxx
>  6: MOV OUT[0], TEMP[2]
>  7: END
>radeonsi: Compiling shader 11
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %6 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #3
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 0, i32 %4) #3
>  %26 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #3
>  %27 = call nsz float @llvm.amdgcn.interp.p2(float %26, float %23, i32 1, i32 0, i32 %4) #3
>  %28 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 0, i32 %4) #3
>  %29 = call nsz float @llvm.amdgcn.interp.p2(float %28, float %23, i32 2, i32 0, i32 %4) #3
>  %30 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 3, i32 0, i32 %4) #3
>  %31 = call nsz float @llvm.amdgcn.interp.p2(float %30, float %23, i32 3, i32 0, i32 %4) #3
>  %32 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 1, i32 %4) #3
>  %33 = call nsz float @llvm.amdgcn.interp.p2(float %32, float %23, i32 0, i32 1, i32 %4) #3
>  %34 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 1, i32 %4) #3
>  %35 = call nsz float @llvm.amdgcn.interp.p2(float %34, float %23, i32 1, i32 1, i32 %4) #3
>  %36 = getelementptr [80 x <8 x i32>], [80 x <8 x i32>] addrspace(2)* %2, i64 0, i64 16, !amdgpu.uniform !0
>  %37 = load <8 x i32>, <8 x i32> addrspace(2)* %36, align 32, !invariant.load !0
>  %38 = bitcast [80 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %39 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %38, i64 0, i64 35, !amdgpu.uniform !0
>  %40 = load <4 x i32>, <4 x i32> addrspace(2)* %39, align 16, !invariant.load !0
>  %41 = bitcast float %33 to i32
>  %42 = bitcast float %35 to i32
>  %43 = insertelement <2 x i32> undef, i32 %41, i32 0
>  %44 = insertelement <2 x i32> %43, i32 %42, i32 1
>  %45 = bitcast <2 x i32> %44 to <2 x float>
>  %46 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %45, <8 x i32> %37, <4 x i32> %40, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3
>  %47 = extractelement <4 x float> %46, i32 0
>  %48 = extractelement <4 x float> %46, i32 1
>  %49 = extractelement <4 x float> %46, i32 2
>  %50 = extractelement <4 x float> %46, i32 3
>  %51 = fmul nsz float %25, %47
>  %52 = fmul nsz float %27, %48
>  %53 = fmul nsz float %29, %49
>  %54 = fmul nsz float %31, %50
>  %55 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %56 = load <4 x i32>, <4 x i32> addrspace(2)* %55, align 16, !invariant.load !0
>  %57 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %56, i32 16)
>  %58 = fcmp nsz oge float %57, %54
>  %59 = select i1 %58, float -1.000000e+00, float 0.000000e+00
>  call void @llvm.AMDGPU.kill(float %59)
>  %60 = bitcast float %3 to i32
>  %61 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %60, 6
>  %62 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %61, float %51, 7
>  %63 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %62, float %52, 8
>  %64 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %63, float %53, 9
>  %65 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %64, float %54, 10
>  %66 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %65, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %66
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #3
>
>; Function Attrs: nounwind
>declare void @llvm.AMDGPU.kill(float) #4
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readonly }
>attributes #3 = { nounwind readnone }
>attributes #4 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1].xyz, GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL CONST[1..2]
>DCL TEMP[0..6], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[1], TEMP[0], SAMP[0], 2D
>  2: MUL TEMP[2], IN[0], TEMP[1]
>  3: FSGE TEMP[3].x, CONST[2].xxxx, TEMP[2].wwww
>  4: AND TEMP[4].x, TEMP[3].xxxx, IMM[0].xxxx
>  5: KILL_IF -TEMP[4].xxxx
>  6: MOV_SAT TEMP[5].x, IN[1].zzzz
>  7: LRP TEMP[6].xyz, TEMP[5].xxxx, CONST[1].xyzz, TEMP[2].xyzz
>  8: MOV TEMP[6].w, TEMP[2].wwww
>  9: MOV OUT[0], TEMP[6]
> 10: END
>radeonsi: Compiling shader 12
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %6 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #3
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 0, i32 %4) #3
>  %26 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #3
>  %27 = call nsz float @llvm.amdgcn.interp.p2(float %26, float %23, i32 1, i32 0, i32 %4) #3
>  %28 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 0, i32 %4) #3
>  %29 = call nsz float @llvm.amdgcn.interp.p2(float %28, float %23, i32 2, i32 0, i32 %4) #3
>  %30 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 3, i32 0, i32 %4) #3
>  %31 = call nsz float @llvm.amdgcn.interp.p2(float %30, float %23, i32 3, i32 0, i32 %4) #3
>  %32 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 1, i32 %4) #3
>  %33 = call nsz float @llvm.amdgcn.interp.p2(float %32, float %23, i32 0, i32 1, i32 %4) #3
>  %34 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 1, i32 %4) #3
>  %35 = call nsz float @llvm.amdgcn.interp.p2(float %34, float %23, i32 1, i32 1, i32 %4) #3
>  %36 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 1, i32 %4) #3
>  %37 = call nsz float @llvm.amdgcn.interp.p2(float %36, float %23, i32 2, i32 1, i32 %4) #3
>  %38 = getelementptr [80 x <8 x i32>], [80 x <8 x i32>] addrspace(2)* %2, i64 0, i64 16, !amdgpu.uniform !0
>  %39 = load <8 x i32>, <8 x i32> addrspace(2)* %38, align 32, !invariant.load !0
>  %40 = bitcast [80 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %41 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %40, i64 0, i64 35, !amdgpu.uniform !0
>  %42 = load <4 x i32>, <4 x i32> addrspace(2)* %41, align 16, !invariant.load !0
>  %43 = bitcast float %33 to i32
>  %44 = bitcast float %35 to i32
>  %45 = insertelement <2 x i32> undef, i32 %43, i32 0
>  %46 = insertelement <2 x i32> %45, i32 %44, i32 1
>  %47 = bitcast <2 x i32> %46 to <2 x float>
>  %48 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %47, <8 x i32> %39, <4 x i32> %42, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3
>  %49 = extractelement <4 x float> %48, i32 0
>  %50 = extractelement <4 x float> %48, i32 1
>  %51 = extractelement <4 x float> %48, i32 2
>  %52 = extractelement <4 x float> %48, i32 3
>  %53 = fmul nsz float %25, %49
>  %54 = fmul nsz float %27, %50
>  %55 = fmul nsz float %29, %51
>  %56 = fmul nsz float %31, %52
>  %57 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %58 = load <4 x i32>, <4 x i32> addrspace(2)* %57, align 16, !invariant.load !0
>  %59 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %58, i32 32)
>  %60 = fcmp nsz oge float %59, %56
>  %61 = select i1 %60, float -1.000000e+00, float 0.000000e+00
>  call void @llvm.AMDGPU.kill(float %61)
>  %62 = call nsz float @llvm.maxnum.f32(float %37, float 0.000000e+00) #3
>  %63 = call nsz float @llvm.minnum.f32(float %62, float 1.000000e+00) #3
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %58, i32 16)
>  %65 = fsub nsz float 1.000000e+00, %63
>  %66 = fmul nsz float %64, %63
>  %67 = fmul nsz float %53, %65
>  %68 = fadd nsz float %66, %67
>  %69 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %58, i32 20)
>  %70 = fmul nsz float %69, %63
>  %71 = fmul nsz float %54, %65
>  %72 = fadd nsz float %70, %71
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %58, i32 24)
>  %74 = fmul nsz float %73, %63
>  %75 = fmul nsz float %55, %65
>  %76 = fadd nsz float %74, %75
>  %77 = bitcast float %3 to i32
>  %78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %77, 6
>  %79 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %78, float %68, 7
>  %80 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %79, float %72, 8
>  %81 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %80, float %76, 9
>  %82 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %81, float %56, 10
>  %83 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %82, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %83
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #3
>
>; Function Attrs: nounwind
>declare void @llvm.AMDGPU.kill(float) #4
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readonly }
>attributes #3 = { nounwind readnone }
>attributes #4 = { nounwind }
>
>!0 = !{}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xy, GENERIC[1]
>DCL CONST[0..24]
>DCL TEMP[0..28], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 0, 0}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1].x, IMM[0].xxxx
>  5: MUL TEMP[3], CONST[8], IN[1].xxxx
>  6: MAD TEMP[4], CONST[9], IN[1].yyyy, TEMP[3]
>  7: MAD TEMP[5].xyz, CONST[10], IN[1].zzzz, TEMP[4]
>  8: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
>  9: RSQ TEMP[7].x, TEMP[6].xxxx
> 10: MUL TEMP[8].xyz, TEMP[5].xyzz, TEMP[7].xxxx
> 11: MOV TEMP[9].xyz, -TEMP[8].xyzx
> 12: DP3 TEMP[10].x, TEMP[9].xyzz, CONST[21].xyzz
> 13: MAX TEMP[11].x, IMM[0].yyyy, TEMP[10].xxxx
> 14: MUL TEMP[12], TEMP[11].xxxx, CONST[22]
> 15: MUL TEMP[13], CONST[8], IN[0].xxxx
> 16: MAD TEMP[14], CONST[9], IN[0].yyyy, TEMP[13]
> 17: MAD TEMP[15], CONST[10], IN[0].zzzz, TEMP[14]
> 18: ADD TEMP[16].xyz, TEMP[15], CONST[11]
> 19: ADD TEMP[17].xyz, TEMP[16].xyzz, -CONST[23].xyzz
> 20: DP3 TEMP[18].x, TEMP[17].xyzz, TEMP[17].xyzz
> 21: SQRT TEMP[19].x, TEMP[18].xxxx
> 22: RCP TEMP[20].x, TEMP[19].xxxx
> 23: MUL TEMP[21].xyz, TEMP[17].xyzz, TEMP[20].xxxx
> 24: FSLT TEMP[22].x, TEMP[19].xxxx, CONST[23].wwww
> 25: UCMP TEMP[23].x, TEMP[22].xxxx, IMM[0].xxxx, TEMP[23].xxxx
> 26: NOT TEMP[24].x, TEMP[22].xxxx
> 27: UCMP TEMP[23].x, TEMP[24].xxxx, IMM[0].yyyy, TEMP[23].xxxx
> 28: DP3 TEMP[25].x, TEMP[9].xyzz, TEMP[21].xyzz
> 29: MAX TEMP[26].x, IMM[0].yyyy, TEMP[25].xxxx
> 30: MUL TEMP[27].x, TEMP[26].xxxx, TEMP[23].xxxx
> 31: MAD TEMP[12], TEMP[27].xxxx, CONST[24], TEMP[12]
> 32: MUL TEMP[12], TEMP[12], IN[3]
> 33: ADD TEMP[12], TEMP[12], CONST[20]
> 34: MIN TEMP[28], IMM[0].xxxx, TEMP[12]
> 35: MOV OUT[2], TEMP[28]
> 36: MOV OUT[3].xy, IN[2].xyxx
> 37: END
>radeonsi: Compiling shader 13
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %45 = fmul nsz float %44, %19
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %47 = fmul nsz float %46, %19
>  %48 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %49 = fmul nsz float %48, %19
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %51 = fmul nsz float %50, %20
>  %52 = fadd nsz float %51, %43
>  %53 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %54 = fmul nsz float %53, %20
>  %55 = fadd nsz float %54, %45
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %57 = fmul nsz float %56, %20
>  %58 = fadd nsz float %57, %47
>  %59 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %60 = fmul nsz float %59, %20
>  %61 = fadd nsz float %60, %49
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %63 = fmul nsz float %62, %21
>  %64 = fadd nsz float %63, %52
>  %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %66 = fmul nsz float %65, %21
>  %67 = fadd nsz float %66, %55
>  %68 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %69 = fmul nsz float %68, %21
>  %70 = fadd nsz float %69, %58
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %72 = fmul nsz float %71, %21
>  %73 = fadd nsz float %72, %61
>  %74 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %75 = fadd nsz float %64, %74
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %77 = fadd nsz float %67, %76
>  %78 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %79 = fadd nsz float %70, %78
>  %80 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %81 = fadd nsz float %73, %80
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %83 = fmul nsz float %82, %25
>  %84 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %85 = fmul nsz float %84, %25
>  %86 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %87 = fmul nsz float %86, %25
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %89 = fmul nsz float %88, %26
>  %90 = fadd nsz float %89, %83
>  %91 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %92 = fmul nsz float %91, %26
>  %93 = fadd nsz float %92, %85
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %95 = fmul nsz float %94, %26
>  %96 = fadd nsz float %95, %87
>  %97 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %98 = fmul nsz float %97, %27
>  %99 = fadd nsz float %98, %90
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %101 = fmul nsz float %100, %27
>  %102 = fadd nsz float %101, %93
>  %103 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %104 = fmul nsz float %103, %27
>  %105 = fadd nsz float %104, %96
>  %106 = fmul nsz float %99, %99
>  %107 = fmul nsz float %102, %102
>  %108 = fadd nsz float %107, %106
>  %109 = fmul nsz float %105, %105
>  %110 = fadd nsz float %108, %109
>  %111 = call nsz float @llvm.sqrt.f32(float %110) #2
>  %112 = fdiv nsz float 1.000000e+00, %111, !fpmath !1
>  %113 = fmul nsz float %99, %112
>  %114 = fmul nsz float %102, %112
>  %115 = fmul nsz float %105, %112
>  %116 = fsub nsz float -0.000000e+00, %113
>  %117 = fsub nsz float -0.000000e+00, %114
>  %118 = fsub nsz float -0.000000e+00, %115
>  %119 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %120 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 340)
>  %121 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 344)
>  %122 = fmul nsz float %119, %116
>  %123 = fmul nsz float %120, %117
>  %124 = fadd nsz float %123, %122
>  %125 = fmul nsz float %121, %118
>  %126 = fadd nsz float %124, %125
>  %127 = call nsz float @llvm.maxnum.f32(float %126, float 0.000000e+00) #2
>  %128 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %129 = fmul nsz float %127, %128
>  %130 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %131 = fmul nsz float %127, %130
>  %132 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %133 = fmul nsz float %127, %132
>  %134 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 364)
>  %135 = fmul nsz float %127, %134
>  %136 = fmul nsz float %82, %19
>  %137 = fmul nsz float %84, %19
>  %138 = fmul nsz float %86, %19
>  %139 = fmul nsz float %88, %20
>  %140 = fadd nsz float %139, %136
>  %141 = fmul nsz float %91, %20
>  %142 = fadd nsz float %141, %137
>  %143 = fmul nsz float %94, %20
>  %144 = fadd nsz float %143, %138
>  %145 = fmul nsz float %97, %21
>  %146 = fadd nsz float %145, %140
>  %147 = fmul nsz float %100, %21
>  %148 = fadd nsz float %147, %142
>  %149 = fmul nsz float %103, %21
>  %150 = fadd nsz float %149, %144
>  %151 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %152 = fadd nsz float %146, %151
>  %153 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %154 = fadd nsz float %148, %153
>  %155 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %156 = fadd nsz float %150, %155
>  %157 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %158 = fsub nsz float %152, %157
>  %159 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %160 = fsub nsz float %154, %159
>  %161 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %162 = fsub nsz float %156, %161
>  %163 = fmul nsz float %158, %158
>  %164 = fmul nsz float %160, %160
>  %165 = fadd nsz float %164, %163
>  %166 = fmul nsz float %162, %162
>  %167 = fadd nsz float %165, %166
>  %168 = call nsz float @llvm.sqrt.f32(float %167) #2
>  %169 = fdiv nsz float 1.000000e+00, %168, !fpmath !1
>  %170 = fmul nsz float %158, %169
>  %171 = fmul nsz float %160, %169
>  %172 = fmul nsz float %162, %169
>  %173 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 380)
>  %174 = fcmp nsz uge float %168, %173
>  %175 = select i1 %174, float 0.000000e+00, float 1.000000e+00
>  %176 = fmul nsz float %170, %116
>  %177 = fmul nsz float %171, %117
>  %178 = fadd nsz float %177, %176
>  %179 = fmul nsz float %172, %118
>  %180 = fadd nsz float %178, %179
>  %181 = call nsz float @llvm.maxnum.f32(float %180, float 0.000000e+00) #2
>  %182 = fmul nsz float %181, %175
>  %183 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %184 = fmul nsz float %182, %183
>  %185 = fadd nsz float %184, %129
>  %186 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %187 = fmul nsz float %182, %186
>  %188 = fadd nsz float %187, %131
>  %189 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %190 = fmul nsz float %182, %189
>  %191 = fadd nsz float %190, %133
>  %192 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 396)
>  %193 = fmul nsz float %182, %192
>  %194 = fadd nsz float %193, %135
>  %195 = fmul nsz float %185, %36
>  %196 = fmul nsz float %188, %37
>  %197 = fmul nsz float %191, %38
>  %198 = fmul nsz float %194, %39
>  %199 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %200 = fadd nsz float %195, %199
>  %201 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 324)
>  %202 = fadd nsz float %196, %201
>  %203 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 328)
>  %204 = fadd nsz float %197, %203
>  %205 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 332)
>  %206 = fadd nsz float %198, %205
>  %207 = call nsz float @llvm.minnum.f32(float %200, float 1.000000e+00) #2
>  %208 = call nsz float @llvm.minnum.f32(float %202, float 1.000000e+00) #2
>  %209 = call nsz float @llvm.minnum.f32(float %204, float 1.000000e+00) #2
>  %210 = call nsz float @llvm.minnum.f32(float %206, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %207, float %208, float %209, float %210, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float undef, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %75, float %77, float %79, float %81, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xyz, GENERIC[1]
>DCL CONST[0..26]
>DCL TEMP[0..34], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 0, 0}
>  0: MUL TEMP[0], CONST[12], IN[0].xxxx
>  1: MAD TEMP[1], CONST[13], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[14], IN[0].zzzz, TEMP[1]
>  3: ADD TEMP[3].z, TEMP[2], CONST[15]
>  4: ADD TEMP[4].x, TEMP[3].zzzz, -CONST[20].xxxx
>  5: MUL TEMP[5].x, TEMP[4].xxxx, CONST[21].xxxx
>  6: MUL TEMP[6], CONST[16], IN[0].xxxx
>  7: MAD TEMP[7], CONST[17], IN[0].yyyy, TEMP[6]
>  8: MAD TEMP[8], CONST[18], IN[0].zzzz, TEMP[7]
>  9: ADD OUT[0], TEMP[8], CONST[19]
> 10: MOV OUT[1].x, IMM[0].xxxx
> 11: MUL TEMP[9], CONST[8], IN[1].xxxx
> 12: MAD TEMP[10], CONST[9], IN[1].yyyy, TEMP[9]
> 13: MAD TEMP[11].xyz, CONST[10], IN[1].zzzz, TEMP[10]
> 14: DP3 TEMP[12].x, TEMP[11].xyzz, TEMP[11].xyzz
> 15: RSQ TEMP[13].x, TEMP[12].xxxx
> 16: MUL TEMP[14].xyz, TEMP[11].xyzz, TEMP[13].xxxx
> 17: MOV TEMP[15].xyz, -TEMP[14].xyzx
> 18: DP3 TEMP[16].x, TEMP[15].xyzz, CONST[23].xyzz
> 19: MAX TEMP[17].x, IMM[0].yyyy, TEMP[16].xxxx
> 20: MUL TEMP[18], TEMP[17].xxxx, CONST[24]
> 21: MUL TEMP[19], CONST[8], IN[0].xxxx
> 22: MAD TEMP[20], CONST[9], IN[0].yyyy, TEMP[19]
> 23: MAD TEMP[21], CONST[10], IN[0].zzzz, TEMP[20]
> 24: ADD TEMP[22].xyz, TEMP[21], CONST[11]
> 25: ADD TEMP[23].xyz, TEMP[22].xyzz, -CONST[25].xyzz
> 26: DP3 TEMP[24].x, TEMP[23].xyzz, TEMP[23].xyzz
> 27: SQRT TEMP[25].x, TEMP[24].xxxx
> 28: RCP TEMP[26].x, TEMP[25].xxxx
> 29: MUL TEMP[27].xyz, TEMP[23].xyzz, TEMP[26].xxxx
> 30: FSLT TEMP[28].x, TEMP[25].xxxx, CONST[25].wwww
> 31: UCMP TEMP[29].x, TEMP[28].xxxx, IMM[0].xxxx, TEMP[29].xxxx
> 32: NOT TEMP[30].x, TEMP[28].xxxx
> 33: UCMP TEMP[29].x, TEMP[30].xxxx, IMM[0].yyyy, TEMP[29].xxxx
> 34: DP3 TEMP[31].x, TEMP[15].xyzz, TEMP[27].xyzz
> 35: MAX TEMP[32].x, IMM[0].yyyy, TEMP[31].xxxx
> 36: MUL TEMP[33].x, TEMP[32].xxxx, TEMP[29].xxxx
> 37: MAD TEMP[18], TEMP[33].xxxx, CONST[26], TEMP[18]
> 38: MUL TEMP[18], TEMP[18], IN[3]
> 39: ADD TEMP[18], TEMP[18], CONST[22]
> 40: MIN TEMP[34], IMM[0].xxxx, TEMP[18]
> 41: MOV OUT[2], TEMP[34]
> 42: MOV OUT[3].xy, IN[2].xyxx
> 43: MOV OUT[3].z, TEMP[5].xxxx
> 44: END
>radeonsi: Compiling shader 14
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 200)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 216)
>  %45 = fmul nsz float %44, %20
>  %46 = fadd nsz float %45, %43
>  %47 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 232)
>  %48 = fmul nsz float %47, %21
>  %49 = fadd nsz float %48, %46
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 248)
>  %51 = fadd nsz float %49, %50
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %53 = fsub nsz float %51, %52
>  %54 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %55 = fmul nsz float %53, %54
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %57 = fmul nsz float %56, %19
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %59 = fmul nsz float %58, %19
>  %60 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %61 = fmul nsz float %60, %19
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %63 = fmul nsz float %62, %19
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %57
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %68 = fmul nsz float %67, %20
>  %69 = fadd nsz float %68, %59
>  %70 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %71 = fmul nsz float %70, %20
>  %72 = fadd nsz float %71, %61
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %74 = fmul nsz float %73, %20
>  %75 = fadd nsz float %74, %63
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %77 = fmul nsz float %76, %21
>  %78 = fadd nsz float %77, %66
>  %79 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %80 = fmul nsz float %79, %21
>  %81 = fadd nsz float %80, %69
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %83 = fmul nsz float %82, %21
>  %84 = fadd nsz float %83, %72
>  %85 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %86 = fmul nsz float %85, %21
>  %87 = fadd nsz float %86, %75
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %89 = fadd nsz float %78, %88
>  %90 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %91 = fadd nsz float %81, %90
>  %92 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %93 = fadd nsz float %84, %92
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %95 = fadd nsz float %87, %94
>  %96 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %97 = fmul nsz float %96, %25
>  %98 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %99 = fmul nsz float %98, %25
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %101 = fmul nsz float %100, %25
>  %102 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %103 = fmul nsz float %102, %26
>  %104 = fadd nsz float %103, %97
>  %105 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %106 = fmul nsz float %105, %26
>  %107 = fadd nsz float %106, %99
>  %108 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %109 = fmul nsz float %108, %26
>  %110 = fadd nsz float %109, %101
>  %111 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %112 = fmul nsz float %111, %27
>  %113 = fadd nsz float %112, %104
>  %114 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %115 = fmul nsz float %114, %27
>  %116 = fadd nsz float %115, %107
>  %117 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %118 = fmul nsz float %117, %27
>  %119 = fadd nsz float %118, %110
>  %120 = fmul nsz float %113, %113
>  %121 = fmul nsz float %116, %116
>  %122 = fadd nsz float %121, %120
>  %123 = fmul nsz float %119, %119
>  %124 = fadd nsz float %122, %123
>  %125 = call nsz float @llvm.sqrt.f32(float %124) #2
>  %126 = fdiv nsz float 1.000000e+00, %125, !fpmath !1
>  %127 = fmul nsz float %113, %126
>  %128 = fmul nsz float %116, %126
>  %129 = fmul nsz float %119, %126
>  %130 = fsub nsz float -0.000000e+00, %127
>  %131 = fsub nsz float -0.000000e+00, %128
>  %132 = fsub nsz float -0.000000e+00, %129
>  %133 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %134 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %135 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %136 = fmul nsz float %133, %130
>  %137 = fmul nsz float %134, %131
>  %138 = fadd nsz float %137, %136
>  %139 = fmul nsz float %135, %132
>  %140 = fadd nsz float %138, %139
>  %141 = call nsz float @llvm.maxnum.f32(float %140, float 0.000000e+00) #2
>  %142 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %143 = fmul nsz float %141, %142
>  %144 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %145 = fmul nsz float %141, %144
>  %146 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %147 = fmul nsz float %141, %146
>  %148 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 396)
>  %149 = fmul nsz float %141, %148
>  %150 = fmul nsz float %96, %19
>  %151 = fmul nsz float %98, %19
>  %152 = fmul nsz float %100, %19
>  %153 = fmul nsz float %102, %20
>  %154 = fadd nsz float %153, %150
>  %155 = fmul nsz float %105, %20
>  %156 = fadd nsz float %155, %151
>  %157 = fmul nsz float %108, %20
>  %158 = fadd nsz float %157, %152
>  %159 = fmul nsz float %111, %21
>  %160 = fadd nsz float %159, %154
>  %161 = fmul nsz float %114, %21
>  %162 = fadd nsz float %161, %156
>  %163 = fmul nsz float %117, %21
>  %164 = fadd nsz float %163, %158
>  %165 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %166 = fadd nsz float %160, %165
>  %167 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %168 = fadd nsz float %162, %167
>  %169 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %170 = fadd nsz float %164, %169
>  %171 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 400)
>  %172 = fsub nsz float %166, %171
>  %173 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 404)
>  %174 = fsub nsz float %168, %173
>  %175 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 408)
>  %176 = fsub nsz float %170, %175
>  %177 = fmul nsz float %172, %172
>  %178 = fmul nsz float %174, %174
>  %179 = fadd nsz float %178, %177
>  %180 = fmul nsz float %176, %176
>  %181 = fadd nsz float %179, %180
>  %182 = call nsz float @llvm.sqrt.f32(float %181) #2
>  %183 = fdiv nsz float 1.000000e+00, %182, !fpmath !1
>  %184 = fmul nsz float %172, %183
>  %185 = fmul nsz float %174, %183
>  %186 = fmul nsz float %176, %183
>  %187 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 412)
>  %188 = fcmp nsz uge float %182, %187
>  %189 = select i1 %188, float 0.000000e+00, float 1.000000e+00
>  %190 = fmul nsz float %184, %130
>  %191 = fmul nsz float %185, %131
>  %192 = fadd nsz float %191, %190
>  %193 = fmul nsz float %186, %132
>  %194 = fadd nsz float %192, %193
>  %195 = call nsz float @llvm.maxnum.f32(float %194, float 0.000000e+00) #2
>  %196 = fmul nsz float %195, %189
>  %197 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 416)
>  %198 = fmul nsz float %196, %197
>  %199 = fadd nsz float %198, %143
>  %200 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 420)
>  %201 = fmul nsz float %196, %200
>  %202 = fadd nsz float %201, %145
>  %203 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 424)
>  %204 = fmul nsz float %196, %203
>  %205 = fadd nsz float %204, %147
>  %206 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 428)
>  %207 = fmul nsz float %196, %206
>  %208 = fadd nsz float %207, %149
>  %209 = fmul nsz float %199, %36
>  %210 = fmul nsz float %202, %37
>  %211 = fmul nsz float %205, %38
>  %212 = fmul nsz float %208, %39
>  %213 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %214 = fadd nsz float %209, %213
>  %215 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %216 = fadd nsz float %210, %215
>  %217 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %218 = fadd nsz float %211, %217
>  %219 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 364)
>  %220 = fadd nsz float %212, %219
>  %221 = call nsz float @llvm.minnum.f32(float %214, float 1.000000e+00) #2
>  %222 = call nsz float @llvm.minnum.f32(float %216, float 1.000000e+00) #2
>  %223 = call nsz float @llvm.minnum.f32(float %218, float 1.000000e+00) #2
>  %224 = call nsz float @llvm.minnum.f32(float %220, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %221, float %222, float %223, float %224, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float %55, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %89, float %91, float %93, float %95, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xy, GENERIC[1]
>DCL CONST[0..28]
>DCL TEMP[0..41], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 2, 0}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1].x, IMM[0].xxxx
>  5: MUL TEMP[3], CONST[8], IN[1].xxxx
>  6: MAD TEMP[4], CONST[9], IN[1].yyyy, TEMP[3]
>  7: MAD TEMP[5].xyz, CONST[10], IN[1].zzzz, TEMP[4]
>  8: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
>  9: RSQ TEMP[7].x, TEMP[6].xxxx
> 10: MUL TEMP[8].xyz, TEMP[5].xyzz, TEMP[7].xxxx
> 11: MOV TEMP[9].xyz, -TEMP[8].xyzx
> 12: MUL TEMP[10], CONST[8], IN[0].xxxx
> 13: MAD TEMP[11], CONST[9], IN[0].yyyy, TEMP[10]
> 14: MAD TEMP[12], CONST[10], IN[0].zzzz, TEMP[11]
> 15: ADD TEMP[13].xyz, TEMP[12], CONST[11]
> 16: DP3 TEMP[14].x, TEMP[9].xyzz, CONST[21].xyzz
> 17: MAX TEMP[15].x, IMM[0].yyyy, TEMP[14].xxxx
> 18: MUL TEMP[16], TEMP[15].xxxx, CONST[23]
> 19: DP3 TEMP[17].x, TEMP[9].xyzz, CONST[22].xyzz
> 20: MAX TEMP[18].x, IMM[0].yyyy, TEMP[17].xxxx
> 21: MAD TEMP[16], TEMP[18].xxxx, CONST[24], TEMP[16]
> 22: ADD TEMP[19].xyz, TEMP[13].xyzz, -CONST[25].xyzz
> 23: DP3 TEMP[20].x, TEMP[19].xyzz, TEMP[19].xyzz
> 24: SQRT TEMP[21].x, TEMP[20].xxxx
> 25: RCP TEMP[22].x, TEMP[21].xxxx
> 26: MUL TEMP[23].xyz, TEMP[19].xyzz, TEMP[22].xxxx
> 27: FSLT TEMP[24].x, TEMP[21].xxxx, CONST[25].wwww
> 28: UCMP TEMP[25].x, TEMP[24].xxxx, IMM[0].xxxx, TEMP[25].xxxx
> 29: NOT TEMP[26].x, TEMP[24].xxxx
> 30: UCMP TEMP[25].x, TEMP[26].xxxx, IMM[0].yyyy, TEMP[25].xxxx
> 31: DP3 TEMP[27].x, TEMP[9].xyzz, TEMP[23].xyzz
> 32: MAX TEMP[28].x, IMM[0].yyyy, TEMP[27].xxxx
> 33: MUL TEMP[29].x, TEMP[28].xxxx, TEMP[25].xxxx
> 34: MAD TEMP[16], TEMP[29].xxxx, CONST[27], TEMP[16]
> 35: ADD TEMP[30].xyz, TEMP[13].xyzz, -CONST[26].xyzz
> 36: DP3 TEMP[31].x, TEMP[30].xyzz, TEMP[30].xyzz
> 37: SQRT TEMP[32].x, TEMP[31].xxxx
> 38: RCP TEMP[33].x, TEMP[32].xxxx
> 39: MUL TEMP[34].xyz, TEMP[30].xyzz, TEMP[33].xxxx
> 40: FSLT TEMP[35].x, TEMP[32].xxxx, CONST[26].wwww
> 41: UCMP TEMP[36].x, TEMP[35].xxxx, IMM[0].xxxx, TEMP[36].xxxx
> 42: NOT TEMP[37].x, TEMP[35].xxxx
> 43: UCMP TEMP[36].x, TEMP[37].xxxx, IMM[0].yyyy, TEMP[36].xxxx
> 44: DP3 TEMP[38].x, TEMP[9].xyzz, TEMP[34].xyzz
> 45: MAX TEMP[39].x, IMM[0].yyyy, TEMP[38].xxxx
> 46: MUL TEMP[40].x, TEMP[39].xxxx, TEMP[36].xxxx
> 47: MAD TEMP[16], TEMP[40].xxxx, CONST[28], TEMP[16]
> 48: MUL TEMP[16], TEMP[16], IN[3]
> 49: ADD TEMP[16], TEMP[16], CONST[20]
> 50: MIN TEMP[41], IMM[0].xxxx, TEMP[16]
> 51: MOV OUT[2], TEMP[41]
> 52: MOV OUT[3].xy, IN[2].xyxx
> 53: END
>radeonsi: Compiling shader 15
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %45 = fmul nsz float %44, %19
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %47 = fmul nsz float %46, %19
>  %48 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %49 = fmul nsz float %48, %19
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %51 = fmul nsz float %50, %20
>  %52 = fadd nsz float %51, %43
>  %53 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %54 = fmul nsz float %53, %20
>  %55 = fadd nsz float %54, %45
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %57 = fmul nsz float %56, %20
>  %58 = fadd nsz float %57, %47
>  %59 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %60 = fmul nsz float %59, %20
>  %61 = fadd nsz float %60, %49
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %63 = fmul nsz float %62, %21
>  %64 = fadd nsz float %63, %52
>  %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %66 = fmul nsz float %65, %21
>  %67 = fadd nsz float %66, %55
>  %68 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %69 = fmul nsz float %68, %21
>  %70 = fadd nsz float %69, %58
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %72 = fmul nsz float %71, %21
>  %73 = fadd nsz float %72, %61
>  %74 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %75 = fadd nsz float %64, %74
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %77 = fadd nsz float %67, %76
>  %78 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %79 = fadd nsz float %70, %78
>  %80 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %81 = fadd nsz float %73, %80
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %83 = fmul nsz float %82, %25
>  %84 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %85 = fmul nsz float %84, %25
>  %86 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %87 = fmul nsz float %86, %25
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %89 = fmul nsz float %88, %26
>  %90 = fadd nsz float %89, %83
>  %91 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %92 = fmul nsz float %91, %26
>  %93 = fadd nsz float %92, %85
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %95 = fmul nsz float %94, %26
>  %96 = fadd nsz float %95, %87
>  %97 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %98 = fmul nsz float %97, %27
>  %99 = fadd nsz float %98, %90
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %101 = fmul nsz float %100, %27
>  %102 = fadd nsz float %101, %93
>  %103 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %104 = fmul nsz float %103, %27
>  %105 = fadd nsz float %104, %96
>  %106 = fmul nsz float %99, %99
>  %107 = fmul nsz float %102, %102
>  %108 = fadd nsz float %107, %106
>  %109 = fmul nsz float %105, %105
>  %110 = fadd nsz float %108, %109
>  %111 = call nsz float @llvm.sqrt.f32(float %110) #2
>  %112 = fdiv nsz float 1.000000e+00, %111, !fpmath !1
>  %113 = fmul nsz float %99, %112
>  %114 = fmul nsz float %102, %112
>  %115 = fmul nsz float %105, %112
>  %116 = fsub nsz float -0.000000e+00, %113
>  %117 = fsub nsz float -0.000000e+00, %114
>  %118 = fsub nsz float -0.000000e+00, %115
>  %119 = fmul nsz float %82, %19
>  %120 = fmul nsz float %84, %19
>  %121 = fmul nsz float %86, %19
>  %122 = fmul nsz float %88, %20
>  %123 = fadd nsz float %122, %119
>  %124 = fmul nsz float %91, %20
>  %125 = fadd nsz float %124, %120
>  %126 = fmul nsz float %94, %20
>  %127 = fadd nsz float %126, %121
>  %128 = fmul nsz float %97, %21
>  %129 = fadd nsz float %128, %123
>  %130 = fmul nsz float %100, %21
>  %131 = fadd nsz float %130, %125
>  %132 = fmul nsz float %103, %21
>  %133 = fadd nsz float %132, %127
>  %134 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %135 = fadd nsz float %129, %134
>  %136 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %137 = fadd nsz float %131, %136
>  %138 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %139 = fadd nsz float %133, %138
>  %140 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %141 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 340)
>  %142 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 344)
>  %143 = fmul nsz float %140, %116
>  %144 = fmul nsz float %141, %117
>  %145 = fadd nsz float %144, %143
>  %146 = fmul nsz float %142, %118
>  %147 = fadd nsz float %145, %146
>  %148 = call nsz float @llvm.maxnum.f32(float %147, float 0.000000e+00) #2
>  %149 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %150 = fmul nsz float %148, %149
>  %151 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %152 = fmul nsz float %148, %151
>  %153 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %154 = fmul nsz float %148, %153
>  %155 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 380)
>  %156 = fmul nsz float %148, %155
>  %157 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %158 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %159 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %160 = fmul nsz float %157, %116
>  %161 = fmul nsz float %158, %117
>  %162 = fadd nsz float %161, %160
>  %163 = fmul nsz float %159, %118
>  %164 = fadd nsz float %162, %163
>  %165 = call nsz float @llvm.maxnum.f32(float %164, float 0.000000e+00) #2
>  %166 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %167 = fmul nsz float %165, %166
>  %168 = fadd nsz float %167, %150
>  %169 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %170 = fmul nsz float %165, %169
>  %171 = fadd nsz float %170, %152
>  %172 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %173 = fmul nsz float %165, %172
>  %174 = fadd nsz float %173, %154
>  %175 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 396)
>  %176 = fmul nsz float %165, %175
>  %177 = fadd nsz float %176, %156
>  %178 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 400)
>  %179 = fsub nsz float %135, %178
>  %180 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 404)
>  %181 = fsub nsz float %137, %180
>  %182 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 408)
>  %183 = fsub nsz float %139, %182
>  %184 = fmul nsz float %179, %179
>  %185 = fmul nsz float %181, %181
>  %186 = fadd nsz float %185, %184
>  %187 = fmul nsz float %183, %183
>  %188 = fadd nsz float %186, %187
>  %189 = call nsz float @llvm.sqrt.f32(float %188) #2
>  %190 = fdiv nsz float 1.000000e+00, %189, !fpmath !1
>  %191 = fmul nsz float %179, %190
>  %192 = fmul nsz float %181, %190
>  %193 = fmul nsz float %183, %190
>  %194 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 412)
>  %195 = fcmp nsz uge float %189, %194
>  %196 = select i1 %195, float 0.000000e+00, float 1.000000e+00
>  %197 = fmul nsz float %191, %116
>  %198 = fmul nsz float %192, %117
>  %199 = fadd nsz float %198, %197
>  %200 = fmul nsz float %193, %118
>  %201 = fadd nsz float %199, %200
>  %202 = call nsz float @llvm.maxnum.f32(float %201, float 0.000000e+00) #2
>  %203 = fmul nsz float %202, %196
>  %204 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 432)
>  %205 = fmul nsz float %203, %204
>  %206 = fadd nsz float %205, %168
>  %207 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 436)
>  %208 = fmul nsz float %203, %207
>  %209 = fadd nsz float %208, %171
>  %210 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 440)
>  %211 = fmul nsz float %203, %210
>  %212 = fadd nsz float %211, %174
>  %213 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 444)
>  %214 = fmul nsz float %203, %213
>  %215 = fadd nsz float %214, %177
>  %216 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 416)
>  %217 = fsub nsz float %135, %216
>  %218 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 420)
>  %219 = fsub nsz float %137, %218
>  %220 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 424)
>  %221 = fsub nsz float %139, %220
>  %222 = fmul nsz float %217, %217
>  %223 = fmul nsz float %219, %219
>  %224 = fadd nsz float %223, %222
>  %225 = fmul nsz float %221, %221
>  %226 = fadd nsz float %224, %225
>  %227 = call nsz float @llvm.sqrt.f32(float %226) #2
>  %228 = fdiv nsz float 1.000000e+00, %227, !fpmath !1
>  %229 = fmul nsz float %217, %228
>  %230 = fmul nsz float %219, %228
>  %231 = fmul nsz float %221, %228
>  %232 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 428)
>  %233 = fcmp nsz uge float %227, %232
>  %234 = select i1 %233, float 0.000000e+00, float 1.000000e+00
>  %235 = fmul nsz float %229, %116
>  %236 = fmul nsz float %230, %117
>  %237 = fadd nsz float %236, %235
>  %238 = fmul nsz float %231, %118
>  %239 = fadd nsz float %237, %238
>  %240 = call nsz float @llvm.maxnum.f32(float %239, float 0.000000e+00) #2
>  %241 = fmul nsz float %240, %234
>  %242 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 448)
>  %243 = fmul nsz float %241, %242
>  %244 = fadd nsz float %243, %206
>  %245 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 452)
>  %246 = fmul nsz float %241, %245
>  %247 = fadd nsz float %246, %209
>  %248 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 456)
>  %249 = fmul nsz float %241, %248
>  %250 = fadd nsz float %249, %212
>  %251 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 460)
>  %252 = fmul nsz float %241, %251
>  %253 = fadd nsz float %252, %215
>  %254 = fmul nsz float %244, %36
>  %255 = fmul nsz float %247, %37
>  %256 = fmul nsz float %250, %38
>  %257 = fmul nsz float %253, %39
>  %258 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %259 = fadd nsz float %254, %258
>  %260 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 324)
>  %261 = fadd nsz float %255, %260
>  %262 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 328)
>  %263 = fadd nsz float %256, %262
>  %264 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 332)
>  %265 = fadd nsz float %257, %264
>  %266 = call nsz float @llvm.minnum.f32(float %259, float 1.000000e+00) #2
>  %267 = call nsz float @llvm.minnum.f32(float %261, float 1.000000e+00) #2
>  %268 = call nsz float @llvm.minnum.f32(float %263, float 1.000000e+00) #2
>  %269 = call nsz float @llvm.minnum.f32(float %265, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %266, float %267, float %268, float %269, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float undef, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %75, float %77, float %79, float %81, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xyz, GENERIC[1]
>DCL CONST[0..30]
>DCL TEMP[0..47], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 2, 0}
>  0: MUL TEMP[0], CONST[12], IN[0].xxxx
>  1: MAD TEMP[1], CONST[13], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[14], IN[0].zzzz, TEMP[1]
>  3: ADD TEMP[3].z, TEMP[2], CONST[15]
>  4: ADD TEMP[4].x, TEMP[3].zzzz, -CONST[20].xxxx
>  5: MUL TEMP[5].x, TEMP[4].xxxx, CONST[21].xxxx
>  6: MUL TEMP[6], CONST[16], IN[0].xxxx
>  7: MAD TEMP[7], CONST[17], IN[0].yyyy, TEMP[6]
>  8: MAD TEMP[8], CONST[18], IN[0].zzzz, TEMP[7]
>  9: ADD OUT[0], TEMP[8], CONST[19]
> 10: MOV OUT[1].x, IMM[0].xxxx
> 11: MUL TEMP[9], CONST[8], IN[1].xxxx
> 12: MAD TEMP[10], CONST[9], IN[1].yyyy, TEMP[9]
> 13: MAD TEMP[11].xyz, CONST[10], IN[1].zzzz, TEMP[10]
> 14: DP3 TEMP[12].x, TEMP[11].xyzz, TEMP[11].xyzz
> 15: RSQ TEMP[13].x, TEMP[12].xxxx
> 16: MUL TEMP[14].xyz, TEMP[11].xyzz, TEMP[13].xxxx
> 17: MOV TEMP[15].xyz, -TEMP[14].xyzx
> 18: MUL TEMP[16], CONST[8], IN[0].xxxx
> 19: MAD TEMP[17], CONST[9], IN[0].yyyy, TEMP[16]
> 20: MAD TEMP[18], CONST[10], IN[0].zzzz, TEMP[17]
> 21: ADD TEMP[19].xyz, TEMP[18], CONST[11]
> 22: DP3 TEMP[20].x, TEMP[15].xyzz, CONST[23].xyzz
> 23: MAX TEMP[21].x, IMM[0].yyyy, TEMP[20].xxxx
> 24: MUL TEMP[22], TEMP[21].xxxx, CONST[25]
> 25: DP3 TEMP[23].x, TEMP[15].xyzz, CONST[24].xyzz
> 26: MAX TEMP[24].x, IMM[0].yyyy, TEMP[23].xxxx
> 27: MAD TEMP[22], TEMP[24].xxxx, CONST[26], TEMP[22]
> 28: ADD TEMP[25].xyz, TEMP[19].xyzz, -CONST[27].xyzz
> 29: DP3 TEMP[26].x, TEMP[25].xyzz, TEMP[25].xyzz
> 30: SQRT TEMP[27].x, TEMP[26].xxxx
> 31: RCP TEMP[28].x, TEMP[27].xxxx
> 32: MUL TEMP[29].xyz, TEMP[25].xyzz, TEMP[28].xxxx
> 33: FSLT TEMP[30].x, TEMP[27].xxxx, CONST[27].wwww
> 34: UCMP TEMP[31].x, TEMP[30].xxxx, IMM[0].xxxx, TEMP[31].xxxx
> 35: NOT TEMP[32].x, TEMP[30].xxxx
> 36: UCMP TEMP[31].x, TEMP[32].xxxx, IMM[0].yyyy, TEMP[31].xxxx
> 37: DP3 TEMP[33].x, TEMP[15].xyzz, TEMP[29].xyzz
> 38: MAX TEMP[34].x, IMM[0].yyyy, TEMP[33].xxxx
> 39: MUL TEMP[35].x, TEMP[34].xxxx, TEMP[31].xxxx
> 40: MAD TEMP[22], TEMP[35].xxxx, CONST[29], TEMP[22]
> 41: ADD TEMP[36].xyz, TEMP[19].xyzz, -CONST[28].xyzz
> 42: DP3 TEMP[37].x, TEMP[36].xyzz, TEMP[36].xyzz
> 43: SQRT TEMP[38].x, TEMP[37].xxxx
> 44: RCP TEMP[39].x, TEMP[38].xxxx
> 45: MUL TEMP[40].xyz, TEMP[36].xyzz, TEMP[39].xxxx
> 46: FSLT TEMP[41].x, TEMP[38].xxxx, CONST[28].wwww
> 47: UCMP TEMP[42].x, TEMP[41].xxxx, IMM[0].xxxx, TEMP[42].xxxx
> 48: NOT TEMP[43].x, TEMP[41].xxxx
> 49: UCMP TEMP[42].x, TEMP[43].xxxx, IMM[0].yyyy, TEMP[42].xxxx
> 50: DP3 TEMP[44].x, TEMP[15].xyzz, TEMP[40].xyzz
> 51: MAX TEMP[45].x, IMM[0].yyyy, TEMP[44].xxxx
> 52: MUL TEMP[46].x, TEMP[45].xxxx, TEMP[42].xxxx
> 53: MAD TEMP[22], TEMP[46].xxxx, CONST[30], TEMP[22]
> 54: MUL TEMP[22], TEMP[22], IN[3]
> 55: ADD TEMP[22], TEMP[22], CONST[22]
> 56: MIN TEMP[47], IMM[0].xxxx, TEMP[22]
> 57: MOV OUT[2], TEMP[47]
> 58: MOV OUT[3].xy, IN[2].xyxx
> 59: MOV OUT[3].z, TEMP[5].xxxx
> 60: END
>radeonsi: Compiling shader 16
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 200)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 216)
>  %45 = fmul nsz float %44, %20
>  %46 = fadd nsz float %45, %43
>  %47 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 232)
>  %48 = fmul nsz float %47, %21
>  %49 = fadd nsz float %48, %46
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 248)
>  %51 = fadd nsz float %49, %50
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %53 = fsub nsz float %51, %52
>  %54 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %55 = fmul nsz float %53, %54
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %57 = fmul nsz float %56, %19
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %59 = fmul nsz float %58, %19
>  %60 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %61 = fmul nsz float %60, %19
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %63 = fmul nsz float %62, %19
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %57
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %68 = fmul nsz float %67, %20
>  %69 = fadd nsz float %68, %59
>  %70 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %71 = fmul nsz float %70, %20
>  %72 = fadd nsz float %71, %61
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %74 = fmul nsz float %73, %20
>  %75 = fadd nsz float %74, %63
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %77 = fmul nsz float %76, %21
>  %78 = fadd nsz float %77, %66
>  %79 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %80 = fmul nsz float %79, %21
>  %81 = fadd nsz float %80, %69
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %83 = fmul nsz float %82, %21
>  %84 = fadd nsz float %83, %72
>  %85 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %86 = fmul nsz float %85, %21
>  %87 = fadd nsz float %86, %75
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %89 = fadd nsz float %78, %88
>  %90 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %91 = fadd nsz float %81, %90
>  %92 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %93 = fadd nsz float %84, %92
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %95 = fadd nsz float %87, %94
>  %96 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %97 = fmul nsz float %96, %25
>  %98 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %99 = fmul nsz float %98, %25
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %101 = fmul nsz float %100, %25
>  %102 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %103 = fmul nsz float %102, %26
>  %104 = fadd nsz float %103, %97
>  %105 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %106 = fmul nsz float %105, %26
>  %107 = fadd nsz float %106, %99
>  %108 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %109 = fmul nsz float %108, %26
>  %110 = fadd nsz float %109, %101
>  %111 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %112 = fmul nsz float %111, %27
>  %113 = fadd nsz float %112, %104
>  %114 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %115 = fmul nsz float %114, %27
>  %116 = fadd nsz float %115, %107
>  %117 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %118 = fmul nsz float %117, %27
>  %119 = fadd nsz float %118, %110
>  %120 = fmul nsz float %113, %113
>  %121 = fmul nsz float %116, %116
>  %122 = fadd nsz float %121, %120
>  %123 = fmul nsz float %119, %119
>  %124 = fadd nsz float %122, %123
>  %125 = call nsz float @llvm.sqrt.f32(float %124) #2
>  %126 = fdiv nsz float 1.000000e+00, %125, !fpmath !1
>  %127 = fmul nsz float %113, %126
>  %128 = fmul nsz float %116, %126
>  %129 = fmul nsz float %119, %126
>  %130 = fsub nsz float -0.000000e+00, %127
>  %131 = fsub nsz float -0.000000e+00, %128
>  %132 = fsub nsz float -0.000000e+00, %129
>  %133 = fmul nsz float %96, %19
>  %134 = fmul nsz float %98, %19
>  %135 = fmul nsz float %100, %19
>  %136 = fmul nsz float %102, %20
>  %137 = fadd nsz float %136, %133
>  %138 = fmul nsz float %105, %20
>  %139 = fadd nsz float %138, %134
>  %140 = fmul nsz float %108, %20
>  %141 = fadd nsz float %140, %135
>  %142 = fmul nsz float %111, %21
>  %143 = fadd nsz float %142, %137
>  %144 = fmul nsz float %114, %21
>  %145 = fadd nsz float %144, %139
>  %146 = fmul nsz float %117, %21
>  %147 = fadd nsz float %146, %141
>  %148 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %149 = fadd nsz float %143, %148
>  %150 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %151 = fadd nsz float %145, %150
>  %152 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %153 = fadd nsz float %147, %152
>  %154 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %155 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %156 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %157 = fmul nsz float %154, %130
>  %158 = fmul nsz float %155, %131
>  %159 = fadd nsz float %158, %157
>  %160 = fmul nsz float %156, %132
>  %161 = fadd nsz float %159, %160
>  %162 = call nsz float @llvm.maxnum.f32(float %161, float 0.000000e+00) #2
>  %163 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 400)
>  %164 = fmul nsz float %162, %163
>  %165 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 404)
>  %166 = fmul nsz float %162, %165
>  %167 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 408)
>  %168 = fmul nsz float %162, %167
>  %169 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 412)
>  %170 = fmul nsz float %162, %169
>  %171 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %172 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %173 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %174 = fmul nsz float %171, %130
>  %175 = fmul nsz float %172, %131
>  %176 = fadd nsz float %175, %174
>  %177 = fmul nsz float %173, %132
>  %178 = fadd nsz float %176, %177
>  %179 = call nsz float @llvm.maxnum.f32(float %178, float 0.000000e+00) #2
>  %180 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 416)
>  %181 = fmul nsz float %179, %180
>  %182 = fadd nsz float %181, %164
>  %183 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 420)
>  %184 = fmul nsz float %179, %183
>  %185 = fadd nsz float %184, %166
>  %186 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 424)
>  %187 = fmul nsz float %179, %186
>  %188 = fadd nsz float %187, %168
>  %189 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 428)
>  %190 = fmul nsz float %179, %189
>  %191 = fadd nsz float %190, %170
>  %192 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 432)
>  %193 = fsub nsz float %149, %192
>  %194 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 436)
>  %195 = fsub nsz float %151, %194
>  %196 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 440)
>  %197 = fsub nsz float %153, %196
>  %198 = fmul nsz float %193, %193
>  %199 = fmul nsz float %195, %195
>  %200 = fadd nsz float %199, %198
>  %201 = fmul nsz float %197, %197
>  %202 = fadd nsz float %200, %201
>  %203 = call nsz float @llvm.sqrt.f32(float %202) #2
>  %204 = fdiv nsz float 1.000000e+00, %203, !fpmath !1
>  %205 = fmul nsz float %193, %204
>  %206 = fmul nsz float %195, %204
>  %207 = fmul nsz float %197, %204
>  %208 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 444)
>  %209 = fcmp nsz uge float %203, %208
>  %210 = select i1 %209, float 0.000000e+00, float 1.000000e+00
>  %211 = fmul nsz float %205, %130
>  %212 = fmul nsz float %206, %131
>  %213 = fadd nsz float %212, %211
>  %214 = fmul nsz float %207, %132
>  %215 = fadd nsz float %213, %214
>  %216 = call nsz float @llvm.maxnum.f32(float %215, float 0.000000e+00) #2
>  %217 = fmul nsz float %216, %210
>  %218 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 464)
>  %219 = fmul nsz float %217, %218
>  %220 = fadd nsz float %219, %182
>  %221 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 468)
>  %222 = fmul nsz float %217, %221
>  %223 = fadd nsz float %222, %185
>  %224 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 472)
>  %225 = fmul nsz float %217, %224
>  %226 = fadd nsz float %225, %188
>  %227 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 476)
>  %228 = fmul nsz float %217, %227
>  %229 = fadd nsz float %228, %191
>  %230 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 448)
>  %231 = fsub nsz float %149, %230
>  %232 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 452)
>  %233 = fsub nsz float %151, %232
>  %234 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 456)
>  %235 = fsub nsz float %153, %234
>  %236 = fmul nsz float %231, %231
>  %237 = fmul nsz float %233, %233
>  %238 = fadd nsz float %237, %236
>  %239 = fmul nsz float %235, %235
>  %240 = fadd nsz float %238, %239
>  %241 = call nsz float @llvm.sqrt.f32(float %240) #2
>  %242 = fdiv nsz float 1.000000e+00, %241, !fpmath !1
>  %243 = fmul nsz float %231, %242
>  %244 = fmul nsz float %233, %242
>  %245 = fmul nsz float %235, %242
>  %246 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 460)
>  %247 = fcmp nsz uge float %241, %246
>  %248 = select i1 %247, float 0.000000e+00, float 1.000000e+00
>  %249 = fmul nsz float %243, %130
>  %250 = fmul nsz float %244, %131
>  %251 = fadd nsz float %250, %249
>  %252 = fmul nsz float %245, %132
>  %253 = fadd nsz float %251, %252
>  %254 = call nsz float @llvm.maxnum.f32(float %253, float 0.000000e+00) #2
>  %255 = fmul nsz float %254, %248
>  %256 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 480)
>  %257 = fmul nsz float %255, %256
>  %258 = fadd nsz float %257, %220
>  %259 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 484)
>  %260 = fmul nsz float %255, %259
>  %261 = fadd nsz float %260, %223
>  %262 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 488)
>  %263 = fmul nsz float %255, %262
>  %264 = fadd nsz float %263, %226
>  %265 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 492)
>  %266 = fmul nsz float %255, %265
>  %267 = fadd nsz float %266, %229
>  %268 = fmul nsz float %258, %36
>  %269 = fmul nsz float %261, %37
>  %270 = fmul nsz float %264, %38
>  %271 = fmul nsz float %267, %39
>  %272 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %273 = fadd nsz float %268, %272
>  %274 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %275 = fadd nsz float %269, %274
>  %276 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %277 = fadd nsz float %270, %276
>  %278 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 364)
>  %279 = fadd nsz float %271, %278
>  %280 = call nsz float @llvm.minnum.f32(float %273, float 1.000000e+00) #2
>  %281 = call nsz float @llvm.minnum.f32(float %275, float 1.000000e+00) #2
>  %282 = call nsz float @llvm.minnum.f32(float %277, float 1.000000e+00) #2
>  %283 = call nsz float @llvm.minnum.f32(float %279, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %280, float %281, float %282, float %283, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float %55, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %89, float %91, float %93, float %95, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xy, GENERIC[1]
>DCL CONST[0..36]
>DCL TEMP[0..67], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 2, 3}
>IMM[2] INT32 {4, 0, 0, 0}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1].x, IMM[0].xxxx
>  5: MUL TEMP[3], CONST[8], IN[1].xxxx
>  6: MAD TEMP[4], CONST[9], IN[1].yyyy, TEMP[3]
>  7: MAD TEMP[5].xyz, CONST[10], IN[1].zzzz, TEMP[4]
>  8: DP3 TEMP[6].x, TEMP[5].xyzz, TEMP[5].xyzz
>  9: RSQ TEMP[7].x, TEMP[6].xxxx
> 10: MUL TEMP[8].xyz, TEMP[5].xyzz, TEMP[7].xxxx
> 11: MOV TEMP[9].xyz, -TEMP[8].xyzx
> 12: MUL TEMP[10], CONST[8], IN[0].xxxx
> 13: MAD TEMP[11], CONST[9], IN[0].yyyy, TEMP[10]
> 14: MAD TEMP[12], CONST[10], IN[0].zzzz, TEMP[11]
> 15: ADD TEMP[13].xyz, TEMP[12], CONST[11]
> 16: DP3 TEMP[14].x, TEMP[9].xyzz, CONST[21].xyzz
> 17: MAX TEMP[15].x, IMM[0].yyyy, TEMP[14].xxxx
> 18: MUL TEMP[16], TEMP[15].xxxx, CONST[25]
> 19: DP3 TEMP[17].x, TEMP[9].xyzz, CONST[22].xyzz
> 20: MAX TEMP[18].x, IMM[0].yyyy, TEMP[17].xxxx
> 21: MAD TEMP[16], TEMP[18].xxxx, CONST[26], TEMP[16]
> 22: DP3 TEMP[19].x, TEMP[9].xyzz, CONST[23].xyzz
> 23: MAX TEMP[20].x, IMM[0].yyyy, TEMP[19].xxxx
> 24: MAD TEMP[16], TEMP[20].xxxx, CONST[27], TEMP[16]
> 25: DP3 TEMP[21].x, TEMP[9].xyzz, CONST[24].xyzz
> 26: MAX TEMP[22].x, IMM[0].yyyy, TEMP[21].xxxx
> 27: MAD TEMP[16], TEMP[22].xxxx, CONST[28], TEMP[16]
> 28: ADD TEMP[23].xyz, TEMP[13].xyzz, -CONST[29].xyzz
> 29: DP3 TEMP[24].x, TEMP[23].xyzz, TEMP[23].xyzz
> 30: SQRT TEMP[25].x, TEMP[24].xxxx
> 31: RCP TEMP[26].x, TEMP[25].xxxx
> 32: MUL TEMP[27].xyz, TEMP[23].xyzz, TEMP[26].xxxx
> 33: FSLT TEMP[28].x, TEMP[25].xxxx, CONST[29].wwww
> 34: UCMP TEMP[29].x, TEMP[28].xxxx, IMM[0].xxxx, TEMP[29].xxxx
> 35: NOT TEMP[30].x, TEMP[28].xxxx
> 36: UCMP TEMP[29].x, TEMP[30].xxxx, IMM[0].yyyy, TEMP[29].xxxx
> 37: DP3 TEMP[31].x, TEMP[9].xyzz, TEMP[27].xyzz
> 38: MAX TEMP[32].x, IMM[0].yyyy, TEMP[31].xxxx
> 39: MUL TEMP[33].x, TEMP[32].xxxx, TEMP[29].xxxx
> 40: MAD TEMP[16], TEMP[33].xxxx, CONST[33], TEMP[16]
> 41: ADD TEMP[34].xyz, TEMP[13].xyzz, -CONST[30].xyzz
> 42: DP3 TEMP[35].x, TEMP[34].xyzz, TEMP[34].xyzz
> 43: SQRT TEMP[36].x, TEMP[35].xxxx
> 44: RCP TEMP[37].x, TEMP[36].xxxx
> 45: MUL TEMP[38].xyz, TEMP[34].xyzz, TEMP[37].xxxx
> 46: FSLT TEMP[39].x, TEMP[36].xxxx, CONST[30].wwww
> 47: UCMP TEMP[40].x, TEMP[39].xxxx, IMM[0].xxxx, TEMP[40].xxxx
> 48: NOT TEMP[41].x, TEMP[39].xxxx
> 49: UCMP TEMP[40].x, TEMP[41].xxxx, IMM[0].yyyy, TEMP[40].xxxx
> 50: DP3 TEMP[42].x, TEMP[9].xyzz, TEMP[38].xyzz
> 51: MAX TEMP[43].x, IMM[0].yyyy, TEMP[42].xxxx
> 52: MUL TEMP[44].x, TEMP[43].xxxx, TEMP[40].xxxx
> 53: MAD TEMP[16], TEMP[44].xxxx, CONST[34], TEMP[16]
> 54: ADD TEMP[45].xyz, TEMP[13].xyzz, -CONST[31].xyzz
> 55: DP3 TEMP[46].x, TEMP[45].xyzz, TEMP[45].xyzz
> 56: SQRT TEMP[47].x, TEMP[46].xxxx
> 57: RCP TEMP[48].x, TEMP[47].xxxx
> 58: MUL TEMP[49].xyz, TEMP[45].xyzz, TEMP[48].xxxx
> 59: FSLT TEMP[50].x, TEMP[47].xxxx, CONST[31].wwww
> 60: UCMP TEMP[51].x, TEMP[50].xxxx, IMM[0].xxxx, TEMP[51].xxxx
> 61: NOT TEMP[52].x, TEMP[50].xxxx
> 62: UCMP TEMP[51].x, TEMP[52].xxxx, IMM[0].yyyy, TEMP[51].xxxx
> 63: DP3 TEMP[53].x, TEMP[9].xyzz, TEMP[49].xyzz
> 64: MAX TEMP[54].x, IMM[0].yyyy, TEMP[53].xxxx
> 65: MUL TEMP[55].x, TEMP[54].xxxx, TEMP[51].xxxx
> 66: MAD TEMP[16], TEMP[55].xxxx, CONST[35], TEMP[16]
> 67: ADD TEMP[56].xyz, TEMP[13].xyzz, -CONST[32].xyzz
> 68: DP3 TEMP[57].x, TEMP[56].xyzz, TEMP[56].xyzz
> 69: SQRT TEMP[58].x, TEMP[57].xxxx
> 70: RCP TEMP[59].x, TEMP[58].xxxx
> 71: MUL TEMP[60].xyz, TEMP[56].xyzz, TEMP[59].xxxx
> 72: FSLT TEMP[61].x, TEMP[58].xxxx, CONST[32].wwww
> 73: UCMP TEMP[62].x, TEMP[61].xxxx, IMM[0].xxxx, TEMP[62].xxxx
> 74: NOT TEMP[63].x, TEMP[61].xxxx
> 75: UCMP TEMP[62].x, TEMP[63].xxxx, IMM[0].yyyy, TEMP[62].xxxx
> 76: DP3 TEMP[64].x, TEMP[9].xyzz, TEMP[60].xyzz
> 77: MAX TEMP[65].x, IMM[0].yyyy, TEMP[64].xxxx
> 78: MUL TEMP[66].x, TEMP[65].xxxx, TEMP[62].xxxx
> 79: MAD TEMP[16], TEMP[66].xxxx, CONST[36], TEMP[16]
> 80: MUL TEMP[16], TEMP[16], IN[3]
> 81: ADD TEMP[16], TEMP[16], CONST[20]
> 82: MIN TEMP[67], IMM[0].xxxx, TEMP[16]
> 83: MOV OUT[2], TEMP[67]
> 84: MOV OUT[3].xy, IN[2].xyxx
> 85: END
>radeonsi: Compiling shader 17
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %45 = fmul nsz float %44, %19
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %47 = fmul nsz float %46, %19
>  %48 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %49 = fmul nsz float %48, %19
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %51 = fmul nsz float %50, %20
>  %52 = fadd nsz float %51, %43
>  %53 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %54 = fmul nsz float %53, %20
>  %55 = fadd nsz float %54, %45
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %57 = fmul nsz float %56, %20
>  %58 = fadd nsz float %57, %47
>  %59 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %60 = fmul nsz float %59, %20
>  %61 = fadd nsz float %60, %49
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %63 = fmul nsz float %62, %21
>  %64 = fadd nsz float %63, %52
>  %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %66 = fmul nsz float %65, %21
>  %67 = fadd nsz float %66, %55
>  %68 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %69 = fmul nsz float %68, %21
>  %70 = fadd nsz float %69, %58
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %72 = fmul nsz float %71, %21
>  %73 = fadd nsz float %72, %61
>  %74 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %75 = fadd nsz float %64, %74
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %77 = fadd nsz float %67, %76
>  %78 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %79 = fadd nsz float %70, %78
>  %80 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %81 = fadd nsz float %73, %80
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %83 = fmul nsz float %82, %25
>  %84 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %85 = fmul nsz float %84, %25
>  %86 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %87 = fmul nsz float %86, %25
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %89 = fmul nsz float %88, %26
>  %90 = fadd nsz float %89, %83
>  %91 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %92 = fmul nsz float %91, %26
>  %93 = fadd nsz float %92, %85
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %95 = fmul nsz float %94, %26
>  %96 = fadd nsz float %95, %87
>  %97 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %98 = fmul nsz float %97, %27
>  %99 = fadd nsz float %98, %90
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %101 = fmul nsz float %100, %27
>  %102 = fadd nsz float %101, %93
>  %103 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %104 = fmul nsz float %103, %27
>  %105 = fadd nsz float %104, %96
>  %106 = fmul nsz float %99, %99
>  %107 = fmul nsz float %102, %102
>  %108 = fadd nsz float %107, %106
>  %109 = fmul nsz float %105, %105
>  %110 = fadd nsz float %108, %109
>  %111 = call nsz float @llvm.sqrt.f32(float %110) #2
>  %112 = fdiv nsz float 1.000000e+00, %111, !fpmath !1
>  %113 = fmul nsz float %99, %112
>  %114 = fmul nsz float %102, %112
>  %115 = fmul nsz float %105, %112
>  %116 = fsub nsz float -0.000000e+00, %113
>  %117 = fsub nsz float -0.000000e+00, %114
>  %118 = fsub nsz float -0.000000e+00, %115
>  %119 = fmul nsz float %82, %19
>  %120 = fmul nsz float %84, %19
>  %121 = fmul nsz float %86, %19
>  %122 = fmul nsz float %88, %20
>  %123 = fadd nsz float %122, %119
>  %124 = fmul nsz float %91, %20
>  %125 = fadd nsz float %124, %120
>  %126 = fmul nsz float %94, %20
>  %127 = fadd nsz float %126, %121
>  %128 = fmul nsz float %97, %21
>  %129 = fadd nsz float %128, %123
>  %130 = fmul nsz float %100, %21
>  %131 = fadd nsz float %130, %125
>  %132 = fmul nsz float %103, %21
>  %133 = fadd nsz float %132, %127
>  %134 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %135 = fadd nsz float %129, %134
>  %136 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %137 = fadd nsz float %131, %136
>  %138 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %139 = fadd nsz float %133, %138
>  %140 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %141 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 340)
>  %142 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 344)
>  %143 = fmul nsz float %140, %116
>  %144 = fmul nsz float %141, %117
>  %145 = fadd nsz float %144, %143
>  %146 = fmul nsz float %142, %118
>  %147 = fadd nsz float %145, %146
>  %148 = call nsz float @llvm.maxnum.f32(float %147, float 0.000000e+00) #2
>  %149 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 400)
>  %150 = fmul nsz float %148, %149
>  %151 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 404)
>  %152 = fmul nsz float %148, %151
>  %153 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 408)
>  %154 = fmul nsz float %148, %153
>  %155 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 412)
>  %156 = fmul nsz float %148, %155
>  %157 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %158 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %159 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %160 = fmul nsz float %157, %116
>  %161 = fmul nsz float %158, %117
>  %162 = fadd nsz float %161, %160
>  %163 = fmul nsz float %159, %118
>  %164 = fadd nsz float %162, %163
>  %165 = call nsz float @llvm.maxnum.f32(float %164, float 0.000000e+00) #2
>  %166 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 416)
>  %167 = fmul nsz float %165, %166
>  %168 = fadd nsz float %167, %150
>  %169 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 420)
>  %170 = fmul nsz float %165, %169
>  %171 = fadd nsz float %170, %152
>  %172 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 424)
>  %173 = fmul nsz float %165, %172
>  %174 = fadd nsz float %173, %154
>  %175 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 428)
>  %176 = fmul nsz float %165, %175
>  %177 = fadd nsz float %176, %156
>  %178 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %179 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %180 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %181 = fmul nsz float %178, %116
>  %182 = fmul nsz float %179, %117
>  %183 = fadd nsz float %182, %181
>  %184 = fmul nsz float %180, %118
>  %185 = fadd nsz float %183, %184
>  %186 = call nsz float @llvm.maxnum.f32(float %185, float 0.000000e+00) #2
>  %187 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 432)
>  %188 = fmul nsz float %186, %187
>  %189 = fadd nsz float %188, %168
>  %190 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 436)
>  %191 = fmul nsz float %186, %190
>  %192 = fadd nsz float %191, %171
>  %193 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 440)
>  %194 = fmul nsz float %186, %193
>  %195 = fadd nsz float %194, %174
>  %196 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 444)
>  %197 = fmul nsz float %186, %196
>  %198 = fadd nsz float %197, %177
>  %199 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %200 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %201 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %202 = fmul nsz float %199, %116
>  %203 = fmul nsz float %200, %117
>  %204 = fadd nsz float %203, %202
>  %205 = fmul nsz float %201, %118
>  %206 = fadd nsz float %204, %205
>  %207 = call nsz float @llvm.maxnum.f32(float %206, float 0.000000e+00) #2
>  %208 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 448)
>  %209 = fmul nsz float %207, %208
>  %210 = fadd nsz float %209, %189
>  %211 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 452)
>  %212 = fmul nsz float %207, %211
>  %213 = fadd nsz float %212, %192
>  %214 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 456)
>  %215 = fmul nsz float %207, %214
>  %216 = fadd nsz float %215, %195
>  %217 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 460)
>  %218 = fmul nsz float %207, %217
>  %219 = fadd nsz float %218, %198
>  %220 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 464)
>  %221 = fsub nsz float %135, %220
>  %222 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 468)
>  %223 = fsub nsz float %137, %222
>  %224 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 472)
>  %225 = fsub nsz float %139, %224
>  %226 = fmul nsz float %221, %221
>  %227 = fmul nsz float %223, %223
>  %228 = fadd nsz float %227, %226
>  %229 = fmul nsz float %225, %225
>  %230 = fadd nsz float %228, %229
>  %231 = call nsz float @llvm.sqrt.f32(float %230) #2
>  %232 = fdiv nsz float 1.000000e+00, %231, !fpmath !1
>  %233 = fmul nsz float %221, %232
>  %234 = fmul nsz float %223, %232
>  %235 = fmul nsz float %225, %232
>  %236 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 476)
>  %237 = fcmp nsz uge float %231, %236
>  %238 = select i1 %237, float 0.000000e+00, float 1.000000e+00
>  %239 = fmul nsz float %233, %116
>  %240 = fmul nsz float %234, %117
>  %241 = fadd nsz float %240, %239
>  %242 = fmul nsz float %235, %118
>  %243 = fadd nsz float %241, %242
>  %244 = call nsz float @llvm.maxnum.f32(float %243, float 0.000000e+00) #2
>  %245 = fmul nsz float %244, %238
>  %246 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 528)
>  %247 = fmul nsz float %245, %246
>  %248 = fadd nsz float %247, %210
>  %249 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 532)
>  %250 = fmul nsz float %245, %249
>  %251 = fadd nsz float %250, %213
>  %252 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 536)
>  %253 = fmul nsz float %245, %252
>  %254 = fadd nsz float %253, %216
>  %255 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 540)
>  %256 = fmul nsz float %245, %255
>  %257 = fadd nsz float %256, %219
>  %258 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 480)
>  %259 = fsub nsz float %135, %258
>  %260 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 484)
>  %261 = fsub nsz float %137, %260
>  %262 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 488)
>  %263 = fsub nsz float %139, %262
>  %264 = fmul nsz float %259, %259
>  %265 = fmul nsz float %261, %261
>  %266 = fadd nsz float %265, %264
>  %267 = fmul nsz float %263, %263
>  %268 = fadd nsz float %266, %267
>  %269 = call nsz float @llvm.sqrt.f32(float %268) #2
>  %270 = fdiv nsz float 1.000000e+00, %269, !fpmath !1
>  %271 = fmul nsz float %259, %270
>  %272 = fmul nsz float %261, %270
>  %273 = fmul nsz float %263, %270
>  %274 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 492)
>  %275 = fcmp nsz uge float %269, %274
>  %276 = select i1 %275, float 0.000000e+00, float 1.000000e+00
>  %277 = fmul nsz float %271, %116
>  %278 = fmul nsz float %272, %117
>  %279 = fadd nsz float %278, %277
>  %280 = fmul nsz float %273, %118
>  %281 = fadd nsz float %279, %280
>  %282 = call nsz float @llvm.maxnum.f32(float %281, float 0.000000e+00) #2
>  %283 = fmul nsz float %282, %276
>  %284 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 544)
>  %285 = fmul nsz float %283, %284
>  %286 = fadd nsz float %285, %248
>  %287 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 548)
>  %288 = fmul nsz float %283, %287
>  %289 = fadd nsz float %288, %251
>  %290 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 552)
>  %291 = fmul nsz float %283, %290
>  %292 = fadd nsz float %291, %254
>  %293 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 556)
>  %294 = fmul nsz float %283, %293
>  %295 = fadd nsz float %294, %257
>  %296 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 496)
>  %297 = fsub nsz float %135, %296
>  %298 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 500)
>  %299 = fsub nsz float %137, %298
>  %300 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 504)
>  %301 = fsub nsz float %139, %300
>  %302 = fmul nsz float %297, %297
>  %303 = fmul nsz float %299, %299
>  %304 = fadd nsz float %303, %302
>  %305 = fmul nsz float %301, %301
>  %306 = fadd nsz float %304, %305
>  %307 = call nsz float @llvm.sqrt.f32(float %306) #2
>  %308 = fdiv nsz float 1.000000e+00, %307, !fpmath !1
>  %309 = fmul nsz float %297, %308
>  %310 = fmul nsz float %299, %308
>  %311 = fmul nsz float %301, %308
>  %312 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 508)
>  %313 = fcmp nsz uge float %307, %312
>  %314 = select i1 %313, float 0.000000e+00, float 1.000000e+00
>  %315 = fmul nsz float %309, %116
>  %316 = fmul nsz float %310, %117
>  %317 = fadd nsz float %316, %315
>  %318 = fmul nsz float %311, %118
>  %319 = fadd nsz float %317, %318
>  %320 = call nsz float @llvm.maxnum.f32(float %319, float 0.000000e+00) #2
>  %321 = fmul nsz float %320, %314
>  %322 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 560)
>  %323 = fmul nsz float %321, %322
>  %324 = fadd nsz float %323, %286
>  %325 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 564)
>  %326 = fmul nsz float %321, %325
>  %327 = fadd nsz float %326, %289
>  %328 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 568)
>  %329 = fmul nsz float %321, %328
>  %330 = fadd nsz float %329, %292
>  %331 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 572)
>  %332 = fmul nsz float %321, %331
>  %333 = fadd nsz float %332, %295
>  %334 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 512)
>  %335 = fsub nsz float %135, %334
>  %336 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 516)
>  %337 = fsub nsz float %137, %336
>  %338 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 520)
>  %339 = fsub nsz float %139, %338
>  %340 = fmul nsz float %335, %335
>  %341 = fmul nsz float %337, %337
>  %342 = fadd nsz float %341, %340
>  %343 = fmul nsz float %339, %339
>  %344 = fadd nsz float %342, %343
>  %345 = call nsz float @llvm.sqrt.f32(float %344) #2
>  %346 = fdiv nsz float 1.000000e+00, %345, !fpmath !1
>  %347 = fmul nsz float %335, %346
>  %348 = fmul nsz float %337, %346
>  %349 = fmul nsz float %339, %346
>  %350 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 524)
>  %351 = fcmp nsz uge float %345, %350
>  %352 = select i1 %351, float 0.000000e+00, float 1.000000e+00
>  %353 = fmul nsz float %347, %116
>  %354 = fmul nsz float %348, %117
>  %355 = fadd nsz float %354, %353
>  %356 = fmul nsz float %349, %118
>  %357 = fadd nsz float %355, %356
>  %358 = call nsz float @llvm.maxnum.f32(float %357, float 0.000000e+00) #2
>  %359 = fmul nsz float %358, %352
>  %360 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 576)
>  %361 = fmul nsz float %359, %360
>  %362 = fadd nsz float %361, %324
>  %363 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 580)
>  %364 = fmul nsz float %359, %363
>  %365 = fadd nsz float %364, %327
>  %366 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 584)
>  %367 = fmul nsz float %359, %366
>  %368 = fadd nsz float %367, %330
>  %369 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 588)
>  %370 = fmul nsz float %359, %369
>  %371 = fadd nsz float %370, %333
>  %372 = fmul nsz float %362, %36
>  %373 = fmul nsz float %365, %37
>  %374 = fmul nsz float %368, %38
>  %375 = fmul nsz float %371, %39
>  %376 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %377 = fadd nsz float %372, %376
>  %378 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 324)
>  %379 = fadd nsz float %373, %378
>  %380 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 328)
>  %381 = fadd nsz float %374, %380
>  %382 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 332)
>  %383 = fadd nsz float %375, %382
>  %384 = call nsz float @llvm.minnum.f32(float %377, float 1.000000e+00) #2
>  %385 = call nsz float @llvm.minnum.f32(float %379, float 1.000000e+00) #2
>  %386 = call nsz float @llvm.minnum.f32(float %381, float 1.000000e+00) #2
>  %387 = call nsz float @llvm.minnum.f32(float %383, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %384, float %385, float %386, float %387, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float undef, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %75, float %77, float %79, float %81, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xyz, GENERIC[1]
>DCL CONST[0..38]
>DCL TEMP[0..73], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 2, 3}
>IMM[2] INT32 {4, 0, 0, 0}
>  0: MUL TEMP[0], CONST[12], IN[0].xxxx
>  1: MAD TEMP[1], CONST[13], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[14], IN[0].zzzz, TEMP[1]
>  3: ADD TEMP[3].z, TEMP[2], CONST[15]
>  4: ADD TEMP[4].x, TEMP[3].zzzz, -CONST[20].xxxx
>  5: MUL TEMP[5].x, TEMP[4].xxxx, CONST[21].xxxx
>  6: MUL TEMP[6], CONST[16], IN[0].xxxx
>  7: MAD TEMP[7], CONST[17], IN[0].yyyy, TEMP[6]
>  8: MAD TEMP[8], CONST[18], IN[0].zzzz, TEMP[7]
>  9: ADD OUT[0], TEMP[8], CONST[19]
> 10: MOV OUT[1].x, IMM[0].xxxx
> 11: MUL TEMP[9], CONST[8], IN[1].xxxx
> 12: MAD TEMP[10], CONST[9], IN[1].yyyy, TEMP[9]
> 13: MAD TEMP[11].xyz, CONST[10], IN[1].zzzz, TEMP[10]
> 14: DP3 TEMP[12].x, TEMP[11].xyzz, TEMP[11].xyzz
> 15: RSQ TEMP[13].x, TEMP[12].xxxx
> 16: MUL TEMP[14].xyz, TEMP[11].xyzz, TEMP[13].xxxx
> 17: MOV TEMP[15].xyz, -TEMP[14].xyzx
> 18: MUL TEMP[16], CONST[8], IN[0].xxxx
> 19: MAD TEMP[17], CONST[9], IN[0].yyyy, TEMP[16]
> 20: MAD TEMP[18], CONST[10], IN[0].zzzz, TEMP[17]
> 21: ADD TEMP[19].xyz, TEMP[18], CONST[11]
> 22: DP3 TEMP[20].x, TEMP[15].xyzz, CONST[23].xyzz
> 23: MAX TEMP[21].x, IMM[0].yyyy, TEMP[20].xxxx
> 24: MUL TEMP[22], TEMP[21].xxxx, CONST[27]
> 25: DP3 TEMP[23].x, TEMP[15].xyzz, CONST[24].xyzz
> 26: MAX TEMP[24].x, IMM[0].yyyy, TEMP[23].xxxx
> 27: MAD TEMP[22], TEMP[24].xxxx, CONST[28], TEMP[22]
> 28: DP3 TEMP[25].x, TEMP[15].xyzz, CONST[25].xyzz
> 29: MAX TEMP[26].x, IMM[0].yyyy, TEMP[25].xxxx
> 30: MAD TEMP[22], TEMP[26].xxxx, CONST[29], TEMP[22]
> 31: DP3 TEMP[27].x, TEMP[15].xyzz, CONST[26].xyzz
> 32: MAX TEMP[28].x, IMM[0].yyyy, TEMP[27].xxxx
> 33: MAD TEMP[22], TEMP[28].xxxx, CONST[30], TEMP[22]
> 34: ADD TEMP[29].xyz, TEMP[19].xyzz, -CONST[31].xyzz
> 35: DP3 TEMP[30].x, TEMP[29].xyzz, TEMP[29].xyzz
> 36: SQRT TEMP[31].x, TEMP[30].xxxx
> 37: RCP TEMP[32].x, TEMP[31].xxxx
> 38: MUL TEMP[33].xyz, TEMP[29].xyzz, TEMP[32].xxxx
> 39: FSLT TEMP[34].x, TEMP[31].xxxx, CONST[31].wwww
> 40: UCMP TEMP[35].x, TEMP[34].xxxx, IMM[0].xxxx, TEMP[35].xxxx
> 41: NOT TEMP[36].x, TEMP[34].xxxx
> 42: UCMP TEMP[35].x, TEMP[36].xxxx, IMM[0].yyyy, TEMP[35].xxxx
> 43: DP3 TEMP[37].x, TEMP[15].xyzz, TEMP[33].xyzz
> 44: MAX TEMP[38].x, IMM[0].yyyy, TEMP[37].xxxx
> 45: MUL TEMP[39].x, TEMP[38].xxxx, TEMP[35].xxxx
> 46: MAD TEMP[22], TEMP[39].xxxx, CONST[35], TEMP[22]
> 47: ADD TEMP[40].xyz, TEMP[19].xyzz, -CONST[32].xyzz
> 48: DP3 TEMP[41].x, TEMP[40].xyzz, TEMP[40].xyzz
> 49: SQRT TEMP[42].x, TEMP[41].xxxx
> 50: RCP TEMP[43].x, TEMP[42].xxxx
> 51: MUL TEMP[44].xyz, TEMP[40].xyzz, TEMP[43].xxxx
> 52: FSLT TEMP[45].x, TEMP[42].xxxx, CONST[32].wwww
> 53: UCMP TEMP[46].x, TEMP[45].xxxx, IMM[0].xxxx, TEMP[46].xxxx
> 54: NOT TEMP[47].x, TEMP[45].xxxx
> 55: UCMP TEMP[46].x, TEMP[47].xxxx, IMM[0].yyyy, TEMP[46].xxxx
> 56: DP3 TEMP[48].x, TEMP[15].xyzz, TEMP[44].xyzz
> 57: MAX TEMP[49].x, IMM[0].yyyy, TEMP[48].xxxx
> 58: MUL TEMP[50].x, TEMP[49].xxxx, TEMP[46].xxxx
> 59: MAD TEMP[22], TEMP[50].xxxx, CONST[36], TEMP[22]
> 60: ADD TEMP[51].xyz, TEMP[19].xyzz, -CONST[33].xyzz
> 61: DP3 TEMP[52].x, TEMP[51].xyzz, TEMP[51].xyzz
> 62: SQRT TEMP[53].x, TEMP[52].xxxx
> 63: RCP TEMP[54].x, TEMP[53].xxxx
> 64: MUL TEMP[55].xyz, TEMP[51].xyzz, TEMP[54].xxxx
> 65: FSLT TEMP[56].x, TEMP[53].xxxx, CONST[33].wwww
> 66: UCMP TEMP[57].x, TEMP[56].xxxx, IMM[0].xxxx, TEMP[57].xxxx
> 67: NOT TEMP[58].x, TEMP[56].xxxx
> 68: UCMP TEMP[57].x, TEMP[58].xxxx, IMM[0].yyyy, TEMP[57].xxxx
> 69: DP3 TEMP[59].x, TEMP[15].xyzz, TEMP[55].xyzz
> 70: MAX TEMP[60].x, IMM[0].yyyy, TEMP[59].xxxx
> 71: MUL TEMP[61].x, TEMP[60].xxxx, TEMP[57].xxxx
> 72: MAD TEMP[22], TEMP[61].xxxx, CONST[37], TEMP[22]
> 73: ADD TEMP[62].xyz, TEMP[19].xyzz, -CONST[34].xyzz
> 74: DP3 TEMP[63].x, TEMP[62].xyzz, TEMP[62].xyzz
> 75: SQRT TEMP[64].x, TEMP[63].xxxx
> 76: RCP TEMP[65].x, TEMP[64].xxxx
> 77: MUL TEMP[66].xyz, TEMP[62].xyzz, TEMP[65].xxxx
> 78: FSLT TEMP[67].x, TEMP[64].xxxx, CONST[34].wwww
> 79: UCMP TEMP[68].x, TEMP[67].xxxx, IMM[0].xxxx, TEMP[68].xxxx
> 80: NOT TEMP[69].x, TEMP[67].xxxx
> 81: UCMP TEMP[68].x, TEMP[69].xxxx, IMM[0].yyyy, TEMP[68].xxxx
> 82: DP3 TEMP[70].x, TEMP[15].xyzz, TEMP[66].xyzz
> 83: MAX TEMP[71].x, IMM[0].yyyy, TEMP[70].xxxx
> 84: MUL TEMP[72].x, TEMP[71].xxxx, TEMP[68].xxxx
> 85: MAD TEMP[22], TEMP[72].xxxx, CONST[38], TEMP[22]
> 86: MUL TEMP[22], TEMP[22], IN[3]
> 87: ADD TEMP[22], TEMP[22], CONST[22]
> 88: MIN TEMP[73], IMM[0].xxxx, TEMP[22]
> 89: MOV OUT[2], TEMP[73]
> 90: MOV OUT[3].xy, IN[2].xyxx
> 91: MOV OUT[3].z, TEMP[5].xxxx
> 92: END
>radeonsi: Compiling shader 18
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 200)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 216)
>  %45 = fmul nsz float %44, %20
>  %46 = fadd nsz float %45, %43
>  %47 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 232)
>  %48 = fmul nsz float %47, %21
>  %49 = fadd nsz float %48, %46
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 248)
>  %51 = fadd nsz float %49, %50
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %53 = fsub nsz float %51, %52
>  %54 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %55 = fmul nsz float %53, %54
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %57 = fmul nsz float %56, %19
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %59 = fmul nsz float %58, %19
>  %60 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %61 = fmul nsz float %60, %19
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %63 = fmul nsz float %62, %19
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %57
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %68 = fmul nsz float %67, %20
>  %69 = fadd nsz float %68, %59
>  %70 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %71 = fmul nsz float %70, %20
>  %72 = fadd nsz float %71, %61
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %74 = fmul nsz float %73, %20
>  %75 = fadd nsz float %74, %63
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %77 = fmul nsz float %76, %21
>  %78 = fadd nsz float %77, %66
>  %79 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %80 = fmul nsz float %79, %21
>  %81 = fadd nsz float %80, %69
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %83 = fmul nsz float %82, %21
>  %84 = fadd nsz float %83, %72
>  %85 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %86 = fmul nsz float %85, %21
>  %87 = fadd nsz float %86, %75
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %89 = fadd nsz float %78, %88
>  %90 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %91 = fadd nsz float %81, %90
>  %92 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %93 = fadd nsz float %84, %92
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %95 = fadd nsz float %87, %94
>  %96 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %97 = fmul nsz float %96, %25
>  %98 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %99 = fmul nsz float %98, %25
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %101 = fmul nsz float %100, %25
>  %102 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %103 = fmul nsz float %102, %26
>  %104 = fadd nsz float %103, %97
>  %105 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %106 = fmul nsz float %105, %26
>  %107 = fadd nsz float %106, %99
>  %108 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %109 = fmul nsz float %108, %26
>  %110 = fadd nsz float %109, %101
>  %111 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %112 = fmul nsz float %111, %27
>  %113 = fadd nsz float %112, %104
>  %114 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %115 = fmul nsz float %114, %27
>  %116 = fadd nsz float %115, %107
>  %117 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %118 = fmul nsz float %117, %27
>  %119 = fadd nsz float %118, %110
>  %120 = fmul nsz float %113, %113
>  %121 = fmul nsz float %116, %116
>  %122 = fadd nsz float %121, %120
>  %123 = fmul nsz float %119, %119
>  %124 = fadd nsz float %122, %123
>  %125 = call nsz float @llvm.sqrt.f32(float %124) #2
>  %126 = fdiv nsz float 1.000000e+00, %125, !fpmath !1
>  %127 = fmul nsz float %113, %126
>  %128 = fmul nsz float %116, %126
>  %129 = fmul nsz float %119, %126
>  %130 = fsub nsz float -0.000000e+00, %127
>  %131 = fsub nsz float -0.000000e+00, %128
>  %132 = fsub nsz float -0.000000e+00, %129
>  %133 = fmul nsz float %96, %19
>  %134 = fmul nsz float %98, %19
>  %135 = fmul nsz float %100, %19
>  %136 = fmul nsz float %102, %20
>  %137 = fadd nsz float %136, %133
>  %138 = fmul nsz float %105, %20
>  %139 = fadd nsz float %138, %134
>  %140 = fmul nsz float %108, %20
>  %141 = fadd nsz float %140, %135
>  %142 = fmul nsz float %111, %21
>  %143 = fadd nsz float %142, %137
>  %144 = fmul nsz float %114, %21
>  %145 = fadd nsz float %144, %139
>  %146 = fmul nsz float %117, %21
>  %147 = fadd nsz float %146, %141
>  %148 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %149 = fadd nsz float %143, %148
>  %150 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %151 = fadd nsz float %145, %150
>  %152 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %153 = fadd nsz float %147, %152
>  %154 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %155 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %156 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %157 = fmul nsz float %154, %130
>  %158 = fmul nsz float %155, %131
>  %159 = fadd nsz float %158, %157
>  %160 = fmul nsz float %156, %132
>  %161 = fadd nsz float %159, %160
>  %162 = call nsz float @llvm.maxnum.f32(float %161, float 0.000000e+00) #2
>  %163 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 432)
>  %164 = fmul nsz float %162, %163
>  %165 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 436)
>  %166 = fmul nsz float %162, %165
>  %167 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 440)
>  %168 = fmul nsz float %162, %167
>  %169 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 444)
>  %170 = fmul nsz float %162, %169
>  %171 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %172 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %173 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %174 = fmul nsz float %171, %130
>  %175 = fmul nsz float %172, %131
>  %176 = fadd nsz float %175, %174
>  %177 = fmul nsz float %173, %132
>  %178 = fadd nsz float %176, %177
>  %179 = call nsz float @llvm.maxnum.f32(float %178, float 0.000000e+00) #2
>  %180 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 448)
>  %181 = fmul nsz float %179, %180
>  %182 = fadd nsz float %181, %164
>  %183 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 452)
>  %184 = fmul nsz float %179, %183
>  %185 = fadd nsz float %184, %166
>  %186 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 456)
>  %187 = fmul nsz float %179, %186
>  %188 = fadd nsz float %187, %168
>  %189 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 460)
>  %190 = fmul nsz float %179, %189
>  %191 = fadd nsz float %190, %170
>  %192 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 400)
>  %193 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 404)
>  %194 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 408)
>  %195 = fmul nsz float %192, %130
>  %196 = fmul nsz float %193, %131
>  %197 = fadd nsz float %196, %195
>  %198 = fmul nsz float %194, %132
>  %199 = fadd nsz float %197, %198
>  %200 = call nsz float @llvm.maxnum.f32(float %199, float 0.000000e+00) #2
>  %201 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 464)
>  %202 = fmul nsz float %200, %201
>  %203 = fadd nsz float %202, %182
>  %204 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 468)
>  %205 = fmul nsz float %200, %204
>  %206 = fadd nsz float %205, %185
>  %207 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 472)
>  %208 = fmul nsz float %200, %207
>  %209 = fadd nsz float %208, %188
>  %210 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 476)
>  %211 = fmul nsz float %200, %210
>  %212 = fadd nsz float %211, %191
>  %213 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 416)
>  %214 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 420)
>  %215 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 424)
>  %216 = fmul nsz float %213, %130
>  %217 = fmul nsz float %214, %131
>  %218 = fadd nsz float %217, %216
>  %219 = fmul nsz float %215, %132
>  %220 = fadd nsz float %218, %219
>  %221 = call nsz float @llvm.maxnum.f32(float %220, float 0.000000e+00) #2
>  %222 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 480)
>  %223 = fmul nsz float %221, %222
>  %224 = fadd nsz float %223, %203
>  %225 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 484)
>  %226 = fmul nsz float %221, %225
>  %227 = fadd nsz float %226, %206
>  %228 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 488)
>  %229 = fmul nsz float %221, %228
>  %230 = fadd nsz float %229, %209
>  %231 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 492)
>  %232 = fmul nsz float %221, %231
>  %233 = fadd nsz float %232, %212
>  %234 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 496)
>  %235 = fsub nsz float %149, %234
>  %236 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 500)
>  %237 = fsub nsz float %151, %236
>  %238 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 504)
>  %239 = fsub nsz float %153, %238
>  %240 = fmul nsz float %235, %235
>  %241 = fmul nsz float %237, %237
>  %242 = fadd nsz float %241, %240
>  %243 = fmul nsz float %239, %239
>  %244 = fadd nsz float %242, %243
>  %245 = call nsz float @llvm.sqrt.f32(float %244) #2
>  %246 = fdiv nsz float 1.000000e+00, %245, !fpmath !1
>  %247 = fmul nsz float %235, %246
>  %248 = fmul nsz float %237, %246
>  %249 = fmul nsz float %239, %246
>  %250 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 508)
>  %251 = fcmp nsz uge float %245, %250
>  %252 = select i1 %251, float 0.000000e+00, float 1.000000e+00
>  %253 = fmul nsz float %247, %130
>  %254 = fmul nsz float %248, %131
>  %255 = fadd nsz float %254, %253
>  %256 = fmul nsz float %249, %132
>  %257 = fadd nsz float %255, %256
>  %258 = call nsz float @llvm.maxnum.f32(float %257, float 0.000000e+00) #2
>  %259 = fmul nsz float %258, %252
>  %260 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 560)
>  %261 = fmul nsz float %259, %260
>  %262 = fadd nsz float %261, %224
>  %263 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 564)
>  %264 = fmul nsz float %259, %263
>  %265 = fadd nsz float %264, %227
>  %266 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 568)
>  %267 = fmul nsz float %259, %266
>  %268 = fadd nsz float %267, %230
>  %269 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 572)
>  %270 = fmul nsz float %259, %269
>  %271 = fadd nsz float %270, %233
>  %272 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 512)
>  %273 = fsub nsz float %149, %272
>  %274 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 516)
>  %275 = fsub nsz float %151, %274
>  %276 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 520)
>  %277 = fsub nsz float %153, %276
>  %278 = fmul nsz float %273, %273
>  %279 = fmul nsz float %275, %275
>  %280 = fadd nsz float %279, %278
>  %281 = fmul nsz float %277, %277
>  %282 = fadd nsz float %280, %281
>  %283 = call nsz float @llvm.sqrt.f32(float %282) #2
>  %284 = fdiv nsz float 1.000000e+00, %283, !fpmath !1
>  %285 = fmul nsz float %273, %284
>  %286 = fmul nsz float %275, %284
>  %287 = fmul nsz float %277, %284
>  %288 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 524)
>  %289 = fcmp nsz uge float %283, %288
>  %290 = select i1 %289, float 0.000000e+00, float 1.000000e+00
>  %291 = fmul nsz float %285, %130
>  %292 = fmul nsz float %286, %131
>  %293 = fadd nsz float %292, %291
>  %294 = fmul nsz float %287, %132
>  %295 = fadd nsz float %293, %294
>  %296 = call nsz float @llvm.maxnum.f32(float %295, float 0.000000e+00) #2
>  %297 = fmul nsz float %296, %290
>  %298 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 576)
>  %299 = fmul nsz float %297, %298
>  %300 = fadd nsz float %299, %262
>  %301 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 580)
>  %302 = fmul nsz float %297, %301
>  %303 = fadd nsz float %302, %265
>  %304 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 584)
>  %305 = fmul nsz float %297, %304
>  %306 = fadd nsz float %305, %268
>  %307 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 588)
>  %308 = fmul nsz float %297, %307
>  %309 = fadd nsz float %308, %271
>  %310 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 528)
>  %311 = fsub nsz float %149, %310
>  %312 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 532)
>  %313 = fsub nsz float %151, %312
>  %314 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 536)
>  %315 = fsub nsz float %153, %314
>  %316 = fmul nsz float %311, %311
>  %317 = fmul nsz float %313, %313
>  %318 = fadd nsz float %317, %316
>  %319 = fmul nsz float %315, %315
>  %320 = fadd nsz float %318, %319
>  %321 = call nsz float @llvm.sqrt.f32(float %320) #2
>  %322 = fdiv nsz float 1.000000e+00, %321, !fpmath !1
>  %323 = fmul nsz float %311, %322
>  %324 = fmul nsz float %313, %322
>  %325 = fmul nsz float %315, %322
>  %326 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 540)
>  %327 = fcmp nsz uge float %321, %326
>  %328 = select i1 %327, float 0.000000e+00, float 1.000000e+00
>  %329 = fmul nsz float %323, %130
>  %330 = fmul nsz float %324, %131
>  %331 = fadd nsz float %330, %329
>  %332 = fmul nsz float %325, %132
>  %333 = fadd nsz float %331, %332
>  %334 = call nsz float @llvm.maxnum.f32(float %333, float 0.000000e+00) #2
>  %335 = fmul nsz float %334, %328
>  %336 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 592)
>  %337 = fmul nsz float %335, %336
>  %338 = fadd nsz float %337, %300
>  %339 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 596)
>  %340 = fmul nsz float %335, %339
>  %341 = fadd nsz float %340, %303
>  %342 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 600)
>  %343 = fmul nsz float %335, %342
>  %344 = fadd nsz float %343, %306
>  %345 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 604)
>  %346 = fmul nsz float %335, %345
>  %347 = fadd nsz float %346, %309
>  %348 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 544)
>  %349 = fsub nsz float %149, %348
>  %350 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 548)
>  %351 = fsub nsz float %151, %350
>  %352 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 552)
>  %353 = fsub nsz float %153, %352
>  %354 = fmul nsz float %349, %349
>  %355 = fmul nsz float %351, %351
>  %356 = fadd nsz float %355, %354
>  %357 = fmul nsz float %353, %353
>  %358 = fadd nsz float %356, %357
>  %359 = call nsz float @llvm.sqrt.f32(float %358) #2
>  %360 = fdiv nsz float 1.000000e+00, %359, !fpmath !1
>  %361 = fmul nsz float %349, %360
>  %362 = fmul nsz float %351, %360
>  %363 = fmul nsz float %353, %360
>  %364 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 556)
>  %365 = fcmp nsz uge float %359, %364
>  %366 = select i1 %365, float 0.000000e+00, float 1.000000e+00
>  %367 = fmul nsz float %361, %130
>  %368 = fmul nsz float %362, %131
>  %369 = fadd nsz float %368, %367
>  %370 = fmul nsz float %363, %132
>  %371 = fadd nsz float %369, %370
>  %372 = call nsz float @llvm.maxnum.f32(float %371, float 0.000000e+00) #2
>  %373 = fmul nsz float %372, %366
>  %374 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 608)
>  %375 = fmul nsz float %373, %374
>  %376 = fadd nsz float %375, %338
>  %377 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 612)
>  %378 = fmul nsz float %373, %377
>  %379 = fadd nsz float %378, %341
>  %380 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 616)
>  %381 = fmul nsz float %373, %380
>  %382 = fadd nsz float %381, %344
>  %383 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 620)
>  %384 = fmul nsz float %373, %383
>  %385 = fadd nsz float %384, %347
>  %386 = fmul nsz float %376, %36
>  %387 = fmul nsz float %379, %37
>  %388 = fmul nsz float %382, %38
>  %389 = fmul nsz float %385, %39
>  %390 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %391 = fadd nsz float %386, %390
>  %392 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %393 = fadd nsz float %387, %392
>  %394 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %395 = fadd nsz float %388, %394
>  %396 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 364)
>  %397 = fadd nsz float %389, %396
>  %398 = call nsz float @llvm.minnum.f32(float %391, float 1.000000e+00) #2
>  %399 = call nsz float @llvm.minnum.f32(float %393, float 1.000000e+00) #2
>  %400 = call nsz float @llvm.minnum.f32(float %395, float 1.000000e+00) #2
>  %401 = call nsz float @llvm.minnum.f32(float %397, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %398, float %399, float %400, float %401, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float %55, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %89, float %91, float %93, float %95, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xy, GENERIC[1]
>DCL CONST[0..52]
>DCL TEMP[0..49], LOCAL
>DCL ADDR[0]
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 2, 3}
>IMM[2] INT32 {4, 5, 6, 7}
>IMM[3] INT32 {8, 0, 0, 0}
>  0: MOV TEMP[0].w, IMM[0].xxxx
>  1: MOV TEMP[0].xyz, IN[0].xyzx
>  2: MUL TEMP[1], CONST[16], IN[0].xxxx
>  3: MAD TEMP[2], CONST[17], IN[0].yyyy, TEMP[1]
>  4: MAD TEMP[3], CONST[18], IN[0].zzzz, TEMP[2]
>  5: ADD OUT[0], TEMP[3], CONST[19]
>  6: MOV OUT[1].x, IMM[0].xxxx
>  7: MOV TEMP[4].w, IMM[0].yyyy
>  8: MOV TEMP[4].xyz, IN[1].xyzx
>  9: MUL TEMP[5], CONST[8], IN[1].xxxx
> 10: MAD TEMP[6], CONST[9], IN[1].yyyy, TEMP[5]
> 11: MAD TEMP[7], CONST[10], IN[1].zzzz, TEMP[6]
> 12: DP3 TEMP[8].x, TEMP[7].xyzz, TEMP[7].xyzz
> 13: RSQ TEMP[9].x, TEMP[8].xxxx
> 14: MUL TEMP[10].xyz, TEMP[7].xyzz, TEMP[9].xxxx
> 15: MOV TEMP[11].xyz, -TEMP[10].xyzx
> 16: MUL TEMP[12], CONST[8], IN[0].xxxx
> 17: MAD TEMP[13], CONST[9], IN[0].yyyy, TEMP[12]
> 18: MAD TEMP[14], CONST[10], IN[0].zzzz, TEMP[13]
> 19: ADD TEMP[15], TEMP[14], CONST[11]
> 20: DP3 TEMP[16].x, TEMP[11].xyzz, CONST[21].xyzz
> 21: MAX TEMP[17].x, IMM[0].yyyy, TEMP[16].xxxx
> 22: MUL TEMP[18], TEMP[17].xxxx, CONST[29]
> 23: DP3 TEMP[19].x, TEMP[11].xyzz, CONST[22].xyzz
> 24: MAX TEMP[20].x, IMM[0].yyyy, TEMP[19].xxxx
> 25: MAD TEMP[18], TEMP[20].xxxx, CONST[30], TEMP[18]
> 26: DP3 TEMP[21].x, TEMP[11].xyzz, CONST[23].xyzz
> 27: MAX TEMP[22].x, IMM[0].yyyy, TEMP[21].xxxx
> 28: MAD TEMP[18], TEMP[22].xxxx, CONST[31], TEMP[18]
> 29: DP3 TEMP[23].x, TEMP[11].xyzz, CONST[24].xyzz
> 30: MAX TEMP[24].x, IMM[0].yyyy, TEMP[23].xxxx
> 31: MAD TEMP[18], TEMP[24].xxxx, CONST[32], TEMP[18]
> 32: DP3 TEMP[25].x, TEMP[11].xyzz, CONST[25].xyzz
> 33: MAX TEMP[26].x, IMM[0].yyyy, TEMP[25].xxxx
> 34: MAD TEMP[18], TEMP[26].xxxx, CONST[33], TEMP[18]
> 35: DP3 TEMP[27].x, TEMP[11].xyzz, CONST[26].xyzz
> 36: MAX TEMP[28].x, IMM[0].yyyy, TEMP[27].xxxx
> 37: MAD TEMP[18], TEMP[28].xxxx, CONST[34], TEMP[18]
> 38: DP3 TEMP[29].x, TEMP[11].xyzz, CONST[27].xyzz
> 39: MAX TEMP[30].x, IMM[0].yyyy, TEMP[29].xxxx
> 40: MAD TEMP[18], TEMP[30].xxxx, CONST[35], TEMP[18]
> 41: DP3 TEMP[31].x, TEMP[11].xyzz, CONST[28].xyzz
> 42: MAX TEMP[32].x, IMM[0].yyyy, TEMP[31].xxxx
> 43: MAD TEMP[18], TEMP[32].xxxx, CONST[36], TEMP[18]
> 44: MOV TEMP[33].x, IMM[3].xxxx
> 45: MOV TEMP[34].x, IMM[1].xxxx
> 46: BGNLOOP
> 47:   ISGE TEMP[35].x, TEMP[34].xxxx, IMM[3].xxxx
> 48:   UIF TEMP[35].xxxx
> 49:     BRK
> 50:   ENDIF
> 51:   UARL ADDR[0].x, TEMP[34].xxxx
> 52:   MOV TEMP[36], CONST[ADDR[0].x+37]
> 53:   UARL ADDR[0].x, TEMP[34].xxxx
> 54:   MOV TEMP[37], CONST[ADDR[0].x+45]
> 55:   ADD TEMP[38].xyz, TEMP[15].xyzz, -TEMP[36].xyzz
> 56:   DP3 TEMP[39].x, TEMP[38].xyzz, TEMP[38].xyzz
> 57:   SQRT TEMP[40].x, TEMP[39].xxxx
> 58:   RCP TEMP[41].x, TEMP[40].xxxx
> 59:   MUL TEMP[42].xyz, TEMP[38].xyzz, TEMP[41].xxxx
> 60:   FSLT TEMP[43].x, TEMP[40].xxxx, TEMP[36].wwww
> 61:   UCMP TEMP[44].x, TEMP[43].xxxx, IMM[0].xxxx, TEMP[44].xxxx
> 62:   NOT TEMP[45].x, TEMP[43].xxxx
> 63:   UCMP TEMP[44].x, TEMP[45].xxxx, IMM[0].yyyy, TEMP[44].xxxx
> 64:   DP3 TEMP[46].x, TEMP[11].xyzz, TEMP[42].xyzz
> 65:   MAX TEMP[47].x, IMM[0].yyyy, TEMP[46].xxxx
> 66:   MUL TEMP[48].x, TEMP[47].xxxx, TEMP[44].xxxx
> 67:   MAD TEMP[18], TEMP[48].xxxx, TEMP[37], TEMP[18]
> 68:   UADD TEMP[34].x, TEMP[34].xxxx, IMM[1].yyyy
> 69: ENDLOOP
> 70: MUL TEMP[18], TEMP[18], IN[3]
> 71: ADD TEMP[18], TEMP[18], CONST[20]
> 72: MIN TEMP[49], IMM[0].xxxx, TEMP[18]
> 73: MOV OUT[2], TEMP[49]
> 74: MOV OUT[3].xy, IN[2].xyxx
> 75: END
>radeonsi: Compiling shader 19
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %45 = fmul nsz float %44, %19
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %47 = fmul nsz float %46, %19
>  %48 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %49 = fmul nsz float %48, %19
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %51 = fmul nsz float %50, %20
>  %52 = fadd nsz float %51, %43
>  %53 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %54 = fmul nsz float %53, %20
>  %55 = fadd nsz float %54, %45
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %57 = fmul nsz float %56, %20
>  %58 = fadd nsz float %57, %47
>  %59 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %60 = fmul nsz float %59, %20
>  %61 = fadd nsz float %60, %49
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %63 = fmul nsz float %62, %21
>  %64 = fadd nsz float %63, %52
>  %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %66 = fmul nsz float %65, %21
>  %67 = fadd nsz float %66, %55
>  %68 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %69 = fmul nsz float %68, %21
>  %70 = fadd nsz float %69, %58
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %72 = fmul nsz float %71, %21
>  %73 = fadd nsz float %72, %61
>  %74 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %75 = fadd nsz float %64, %74
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %77 = fadd nsz float %67, %76
>  %78 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %79 = fadd nsz float %70, %78
>  %80 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %81 = fadd nsz float %73, %80
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %83 = fmul nsz float %82, %25
>  %84 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %85 = fmul nsz float %84, %25
>  %86 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %87 = fmul nsz float %86, %25
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %89 = fmul nsz float %88, %26
>  %90 = fadd nsz float %89, %83
>  %91 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %92 = fmul nsz float %91, %26
>  %93 = fadd nsz float %92, %85
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %95 = fmul nsz float %94, %26
>  %96 = fadd nsz float %95, %87
>  %97 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %98 = fmul nsz float %97, %27
>  %99 = fadd nsz float %98, %90
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %101 = fmul nsz float %100, %27
>  %102 = fadd nsz float %101, %93
>  %103 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %104 = fmul nsz float %103, %27
>  %105 = fadd nsz float %104, %96
>  %106 = fmul nsz float %99, %99
>  %107 = fmul nsz float %102, %102
>  %108 = fadd nsz float %107, %106
>  %109 = fmul nsz float %105, %105
>  %110 = fadd nsz float %108, %109
>  %111 = call nsz float @llvm.sqrt.f32(float %110) #2
>  %112 = fdiv nsz float 1.000000e+00, %111, !fpmath !1
>  %113 = fmul nsz float %99, %112
>  %114 = fmul nsz float %102, %112
>  %115 = fmul nsz float %105, %112
>  %116 = fsub nsz float -0.000000e+00, %113
>  %117 = fsub nsz float -0.000000e+00, %114
>  %118 = fsub nsz float -0.000000e+00, %115
>  %119 = fmul nsz float %82, %19
>  %120 = fmul nsz float %84, %19
>  %121 = fmul nsz float %86, %19
>  %122 = fmul nsz float %88, %20
>  %123 = fadd nsz float %122, %119
>  %124 = fmul nsz float %91, %20
>  %125 = fadd nsz float %124, %120
>  %126 = fmul nsz float %94, %20
>  %127 = fadd nsz float %126, %121
>  %128 = fmul nsz float %97, %21
>  %129 = fadd nsz float %128, %123
>  %130 = fmul nsz float %100, %21
>  %131 = fadd nsz float %130, %125
>  %132 = fmul nsz float %103, %21
>  %133 = fadd nsz float %132, %127
>  %134 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %135 = fadd nsz float %129, %134
>  %136 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %137 = fadd nsz float %131, %136
>  %138 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %139 = fadd nsz float %133, %138
>  %140 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %141 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 340)
>  %142 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 344)
>  %143 = fmul nsz float %140, %116
>  %144 = fmul nsz float %141, %117
>  %145 = fadd nsz float %144, %143
>  %146 = fmul nsz float %142, %118
>  %147 = fadd nsz float %145, %146
>  %148 = call nsz float @llvm.maxnum.f32(float %147, float 0.000000e+00) #2
>  %149 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 464)
>  %150 = fmul nsz float %148, %149
>  %151 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 468)
>  %152 = fmul nsz float %148, %151
>  %153 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 472)
>  %154 = fmul nsz float %148, %153
>  %155 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 476)
>  %156 = fmul nsz float %148, %155
>  %157 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %158 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %159 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %160 = fmul nsz float %157, %116
>  %161 = fmul nsz float %158, %117
>  %162 = fadd nsz float %161, %160
>  %163 = fmul nsz float %159, %118
>  %164 = fadd nsz float %162, %163
>  %165 = call nsz float @llvm.maxnum.f32(float %164, float 0.000000e+00) #2
>  %166 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 480)
>  %167 = fmul nsz float %165, %166
>  %168 = fadd nsz float %167, %150
>  %169 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 484)
>  %170 = fmul nsz float %165, %169
>  %171 = fadd nsz float %170, %152
>  %172 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 488)
>  %173 = fmul nsz float %165, %172
>  %174 = fadd nsz float %173, %154
>  %175 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 492)
>  %176 = fmul nsz float %165, %175
>  %177 = fadd nsz float %176, %156
>  %178 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %179 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %180 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %181 = fmul nsz float %178, %116
>  %182 = fmul nsz float %179, %117
>  %183 = fadd nsz float %182, %181
>  %184 = fmul nsz float %180, %118
>  %185 = fadd nsz float %183, %184
>  %186 = call nsz float @llvm.maxnum.f32(float %185, float 0.000000e+00) #2
>  %187 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 496)
>  %188 = fmul nsz float %186, %187
>  %189 = fadd nsz float %188, %168
>  %190 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 500)
>  %191 = fmul nsz float %186, %190
>  %192 = fadd nsz float %191, %171
>  %193 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 504)
>  %194 = fmul nsz float %186, %193
>  %195 = fadd nsz float %194, %174
>  %196 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 508)
>  %197 = fmul nsz float %186, %196
>  %198 = fadd nsz float %197, %177
>  %199 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %200 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %201 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %202 = fmul nsz float %199, %116
>  %203 = fmul nsz float %200, %117
>  %204 = fadd nsz float %203, %202
>  %205 = fmul nsz float %201, %118
>  %206 = fadd nsz float %204, %205
>  %207 = call nsz float @llvm.maxnum.f32(float %206, float 0.000000e+00) #2
>  %208 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 512)
>  %209 = fmul nsz float %207, %208
>  %210 = fadd nsz float %209, %189
>  %211 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 516)
>  %212 = fmul nsz float %207, %211
>  %213 = fadd nsz float %212, %192
>  %214 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 520)
>  %215 = fmul nsz float %207, %214
>  %216 = fadd nsz float %215, %195
>  %217 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 524)
>  %218 = fmul nsz float %207, %217
>  %219 = fadd nsz float %218, %198
>  %220 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 400)
>  %221 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 404)
>  %222 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 408)
>  %223 = fmul nsz float %220, %116
>  %224 = fmul nsz float %221, %117
>  %225 = fadd nsz float %224, %223
>  %226 = fmul nsz float %222, %118
>  %227 = fadd nsz float %225, %226
>  %228 = call nsz float @llvm.maxnum.f32(float %227, float 0.000000e+00) #2
>  %229 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 528)
>  %230 = fmul nsz float %228, %229
>  %231 = fadd nsz float %230, %210
>  %232 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 532)
>  %233 = fmul nsz float %228, %232
>  %234 = fadd nsz float %233, %213
>  %235 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 536)
>  %236 = fmul nsz float %228, %235
>  %237 = fadd nsz float %236, %216
>  %238 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 540)
>  %239 = fmul nsz float %228, %238
>  %240 = fadd nsz float %239, %219
>  %241 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 416)
>  %242 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 420)
>  %243 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 424)
>  %244 = fmul nsz float %241, %116
>  %245 = fmul nsz float %242, %117
>  %246 = fadd nsz float %245, %244
>  %247 = fmul nsz float %243, %118
>  %248 = fadd nsz float %246, %247
>  %249 = call nsz float @llvm.maxnum.f32(float %248, float 0.000000e+00) #2
>  %250 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 544)
>  %251 = fmul nsz float %249, %250
>  %252 = fadd nsz float %251, %231
>  %253 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 548)
>  %254 = fmul nsz float %249, %253
>  %255 = fadd nsz float %254, %234
>  %256 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 552)
>  %257 = fmul nsz float %249, %256
>  %258 = fadd nsz float %257, %237
>  %259 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 556)
>  %260 = fmul nsz float %249, %259
>  %261 = fadd nsz float %260, %240
>  %262 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 432)
>  %263 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 436)
>  %264 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 440)
>  %265 = fmul nsz float %262, %116
>  %266 = fmul nsz float %263, %117
>  %267 = fadd nsz float %266, %265
>  %268 = fmul nsz float %264, %118
>  %269 = fadd nsz float %267, %268
>  %270 = call nsz float @llvm.maxnum.f32(float %269, float 0.000000e+00) #2
>  %271 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 560)
>  %272 = fmul nsz float %270, %271
>  %273 = fadd nsz float %272, %252
>  %274 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 564)
>  %275 = fmul nsz float %270, %274
>  %276 = fadd nsz float %275, %255
>  %277 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 568)
>  %278 = fmul nsz float %270, %277
>  %279 = fadd nsz float %278, %258
>  %280 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 572)
>  %281 = fmul nsz float %270, %280
>  %282 = fadd nsz float %281, %261
>  %283 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 448)
>  %284 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 452)
>  %285 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 456)
>  %286 = fmul nsz float %283, %116
>  %287 = fmul nsz float %284, %117
>  %288 = fadd nsz float %287, %286
>  %289 = fmul nsz float %285, %118
>  %290 = fadd nsz float %288, %289
>  %291 = call nsz float @llvm.maxnum.f32(float %290, float 0.000000e+00) #2
>  %292 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 576)
>  %293 = fmul nsz float %291, %292
>  %294 = fadd nsz float %293, %273
>  %295 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 580)
>  %296 = fmul nsz float %291, %295
>  %297 = fadd nsz float %296, %276
>  %298 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 584)
>  %299 = fmul nsz float %291, %298
>  %300 = fadd nsz float %299, %279
>  %301 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 588)
>  %302 = fmul nsz float %291, %301
>  %303 = fadd nsz float %302, %282
>  br label %loop46
>
>loop46:                                           ; preds = %endif50, %main_body
>  %304 = phi i32 [ 0, %main_body ], [ %353, %endif50 ]
>  %.010 = phi float [ %303, %main_body ], [ %352, %endif50 ]
>  %.09 = phi float [ %300, %main_body ], [ %350, %endif50 ]
>  %.08 = phi float [ %297, %main_body ], [ %348, %endif50 ]
>  %.0 = phi float [ %294, %main_body ], [ %346, %endif50 ]
>  %305 = icmp sgt i32 %304, 7
>  br i1 %305, label %endloop69, label %endif50
>
>endif50:                                          ; preds = %loop46
>  %306 = shl i32 %304, 4
>  %307 = add i32 %306, 592
>  %308 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %307)
>  %309 = add i32 %306, 596
>  %310 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %309)
>  %311 = add i32 %306, 600
>  %312 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %311)
>  %313 = add i32 %306, 604
>  %314 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %313)
>  %315 = add i32 %306, 720
>  %316 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %315)
>  %317 = add i32 %306, 724
>  %318 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %317)
>  %319 = add i32 %306, 728
>  %320 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %319)
>  %321 = add i32 %306, 732
>  %322 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %321)
>  %323 = fsub nsz float %135, %308
>  %324 = fsub nsz float %137, %310
>  %325 = fsub nsz float %139, %312
>  %326 = fmul nsz float %323, %323
>  %327 = fmul nsz float %324, %324
>  %328 = fadd nsz float %327, %326
>  %329 = fmul nsz float %325, %325
>  %330 = fadd nsz float %328, %329
>  %331 = call nsz float @llvm.sqrt.f32(float %330) #2
>  %332 = fdiv nsz float 1.000000e+00, %331, !fpmath !1
>  %333 = fmul nsz float %323, %332
>  %334 = fmul nsz float %324, %332
>  %335 = fmul nsz float %325, %332
>  %336 = fcmp nsz olt float %331, %314
>  %337 = select i1 %336, float 1.000000e+00, float 0.000000e+00
>  %338 = fmul nsz float %333, %116
>  %339 = fmul nsz float %334, %117
>  %340 = fadd nsz float %339, %338
>  %341 = fmul nsz float %335, %118
>  %342 = fadd nsz float %340, %341
>  %343 = call nsz float @llvm.maxnum.f32(float %342, float 0.000000e+00) #2
>  %344 = fmul nsz float %343, %337
>  %345 = fmul nsz float %344, %316
>  %346 = fadd nsz float %345, %.0
>  %347 = fmul nsz float %344, %318
>  %348 = fadd nsz float %347, %.08
>  %349 = fmul nsz float %344, %320
>  %350 = fadd nsz float %349, %.09
>  %351 = fmul nsz float %344, %322
>  %352 = fadd nsz float %351, %.010
>  %353 = add i32 %304, 1
>  br label %loop46
>
>endloop69:                                        ; preds = %loop46
>  %354 = fmul nsz float %.0, %36
>  %355 = fmul nsz float %.08, %37
>  %356 = fmul nsz float %.09, %38
>  %357 = fmul nsz float %.010, %39
>  %358 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %359 = fadd nsz float %354, %358
>  %360 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 324)
>  %361 = fadd nsz float %355, %360
>  %362 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 328)
>  %363 = fadd nsz float %356, %362
>  %364 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 332)
>  %365 = fadd nsz float %357, %364
>  %366 = call nsz float @llvm.minnum.f32(float %359, float 1.000000e+00) #2
>  %367 = call nsz float @llvm.minnum.f32(float %361, float 1.000000e+00) #2
>  %368 = call nsz float @llvm.minnum.f32(float %363, float 1.000000e+00) #2
>  %369 = call nsz float @llvm.minnum.f32(float %365, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %366, float %367, float %368, float %369, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float undef, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %75, float %77, float %79, float %81, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].xyz, GENERIC[1]
>DCL CONST[0..54]
>DCL TEMP[0..55], LOCAL
>DCL ADDR[0]
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>IMM[1] INT32 {0, 1, 2, 3}
>IMM[2] INT32 {4, 5, 6, 7}
>IMM[3] INT32 {8, 0, 0, 0}
>  0: MOV TEMP[0].w, IMM[0].xxxx
>  1: MOV TEMP[0].xyz, IN[0].xyzx
>  2: MUL TEMP[1], CONST[12], IN[0].xxxx
>  3: MAD TEMP[2], CONST[13], IN[0].yyyy, TEMP[1]
>  4: MAD TEMP[3], CONST[14], IN[0].zzzz, TEMP[2]
>  5: ADD TEMP[4], TEMP[3], CONST[15]
>  6: ADD TEMP[5].x, TEMP[4].zzzz, -CONST[20].xxxx
>  7: MUL TEMP[6].x, TEMP[5].xxxx, CONST[21].xxxx
>  8: MUL TEMP[7], CONST[16], IN[0].xxxx
>  9: MAD TEMP[8], CONST[17], IN[0].yyyy, TEMP[7]
> 10: MAD TEMP[9], CONST[18], IN[0].zzzz, TEMP[8]
> 11: ADD OUT[0], TEMP[9], CONST[19]
> 12: MOV OUT[1].x, IMM[0].xxxx
> 13: MOV TEMP[10].w, IMM[0].yyyy
> 14: MOV TEMP[10].xyz, IN[1].xyzx
> 15: MUL TEMP[11], CONST[8], IN[1].xxxx
> 16: MAD TEMP[12], CONST[9], IN[1].yyyy, TEMP[11]
> 17: MAD TEMP[13], CONST[10], IN[1].zzzz, TEMP[12]
> 18: DP3 TEMP[14].x, TEMP[13].xyzz, TEMP[13].xyzz
> 19: RSQ TEMP[15].x, TEMP[14].xxxx
> 20: MUL TEMP[16].xyz, TEMP[13].xyzz, TEMP[15].xxxx
> 21: MOV TEMP[17].xyz, -TEMP[16].xyzx
> 22: MUL TEMP[18], CONST[8], IN[0].xxxx
> 23: MAD TEMP[19], CONST[9], IN[0].yyyy, TEMP[18]
> 24: MAD TEMP[20], CONST[10], IN[0].zzzz, TEMP[19]
> 25: ADD TEMP[21], TEMP[20], CONST[11]
> 26: DP3 TEMP[22].x, TEMP[17].xyzz, CONST[23].xyzz
> 27: MAX TEMP[23].x, IMM[0].yyyy, TEMP[22].xxxx
> 28: MUL TEMP[24], TEMP[23].xxxx, CONST[31]
> 29: DP3 TEMP[25].x, TEMP[17].xyzz, CONST[24].xyzz
> 30: MAX TEMP[26].x, IMM[0].yyyy, TEMP[25].xxxx
> 31: MAD TEMP[24], TEMP[26].xxxx, CONST[32], TEMP[24]
> 32: DP3 TEMP[27].x, TEMP[17].xyzz, CONST[25].xyzz
> 33: MAX TEMP[28].x, IMM[0].yyyy, TEMP[27].xxxx
> 34: MAD TEMP[24], TEMP[28].xxxx, CONST[33], TEMP[24]
> 35: DP3 TEMP[29].x, TEMP[17].xyzz, CONST[26].xyzz
> 36: MAX TEMP[30].x, IMM[0].yyyy, TEMP[29].xxxx
> 37: MAD TEMP[24], TEMP[30].xxxx, CONST[34], TEMP[24]
> 38: DP3 TEMP[31].x, TEMP[17].xyzz, CONST[27].xyzz
> 39: MAX TEMP[32].x, IMM[0].yyyy, TEMP[31].xxxx
> 40: MAD TEMP[24], TEMP[32].xxxx, CONST[35], TEMP[24]
> 41: DP3 TEMP[33].x, TEMP[17].xyzz, CONST[28].xyzz
> 42: MAX TEMP[34].x, IMM[0].yyyy, TEMP[33].xxxx
> 43: MAD TEMP[24], TEMP[34].xxxx, CONST[36], TEMP[24]
> 44: DP3 TEMP[35].x, TEMP[17].xyzz, CONST[29].xyzz
> 45: MAX TEMP[36].x, IMM[0].yyyy, TEMP[35].xxxx
> 46: MAD TEMP[24], TEMP[36].xxxx, CONST[37], TEMP[24]
> 47: DP3 TEMP[37].x, TEMP[17].xyzz, CONST[30].xyzz
> 48: MAX TEMP[38].x, IMM[0].yyyy, TEMP[37].xxxx
> 49: MAD TEMP[24], TEMP[38].xxxx, CONST[38], TEMP[24]
> 50: MOV TEMP[39].x, IMM[3].xxxx
> 51: MOV TEMP[40].x, IMM[1].xxxx
> 52: BGNLOOP
> 53:   ISGE TEMP[41].x, TEMP[40].xxxx, IMM[3].xxxx
> 54:   UIF TEMP[41].xxxx
> 55:     BRK
> 56:   ENDIF
> 57:   UARL ADDR[0].x, TEMP[40].xxxx
> 58:   MOV TEMP[42], CONST[ADDR[0].x+39]
> 59:   UARL ADDR[0].x, TEMP[40].xxxx
> 60:   MOV TEMP[43], CONST[ADDR[0].x+47]
> 61:   ADD TEMP[44].xyz, TEMP[21].xyzz, -TEMP[42].xyzz
> 62:   DP3 TEMP[45].x, TEMP[44].xyzz, TEMP[44].xyzz
> 63:   SQRT TEMP[46].x, TEMP[45].xxxx
> 64:   RCP TEMP[47].x, TEMP[46].xxxx
> 65:   MUL TEMP[48].xyz, TEMP[44].xyzz, TEMP[47].xxxx
> 66:   FSLT TEMP[49].x, TEMP[46].xxxx, TEMP[42].wwww
> 67:   UCMP TEMP[50].x, TEMP[49].xxxx, IMM[0].xxxx, TEMP[50].xxxx
> 68:   NOT TEMP[51].x, TEMP[49].xxxx
> 69:   UCMP TEMP[50].x, TEMP[51].xxxx, IMM[0].yyyy, TEMP[50].xxxx
> 70:   DP3 TEMP[52].x, TEMP[17].xyzz, TEMP[48].xyzz
> 71:   MAX TEMP[53].x, IMM[0].yyyy, TEMP[52].xxxx
> 72:   MUL TEMP[54].x, TEMP[53].xxxx, TEMP[50].xxxx
> 73:   MAD TEMP[24], TEMP[54].xxxx, TEMP[43], TEMP[24]
> 74:   UADD TEMP[40].x, TEMP[40].xxxx, IMM[1].yyyy
> 75: ENDLOOP
> 76: MUL TEMP[24], TEMP[24], IN[3]
> 77: ADD TEMP[24], TEMP[24], CONST[22]
> 78: MIN TEMP[55], IMM[0].xxxx, TEMP[24]
> 79: MOV OUT[2], TEMP[55]
> 80: MOV OUT[3].xy, IN[2].xyxx
> 81: MOV OUT[3].z, TEMP[6].xxxx
> 82: END
>radeonsi: Compiling shader 20
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %17 = load <4 x i32>, <4 x i32> addrspace(2)* %16, align 16, !invariant.load !0
>  %18 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %17, i32 %12, i32 0, i1 false, i1 false) #2
>  %19 = extractelement <4 x float> %18, i32 0
>  %20 = extractelement <4 x float> %18, i32 1
>  %21 = extractelement <4 x float> %18, i32 2
>  %22 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %23 = load <4 x i32>, <4 x i32> addrspace(2)* %22, align 16, !invariant.load !0
>  %24 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %23, i32 %13, i32 0, i1 false, i1 false) #2
>  %25 = extractelement <4 x float> %24, i32 0
>  %26 = extractelement <4 x float> %24, i32 1
>  %27 = extractelement <4 x float> %24, i32 2
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 3, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %34, i32 %15, i32 0, i1 false, i1 false) #2
>  %36 = extractelement <4 x float> %35, i32 0
>  %37 = extractelement <4 x float> %35, i32 1
>  %38 = extractelement <4 x float> %35, i32 2
>  %39 = extractelement <4 x float> %35, i32 3
>  %40 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %41 = load <4 x i32>, <4 x i32> addrspace(2)* %40, align 16, !invariant.load !0
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 200)
>  %43 = fmul nsz float %42, %19
>  %44 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 216)
>  %45 = fmul nsz float %44, %20
>  %46 = fadd nsz float %45, %43
>  %47 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 232)
>  %48 = fmul nsz float %47, %21
>  %49 = fadd nsz float %48, %46
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 248)
>  %51 = fadd nsz float %49, %50
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 320)
>  %53 = fsub nsz float %51, %52
>  %54 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 336)
>  %55 = fmul nsz float %53, %54
>  %56 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 256)
>  %57 = fmul nsz float %56, %19
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 260)
>  %59 = fmul nsz float %58, %19
>  %60 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 264)
>  %61 = fmul nsz float %60, %19
>  %62 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 268)
>  %63 = fmul nsz float %62, %19
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 272)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %57
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 276)
>  %68 = fmul nsz float %67, %20
>  %69 = fadd nsz float %68, %59
>  %70 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 280)
>  %71 = fmul nsz float %70, %20
>  %72 = fadd nsz float %71, %61
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 284)
>  %74 = fmul nsz float %73, %20
>  %75 = fadd nsz float %74, %63
>  %76 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 288)
>  %77 = fmul nsz float %76, %21
>  %78 = fadd nsz float %77, %66
>  %79 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 292)
>  %80 = fmul nsz float %79, %21
>  %81 = fadd nsz float %80, %69
>  %82 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 296)
>  %83 = fmul nsz float %82, %21
>  %84 = fadd nsz float %83, %72
>  %85 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 300)
>  %86 = fmul nsz float %85, %21
>  %87 = fadd nsz float %86, %75
>  %88 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 304)
>  %89 = fadd nsz float %78, %88
>  %90 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 308)
>  %91 = fadd nsz float %81, %90
>  %92 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 312)
>  %93 = fadd nsz float %84, %92
>  %94 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 316)
>  %95 = fadd nsz float %87, %94
>  %96 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 128)
>  %97 = fmul nsz float %96, %25
>  %98 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 132)
>  %99 = fmul nsz float %98, %25
>  %100 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 136)
>  %101 = fmul nsz float %100, %25
>  %102 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 144)
>  %103 = fmul nsz float %102, %26
>  %104 = fadd nsz float %103, %97
>  %105 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 148)
>  %106 = fmul nsz float %105, %26
>  %107 = fadd nsz float %106, %99
>  %108 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 152)
>  %109 = fmul nsz float %108, %26
>  %110 = fadd nsz float %109, %101
>  %111 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 160)
>  %112 = fmul nsz float %111, %27
>  %113 = fadd nsz float %112, %104
>  %114 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 164)
>  %115 = fmul nsz float %114, %27
>  %116 = fadd nsz float %115, %107
>  %117 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 168)
>  %118 = fmul nsz float %117, %27
>  %119 = fadd nsz float %118, %110
>  %120 = fmul nsz float %113, %113
>  %121 = fmul nsz float %116, %116
>  %122 = fadd nsz float %121, %120
>  %123 = fmul nsz float %119, %119
>  %124 = fadd nsz float %122, %123
>  %125 = call nsz float @llvm.sqrt.f32(float %124) #2
>  %126 = fdiv nsz float 1.000000e+00, %125, !fpmath !1
>  %127 = fmul nsz float %113, %126
>  %128 = fmul nsz float %116, %126
>  %129 = fmul nsz float %119, %126
>  %130 = fsub nsz float -0.000000e+00, %127
>  %131 = fsub nsz float -0.000000e+00, %128
>  %132 = fsub nsz float -0.000000e+00, %129
>  %133 = fmul nsz float %96, %19
>  %134 = fmul nsz float %98, %19
>  %135 = fmul nsz float %100, %19
>  %136 = fmul nsz float %102, %20
>  %137 = fadd nsz float %136, %133
>  %138 = fmul nsz float %105, %20
>  %139 = fadd nsz float %138, %134
>  %140 = fmul nsz float %108, %20
>  %141 = fadd nsz float %140, %135
>  %142 = fmul nsz float %111, %21
>  %143 = fadd nsz float %142, %137
>  %144 = fmul nsz float %114, %21
>  %145 = fadd nsz float %144, %139
>  %146 = fmul nsz float %117, %21
>  %147 = fadd nsz float %146, %141
>  %148 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 176)
>  %149 = fadd nsz float %143, %148
>  %150 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 180)
>  %151 = fadd nsz float %145, %150
>  %152 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 184)
>  %153 = fadd nsz float %147, %152
>  %154 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 368)
>  %155 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 372)
>  %156 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 376)
>  %157 = fmul nsz float %154, %130
>  %158 = fmul nsz float %155, %131
>  %159 = fadd nsz float %158, %157
>  %160 = fmul nsz float %156, %132
>  %161 = fadd nsz float %159, %160
>  %162 = call nsz float @llvm.maxnum.f32(float %161, float 0.000000e+00) #2
>  %163 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 496)
>  %164 = fmul nsz float %162, %163
>  %165 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 500)
>  %166 = fmul nsz float %162, %165
>  %167 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 504)
>  %168 = fmul nsz float %162, %167
>  %169 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 508)
>  %170 = fmul nsz float %162, %169
>  %171 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 384)
>  %172 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 388)
>  %173 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 392)
>  %174 = fmul nsz float %171, %130
>  %175 = fmul nsz float %172, %131
>  %176 = fadd nsz float %175, %174
>  %177 = fmul nsz float %173, %132
>  %178 = fadd nsz float %176, %177
>  %179 = call nsz float @llvm.maxnum.f32(float %178, float 0.000000e+00) #2
>  %180 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 512)
>  %181 = fmul nsz float %179, %180
>  %182 = fadd nsz float %181, %164
>  %183 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 516)
>  %184 = fmul nsz float %179, %183
>  %185 = fadd nsz float %184, %166
>  %186 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 520)
>  %187 = fmul nsz float %179, %186
>  %188 = fadd nsz float %187, %168
>  %189 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 524)
>  %190 = fmul nsz float %179, %189
>  %191 = fadd nsz float %190, %170
>  %192 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 400)
>  %193 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 404)
>  %194 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 408)
>  %195 = fmul nsz float %192, %130
>  %196 = fmul nsz float %193, %131
>  %197 = fadd nsz float %196, %195
>  %198 = fmul nsz float %194, %132
>  %199 = fadd nsz float %197, %198
>  %200 = call nsz float @llvm.maxnum.f32(float %199, float 0.000000e+00) #2
>  %201 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 528)
>  %202 = fmul nsz float %200, %201
>  %203 = fadd nsz float %202, %182
>  %204 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 532)
>  %205 = fmul nsz float %200, %204
>  %206 = fadd nsz float %205, %185
>  %207 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 536)
>  %208 = fmul nsz float %200, %207
>  %209 = fadd nsz float %208, %188
>  %210 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 540)
>  %211 = fmul nsz float %200, %210
>  %212 = fadd nsz float %211, %191
>  %213 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 416)
>  %214 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 420)
>  %215 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 424)
>  %216 = fmul nsz float %213, %130
>  %217 = fmul nsz float %214, %131
>  %218 = fadd nsz float %217, %216
>  %219 = fmul nsz float %215, %132
>  %220 = fadd nsz float %218, %219
>  %221 = call nsz float @llvm.maxnum.f32(float %220, float 0.000000e+00) #2
>  %222 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 544)
>  %223 = fmul nsz float %221, %222
>  %224 = fadd nsz float %223, %203
>  %225 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 548)
>  %226 = fmul nsz float %221, %225
>  %227 = fadd nsz float %226, %206
>  %228 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 552)
>  %229 = fmul nsz float %221, %228
>  %230 = fadd nsz float %229, %209
>  %231 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 556)
>  %232 = fmul nsz float %221, %231
>  %233 = fadd nsz float %232, %212
>  %234 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 432)
>  %235 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 436)
>  %236 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 440)
>  %237 = fmul nsz float %234, %130
>  %238 = fmul nsz float %235, %131
>  %239 = fadd nsz float %238, %237
>  %240 = fmul nsz float %236, %132
>  %241 = fadd nsz float %239, %240
>  %242 = call nsz float @llvm.maxnum.f32(float %241, float 0.000000e+00) #2
>  %243 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 560)
>  %244 = fmul nsz float %242, %243
>  %245 = fadd nsz float %244, %224
>  %246 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 564)
>  %247 = fmul nsz float %242, %246
>  %248 = fadd nsz float %247, %227
>  %249 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 568)
>  %250 = fmul nsz float %242, %249
>  %251 = fadd nsz float %250, %230
>  %252 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 572)
>  %253 = fmul nsz float %242, %252
>  %254 = fadd nsz float %253, %233
>  %255 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 448)
>  %256 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 452)
>  %257 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 456)
>  %258 = fmul nsz float %255, %130
>  %259 = fmul nsz float %256, %131
>  %260 = fadd nsz float %259, %258
>  %261 = fmul nsz float %257, %132
>  %262 = fadd nsz float %260, %261
>  %263 = call nsz float @llvm.maxnum.f32(float %262, float 0.000000e+00) #2
>  %264 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 576)
>  %265 = fmul nsz float %263, %264
>  %266 = fadd nsz float %265, %245
>  %267 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 580)
>  %268 = fmul nsz float %263, %267
>  %269 = fadd nsz float %268, %248
>  %270 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 584)
>  %271 = fmul nsz float %263, %270
>  %272 = fadd nsz float %271, %251
>  %273 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 588)
>  %274 = fmul nsz float %263, %273
>  %275 = fadd nsz float %274, %254
>  %276 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 464)
>  %277 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 468)
>  %278 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 472)
>  %279 = fmul nsz float %276, %130
>  %280 = fmul nsz float %277, %131
>  %281 = fadd nsz float %280, %279
>  %282 = fmul nsz float %278, %132
>  %283 = fadd nsz float %281, %282
>  %284 = call nsz float @llvm.maxnum.f32(float %283, float 0.000000e+00) #2
>  %285 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 592)
>  %286 = fmul nsz float %284, %285
>  %287 = fadd nsz float %286, %266
>  %288 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 596)
>  %289 = fmul nsz float %284, %288
>  %290 = fadd nsz float %289, %269
>  %291 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 600)
>  %292 = fmul nsz float %284, %291
>  %293 = fadd nsz float %292, %272
>  %294 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 604)
>  %295 = fmul nsz float %284, %294
>  %296 = fadd nsz float %295, %275
>  %297 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 480)
>  %298 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 484)
>  %299 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 488)
>  %300 = fmul nsz float %297, %130
>  %301 = fmul nsz float %298, %131
>  %302 = fadd nsz float %301, %300
>  %303 = fmul nsz float %299, %132
>  %304 = fadd nsz float %302, %303
>  %305 = call nsz float @llvm.maxnum.f32(float %304, float 0.000000e+00) #2
>  %306 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 608)
>  %307 = fmul nsz float %305, %306
>  %308 = fadd nsz float %307, %287
>  %309 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 612)
>  %310 = fmul nsz float %305, %309
>  %311 = fadd nsz float %310, %290
>  %312 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 616)
>  %313 = fmul nsz float %305, %312
>  %314 = fadd nsz float %313, %293
>  %315 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 620)
>  %316 = fmul nsz float %305, %315
>  %317 = fadd nsz float %316, %296
>  br label %loop52
>
>loop52:                                           ; preds = %endif56, %main_body
>  %318 = phi i32 [ 0, %main_body ], [ %367, %endif56 ]
>  %.010 = phi float [ %317, %main_body ], [ %366, %endif56 ]
>  %.09 = phi float [ %314, %main_body ], [ %364, %endif56 ]
>  %.08 = phi float [ %311, %main_body ], [ %362, %endif56 ]
>  %.0 = phi float [ %308, %main_body ], [ %360, %endif56 ]
>  %319 = icmp sgt i32 %318, 7
>  br i1 %319, label %endloop75, label %endif56
>
>endif56:                                          ; preds = %loop52
>  %320 = shl i32 %318, 4
>  %321 = add i32 %320, 624
>  %322 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %321)
>  %323 = add i32 %320, 628
>  %324 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %323)
>  %325 = add i32 %320, 632
>  %326 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %325)
>  %327 = add i32 %320, 636
>  %328 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %327)
>  %329 = add i32 %320, 752
>  %330 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %329)
>  %331 = add i32 %320, 756
>  %332 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %331)
>  %333 = add i32 %320, 760
>  %334 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %333)
>  %335 = add i32 %320, 764
>  %336 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 %335)
>  %337 = fsub nsz float %149, %322
>  %338 = fsub nsz float %151, %324
>  %339 = fsub nsz float %153, %326
>  %340 = fmul nsz float %337, %337
>  %341 = fmul nsz float %338, %338
>  %342 = fadd nsz float %341, %340
>  %343 = fmul nsz float %339, %339
>  %344 = fadd nsz float %342, %343
>  %345 = call nsz float @llvm.sqrt.f32(float %344) #2
>  %346 = fdiv nsz float 1.000000e+00, %345, !fpmath !1
>  %347 = fmul nsz float %337, %346
>  %348 = fmul nsz float %338, %346
>  %349 = fmul nsz float %339, %346
>  %350 = fcmp nsz olt float %345, %328
>  %351 = select i1 %350, float 1.000000e+00, float 0.000000e+00
>  %352 = fmul nsz float %347, %130
>  %353 = fmul nsz float %348, %131
>  %354 = fadd nsz float %353, %352
>  %355 = fmul nsz float %349, %132
>  %356 = fadd nsz float %354, %355
>  %357 = call nsz float @llvm.maxnum.f32(float %356, float 0.000000e+00) #2
>  %358 = fmul nsz float %357, %351
>  %359 = fmul nsz float %358, %330
>  %360 = fadd nsz float %359, %.0
>  %361 = fmul nsz float %358, %332
>  %362 = fadd nsz float %361, %.08
>  %363 = fmul nsz float %358, %334
>  %364 = fadd nsz float %363, %.09
>  %365 = fmul nsz float %358, %336
>  %366 = fadd nsz float %365, %.010
>  %367 = add i32 %318, 1
>  br label %loop52
>
>endloop75:                                        ; preds = %loop52
>  %368 = fmul nsz float %.0, %36
>  %369 = fmul nsz float %.08, %37
>  %370 = fmul nsz float %.09, %38
>  %371 = fmul nsz float %.010, %39
>  %372 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 352)
>  %373 = fadd nsz float %368, %372
>  %374 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 356)
>  %375 = fadd nsz float %369, %374
>  %376 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 360)
>  %377 = fadd nsz float %370, %376
>  %378 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %41, i32 364)
>  %379 = fadd nsz float %371, %378
>  %380 = call nsz float @llvm.minnum.f32(float %373, float 1.000000e+00) #2
>  %381 = call nsz float @llvm.minnum.f32(float %375, float 1.000000e+00) #2
>  %382 = call nsz float @llvm.minnum.f32(float %377, float 1.000000e+00) #2
>  %383 = call nsz float @llvm.minnum.f32(float %379, float 1.000000e+00) #2
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %380, float %381, float %382, float %383, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float %55, float undef, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %89, float %91, float %93, float %95, i1 false, i1 false) #4
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #4
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.sqrt.f32(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #3
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #4
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind readnone speculatable }
>attributes #4 = { nounwind }
>
>!0 = !{}
>!1 = !{float 2.500000e+00}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL CONST[0..19]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1].x, IMM[0].xxxx
>  5: MOV OUT[2], IN[1]
>  6: END
>radeonsi: Compiling shader 21
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %14 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %15 = load <4 x i32>, <4 x i32> addrspace(2)* %14, align 16, !invariant.load !0
>  %16 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %15, i32 %12, i32 0, i1 false, i1 false) #2
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = extractelement <4 x float> %16, i32 1
>  %19 = extractelement <4 x float> %16, i32 2
>  %20 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %21 = load <4 x i32>, <4 x i32> addrspace(2)* %20, align 16, !invariant.load !0
>  %22 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %21, i32 %13, i32 0, i1 false, i1 false) #2
>  %23 = extractelement <4 x float> %22, i32 0
>  %24 = extractelement <4 x float> %22, i32 1
>  %25 = extractelement <4 x float> %22, i32 2
>  %26 = extractelement <4 x float> %22, i32 3
>  %27 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %28 = load <4 x i32>, <4 x i32> addrspace(2)* %27, align 16, !invariant.load !0
>  %29 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 256)
>  %30 = fmul nsz float %29, %17
>  %31 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 260)
>  %32 = fmul nsz float %31, %17
>  %33 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 264)
>  %34 = fmul nsz float %33, %17
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 268)
>  %36 = fmul nsz float %35, %17
>  %37 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 272)
>  %38 = fmul nsz float %37, %18
>  %39 = fadd nsz float %38, %30
>  %40 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 276)
>  %41 = fmul nsz float %40, %18
>  %42 = fadd nsz float %41, %32
>  %43 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 280)
>  %44 = fmul nsz float %43, %18
>  %45 = fadd nsz float %44, %34
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 284)
>  %47 = fmul nsz float %46, %18
>  %48 = fadd nsz float %47, %36
>  %49 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 288)
>  %50 = fmul nsz float %49, %19
>  %51 = fadd nsz float %50, %39
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 292)
>  %53 = fmul nsz float %52, %19
>  %54 = fadd nsz float %53, %42
>  %55 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 296)
>  %56 = fmul nsz float %55, %19
>  %57 = fadd nsz float %56, %45
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 300)
>  %59 = fmul nsz float %58, %19
>  %60 = fadd nsz float %59, %48
>  %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 304)
>  %62 = fadd nsz float %51, %61
>  %63 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 308)
>  %64 = fadd nsz float %54, %63
>  %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 312)
>  %66 = fadd nsz float %57, %65
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 316)
>  %68 = fadd nsz float %60, %67
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %23, float %24, float %25, float %26, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %62, float %64, float %66, float %68, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #3
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #3
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>radeonsi: Compiling shader 22
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %6 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #2
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 0, i32 %4) #2
>  %26 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #2
>  %27 = call nsz float @llvm.amdgcn.interp.p2(float %26, float %23, i32 1, i32 0, i32 %4) #2
>  %28 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 0, i32 %4) #2
>  %29 = call nsz float @llvm.amdgcn.interp.p2(float %28, float %23, i32 2, i32 0, i32 %4) #2
>  %30 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 3, i32 0, i32 %4) #2
>  %31 = call nsz float @llvm.amdgcn.interp.p2(float %30, float %23, i32 3, i32 0, i32 %4) #2
>  %32 = bitcast float %3 to i32
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %32, 6
>  %34 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %33, float %25, 7
>  %35 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %34, float %27, 8
>  %36 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %35, float %29, 9
>  %37 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %36, float %31, 10
>  %38 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readnone }
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1].x, PSIZE
>DCL OUT[2], GENERIC[0]
>DCL OUT[3].x, GENERIC[1]
>DCL CONST[0..21]
>DCL TEMP[0..7], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1].x, IMM[0].xxxx
>  5: MOV OUT[2], IN[1]
>  6: MUL TEMP[3], CONST[12], IN[0].xxxx
>  7: MAD TEMP[4], CONST[13], IN[0].yyyy, TEMP[3]
>  8: MAD TEMP[5], CONST[14], IN[0].zzzz, TEMP[4]
>  9: ADD TEMP[6].z, TEMP[5], CONST[15]
> 10: ADD TEMP[7].x, TEMP[6].zzzz, -CONST[20].xxxx
> 11: MUL OUT[3].x, TEMP[7].xxxx, CONST[21].xxxx
> 12: END
>radeonsi: Compiling shader 23
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %14 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %15 = load <4 x i32>, <4 x i32> addrspace(2)* %14, align 16, !invariant.load !0
>  %16 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %15, i32 %12, i32 0, i1 false, i1 false) #2
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = extractelement <4 x float> %16, i32 1
>  %19 = extractelement <4 x float> %16, i32 2
>  %20 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %21 = load <4 x i32>, <4 x i32> addrspace(2)* %20, align 16, !invariant.load !0
>  %22 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %21, i32 %13, i32 0, i1 false, i1 false) #2
>  %23 = extractelement <4 x float> %22, i32 0
>  %24 = extractelement <4 x float> %22, i32 1
>  %25 = extractelement <4 x float> %22, i32 2
>  %26 = extractelement <4 x float> %22, i32 3
>  %27 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %28 = load <4 x i32>, <4 x i32> addrspace(2)* %27, align 16, !invariant.load !0
>  %29 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 256)
>  %30 = fmul nsz float %29, %17
>  %31 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 260)
>  %32 = fmul nsz float %31, %17
>  %33 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 264)
>  %34 = fmul nsz float %33, %17
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 268)
>  %36 = fmul nsz float %35, %17
>  %37 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 272)
>  %38 = fmul nsz float %37, %18
>  %39 = fadd nsz float %38, %30
>  %40 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 276)
>  %41 = fmul nsz float %40, %18
>  %42 = fadd nsz float %41, %32
>  %43 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 280)
>  %44 = fmul nsz float %43, %18
>  %45 = fadd nsz float %44, %34
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 284)
>  %47 = fmul nsz float %46, %18
>  %48 = fadd nsz float %47, %36
>  %49 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 288)
>  %50 = fmul nsz float %49, %19
>  %51 = fadd nsz float %50, %39
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 292)
>  %53 = fmul nsz float %52, %19
>  %54 = fadd nsz float %53, %42
>  %55 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 296)
>  %56 = fmul nsz float %55, %19
>  %57 = fadd nsz float %56, %45
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 300)
>  %59 = fmul nsz float %58, %19
>  %60 = fadd nsz float %59, %48
>  %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 304)
>  %62 = fadd nsz float %51, %61
>  %63 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 308)
>  %64 = fadd nsz float %54, %63
>  %65 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 312)
>  %66 = fadd nsz float %57, %65
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 316)
>  %68 = fadd nsz float %60, %67
>  %69 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 200)
>  %70 = fmul nsz float %69, %17
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 216)
>  %72 = fmul nsz float %71, %18
>  %73 = fadd nsz float %72, %70
>  %74 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 232)
>  %75 = fmul nsz float %74, %19
>  %76 = fadd nsz float %75, %73
>  %77 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 248)
>  %78 = fadd nsz float %76, %77
>  %79 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 320)
>  %80 = fsub nsz float %78, %79
>  %81 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %28, i32 336)
>  %82 = fmul nsz float %80, %81
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %23, float %24, float %25, float %26, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %82, float undef, float undef, float undef, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %62, float %64, float %66, float %68, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 1, float 1.000000e+00, float undef, float undef, float undef, i1 true, i1 false) #3
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #3
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1].x, GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0]
>DCL TEMP[0..1], LOCAL
>  0: MOV_SAT TEMP[0].x, IN[1].xxxx
>  1: LRP TEMP[1].xyz, TEMP[0].xxxx, CONST[0].xyzz, IN[0].xyzz
>  2: MOV TEMP[1].w, IN[0].wwww
>  3: MOV OUT[0], TEMP[1]
>  4: END
>radeonsi: Compiling shader 24
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %6 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 1, i32 %4) #2
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 1, i32 %4) #2
>  %26 = call nsz float @llvm.maxnum.f32(float %25, float 0.000000e+00) #2
>  %27 = call nsz float @llvm.minnum.f32(float %26, float 1.000000e+00) #2
>  %28 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 0)
>  %31 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #2
>  %32 = call nsz float @llvm.amdgcn.interp.p2(float %31, float %23, i32 0, i32 0, i32 %4) #2
>  %33 = fsub nsz float 1.000000e+00, %27
>  %34 = fmul nsz float %30, %27
>  %35 = fmul nsz float %32, %33
>  %36 = fadd nsz float %34, %35
>  %37 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 4)
>  %38 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #2
>  %39 = call nsz float @llvm.amdgcn.interp.p2(float %38, float %23, i32 1, i32 0, i32 %4) #2
>  %40 = fmul nsz float %37, %27
>  %41 = fmul nsz float %39, %33
>  %42 = fadd nsz float %40, %41
>  %43 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %29, i32 8)
>  %44 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 0, i32 %4) #2
>  %45 = call nsz float @llvm.amdgcn.interp.p2(float %44, float %23, i32 2, i32 0, i32 %4) #2
>  %46 = fmul nsz float %43, %27
>  %47 = fmul nsz float %45, %33
>  %48 = fadd nsz float %46, %47
>  %49 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 3, i32 0, i32 %4) #2
>  %50 = call nsz float @llvm.amdgcn.interp.p2(float %49, float %23, i32 3, i32 0, i32 %4) #2
>  %51 = bitcast float %3 to i32
>  %52 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %51, 6
>  %53 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %52, float %36, 7
>  %54 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %53, float %42, 8
>  %55 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %54, float %48, 9
>  %56 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %55, float %50, 10
>  %57 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %56, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %57
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readnone }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0]
>DCL TEMP[0..1], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: FSGE TEMP[0].x, CONST[0].xxxx, IN[0].wwww
>  1: AND TEMP[1].x, TEMP[0].xxxx, IMM[0].xxxx
>  2: KILL_IF -TEMP[1].xxxx
>  3: MOV OUT[0], IN[0]
>  4: END
>radeonsi: Compiling shader 25
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %22, i32 0)
>  %24 = bitcast <2 x i32> %6 to <2 x float>
>  %25 = extractelement <2 x float> %24, i32 0
>  %26 = extractelement <2 x float> %24, i32 1
>  %27 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 3, i32 0, i32 %4) #1
>  %28 = call nsz float @llvm.amdgcn.interp.p2(float %27, float %26, i32 3, i32 0, i32 %4) #1
>  %29 = fcmp nsz oge float %23, %28
>  %30 = select i1 %29, float -1.000000e+00, float 0.000000e+00
>  call void @llvm.AMDGPU.kill(float %30)
>  %31 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 0, i32 0, i32 %4) #1
>  %32 = call nsz float @llvm.amdgcn.interp.p2(float %31, float %26, i32 0, i32 0, i32 %4) #1
>  %33 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 1, i32 0, i32 %4) #1
>  %34 = call nsz float @llvm.amdgcn.interp.p2(float %33, float %26, i32 1, i32 0, i32 %4) #1
>  %35 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 2, i32 0, i32 %4) #1
>  %36 = call nsz float @llvm.amdgcn.interp.p2(float %35, float %26, i32 2, i32 0, i32 %4) #1
>  %37 = bitcast float %3 to i32
>  %38 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %37, 6
>  %39 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %32, 7
>  %40 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 8
>  %41 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %40, float %36, 9
>  %42 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %41, float %28, 10
>  %43 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %42, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %43
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.AMDGPU.kill(float) #3
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readnone speculatable }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1].x, GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL CONST[0..1]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: FSGE TEMP[0].x, CONST[1].xxxx, IN[0].wwww
>  1: AND TEMP[1].x, TEMP[0].xxxx, IMM[0].xxxx
>  2: KILL_IF -TEMP[1].xxxx
>  3: MOV_SAT TEMP[2].x, IN[1].xxxx
>  4: LRP TEMP[3].xyz, TEMP[2].xxxx, CONST[0].xyzz, IN[0].xyzz
>  5: MOV TEMP[3].w, IN[0].wwww
>  6: MOV OUT[0], TEMP[3]
>  7: END
>radeonsi: Compiling shader 26
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %22, i32 16)
>  %24 = bitcast <2 x i32> %6 to <2 x float>
>  %25 = extractelement <2 x float> %24, i32 0
>  %26 = extractelement <2 x float> %24, i32 1
>  %27 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 3, i32 0, i32 %4) #1
>  %28 = call nsz float @llvm.amdgcn.interp.p2(float %27, float %26, i32 3, i32 0, i32 %4) #1
>  %29 = fcmp nsz oge float %23, %28
>  %30 = select i1 %29, float -1.000000e+00, float 0.000000e+00
>  call void @llvm.AMDGPU.kill(float %30)
>  %31 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 0, i32 1, i32 %4) #1
>  %32 = call nsz float @llvm.amdgcn.interp.p2(float %31, float %26, i32 0, i32 1, i32 %4) #1
>  %33 = call nsz float @llvm.maxnum.f32(float %32, float 0.000000e+00) #1
>  %34 = call nsz float @llvm.minnum.f32(float %33, float 1.000000e+00) #1
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %22, i32 0)
>  %36 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 0, i32 0, i32 %4) #1
>  %37 = call nsz float @llvm.amdgcn.interp.p2(float %36, float %26, i32 0, i32 0, i32 %4) #1
>  %38 = fsub nsz float 1.000000e+00, %34
>  %39 = fmul nsz float %35, %34
>  %40 = fmul nsz float %37, %38
>  %41 = fadd nsz float %39, %40
>  %42 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %22, i32 4)
>  %43 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 1, i32 0, i32 %4) #1
>  %44 = call nsz float @llvm.amdgcn.interp.p2(float %43, float %26, i32 1, i32 0, i32 %4) #1
>  %45 = fmul nsz float %42, %34
>  %46 = fmul nsz float %44, %38
>  %47 = fadd nsz float %45, %46
>  %48 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %22, i32 8)
>  %49 = call nsz float @llvm.amdgcn.interp.p1(float %25, i32 2, i32 0, i32 %4) #1
>  %50 = call nsz float @llvm.amdgcn.interp.p2(float %49, float %26, i32 2, i32 0, i32 %4) #1
>  %51 = fmul nsz float %48, %34
>  %52 = fmul nsz float %50, %38
>  %53 = fadd nsz float %51, %52
>  %54 = bitcast float %3 to i32
>  %55 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %54, 6
>  %56 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %55, float %41, 7
>  %57 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %56, float %47, 8
>  %58 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %57, float %53, 9
>  %59 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %58, float %28, 10
>  %60 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %59, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %60
>}
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.AMDGPU.kill(float) #3
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.maxnum.f32(float, float) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.minnum.f32(float, float) #2
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone }
>attributes #2 = { nounwind readnone speculatable }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>Texture #1 16,16
>Texture #2 16,16
>SHADER KEY
>  part.vs.prolog.instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  mono.u.vs_export_prim_id = 0
>  opt.hw_vs.kill_outputs = 0x0
>  opt.hw_vs.clip_disable = 0
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s8, v0 ; 32080008
>	v_mov_b32_e32 v5, v4          ; 7E0A0304
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[6:7], 0x0                  ; C00A0003 00000000
>	s_load_dwordx4 s[4:7], s[6:7], 0x10                 ; C00A0103 00000010
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	buffer_load_format_xyzw v[0:3], v5, s[4:7], 0 idxen ; E00C2000 80010005
>	buffer_load_format_xyzw v[4:7], v4, s[0:3], 0 idxen ; E00C2000 80000404
>	s_waitcnt vmcnt(1)                                  ; BF8C0F71
>	exp param0 v0, v1, v2, v3                           ; C400020F 03020100
>	s_waitcnt vmcnt(0)                                  ; BF8C0F70
>	exp pos0 v4, v5, v6, v7 done                        ; C40008CF 07060504
>	s_endpgm                                            ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 16
>VGPRS: 8
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 72 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>	s_mov_b32 m0, s7                 ; BEFC0007
>	v_interp_mov_f32 v0, p0, attr0.x ; D4020002
>	v_interp_mov_f32 v1, p0, attr0.y ; D4060102
>	v_interp_mov_f32 v2, p0, attr0.z ; D40A0202
>	v_interp_mov_f32 v3, p0, attr0.w ; D40E0302
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32 v0, v0, v1        ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32 v1, v2, v3        ; D2960001 00020702
>	exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100
>	s_endpgm                              ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0020
>*** SHADER STATS ***
>SGPRS: 10
>VGPRS: 16
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 48 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>Check TextureID
>finished(2)!!
>Background_InitTextures()
>Sprite_InitTextures()
>Font_InitTextures()
>IO Init
>Process Messages
>Splash!
>Start Frame
>Part Create Textures
>Debug Init Remote Interface
>VM Init
>Create Score Form
>Create Load Form
>Create Error Form
>Do The Work
>LoadGameData()
>initialise everything!
>Process Chunk: GEN8   720
>Process Chunk: OPTN   64
>Process Chunk: LANG   12
>Process Chunk: EXTN   4
>Process Chunk: SOND   39244
>Audio_Load()
>Process Chunk: AGRP   4
>AudioGroup_Load()
>Process Chunk: SPRT   5940876
>Process Chunk: BGND   2236
>Process Chunk: PATH   196
>Process Chunk: SCPT   5632
>Process Chunk: GLOB   4
>Process Chunk: SHDR   228
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2].xy, GENERIC[1]
>DCL CONST[0..19]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[2].xy, IN[2].xyxx
>  5: MOV OUT[1], IN[1]
>  6: END
>radeonsi: Compiling shader 27
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %15 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <4 x i32>, <4 x i32> addrspace(2)* %15, align 16, !invariant.load !0
>  %17 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %16, i32 %12, i32 0, i1 false, i1 false) #2
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = extractelement <4 x float> %17, i32 1
>  %20 = extractelement <4 x float> %17, i32 2
>  %21 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %22, i32 %13, i32 0, i1 false, i1 false) #2
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = extractelement <4 x float> %23, i32 2
>  %27 = extractelement <4 x float> %23, i32 3
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 256)
>  %36 = fmul nsz float %35, %18
>  %37 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 260)
>  %38 = fmul nsz float %37, %18
>  %39 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 264)
>  %40 = fmul nsz float %39, %18
>  %41 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 268)
>  %42 = fmul nsz float %41, %18
>  %43 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 272)
>  %44 = fmul nsz float %43, %19
>  %45 = fadd nsz float %44, %36
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 276)
>  %47 = fmul nsz float %46, %19
>  %48 = fadd nsz float %47, %38
>  %49 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 280)
>  %50 = fmul nsz float %49, %19
>  %51 = fadd nsz float %50, %40
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 284)
>  %53 = fmul nsz float %52, %19
>  %54 = fadd nsz float %53, %42
>  %55 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 288)
>  %56 = fmul nsz float %55, %20
>  %57 = fadd nsz float %56, %45
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 292)
>  %59 = fmul nsz float %58, %20
>  %60 = fadd nsz float %59, %48
>  %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 296)
>  %62 = fmul nsz float %61, %20
>  %63 = fadd nsz float %62, %51
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 300)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %54
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 304)
>  %68 = fadd nsz float %57, %67
>  %69 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 308)
>  %70 = fadd nsz float %60, %69
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 312)
>  %72 = fadd nsz float %63, %71
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 316)
>  %74 = fadd nsz float %66, %73
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %24, float %25, float %26, float %27, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float undef, float undef, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %68, float %70, float %72, float %74, i1 true, i1 false) #3
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #3
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>FRAG
>PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1
>DCL IN[0], GENERIC[0], PERSPECTIVE
>DCL IN[1].xy, GENERIC[1], PERSPECTIVE
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL CONST[1]
>DCL TEMP[0..3], LOCAL
>IMM[0] FLT32 {    0.2990,     0.5870,     0.1140,     0.0000}
>  0: MOV TEMP[0].xy, IN[1].xyyy
>  1: TEX TEMP[1], TEMP[0], SAMP[0], 2D
>  2: DP3 TEMP[2].x, TEMP[1].xyzz, IMM[0].xyzz
>  3: LRP TEMP[3].xyz, CONST[1].xxxx, TEMP[2].xxxx, TEMP[1].xyzz
>  4: MOV TEMP[3].w, TEMP[1].wwww
>  5: MUL OUT[0], IN[0], TEMP[3]
>  6: END
>radeonsi: Compiling shader 28
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %6 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 1, i32 %4) #3
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 1, i32 %4) #3
>  %26 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 1, i32 %4) #3
>  %27 = call nsz float @llvm.amdgcn.interp.p2(float %26, float %23, i32 1, i32 1, i32 %4) #3
>  %28 = getelementptr [80 x <8 x i32>], [80 x <8 x i32>] addrspace(2)* %2, i64 0, i64 16, !amdgpu.uniform !0
>  %29 = load <8 x i32>, <8 x i32> addrspace(2)* %28, align 32, !invariant.load !0
>  %30 = bitcast [80 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %31 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %30, i64 0, i64 35, !amdgpu.uniform !0
>  %32 = load <4 x i32>, <4 x i32> addrspace(2)* %31, align 16, !invariant.load !0
>  %33 = bitcast float %25 to i32
>  %34 = bitcast float %27 to i32
>  %35 = insertelement <2 x i32> undef, i32 %33, i32 0
>  %36 = insertelement <2 x i32> %35, i32 %34, i32 1
>  %37 = bitcast <2 x i32> %36 to <2 x float>
>  %38 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> %37, <8 x i32> %29, <4 x i32> %32, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #3
>  %39 = extractelement <4 x float> %38, i32 0
>  %40 = extractelement <4 x float> %38, i32 1
>  %41 = extractelement <4 x float> %38, i32 2
>  %42 = extractelement <4 x float> %38, i32 3
>  %43 = fmul nsz float %39, 0x3FD322D0E0000000
>  %44 = fmul nsz float %40, 0x3FE2C8B440000000
>  %45 = fadd nsz float %44, %43
>  %46 = fmul nsz float %41, 0x3FBD2F1AA0000000
>  %47 = fadd nsz float %45, %46
>  %48 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %49 = load <4 x i32>, <4 x i32> addrspace(2)* %48, align 16, !invariant.load !0
>  %50 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %49, i32 16)
>  %51 = fsub nsz float 1.000000e+00, %50
>  %52 = fmul nsz float %47, %50
>  %53 = fmul nsz float %39, %51
>  %54 = fadd nsz float %52, %53
>  %55 = fmul nsz float %40, %51
>  %56 = fadd nsz float %52, %55
>  %57 = fmul nsz float %41, %51
>  %58 = fadd nsz float %52, %57
>  %59 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #3
>  %60 = call nsz float @llvm.amdgcn.interp.p2(float %59, float %23, i32 0, i32 0, i32 %4) #3
>  %61 = fmul nsz float %60, %54
>  %62 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #3
>  %63 = call nsz float @llvm.amdgcn.interp.p2(float %62, float %23, i32 1, i32 0, i32 %4) #3
>  %64 = fmul nsz float %63, %56
>  %65 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 2, i32 0, i32 %4) #3
>  %66 = call nsz float @llvm.amdgcn.interp.p2(float %65, float %23, i32 2, i32 0, i32 %4) #3
>  %67 = fmul nsz float %66, %58
>  %68 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 3, i32 0, i32 %4) #3
>  %69 = call nsz float @llvm.amdgcn.interp.p2(float %68, float %23, i32 3, i32 0, i32 %4) #3
>  %70 = fmul nsz float %69, %42
>  %71 = bitcast float %3 to i32
>  %72 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %71, 6
>  %73 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %72, float %61, 7
>  %74 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %73, float %64, 8
>  %75 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %74, float %67, 9
>  %76 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %75, float %70, 10
>  %77 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %76, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %77
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1) #2
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #3
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readonly }
>attributes #3 = { nounwind readnone }
>
>!0 = !{}
>
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>DCL OUT[2].xy, GENERIC[1]
>DCL CONST[0..19]
>DCL TEMP[0..2], LOCAL
>IMM[0] FLT32 {    1.0000,     0.0000,     0.0000,     0.0000}
>  0: MUL TEMP[0], CONST[16], IN[0].xxxx
>  1: MAD TEMP[1], CONST[17], IN[0].yyyy, TEMP[0]
>  2: MAD TEMP[2], CONST[18], IN[0].zzzz, TEMP[1]
>  3: ADD OUT[0], TEMP[2], CONST[19]
>  4: MOV OUT[1], IN[1]
>  5: MOV OUT[2].xy, IN[2].xyxx
>  6: END
>radeonsi: Compiling shader 29
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs void @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32) #0 {
>main_body:
>  %15 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %16 = load <4 x i32>, <4 x i32> addrspace(2)* %15, align 16, !invariant.load !0
>  %17 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %16, i32 %12, i32 0, i1 false, i1 false) #2
>  %18 = extractelement <4 x float> %17, i32 0
>  %19 = extractelement <4 x float> %17, i32 1
>  %20 = extractelement <4 x float> %17, i32 2
>  %21 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 1, !amdgpu.uniform !0
>  %22 = load <4 x i32>, <4 x i32> addrspace(2)* %21, align 16, !invariant.load !0
>  %23 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %22, i32 %13, i32 0, i1 false, i1 false) #2
>  %24 = extractelement <4 x float> %23, i32 0
>  %25 = extractelement <4 x float> %23, i32 1
>  %26 = extractelement <4 x float> %23, i32 2
>  %27 = extractelement <4 x float> %23, i32 3
>  %28 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 2, !amdgpu.uniform !0
>  %29 = load <4 x i32>, <4 x i32> addrspace(2)* %28, align 16, !invariant.load !0
>  %30 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %29, i32 %14, i32 0, i1 false, i1 false) #2
>  %31 = extractelement <4 x float> %30, i32 0
>  %32 = extractelement <4 x float> %30, i32 1
>  %33 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %34 = load <4 x i32>, <4 x i32> addrspace(2)* %33, align 16, !invariant.load !0
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 256)
>  %36 = fmul nsz float %35, %18
>  %37 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 260)
>  %38 = fmul nsz float %37, %18
>  %39 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 264)
>  %40 = fmul nsz float %39, %18
>  %41 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 268)
>  %42 = fmul nsz float %41, %18
>  %43 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 272)
>  %44 = fmul nsz float %43, %19
>  %45 = fadd nsz float %44, %36
>  %46 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 276)
>  %47 = fmul nsz float %46, %19
>  %48 = fadd nsz float %47, %38
>  %49 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 280)
>  %50 = fmul nsz float %49, %19
>  %51 = fadd nsz float %50, %40
>  %52 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 284)
>  %53 = fmul nsz float %52, %19
>  %54 = fadd nsz float %53, %42
>  %55 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 288)
>  %56 = fmul nsz float %55, %20
>  %57 = fadd nsz float %56, %45
>  %58 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 292)
>  %59 = fmul nsz float %58, %20
>  %60 = fadd nsz float %59, %48
>  %61 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 296)
>  %62 = fmul nsz float %61, %20
>  %63 = fadd nsz float %62, %51
>  %64 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 300)
>  %65 = fmul nsz float %64, %20
>  %66 = fadd nsz float %65, %54
>  %67 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 304)
>  %68 = fadd nsz float %57, %67
>  %69 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 308)
>  %70 = fadd nsz float %60, %69
>  %71 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 312)
>  %72 = fadd nsz float %63, %71
>  %73 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %34, i32 316)
>  %74 = fadd nsz float %66, %73
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %24, float %25, float %26, float %27, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float %31, float %32, float undef, float undef, i1 false, i1 false) #3
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %68, float %70, float %72, float %74, i1 true, i1 false) #3
>  ret void
>}
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #2
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #3
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readonly }
>attributes #2 = { nounwind readnone }
>attributes #3 = { nounwind }
>
>!0 = !{}
>
>Process Chunk: FONT   94040
>Process Chunk: TMLN   4
>Process Chunk: OBJT   771428
>Process Chunk: ROOM   7065044
>Process Chunk: DAFL   0
>Process Chunk: TPAG   339176
>Process Chunk: CODE   5150804
>Process Chunk: VARI   324232
>Process Chunk: FUNC   174016
>Process Chunk: STRG   729164
>Process Chunk: TXTR   46508568
>Process Chunk: AUDO   177390090
>Audio_WAVs()
>PrepareGame()
>Extension_Prepare() 
>Code_Constant_Prepare() 
>Script_Prepare() 
>TimeLine_Prepare() 
>Object_Prepare() 
>Preparing 1608 objects:
>	Objects 0: Mage_Cinematic_obj
>	Objects 512: Soul_Bubbling_obj
>	Objects 1024: Necromancer_Hand_obj
>	Objects 1536: Land_Slide_Dungeon_obj
>	Objects 1: Boss_Screen_obj
>	Objects 513: Molten_Explosion_obj
>	Objects 1025: Teeth_obj
>	Objects 1537: Land_Slide_obj
>	Objects 2: Damien_Cinematic_obj
>	Objects 514: Mortar_obj
>	Objects 1026: Horus_obj
>	Objects 1538: Mevius_Spike_Ground_obj
>	Objects 3: Select_Controller_obj
>	Objects 515: Mummy_Hand_obj
>	Objects 1027: Nomad_Splash_obj
>	Objects 1539: Molten_Ground_obj
>	Objects 4: Select_Parent_obj
>	Objects 516: Mummy_Hand_Trap_obj
>	Objects 1028: Sand_Fade_obj
>	Objects 1540: Rock_Pillar_obj
>	Objects 5: Select_Viking_obj
>	Objects 517: Necronomicon_Area_obj
>	Objects 1029: Sand_obj
>	Objects 1541: Slime_Drop_obj
>	Objects 6: Select_Pyro_obj
>	Objects 518: Necronomicon_Book_obj
>	Objects 1030: Nomad_Tornado_Mask_obj
>	Objects 1542: Slime_Pool_obj
>	Objects 7: Select_Marksman_obj
>	Objects 519: Nether_Bolt_obj
>	Objects 1031: Nomad_Tornado_obj
>	Objects 1543: Spike_Ball_Creator_obj
>	Objects 8: Select_Nomad_obj
>	Objects 520: Ooze_Ground_obj
>	Objects 1032: Illusion_obj
>	Objects 1544: Spike_Ball_obj
>	Objects 9: Select_Pirate_obj
>	Objects 521: Ooze_Splat_obj
>	Objects 1033: Sandstorm_obj
>	Objects 1545: Spike_Block_Horizontal_obj
>	Objects 10: Select_Redneck_obj
>	Objects 522: Parasect_Blood_obj
>	Objects 1034: Sandstorm_Creator_obj
>	Objects 1546: Spike_Block_Random_obj
>	Objects 11: Select_Necromancer_obj
>	Objects 523: Parasectoid_Blood_obj
>	Objects 1035: Tornado_Creator_obj
>	Objects 1547: Spike_Block_Vertical_obj
>	Objects 12: Select_Samurai_obj
>	Objects 524: Rotating_Soul_obj
>	Objects 1036: Traveler_Scimitar_obj
>	Objects 1548: Spike_Hole_Dungeon_obj
>	Objects 13: Select_Paladin_obj
>	Objects 525: Skull_Fade_obj
>	Objects 1037: Tornado_obj
>	Objects 1549: Spike_Hole_obj
>	Objects 14: Select_Amazon_obj
>	Objects 526: Skull_obj
>	Objects 1038: Tornado_Small_obj
>	Objects 1550: Spike_obj
>	Objects 15: Select_Demon_Slayer_obj
>	Objects 527: Skull_Reaper_obj
>	Objects 1039: Scimitar_obj
>	Objects 1551: Spike_Placeable_obj
>	Objects 16: Select_Demon_obj
>	Objects 528: Spell_obj
>	Objects 1040: Holy_Nova_obj
>	Objects 1552: Spike_Row_obj
>	Objects 17: Select_Steve_obj
>	Objects 529: Spell_Rain_obj
>	Objects 1041: Divine_Shield_obj
>	Objects 1553: Spikeball_Trap_obj
>	Objects 18: Select_Shaman_obj
>	Objects 530: Spider_Web_Ball_obj
>	Objects 1042: Shield_Bash_Orb_obj
>	Objects 1554: Stone_Guardian_obj
>	Objects 19: Select_White_Mage_obj
>	Objects 531: Spider_Web_obj
>	Objects 1043: Shield_Bash_Effect_obj
>	Objects 1555: Toxic_Meteor_obj
>	Objects 20: Block_2_obj
>	Objects 532: Spike_Hook_Hitbox_obj
>	Objects 1044: Shield_Bash_obj
>	Objects 1556: Trap_Flame_obj
>	Objects 21: Block_3_obj
>	Objects 533: Spike_Hook_obj
>	Objects 1045: Paladin_Rotating_Shield_obj
>	Objects 1557: Trap_Parent_obj
>	Objects 22: Block_4_obj
>	Objects 534: Spikeball_Enchant_obj
>	Objects 1046: Paladin_Rotating_Shield_2_obj
>	Objects 1558: Trap_Parent_Player_obj
>	Objects 23: Block_5_obj
>	Objects 535: Stalagmite_obj
>	Objects 1047: Magic_Hammer_obj
>	Objects 1559: Turret_Arrow_Down_obj
>	Objects 24: Block_obj
>	Objects 536: Stalagmites_Air_obj
>	Objects 1048: Chain_Lightning_Paladin_obj
>	Objects 1560: Turret_Arrow_Left_obj
>	Objects 25: Room_Changer_obj
>	Objects 537: Steam_Sale_obj
>	Objects 1049: Anchor_obj
>	Objects 1561: Turret_Arrow_Right_obj
>	Objects 26: Boss_Health_obj
>	Objects 538: Storm_Enemy_obj
>	Objects 1050: Bomb_Rain_obj
>	Objects 1562: Turret_Arrow_Up_obj
>	Objects 27: Camera_obj
>	Objects 539: Storm_Red_obj
>	Objects 1051: Cannonball_obj
>	Objects 1563: Volcano_Flame_obj
>	Objects 28: Charm_Inspect_obj
>	Objects 540: Sword_Fall_obj
>	Objects 1052: Mark_obj
>	Objects 1564: Volcano_obj
>	Objects 29: Inventory_Stash_obj
>	Objects 541: Tentacle_obj
>	Objects 1053: Pirate_Anchor_Smash_obj
>	Objects 1565: Menu_Snow_obj
>	Objects 30: Class_Sound_obj
>	Objects 542: Thunder_Orb_obj
>	Objects 1054: Pirate_Bullet_obj
>	Objects 1566: Snow_Flake_Menu_obj
>	Objects 31: Console_Save_obj
>	Objects 543: Thunder_Storm_Area_obj
>	Objects 1055: Explosion_X_Spot_obj
>	Objects 1567: Town_Fog_obj
>	Objects 32: Controller_obj
>	Objects 544: Trap_Bouncy_obj
>	Objects 1056: Armageddon_obj
>	Objects 1568: Wind_obj
>	Objects 33: Darkness_Overlay_obj
>	Objects 545: Waller_Wall_obj
>	Objects 1057: Fireball_Hydra_obj
>	Objects 1569: Boss_Wind_Controller_obj
>	Objects 34: Dungeon_Light_obj
>	Objects 546: Attack_Fly_obj
>	Objects 1058: Blaze_obj
>	Objects 1570: Dust_Controller_obj
>	Objects 35: Flash_White_obj
>	Objects 547: Bride_obj
>	Objects 1059: Fire_Flame_obj
>	Objects 1571: Dust_Flying_obj
>	Objects 36: Menu_Scheme_Option_obj
>	Objects 548: Burning_Legion_obj
>	Objects 1060: Fire_Nova_obj
>	Objects 1572: Foliage_Controller_obj
>	Objects 37: View_Option_obj
>	Objects 549: Chilling_Head_obj
>	Objects 1061: Fireball_Large_obj
>	Objects 1573: Foliage_obj
>	Objects 38: Resolution_Option_obj
>	Objects 550: Corrosive_Ooze_obj
>	Objects 1062: Fireball_obj
>	Objects 1574: Rain_Controller_obj
>	Objects 39: Windowed_Size_obj
>	Objects 551: Corrupted_Monk_obj
>	Objects 1063: Firefly_obj
>	Objects 1575: Cathedral_Controller_obj
>	Objects 40: Performance_Option_obj
>	Objects 552: Cursed_Doll_obj
>	Objects 1064: Fireswarm_obj
>	Objects 1576: Rain_obj
>	Objects 41: Scanlines_Option_obj
>	Objects 553: Damned_Legion_obj
>	Objects 1065: Hydra_obj
>	Objects 1577: Snow_Controller_obj
>	Objects 42: Shake_Option_obj
>	Objects 554: Desert_Beast_obj
>	Objects 1066: Hydra_Item_obj
>	Objects 1578: Snow_Flake_obj
>	Objects 43: FPS_Option_obj
>	Objects 555: Desert_Skeleton_obj
>	Objects 1067: Meteor_obj
>	Objects 1579: Sun_Controller_obj
>	Objects 44: Combat_Text_Option_obj
>	Objects 556: Devilkin_Goblin_obj
>	Objects 1068: Pyromancer_Dust_obj
>	Objects 1580: Sun_Ray_obj
>	Objects 45: Slider_Darkness_obj
>	Objects 557: Doll_Corpse_obj
>	Objects 1069: Bear_Trap_obj
>	Objects 1581: Water_Splash_obj
>	Objects 46: Name_Option_obj
>	Objects 558: Dragon_Whelp_obj
>	Objects 1070: Molotov_obj
>	Objects 1582: Wind_Fire_obj
>	Objects 47: Health_Option_obj
>	Objects 559: Dust_Feeder_obj
>	Objects 1071: Pickup_Truck_obj
>	Objects 1583: Wind_Controller_obj
>	Objects 48: Music_Option_obj
>	Objects 560: Earth_Elemental_obj
>	Objects 1072: Redneck_Stomp_obj
>	Objects 1584: Wind_Particle_obj
>	Objects 49: Slider_Master_obj
>	Objects 561: Ent_obj
>	Objects 1073: Spin_Hitbox_obj
>	Objects 1585: Abomination_Wind_obj
>	Objects 50: Vibration_Option_obj
>	Objects 562: Fetish_Doll_obj
>	Objects 1074: Spin_Sound_obj
>	Objects 1586: Damien_Puppet_obj
>	Objects 51: Voice_Option_obj
>	Objects 563: Frost_Dragon_obj
>	Objects 1075: Tire_obj
>	Objects 1587: Camera_Move_Right
>	Objects 52: Options_Video_obj
>	Objects 564: Frost_Skeleton_obj
>	Objects 1076: Truck_Bullet_obj
>	Objects 1588: Wormhole_Pack_Parent_obj
>	Objects 53: Options_Audio_obj
>	Objects 565: Frozen_Goblin_obj
>	Objects 1077: Vorpal_Illusion_obj
>	Objects 1589: Wormhole_Pack_Melee_obj
>	Objects 54: Options_Controls_obj
>	Objects 566: Fungus_Monster_obj
>	Objects 1078: Zen_Tornado_obj
>	Objects 1590: Wormhole_Pack_Ranged_obj
>	Objects 55: Redeem_Code_obj
>	Objects 567: Ghost_Archer_obj
>	Objects 1079: Vorpal_Ghost_obj
>	Objects 1591: Wormhole_Pack_Mixed_obj
>	Objects 56: Options_Back_obj
>	Objects 568: Ghost_Skeleton_obj
>	Objects 1080: Zen_Wind_obj
>	Objects 1592: Zeppelin_Squares_obj
>	Objects 57: Controls_Reset_obj
>	Objects 569: Giant_obj
>	Objects 1081: Lightning_Enchant_Hit_obj
>	Objects 1593: Tracks_obj
>	Objects 58: Controls_Changer_obj
>	Objects 570: Goblin_Bomber_obj
>	Objects 1082: Vorpal_Strike_Orb_obj
>	Objects 1594: Wormhole_Gaps_obj
>	Objects 59: Options_Control_obj
>	Objects 571: Goblin_Cannoner_obj
>	Objects 1083: Vorpal_Strike_obj
>	Objects 1595: Wormhole_Block_obj
>	Objects 60: Gamepad_obj
>	Objects 572: Goblin_obj
>	Objects 1084: Ice_Enchant_Hit_obj
>	Objects 1596: Generate_Wormhole_obj
>	Objects 61: ID_Check_obj
>	Objects 573: Goblin_Treasure_obj
>	Objects 1085: Ice_Shred_obj
>	Objects 1597: catalog_node
>	Objects 62: Inventory_Log_obj
>	Objects 574: Haunted_Book_obj
>	Objects 1086: Spinning_Katana_obj
>	Objects 1598: dungeonGenerator
>	Objects 63: Inventory_Merchant_obj
>	Objects 575: Headless_Buttler_obj
>	Objects 1087: Waijin_Stone_obj
>	Objects 1599: dungeonGeneratorJumping
>	Objects 64: Inventory_Merchant_Old_obj
>	Objects 576: Hell_Beast_obj
>	Objects 1088: Chain_Lightning_Shaman_obj
>	Objects 1600: dungeonGeneratorWall
>	Objects 65: Inventory_Trade_obj
>	Objects 577: Hollow_Stump_obj
>	Objects 1089: Lava_Spill_obj
>	Objects 1601: dungeonWallDestroyer
>	Objects 66: Level_Start_obj
>	Objects 578: Horror_obj
>	Objects 1090: Elemental_Blast_obj
>	Objects 1602: o_bsp_leaf
>	Objects 67: Logo_obj
>	Objects 579: Ice_Elemental_obj
>	Objects 1091: Totem_Rock_obj
>	Objects 1603: o_bsp_puzzle
>	Objects 68: Menu_Controller_obj
>	Objects 580: Illuminated_Stone_obj
>	Objects 1092: Totem_Nova_obj
>	Objects 1604: o_bsp_tunnel
>	Objects 69: Menu_Animation_obj
>	Objects 581: Imp_obj
>	Objects 1093: Shaman_Totem_Basic_obj
>	Objects 1605: preset_editor
>	Objects 70: Mobile_Controls_obj
>	Objects 582: Jormungar_obj
>	Objects 1094: Shaman_Totem_Storm_obj
>	Objects 1606: preset_editor_bg
>	Objects 71: Voice_Test_obj
>	Objects 583: Karp_obj
>	Objects 1095: Shaman_Totem_Fire_obj
>	Objects 1607: dungeonLadderDoorDestroyer
>	Objects 72: Queue_Controller_obj
>	Objects 584: Kiwi_obj
>	Objects 1096: Shaman_Totem_Earth_obj
>	Objects 73: Chat_Ingame_obj
>	Objects 585: Levitating_Horror_obj
>	Objects 1097: Shaman_Projectile_obj
>	Objects 74: Chat_Back_obj
>	Objects 586: Maggot_obj
>	Objects 1098: Poo_obj
>	Objects 75: Chat_obj
>	Objects 587: Mummy_obj
>	Objects 1099: Charge_obj
>	Objects 76: Chat_Serverlist_obj
>	Objects 588: Nautilus_obj
>	Objects 1100: Hitbox_obj
>	Objects 77: Chat_Guild_obj
>	Objects 589: Ninji_obj
>	Objects 1101: Shockwave_obj
>	Objects 78: Chat_Siege_obj
>	Objects 590: Organic_Anomaly_obj
>	Objects 1102: Viking_Shockwave_obj
>	Objects 79: Chat_Highscores_obj
>	Objects 591: Parasect_obj
>	Objects 1103: Shout_Talent_obj
>	Objects 80: Ranking_Get_obj
>	Objects 592: Piranha_obj
>	Objects 1104: Shout_obj
>	Objects 81: Players_Get_obj
>	Objects 593: Rat_obj
>	Objects 1105: Viking_Bash_obj
>	Objects 82: Client_obj
>	Objects 594: Rift_Grunt_obj
>	Objects 1106: Viking_Splash_obj
>	Objects 83: Enemy_Ghost_obj
>	Objects 595: Samurai_Skeleton_obj
>	Objects 1107: Absorb_Shield_obj
>	Objects 84: Get_Siege_obj
>	Objects 596: Sand_Wasp_obj
>	Objects 1108: White_Mage_Fire_obj
>	Objects 85: Load_Inventory_obj
>	Objects 597: Shinigami_obj
>	Objects 1109: Chain_Lightning_White_Mage_obj
>	Objects 86: Load_Inventory_All_obj
>	Objects 598: Skeleton_Archer_obj
>	Objects 1110: Mana_Orb_obj
>	Objects 87: Choose_Region_obj
>	Objects 599: Skeleton_Mage_obj
>	Objects 1111: Mana_Area_obj
>	Objects 88: Bugtracker_obj
>	Objects 600: Skeleton_obj
>	Objects 1112: Mana_Orb_Aoe_obj
>	Objects 89: Login_Message_obj
>	Objects 601: Spider_obj
>	Objects 1113: Heal_obj
>	Objects 90: Login_Back_obj
>	Objects 602: Wendigo_obj
>	Objects 1114: Cursed_obj
>	Objects 91: Login_obj
>	Objects 603: Worm_obj
>	Objects 1115: Healing_Zone_obj
>	Objects 92: Resend_Email_obj
>	Objects 604: Worm_Piece_obj
>	Objects 1116: White_Mage_Curse_obj
>	Objects 93: Password_obj
>	Objects 605: Yeti_obj
>	Objects 1117: White_Mage_Spell_obj
>	Objects 94: Register_New_obj
>	Objects 606: Zombie_obj
>	Objects 1118: White_Mage_Soul_obj
>	Objects 95: Textfield_Parent_obj
>	Objects 607: Burning_Legion_Passive_obj
>	Objects 1119: Collision_Parent_obj
>	Objects 96: Username_obj
>	Objects 608: Chilling_Head_Passive_obj
>	Objects 1120: Collision_Prop_obj
>	Objects 97: Forgot_Password_obj
>	Objects 609: Corrosive_Ooze_Passive_obj
>	Objects 1121: Big_Wall_Block_obj
>	Objects 98: Server_Get_Text_obj
>	Objects 610: Damned_Legion_Passive_obj
>	Objects 1122: Invisible_Wall_obj
>	Objects 99: Viking_Login_obj
>	Objects 611: Desert_Beast_Passive_obj
>	Objects 1123: Pentagram_Boss_obj
>	Objects 100: Multiplayer_Settings_obj
>	Objects 612: Desert_Skeleton_Passive_obj
>	Objects 1124: Pentagram_obj
>	Objects 101: Player_Ghost_obj
>	Objects 613: Devilkin_Goblin_Passive_obj
>	Objects 1125: Gate_Down_obj
>	Objects 102: Save_Siege_obj
>	Objects 614: Dragon_Whelp_Passive_obj
>	Objects 1126: Gate_Wooden_Vertical_obj
>	Objects 103: Save_Endgame_obj
>	Objects 615: Ent_Passive_obj
>	Objects 1127: Gate_Left_obj
>	Objects 104: Siege_Highscores_obj
>	Objects 616: Frost_Dragon_Passive_obj
>	Objects 1128: Gate_Wooden_Left_obj
>	Objects 105: Get_Siege_Top_obj
>	Objects 617: Frost_Goblin_Passive_obj
>	Objects 1129: Gate_Wooden_Left_Open_obj
>	Objects 106: Ranking_Difficulty_obj
>	Objects 618: Frost_Skeleton_Passive_obj
>	Objects 1130: Gate_Wooden_Right_Open_obj
>	Objects 107: Get_Endgame_Top_obj
>	Objects 619: Fungus_Monster_Passive_obj
>	Objects 1131: Gate_Wooden_Right_obj
>	Objects 108: Ranking_Hardcore_obj
>	Objects 620: Ghost_Skeleton_Archer_Passive_obj
>	Objects 1132: Gate_Up_obj
>	Objects 109: Endgame_Highscores_obj
>	Objects 621: Ghost_Skeleton_Passive_obj
>	Objects 1133: Gate_Right_obj
>	Objects 110: Ready_obj
>	Objects 622: Goblin_Bomber_Passive_obj
>	Objects 1134: Gate_Parent_obj
>	Objects 111: Register_Back_obj
>	Objects 623: Goblin_Cannoner_Passive_obj
>	Objects 1135: Wormhole_Upgrade_obj
>	Objects 112: Register_Email_obj
>	Objects 624: Goblin_Passive_obj
>	Objects 1136: Crystal_Diamond_2_obj
>	Objects 113: Register_obj
>	Objects 625: Apple_Passive_obj
>	Objects 1137: Crystal_Diamond_3_obj
>	Objects 114: Register_Password_2_obj
>	Objects 626: Haunted_Book_Passive_obj
>	Objects 1138: Crystal_Display_obj
>	Objects 115: Register_Password_obj
>	Objects 627: Hell_Beast_Passive_obj
>	Objects 1139: Crystal_Ball_2_obj
>	Objects 116: Register_Username_obj
>	Objects 628: Hollow_Stump_Passive_obj
>	Objects 1140: Crystal_Column_obj
>	Objects 117: Report_Tab_obj
>	Objects 629: Horror_Passive_obj
>	Objects 1141: Turbine_obj
>	Objects 118: Player_Update_obj
>	Objects 630: Illuminated_Stone_Passive_obj
>	Objects 1142: Turbine_Half_obj
>	Objects 119: Guild_Add_obj
>	Objects 631: Imp_Passive_obj
>	Objects 1143: Crystal_Ball_1_obj
>	Objects 120: Guild_Player_Get_obj
>	Objects 632: Karp_Passive_obj
>	Objects 1144: Crystal_Arch_obj
>	Objects 121: Get_Season_Wormhole_obj
>	Objects 633: Lammas_obj
>	Objects 1145: Jungle_Water_obj
>	Objects 122: Get_Season_Event_obj
>	Objects 634: Maggot_Passive_obj
>	Objects 1146: Jungle_Hut_obj
>	Objects 123: Guild_Player_Add_obj
>	Objects 635: Mimic_obj
>	Objects 1147: Crystal_Diamond_1_obj
>	Objects 124: Save_Character_obj
>	Objects 636: Moss_Goblin_Passive_obj
>	Objects 1148: Totem_obj
>	Objects 125: Save_Delete_obj
>	Objects 637: Mummy_Passive_obj
>	Objects 1149: Flagpole_obj
>	Objects 126: Save_obj
>	Objects 638: Nest_Parent_obj
>	Objects 1150: Jungle_Arch_obj
>	Objects 127: Save_Reset_Stats_obj
>	Objects 639: Beast_Cove_obj
>	Objects 1151: Anubis_Statue_obj
>	Objects 128: Save_Reset_Talents_obj
>	Objects 640: Bone_Lair_obj
>	Objects 1152: Arreat_Statue_obj
>	Objects 129: Save_Shop_obj
>	Objects 641: Goblin_Den_obj
>	Objects 1153: Arreat_Tiles_obj
>	Objects 130: Save_Wormhole_obj
>	Objects 642: Maggot_Lair_obj
>	Objects 1154: Cactus_obj
>	Objects 131: Server_obj
>	Objects 643: Piranha_Cave_obj
>	Objects 1155: Desert_Arch_obj
>	Objects 132: Server_Peer_obj
>	Objects 644: Rat_Nest_obj
>	Objects 1156: Desert_Dirt_obj
>	Objects 133: Server_Ghost_obj
>	Objects 645: Samurai_Altar_obj
>	Objects 1157: Desert_Fence_Angled_obj
>	Objects 134: Tab_Classic_obj
>	Objects 646: Sarkofagus_obj
>	Objects 1158: Desert_Fence_obj
>	Objects 135: Tab_KoD_obj
>	Objects 647: Skeletal_Cave_obj
>	Objects 1159: Desert_Hut_1_obj
>	Objects 136: Tab_DoH_obj
>	Objects 648: Stump_Nest_obj
>	Objects 1160: Desert_Hut_2_obj
>	Objects 137: Tab_WoM_obj
>	Objects 649: Ninji_Passive_obj
>	Objects 1161: Desert_Impale_obj
>	Objects 138: Server_Password_obj
>	Objects 650: Parasect_Passive_obj
>	Objects 1162: Desert_Oasis_obj
>	Objects 139: Connect_obj
>	Objects 651: Piranha_Passive_obj
>	Objects 1163: Desert_Spot_obj
>	Objects 140: Create_obj
>	Objects 652: Rat_Passive_obj
>	Objects 1164: Desert_Statue_Hand_obj
>	Objects 141: Guilds_obj
>	Objects 653: Rift_Grunt_Passive_obj
>	Objects 1165: Desert_Statue_Head_obj
>	Objects 142: Help_obj
>	Objects 654: Samurai_Skeleton_Passive_obj
>	Objects 1166: Oasis_Palm_obj
>	Objects 143: Join_obj
>	Objects 655: Skeleton_Archer_Passive_obj
>	Objects 1167: Desert_Pillar_obj
>	Objects 144: Multiplayer_Servers_obj
>	Objects 656: Skeleton_Mage_Passive_obj
>	Objects 1168: Oasis_Plant_obj
>	Objects 145: Ping_obj
>	Objects 657: Skeleton_Passive_obj
>	Objects 1169: Palm_obj
>	Objects 146: Refresh_obj
>	Objects 658: Spider_Passive_obj
>	Objects 1170: Prop_1_Desert_obj
>	Objects 147: Server_Add_obj
>	Objects 659: Zombie_Passive_obj
>	Objects 1171: Prop_2_Desert_obj
>	Objects 148: Server_Dummy_obj
>	Objects 660: Parent_Ancient_obj
>	Objects 1172: Prop_3_Desert_obj
>	Objects 149: Server_Get_obj
>	Objects 661: Earthworm_Jack_obj
>	Objects 1173: Prop_7_Desert_obj
>	Objects 150: Server_Update_obj
>	Objects 662: Black_Widow_obj
>	Objects 1174: Prop_8_Desert_obj
>	Objects 151: Sort_obj
>	Objects 663: Plague_Rat_obj
>	Objects 1175: Prop_9_Desert_obj
>	Objects 152: PAS_Logo_obj
>	Objects 664: Abyssal_Imp_obj
>	Objects 1176: Ratas_obj
>	Objects 153: Path_Block_obj
>	Objects 665: Icehowl_obj
>	Objects 1177: Waterfall_obj
>	Objects 154: Pause_obj
>	Objects 666: Freezing_Monstrosity_obj
>	Objects 1178: Waterfall_Dark_obj
>	Objects 155: Player_Start_Voice_obj
>	Objects 667: Colossal_Legion_obj
>	Objects 1179: Branch_obj
>	Objects 156: Prompt_Cloud_obj
>	Objects 668: Environment_Piece_1_obj
>	Objects 1180: Bush_Garden_obj
>	Objects 157: Prompt_DLC_2_obj
>	Objects 669: Bushes_obj
>	Objects 1181: Bush_obj
>	Objects 158: Prompt_DLC_3_obj
>	Objects 670: Environment_Piece_2_obj
>	Objects 1182: Bush_Parent_obj
>	Objects 159: Prompt_DLC_obj
>	Objects 671: Environment_Piece_3_obj
>	Objects 1183: Bush_Vertical_obj
>	Objects 160: Prompt_Shaman_obj
>	Objects 672: Environment_Piece_4_obj
>	Objects 1184: Camp_Fire_obj
>	Objects 161: Prompt_EA_obj
>	Objects 673: Environment_Piece_5_obj
>	Objects 1185: Corpse_Soldier_obj
>	Objects 162: Prompt_Parent_obj
>	Objects 674: Lock_Fort_obj
>	Objects 1186: Pumpkin_obj
>	Objects 163: Prompt_Port_obj
>	Objects 675: Mystery_Hat_Parent_obj
>	Objects 1187: Random_Pumpkin_obj
>	Objects 164: Prompt_Whats_New_obj
>	Objects 676: Gurags_Heart_obj
>	Objects 1188: Bamboo_obj
>	Objects 165: Prompt_Guild_Invite_obj
>	Objects 677: Mystery_Hat_1_obj
>	Objects 1189: Fence_obj
>	Objects 166: Prompt_Mystery_Hat_obj
>	Objects 678: Mystery_Hat_2_obj
>	Objects 1190: Statue_Mevius_obj
>	Objects 167: Prompt_Guild_obj
>	Objects 679: Mystery_Hat_3_obj
>	Objects 1191: Fence_Plant_obj
>	Objects 168: Prompt_Profile_obj
>	Objects 680: Mystery_Hat_4_obj
>	Objects 1192: Column_obj
>	Objects 169: Prompt_Server_obj
>	Objects 681: Mystery_Hat_5_obj
>	Objects 1193: Fire_Fly_obj
>	Objects 170: Prompt_Server_Siege_obj
>	Objects 682: Mystery_Hat_6_obj
>	Objects 1194: Flag_obj
>	Objects 171: Prop_Controller_obj
>	Objects 683: Mystery_Hat_7_obj
>	Objects 1195: Flower_Bed_obj
>	Objects 172: PS_Controller_obj
>	Objects 684: Wormhole_Key_obj
>	Objects 1196: Flowers_obj
>	Objects 173: Sheep_Controller_obj
>	Objects 685: Deaths_Sigil_obj
>	Objects 1197: Flowers_Still_obj
>	Objects 174: Sheep_Spawner_obj
>	Objects 686: Damiens_Eye_obj
>	Objects 1198: Garden_Flower_obj
>	Objects 175: Slot_Machine_obj
>	Objects 687: Anubis_Ankh_obj
>	Objects 1199: Hand_Prop_obj
>	Objects 176: Spawner_obj
>	Objects 688: Karp_Kings_Bellybutton_obj
>	Objects 1200: Plant_Big_2_obj
>	Objects 177: Spectator_obj
>	Objects 689: Satans_Horn_obj
>	Objects 1201: Plant_Big_obj
>	Objects 178: Tatti_1_obj
>	Objects 690: Charm_Ground_obj
>	Objects 1202: Plant_Big_Stacked_obj
>	Objects 179: Tatti_2_obj
>	Objects 691: Loot_Ground_obj
>	Objects 1203: Prop_1_Dark_obj
>	Objects 180: Wall_Creator_obj
>	Objects 692: Halloween_Apple_obj
>	Objects 1204: Prop_1_obj
>	Objects 181: Water_Block_obj
>	Objects 693: Halloween_Candy_obj
>	Objects 1205: Prop_1_Static_obj
>	Objects 182: Worm_Hole_Spawner_obj
>	Objects 694: Halloween_Basket_obj
>	Objects 1206: Hang_obj
>	Objects 183: Grayscale_obj
>	Objects 695: Snowman_Head_obj
>	Objects 1207: Prop_13_obj
>	Objects 184: Shaking_Text_obj
>	Objects 696: Pile_Of_Socks_obj
>	Objects 1208: Prop_14_obj
>	Objects 185: You_Have_obj
>	Objects 697: Xmas_Star_obj
>	Objects 1209: Prop_2_obj
>	Objects 186: Unlocked_obj
>	Objects 698: Xmas_Tree_Town_obj
>	Objects 1210: Prop_3_obj
>	Objects 187: Nightmare_obj
>	Objects 699: Xmas_Tree_obj
>	Objects 1211: Prop_7_obj
>	Objects 188: Hell_obj
>	Objects 700: Christmas_Candy_Cane_obj
>	Objects 1212: Random_Tree_obj
>	Objects 189: Inferno_obj
>	Objects 701: Christmas_Snowball_obj
>	Objects 1213: Risuja_obj
>	Objects 190: Agony_obj
>	Objects 702: Christmas_Light_obj
>	Objects 1214: Torso_Prop_obj
>	Objects 191: Destruction_obj
>	Objects 703: Christmas_Snow_Pile_obj
>	Objects 1215: Skull_Prop_obj
>	Objects 192: The_End_obj
>	Objects 704: Christmas_Snowball_Item_obj
>	Objects 1216: Torch_Random_obj
>	Objects 193: Credits_1_obj
>	Objects 705: Armor_Rack_obj
>	Objects 1217: Torch_obj
>	Objects 194: Credits_2_obj
>	Objects 706: Box_obj
>	Objects 1218: Ruin_1_obj
>	Objects 195: Credits_3_obj
>	Objects 707: Box_Placeable_obj
>	Objects 1219: Ruin_2_obj
>	Objects 196: Credits_4_obj
>	Objects 708: Box_Spawner_obj
>	Objects 1220: Ruin_3_obj
>	Objects 197: Bridge_Creator_obj
>	Objects 709: Chest_Drop_obj
>	Objects 1221: Ruin_4_obj
>	Objects 198: Bridge_obj
>	Objects 710: Chest_obj
>	Objects 1222: Tile_Pillar_Curvy_obj
>	Objects 199: Crypt_obj
>	Objects 711: Mystery_Chest_obj
>	Objects 1223: Sword_Ground_obj
>	Objects 200: Draft_Down_obj
>	Objects 712: Coin_obj
>	Objects 1224: Prop_6_obj
>	Objects 201: Draft_Left_obj
>	Objects 713: Coin_Parent_obj
>	Objects 1225: Tree_obj
>	Objects 202: Draft_Parent_obj
>	Objects 714: Coin_Rain_obj
>	Objects 1226: Mayan_Tree_obj
>	Objects 203: Draft_Right_obj
>	Objects 715: Crystal_Key_obj
>	Objects 1227: Tile_Pillar_obj
>	Objects 204: Draft_Up_obj
>	Objects 716: Crystal_obj
>	Objects 1228: Rock_obj
>	Objects 205: Dungeon_Block_1_obj
>	Objects 717: Flying_Relic_obj
>	Objects 1229: Tile_Pillar_Random_obj
>	Objects 206: Dungeon_Block_2_obj
>	Objects 718: Devil_Shrine_obj
>	Objects 1230: Street_Lamp_obj
>	Objects 207: Dungeon_Block_3_obj
>	Objects 719: Dungeon_Shop_Back_obj
>	Objects 1231: Forest_Spot_obj
>	Objects 208: Dungeon_Boss_obj
>	Objects 720: Flame_Lava_Rail_obj
>	Objects 1232: Table_1_obj
>	Objects 209: Dungeon_Gate_obj
>	Objects 721: Flame_obj
>	Objects 1233: Manor_Pillar_obj
>	Objects 210: Dungeon_Gate_Enemies_obj
>	Objects 722: Flame_Small_obj
>	Objects 1234: Table_2_obj
>	Objects 211: Dungeon_Gate_Vertical_obj
>	Objects 723: Flame_Tire_obj
>	Objects 1235: Chair_1_obj
>	Objects 212: Dungeon_Gate_Vertical_2_obj
>	Objects 724: Health_Shrine_obj
>	Objects 1236: Manor_Torch_obj
>	Objects 213: Dungeon_Gate_Vertical_3_obj
>	Objects 725: Item_Altar_obj
>	Objects 1237: Manor_Torch_Mevius_obj
>	Objects 214: Dungeon_Spawn_Player_1_obj
>	Objects 726: Item_obj
>	Objects 1238: Chair_2_obj
>	Objects 215: Dungeon_Spawn_Player_2_obj
>	Objects 727: Key_obj
>	Objects 1239: Chair_3_obj
>	Objects 216: Dungeon_Spawn_Player_3_obj
>	Objects 728: Lock_obj
>	Objects 1240: Chair_4_obj
>	Objects 217: Dungeon_Spawn_Player_4_obj
>	Objects 729: Magic_Potion_obj
>	Objects 1241: Mevius_Painting_obj
>	Objects 218: Dungeon_Spawner_1_obj
>	Objects 730: Potion_Box_2_obj
>	Objects 1242: Wine_Glass_1_obj
>	Objects 219: Dungeon_Spawner_2_obj
>	Objects 731: Potion_Box_obj
>	Objects 1243: Wine_Glass_2_obj
>	Objects 220: Dungeon_Spawner_3_obj
>	Objects 732: Potion_Use_Box_2_obj
>	Objects 1244: Wine_Glass_3_obj
>	Objects 221: Dungeon_Spawner_4_obj
>	Objects 733: Potion_Use_Box_obj
>	Objects 1245: Arcane_Prop_1_obj
>	Objects 222: Dungeon_Start_obj
>	Objects 734: Shrine_obj
>	Objects 1246: Rock_Junk_1_obj
>	Objects 223: Dungeon_Trigger_1_obj
>	Objects 735: Stamina_Rack_obj
>	Objects 1247: Manor_Front_obj
>	Objects 224: Dungeon_Trigger_2_obj
>	Objects 736: Strength_Rack_obj
>	Objects 1248: Rock_Junk_2_obj
>	Objects 225: Dungeon_Trigger_3_obj
>	Objects 737: Swiftness_Rack_obj
>	Objects 1249: Rock_Junk_3_obj
>	Objects 226: Dungeon_Trigger_4_obj
>	Objects 738: Text_Box_2_obj
>	Objects 1250: Hydra_Statue_obj
>	Objects 227: Lever_Parent_obj
>	Objects 739: Text_Box_obj
>	Objects 1251: Garden_Passage_obj
>	Objects 228: Lever_Bridge_Block_obj
>	Objects 740: Textbox_Parent_2_obj
>	Objects 1252: Top_Fence_Zen_obj
>	Objects 229: Lever_Bridge_obj
>	Objects 741: Textbox_Parent_obj
>	Objects 1253: Fish_Water_obj
>	Objects 230: Lever_obj
>	Objects 742: Treasure_Buy_Button_1_obj
>	Objects 1254: Bamboo_Water_obj
>	Objects 231: Lever_2_obj
>	Objects 743: Treasure_Buy_Button_2_obj
>	Objects 1255: Bottom_Fence_Zen_obj
>	Objects 232: Lever_3_obj
>	Objects 744: Treasure_Buy_Button_3_obj
>	Objects 1256: Zen_Lamp_obj
>	Objects 233: Lever_Statue_obj
>	Objects 745: Treasure_Buy_Button_4_obj
>	Objects 1257: Boat_Water_obj
>	Objects 234: Trap_Door_Parent_obj
>	Objects 746: Treasure_Buy_Button_5_obj
>	Objects 1258: Zen_Hut_obj
>	Objects 235: Luukku_obj
>	Objects 747: Treasure_Buy_Button_6_obj
>	Objects 1259: Water_Dirt_Spot_obj
>	Objects 236: Boss_Text_obj
>	Objects 748: Treasure_Buy_Button_Grey_obj
>	Objects 1260: Zen_Torch_obj
>	Objects 237: Boss_Dungeon_obj
>	Objects 749: Treasure_Dungeon_obj
>	Objects 1261: Zen_Statue_Pillar_obj
>	Objects 238: Karp_King_Dungeon_obj
>	Objects 750: Treasure_Fort_Frames_obj
>	Objects 1262: Zen_Waterpool_obj
>	Objects 239: Puzzle_Block_obj
>	Objects 751: Treasure_Fort_obj
>	Objects 1263: Zen_Pillar_obj
>	Objects 240: Puzzle_Block_Platform_obj
>	Objects 752: Treasure_Gate_obj
>	Objects 1264: Tree_Zen_obj
>	Objects 241: Puzzle_Button_obj
>	Objects 753: Urn_obj
>	Objects 1265: Random_Tree_Zen_obj
>	Objects 242: Puzzle_Pillar_obj
>	Objects 754: Urn_Randomed_obj
>	Objects 1266: Cage_Hanging_obj
>	Objects 243: Puzzle_Step_obj
>	Objects 755: Scroll_Controller_obj
>	Objects 1267: Cage_Hanging_Shadow_obj
>	Objects 244: Reset_Puzzle_obj
>	Objects 756: Relics_Tab_obj
>	Objects 1268: Candle_Stand_obj
>	Objects 245: Tikkaat_obj
>	Objects 757: Statistics_Tab_obj
>	Objects 1269: Cathedral_Bench_obj
>	Objects 246: Puzzle_Grave_1_obj
>	Objects 758: Achievements_Tab_obj
>	Objects 1270: Cathedral_Holy_Water_obj
>	Objects 247: Puzzle_Grave_2_obj
>	Objects 759: Achievements_Back_obj
>	Objects 1271: Cathedral_Light_obj
>	Objects 248: Puzzle_Grave_3_obj
>	Objects 760: Achievements_Draw_obj
>	Objects 1272: Cathedral_Pillar_Horizontal_obj
>	Objects 249: Grave_Creator_obj
>	Objects 761: Relics_Controller_obj
>	Objects 1273: Cathedral_Pillar_obj
>	Objects 250: Puzzle_Grave_Fake_obj
>	Objects 762: Relic_Info_obj
>	Objects 1274: Cathedral_Pillar_Shred_obj
>	Objects 251: Wooden_Draft_Down_obj
>	Objects 763: Relic_obj
>	Objects 1275: Cathedral_Stone_obj
>	Objects 252: Wooden_Draft_Left_obj
>	Objects 764: Castle_Front_obj
>	Objects 1276: Cathedral_Table_obj
>	Objects 253: Wooden_Draft_Right_obj
>	Objects 765: Back_Small_obj
>	Objects 1277: Cathedral_Table_Reverse_obj
>	Objects 254: Wooden_Draft_Up_obj
>	Objects 766: Choose_Controller_obj
>	Objects 1278: Cathedral_Window_Light_obj
>	Objects 255: Achi_Item_obj
>	Objects 767: Choose_Parent_obj
>	Objects 1279: Cathedral_Window_obj
>	Objects 256: Achievement_obj
>	Objects 768: Choose_List_obj
>	Objects 1280: Eyes_obj
>	Objects 257: Acid_Bubble_obj
>	Objects 769: Choosing_Back_obj
>	Objects 1281: Hay_Pile_obj
>	Objects 258: Additional_Laser_obj
>	Objects 770: Load_obj
>	Objects 1282: Hell_Stone_obj
>	Objects 259: Big_Poof_obj
>	Objects 771: Load_Shop_obj
>	Objects 1283: Lava_Bubble_obj
>	Objects 260: Black_Fade_In_obj
>	Objects 772: Choose_1_obj
>	Objects 1284: Lava_Rail_obj
>	Objects 261: Black_Fade_Out_obj
>	Objects 773: Choose_2_obj
>	Objects 1285: Nightmare_Torch_obj
>	Objects 262: Blood_Fly_obj
>	Objects 774: Choose_3_obj
>	Objects 1286: Prison_Fog_Creator_obj
>	Objects 263: Blood_Ground_obj
>	Objects 775: Choose_7_obj
>	Objects 1287: Prison_Tile_1_obj
>	Objects 264: Blood_Poof_obj
>	Objects 776: Choose_8_obj
>	Objects 1288: Prison_Tile_2_obj
>	Objects 265: Bloodsplat_obj
>	Objects 777: Choose_9_obj
>	Objects 1289: Prison_Tile_3_obj
>	Objects 266: Blue_Clouds_Death_obj
>	Objects 778: Choose_4_obj
>	Objects 1290: Prison_Tile_4_obj
>	Objects 267: Cannon_Muzzle_Fire_obj
>	Objects 779: Choose_5_obj
>	Objects 1291: Prisoner_Rotting_obj
>	Objects 268: Coin_Poof_obj
>	Objects 780: Choose_6_obj
>	Objects 1292: Rails_Trees_obj
>	Objects 269: Coin_Text_obj
>	Objects 781: Choose_10_obj
>	Objects 1293: Random_Tree_Depths_Of_Hell_obj
>	Objects 270: Combat_Text_obj
>	Objects 782: Choose_11_obj
>	Objects 1294: Random_Tree_Highlands_obj
>	Objects 271: Combo_Text_obj
>	Objects 783: Choose_12_obj
>	Objects 1295: Sand_Bump_obj
>	Objects 272: Spell_AOE_obj
>	Objects 784: Choose_13_obj
>	Objects 1296: Train_Tires_obj
>	Objects 273: Corpse_obj
>	Objects 785: Choose_14_obj
>	Objects 1297: Pyramide_Element_obj
>	Objects 274: Crater_obj
>	Objects 786: Choose_15_obj
>	Objects 1298: Pyramide_Spikes_obj
>	Objects 275: Crater_Small_obj
>	Objects 787: Choose_16_obj
>	Objects 1299: Act3_Void_obj
>	Objects 276: Dust_Cloud_obj
>	Objects 788: Choose_17_obj
>	Objects 1300: Big_Pond_1_Mask_obj
>	Objects 277: Enemy_Explosion_obj
>	Objects 789: Choose_18_obj
>	Objects 1301: Big_Pond_1_obj
>	Objects 278: Mana_Regen_obj
>	Objects 790: Shop_Small_obj
>	Objects 1302: Big_Pond_2_Mask_obj
>	Objects 279: Enemy_Ground_obj
>	Objects 791: Switch_Page_Mobile_obj
>	Objects 1303: Big_Pond_2_obj
>	Objects 280: Enemy_Poof_obj
>	Objects 792: Play_1_Player_obj
>	Objects 1304: Dirt_obj
>	Objects 281: Enemy_Scratch_obj
>	Objects 793: Play_2_Player_obj
>	Objects 1305: Pumpkin_Patch_obj
>	Objects 282: Event_Text_obj
>	Objects 794: Play_Keyboard_obj
>	Objects 1306: Dirt_Parent_obj
>	Objects 283: Explosion_Visual_Small_obj
>	Objects 795: Play_Gamepad_obj
>	Objects 1307: Dirt_Pentagram_obj
>	Objects 284: Explosion_Ball_Friendly_obj
>	Objects 796: Play_Back_obj
>	Objects 1308: Dirt_Zen_obj
>	Objects 285: Explosion_Ball_obj
>	Objects 797: Google_Play_Ad_obj
>	Objects 1309: Garden_1_obj
>	Objects 286: Explosion_Chemical_obj
>	Objects 798: App_Store_Ad_obj
>	Objects 1310: Garden_2_obj
>	Objects 287: Explosion_Fireball_obj
>	Objects 799: IAP_1_obj
>	Objects 1311: Garden_3_obj
>	Objects 288: Explosion_Lightning_obj
>	Objects 800: IAP_2_obj
>	Objects 1312: Garden_4_obj
>	Objects 289: Explosion_Meteor_obj
>	Objects 801: IAP_3_obj
>	Objects 1313: Garden_5_obj
>	Objects 290: Explosion_obj
>	Objects 802: IAP_4_obj
>	Objects 1314: Garden_Parent_obj
>	Objects 291: Explosion_Instakill_obj
>	Objects 803: Menu_Logo_obj
>	Objects 1315: Garden_Pentagram_obj
>	Objects 292: Explosion_Trap_obj
>	Objects 804: Season_obj
>	Objects 1316: Garden_Pond_obj
>	Objects 293: Explosion_Potion_obj
>	Objects 805: Menu_Logo_Mobile_obj
>	Objects 1317: Grass_obj
>	Objects 294: Fade_In_obj
>	Objects 806: Ladder_obj
>	Objects 1318: Ice_Pond_obj
>	Objects 295: Fade_Out_obj
>	Objects 807: PanicNet_Logo_obj
>	Objects 1319: Icy_Ground_obj
>	Objects 296: Fireball_Fade_obj
>	Objects 808: Android_Ad_obj
>	Objects 1320: Path_Castle_obj
>	Objects 297: Flying_Parent_obj
>	Objects 809: Steam_Wheel_Menu_obj
>	Objects 1321: Path_Pentagram_obj
>	Objects 298: Intro_Text_obj
>	Objects 810: Keyboard_obj
>	Objects 1322: Pond_obj
>	Objects 299: Glimmer_obj
>	Objects 811: Menu_Play_obj
>	Objects 1323: Railroad_obj
>	Objects 300: Gore_Meat_obj
>	Objects 812: Menu_Multiplayer_obj
>	Objects 1324: Small_Dirt_obj
>	Objects 301: Graveyard_Fog_obj
>	Objects 813: Menu_Options_obj
>	Objects 1325: Winter_Cliff_obj
>	Objects 302: Ground_Shred_obj
>	Objects 814: Menu_Achievements_obj
>	Objects 1326: Winter_Void_obj
>	Objects 303: Health_Particle_obj
>	Objects 815: Menu_Siege_obj
>	Objects 1327: Zen_River_obj
>	Objects 304: Health_Pick_obj
>	Objects 816: Choosing_Back_Menu_obj
>	Objects 1328: Prop_1_Sheep_obj
>	Objects 305: Holy_Shield_obj
>	Objects 817: Menu_Back_obj
>	Objects 1329: Prop_2_Sheep_obj
>	Objects 306: Holy_Shock_obj
>	Objects 818: Dlc_Token_obj
>	Objects 1330: Prop_3_Sheep_obj
>	Objects 307: Honey_Pool_obj
>	Objects 819: Login_Backgrounds_obj
>	Objects 1331: Prop_4_Sheep_obj
>	Objects 308: Ice_Enchant_Perish_obj
>	Objects 820: Register_Backgrounds_obj
>	Objects 1332: Halloween_Candle_1_obj
>	Objects 309: Keygen_obj
>	Objects 821: Controller_Info_obj
>	Objects 1333: Halloween_Candle_2_spr
>	Objects 310: KG_1000_obj
>	Objects 822: Back_Tab_obj
>	Objects 1334: Halloween_Pumpkin_obj
>	Objects 311: Laser_Beam_obj
>	Objects 823: Clothing_Tab_obj
>	Objects 1335: Halloween_Coffin_spr
>	Objects 312: Level_Up_obj
>	Objects 824: Minion_Tab_obj
>	Objects 1336: Halloween_Cape_spr
>	Objects 313: Light_Blue_Clouds_obj
>	Objects 825: Name_Color_Tab_obj
>	Objects 1337: Candy_Cane_Prop_obj
>	Objects 314: Light_Effect_obj
>	Objects 826: Portrait_Tab_obj
>	Objects 1338: Zen_Torch_Town_obj
>	Objects 315: Light_Luukku_obj
>	Objects 827: Shop_Redeem_obj
>	Objects 1339: Candle_Stand_Town_obj
>	Objects 316: Light_obj
>	Objects 828: Dummy_Hat_obj
>	Objects 1340: Grave_Sheep_Creator_obj
>	Objects 317: Lightning_Enchant_Shred_obj
>	Objects 829: Dummy_Minion_obj
>	Objects 1341: Grave_Sheep_obj
>	Objects 318: Lightning_obj
>	Objects 830: Name_Colors_obj
>	Objects 1342: Portal_Sheeponia_obj
>	Objects 319: Maggot_Bubble_obj
>	Objects 831: Portraits_obj
>	Objects 1343: Sheep_Number_obj
>	Objects 320: Moonshine_obj
>	Objects 832: Shop_Control_obj
>	Objects 1344: Statue_Sheep_obj
>	Objects 321: Muzzle_Fire_obj
>	Objects 833: Iap_T4_obj
>	Objects 1345: Hydra_Statue_Town_obj
>	Objects 322: Note_obj
>	Objects 834: Iap_T3_obj
>	Objects 1346: Grave_Town_obj
>	Objects 323: Oil_Fly_obj
>	Objects 835: Iap_T2_obj
>	Objects 1347: Cactus_Town_obj
>	Objects 324: Water_Overlay_obj
>	Objects 836: Iap_T1_obj
>	Objects 1348: Portal_Platform_obj
>	Objects 325: paska_vittu_obj
>	Objects 837: Iap_Retrieve_obj
>	Objects 1349: Tinker_Platform_obj
>	Objects 326: Pentagram_Particle_obj
>	Objects 838: Iap_Gold_Boost_obj
>	Objects 1350: Portal_Platform_Cathedral_obj
>	Objects 327: Plant_Shred_obj
>	Objects 839: Iap_Exp_Boost_obj
>	Objects 1351: Portal_Platform_Sand_obj
>	Objects 328: Plant_Zen_Remains_obj
>	Objects 840: Iap_DLC_obj
>	Objects 1352: Portal_Platform_Snow_obj
>	Objects 329: Puke_obj
>	Objects 841: Blaze_Hellfire_obj
>	Objects 1353: Portal_Platform_Wood_obj
>	Objects 330: Question_obj
>	Objects 842: Flame_Hellfire_obj
>	Objects 1354: Portal_Platform_Jungle_obj
>	Objects 331: Sand_Clouds_obj
>	Objects 843: Hellfire_obj
>	Objects 1355: Village_Well_obj
>	Objects 332: Snow_Splash_obj
>	Objects 844: Direction_Arrow_obj
>	Objects 1356: Portal_Platform_Zen_obj
>	Objects 333: Soul_Enemy_obj
>	Objects 845: Direction_Arrow_Portal_obj
>	Objects 1357: Difficulty_Text_Platform_obj
>	Objects 334: Soul_Explosion_obj
>	Objects 846: Enemy_Damage_Parent_obj
>	Objects 1358: Act_Worker_obj
>	Objects 335: Stomp_obj
>	Objects 847: Enemy_Damage_Parent_Projectile_obj
>	Objects 1359: Beachball_obj
>	Objects 336: Trail_obj
>	Objects 848: Alert_obj
>	Objects 1360: Valve_Platform_obj
>	Objects 337: Stoneskin_obj
>	Objects 849: Player_Silhouette_obj
>	Objects 1361: Difficulty_Platform_obj
>	Objects 338: Tornado_Clouds_obj
>	Objects 850: Blood_Orb_obj
>	Objects 1362: Attack_Dummy_obj
>	Objects 339: Traveler_obj
>	Objects 851: Duck_obj
>	Objects 1363: Zone_1_obj
>	Objects 340: Oil_Ground_obj
>	Objects 852: Rainbow_Creator_obj
>	Objects 1364: Zone_2_obj
>	Objects 341: Treasure_Goblin_Poof_obj
>	Objects 853: Angel_Wings_obj
>	Objects 1365: Zone_3_obj
>	Objects 342: Water_Bubble_Direction_obj
>	Objects 854: Apocalypse_obj
>	Objects 1366: Zone_4_obj
>	Objects 343: Water_Bubble_obj
>	Objects 855: Apple_obj
>	Objects 1367: Zone_5_obj
>	Objects 344: Water_Mark_obj
>	Objects 856: Balalayka_obj
>	Objects 1368: The_Void_Portal_obj
>	Objects 345: Whirl_Fade_obj
>	Objects 857: Beer_Fly_obj
>	Objects 1369: The_Void_Inside_Portal_obj
>	Objects 346: Whirl_obj
>	Objects 858: Beer_Ground_obj
>	Objects 1370: Portal_Act_1_obj
>	Objects 347: White_Clouds_Angel_obj
>	Objects 859: Blazing_Boots_obj
>	Objects 1371: Portal_Act_2_obj
>	Objects 348: Viking_Bash_Effect_obj
>	Objects 860: Blood_Shockwave_obj
>	Objects 1372: Portal_Act_3_obj
>	Objects 349: Volcano_Particle_obj
>	Objects 861: Bomb_obj
>	Objects 1373: Portal_Act_4_obj
>	Objects 350: You_Died_obj
>	Objects 862: Boomerang_obj
>	Objects 1374: Portal_Act_5_obj
>	Objects 351: Movie_Screen_obj
>	Objects 863: Bouncy_obj
>	Objects 1375: Portal_Act_6_obj
>	Objects 352: Abomination_Radius_obj
>	Objects 864: Cactus_Grow_obj
>	Objects 1376: Portal_Act_7_obj
>	Objects 353: Abomination_Spike_obj
>	Objects 865: Candy_Crusher_obj
>	Objects 1377: Portal_Act_8_obj
>	Objects 354: Gabriel_obj
>	Objects 866: Candy_Rain_obj
>	Objects 1378: Castle_Hut_2_obj
>	Objects 355: Gabriel_Lightning_obj
>	Objects 867: Chain_Lightning_obj
>	Objects 1379: Castle_Hut_obj
>	Objects 356: Abomination_WH_obj
>	Objects 868: Cold_Hit_obj
>	Objects 1380: Barrel_obj
>	Objects 357: Annie_Arrow_obj
>	Objects 869: Critical_obj
>	Objects 1381: Fire_obj
>	Objects 358: Annie_Fire_obj
>	Objects 870: Dart_obj
>	Objects 1382: Fountain_obj
>	Objects 359: Annie_Ghost_WH_obj
>	Objects 871: Delicious_Pie_obj
>	Objects 1383: Fountain_Random_obj
>	Objects 360: Annie_Puppet_obj
>	Objects 872: Dragon_Flame_obj
>	Objects 1384: Prop_10_obj
>	Objects 361: Gabriel_Rock_obj
>	Objects 873: Explosion_Item_obj
>	Objects 1385: Raizo_Statue_obj
>	Objects 362: Annie_WH_obj
>	Objects 874: Fire_Hit_obj
>	Objects 1386: Big_Ruins_obj
>	Objects 363: Parasectoid_WH_obj
>	Objects 875: Flame_Odin_obj
>	Objects 1387: Pyramid_Torch_obj
>	Objects 364: Kaboraga_WH_obj
>	Objects 876: Fly_Ball_Eye_obj
>	Objects 1388: Candle_1_obj
>	Objects 365: Parasectoid_Moon_obj
>	Objects 877: Frostmourne_Ice_obj
>	Objects 1389: Blood_Spot_obj
>	Objects 366: Parasectoid_DNA_obj
>	Objects 878: Headphones_obj
>	Objects 1390: Candle_2_obj
>	Objects 367: Parasectoid_WH_Blood_obj
>	Objects 879: Hit_obj
>	Objects 1391: Kings_Throne_obj
>	Objects 368: Demon_Lightning_obj
>	Objects 880: Homing_Fly_obj
>	Objects 1392: Rock_Shred_obj
>	Objects 369: Pyramid_WH_obj
>	Objects 881: Honey_Ball_obj
>	Objects 1393: Kings_Banner_obj
>	Objects 370: Pyramid_Tornado_obj
>	Objects 882: Hook_obj
>	Objects 1394: Shovel_obj
>	Objects 371: Kaboraga_Hands_obj
>	Objects 883: Thiefs_Glove_obj
>	Objects 1395: Bone_Passage_obj
>	Objects 372: Demon_God_obj
>	Objects 884: Ice_Flame_obj
>	Objects 1396: Karp_King_Statue_obj
>	Objects 373: Wall_Indicator_obj
>	Objects 885: Impale_obj
>	Objects 1397: Bone_Spike_obj
>	Objects 374: Mummy_Anubis_obj
>	Objects 886: Knockback_obj
>	Objects 1398: Bubble_Crack_obj
>	Objects 375: Chain_Anubis_obj
>	Objects 887: Laser_obj
>	Objects 1399: Cart_obj
>	Objects 376: Sarkofagus_Anubis_obj
>	Objects 888: Poison_obj
>	Objects 1400: Book_Shelf_Large_obj
>	Objects 377: Anubis_New_obj
>	Objects 889: Rainbow_Drool_obj
>	Objects 1401: Book_Shelf_Small_obj
>	Objects 378: Elemental_obj
>	Objects 890: Razor_Leaves_obj
>	Objects 1402: Crystal_Node_obj
>	Objects 379: Gurag_Minion_obj
>	Objects 891: Rocket_Barrage_obj
>	Objects 1403: Grave_obj
>	Objects 380: Gurag_Orbiter_obj
>	Objects 892: Satans_Horn_Hitbox_obj
>	Objects 1404: Graveyard_1_obj
>	Objects 381: Orbiter_Shoot_obj
>	Objects 893: Shiv_Creator_obj
>	Objects 1405: Impaled_Spike_obj
>	Objects 382: Reaper_obj
>	Objects 894: Shiv_obj
>	Objects 1406: Mining_Site_obj
>	Objects 383: Karp_King_obj
>	Objects 895: Shout_Balalayka
>	Objects 1407: Mushroom_obj
>	Objects 384: Anubis_obj
>	Objects 896: Skull_Player_obj
>	Objects 1408: Statue_Dungeon_obj
>	Objects 385: Satan_obj
>	Objects 897: Shuriken_obj
>	Objects 1409: Light_Mushroom_obj
>	Objects 386: Satans_Left_Hand_obj
>	Objects 898: Small_Spikey_obj
>	Objects 1410: Passage_obj
>	Objects 387: Satans_Right_Hand_obj
>	Objects 899: Squishy_obj
>	Objects 1411: Pick_Axe_obj
>	Objects 388: Damien_obj
>	Objects 900: Squishy_Rock_obj
>	Objects 1412: Prop_2_Dark_obj
>	Objects 389: Mevius_Spike_Controller_obj
>	Objects 901: Stickman_obj
>	Objects 1413: Prop_9_obj
>	Objects 390: Mevius_Chain_Controller_obj
>	Objects 902: Storm_obj
>	Objects 1414: Pylvas_obj
>	Objects 391: Shelf_Pieces_obj
>	Objects 903: Sun_Flare_obj
>	Objects 1415: Temple_Pillar_obj
>	Objects 392: Mevius_Wall_obj
>	Objects 904: Sushi_Projectile_obj
>	Objects 1416: Dungeon_Pillar_obj
>	Objects 393: Mevius_Soul_obj
>	Objects 905: Titan_obj
>	Objects 1417: Ruins_obj
>	Objects 394: Mevius_Puppet_obj
>	Objects 906: Vadjra_obj
>	Objects 1418: Sea_Shred_obj
>	Objects 395: Mevius_obj
>	Objects 907: Wisp_Necromancers_Finger_obj
>	Objects 1419: Sea_Star_obj
>	Objects 396: Mevius_Chain_obj
>	Objects 908: Minion_Arrow_obj
>	Objects 1420: Wall_Cemetary_obj
>	Objects 397: Damien_Destructor_obj
>	Objects 909: Minion_Dead_obj
>	Objects 1421: Wall_Desert_obj
>	Objects 398: Damien_Block_Parent_obj
>	Objects 910: Multiplayer_Dead_obj
>	Objects 1422: Wall_Night_obj
>	Objects 399: Damien_Block_1_obj
>	Objects 911: Nyan_obj
>	Objects 1423: Wall_obj
>	Objects 400: Damien_Block_2_obj
>	Objects 912: Astral_Wolf_obj
>	Objects 1424: Wall_Train_obj
>	Objects 401: Damien_Block_3_obj
>	Objects 913: Hitbox_Parrot_obj
>	Objects 1425: Wall_Bush_obj
>	Objects 402: Damien_Block_4_obj
>	Objects 914: Hitbox_Summon_obj
>	Objects 1426: Wall_Winter_obj
>	Objects 403: Damien_Ball_obj
>	Objects 915: Minion_obj
>	Objects 1427: Wall_Wooden_obj
>	Objects 404: Damien_Charge_obj
>	Objects 916: Pickled_Zombie_obj
>	Objects 1428: Wall_Void_obj
>	Objects 405: Damien_2_obj
>	Objects 917: Spell_Summon_obj
>	Objects 1429: Wall_Cathedral_obj
>	Objects 406: Damien_Head_2_obj
>	Objects 918: Summon_Golem_obj
>	Objects 1430: Wall_Pumpkin_obj
>	Objects 407: Boss_Spawner_obj
>	Objects 919: Summon_Mage_obj
>	Objects 1431: Wall_Wooden_Winter_obj
>	Objects 408: Damien_Head_obj
>	Objects 920: Summon_Mauler_obj
>	Objects 1432: Wall_Zen_obj
>	Objects 409: Worm_Hole_Boss_Spawner_obj
>	Objects 921: Summon_Parent_obj
>	Objects 1433: Wall_Parent_obj
>	Objects 410: Gurag_Bolt_obj
>	Objects 922: Parrot_obj
>	Objects 1434: Column_Winter_obj
>	Objects 411: Reaper_Scythe_obj
>	Objects 923: Demon_Sheep_obj
>	Objects 1435: Snow_Hut_obj
>	Objects 412: Scythe_Reaper_Death_obj
>	Objects 924: Dragon_Enchant_obj
>	Objects 1436: Snow_Hut_2_obj
>	Objects 413: Uber_Damien_obj
>	Objects 925: Fetus_obj
>	Objects 1437: Snowman_obj
>	Objects 414: Gate_Keeper_obj
>	Objects 926: Skullbat_obj
>	Objects 1438: Random_Tree_Winter_obj
>	Objects 415: Death_Hand_Effect_obj
>	Objects 927: Gull_of_Doom_obj
>	Objects 1439: Snow_Junk_obj
>	Objects 416: Destroy_Relics_obj
>	Objects 928: Ancient_Rock_obj
>	Objects 1440: Prop_1_Winter_obj
>	Objects 417: Akrea_obj
>	Objects 929: Shrunken_Head_obj
>	Objects 1441: Prop_2_Winter_obj
>	Objects 418: Beketamun_obj
>	Objects 930: Dungeon_Lantern_obj
>	Objects 1442: Prop_3_Winter_obj
>	Objects 419: Dahzul_obj
>	Objects 931: Karp_Head_obj
>	Objects 1443: Prop_5_Winter_obj
>	Objects 420: Eye_obj
>	Objects 932: Minisect_obj
>	Objects 1444: Prop_9_Winter_obj
>	Objects 421: Eye_Small_Side_2_obj
>	Objects 933: The_Eye_obj
>	Objects 1445: Lake_Crystal_obj
>	Objects 422: Eye_Small_Side_obj
>	Objects 934: Honey_Bee_obj
>	Objects 1446: Dungeon_Ice_Pillar_obj
>	Objects 423: Ent_Boss_obj
>	Objects 935: Zeppelin_obj
>	Objects 1447: Crystal_Junk_obj
>	Objects 424: Abomination_obj
>	Objects 936: Money_Bag_obj
>	Objects 1448: Crystal_Altar_obj
>	Objects 425: Kayo_obj
>	Objects 937: Fedora_obj
>	Objects 1449: Winter_Ruins_obj
>	Objects 426: Mask_obj
>	Objects 938: Ankh_obj
>	Objects 1450: Winter_Blood_Spot_obj
>	Objects 427: Khorga_obj
>	Objects 939: Guardian_Angel_obj
>	Objects 1451: Moon_Platform_obj
>	Objects 428: Kayako_obj
>	Objects 940: Ice_Enchant_obj
>	Objects 1452: Moon_Stone_obj
>	Objects 429: Pontus_obj
>	Objects 941: Jar_Fly_obj
>	Objects 1453: Round_Platform_obj
>	Objects 430: Parasectoid_obj
>	Objects 942: Lightning_Enchant_obj
>	Objects 1454: Round_Stone_obj
>	Objects 431: Sheep_King_obj
>	Objects 943: Orbit_Arranger_obj
>	Objects 1455: Square_Platform_obj
>	Objects 432: Kungo_obj
>	Objects 944: Orbit_Parent_obj
>	Objects 1456: Square_Stone_obj
>	Objects 433: Hayro_obj
>	Objects 945: Shredder_obj
>	Objects 1457: Triangle_Platform_obj
>	Objects 434: Hololo_obj
>	Objects 946: Templar_Shield_obj
>	Objects 1458: Triangle_Stone_obj
>	Objects 435: Pogocho_obj
>	Objects 947: Vorpal_Enchant_obj
>	Objects 1459: Obelisk_obj
>	Objects 436: Kaw_obj
>	Objects 948: Paladin_2_obj
>	Objects 1460: Bard_NPC_obj
>	Objects 437: Sir_Jonathan_obj
>	Objects 949: Paladin_obj
>	Objects 1461: David_NPC_obj
>	Objects 438: Kalcifer_obj
>	Objects 950: Pirate_obj
>	Objects 1462: DR_Tinker_Dink_NPC_obj
>	Objects 439: Colossal_Anomaly_obj
>	Objects 951: Pirate_2_obj
>	Objects 1463: Edward_NPC_obj
>	Objects 440: Igor_obj
>	Objects 952: Pyromancer_2_obj
>	Objects 1464: Eric_NPC_obj
>	Objects 441: Gaben_obj
>	Objects 953: Pyromancer_obj
>	Objects 1465: Gar_Nor_NPC_obj
>	Objects 442: Garguth_obj
>	Objects 954: White_Mage_obj
>	Objects 1466: Ishmail_NPC_obj
>	Objects 443: Flesh_Plant_obj
>	Objects 955: White_Mage_2_obj
>	Objects 1467: Jack_The_Ripper_NPC_obj
>	Objects 444: Gimbo_obj
>	Objects 956: Necromancer_obj
>	Objects 1468: Kayla_NPC_obj
>	Objects 445: James_obj
>	Objects 957: Necromancer_2_obj
>	Objects 1469: Land_Lord_Kukkonen_NPC_obj
>	Objects 446: Nightmare_Ooze_obj
>	Objects 958: Nomad_2_obj
>	Objects 1470: Magister_Kujala_NPC_obj
>	Objects 447: Necronomicon_obj
>	Objects 959: Nomad_obj
>	Objects 1471: Princess_Kiril_NPC_obj
>	Objects 448: Gargorath_obj
>	Objects 960: Marksman_obj
>	Objects 1472: Sir_Abel_NPC_obj
>	Objects 449: Player_Sound_obj
>	Objects 961: Shaman_obj
>	Objects 1473: Um_NPC_obj
>	Objects 450: Portal_obj
>	Objects 962: Shaman_2_obj
>	Objects 1474: Volgar_NPC_obj
>	Objects 451: Portal_Siege_obj
>	Objects 963: Marksman_2_obj
>	Objects 1475: Pumpkin_NPC_obj
>	Objects 452: Portal_Town_obj
>	Objects 964: Steve_obj
>	Objects 1476: The_Sarcaster_obj
>	Objects 453: Portal_Zone_obj
>	Objects 965: Demon_Spawn_obj
>	Objects 1477: Town_Stash_obj
>	Objects 454: PVP_Portal_obj
>	Objects 966: Demon_Spawn_2_obj
>	Objects 1478: Christmas_Note_obj
>	Objects 455: Tinker_Dink_Portal_obj
>	Objects 967: Amazon_obj
>	Objects 1479: Snowman_NPC_obj
>	Objects 456: Wormhole_Portal_obj
>	Objects 968: Amazon_2_obj
>	Objects 1480: Quest_Text_obj
>	Objects 457: Sheep_King_Spawner_obj
>	Objects 969: Demon_Slayer_obj
>	Objects 1481: Bard_Guitar_obj
>	Objects 458: Enemy_Creator_obj
>	Objects 970: Demon_Slayer_2_obj
>	Objects 1482: Quest_NPC_Parent_obj
>	Objects 459: Enemy_Parent_obj
>	Objects 971: Redneck_obj
>	Objects 1483: Bone_Quest_obj
>	Objects 460: Enemy_Parent_Active_obj
>	Objects 972: Redneck_2_obj
>	Objects 1484: Generator_obj
>	Objects 461: Enemy_Parent_Passive_obj
>	Objects 973: Samurai_obj
>	Objects 1485: Item_Pickup_Effect_obj
>	Objects 462: Acid_Ground_obj
>	Objects 974: Samurai_2_obj
>	Objects 1486: Shop_Decoration_obj
>	Objects 463: Anomaly_Blood_obj
>	Objects 975: Viking_2_obj
>	Objects 1487: Jacks_Box_obj
>	Objects 464: Anomaly_Shred_obj
>	Objects 976: Viking_obj
>	Objects 1488: Jacks_Key_obj
>	Objects 465: Anubis_Charged_Bolt_obj
>	Objects 977: Doom_Particle_obj
>	Objects 1489: Metal_Debris_obj
>	Objects 466: Anubis_Controller_obj
>	Objects 978: Player_1_obj
>	Objects 1490: Candy_Halloween_obj
>	Objects 467: Anubis_Light_obj
>	Objects 979: Player_2_obj
>	Objects 1491: Moonshine_Quest_obj
>	Objects 468: Anubis_Meteor_obj
>	Objects 980: Player_Arrow_obj
>	Objects 1492: Prisoner_Quest_obj
>	Objects 469: Arrow_Enemy_obj
>	Objects 981: Player_Damage_Parent_obj
>	Objects 1493: Prisoner_Rescued_obj
>	Objects 470: Arrow_Trap_obj
>	Objects 982: Player_Damage_Parent_Projectile_obj
>	Objects 1494: Quest_Mushroom_obj
>	Objects 471: Betankhamun_Tornado_obj
>	Objects 983: Player_obj
>	Objects 1495: Quest_Object_Parent_obj
>	Objects 472: Bonerang_obj
>	Objects 984: Player_Burning_obj
>	Objects 1496: Shop_Keeper_obj
>	Objects 473: Cannon_Tower_Projectile_obj
>	Objects 985: Healthglobe_obj
>	Objects 1497: Thank_You_obj
>	Objects 474: Charge_Effect_obj
>	Objects 986: Managlobe_obj
>	Objects 1498: Treasure_Mark_obj
>	Objects 475: Charged_Bolt_obj
>	Objects 987: Projectile_Parent_obj
>	Objects 1499: Um_Altar_obj
>	Objects 476: Charged_Creator_obj
>	Objects 988: Poison_Gas_obj
>	Objects 1500: Dust_Creator_obj
>	Objects 477: Charged_Stopper_obj
>	Objects 989: Leap_Mask_obj
>	Objects 1501: Falling_Debris_obj
>	Objects 478: Dahzul_Bouncy_obj
>	Objects 990: Amazon_Thunderstorm_obj
>	Objects 1502: Falling_Dust_obj
>	Objects 479: Death_Spawn_obj
>	Objects 991: Amazon_Chain_Lightning_obj
>	Objects 1503: Shake_Mini_obj
>	Objects 480: Elemental_Rock_2_obj
>	Objects 992: Spear_obj
>	Objects 1504: Shake_Miniboss_obj
>	Objects 481: Elemental_Rock_obj
>	Objects 993: Spear_Ground_obj
>	Objects 1505: Shake_Minor_obj
>	Objects 482: Enemy_Ball_Large_obj
>	Objects 994: Hitbox_Demonslayer_1_obj
>	Objects 1506: Shake_obj
>	Objects 483: Enemy_Ball_obj
>	Objects 995: Hitbox_Demonslayer_2_obj
>	Objects 1507: Shake_Parent_obj
>	Objects 484: Enemy_Ball_Stone_Head_obj
>	Objects 996: Demon_Shredder_obj
>	Objects 1508: Shake_Cathedral_obj
>	Objects 485: Entagle_obj
>	Objects 997: Swirling_Katanas_obj
>	Objects 1509: Shake_Small_obj
>	Objects 486: Exploding_Flower_obj
>	Objects 998: Execute_obj
>	Objects 1510: Monument_obj
>	Objects 487: Falling_Meteor_obj
>	Objects 999: Demon_Slayer_Bullet_obj
>	Objects 1511: Acid_Creator_obj
>	Objects 488: Falling_Rock_Shred_obj
>	Objects 1000: Stun_Hitbox_obj
>	Objects 1512: Black_Hole_Effect_obj
>	Objects 489: Fire_Meteor_Spot_obj
>	Objects 1001: Spread_Shot_obj
>	Objects 1513: Black_Hole_obj
>	Objects 490: Fire_Nova_Enemy_obj
>	Objects 1002: Scatter_Demon_Slayer_obj
>	Objects 1514: Blowfish_obj
>	Objects 491: Fireball_Enemy_obj
>	Objects 1003: Blood_Demon_obj
>	Objects 1515: Boulder_Shadow_obj
>	Objects 492: Flame_Meteor_obj
>	Objects 1004: Blood_Surge_obj
>	Objects 1516: Cannon_Tower_obj
>	Objects 493: Flesh_Sprout_obj
>	Objects 1005: Blood_Bolt_obj
>	Objects 1517: Chilling_Tornado_obj
>	Objects 494: Frost_Arrow_Volley_obj
>	Objects 1006: Arrow_obj
>	Objects 1518: Dart_Hole_obj
>	Objects 495: Frost_Nova_Enemy_obj
>	Objects 1007: Arrow_Rampage_obj
>	Objects 1519: Deadly_Boulder_obj
>	Objects 496: Frost_Skeleton_Whirlwind_obj
>	Objects 1008: Boom_obj
>	Objects 1520: Deadly_Ground_obj
>	Objects 497: Frost_Volley_Area_obj
>	Objects 1009: Mine_obj
>	Objects 1521: Devil_Head_obj
>	Objects 498: Giant_Shockwave_obj
>	Objects 1010: Arrow_Ground_obj
>	Objects 1522: Enemy_Flame_obj
>	Objects 499: Gurag_Shockwave_obj
>	Objects 1011: Blaze_Marksman_obj
>	Objects 1523: Event_Goblin_Spawner_obj
>	Objects 500: Homing_Fly
>	Objects 1012: Missile_obj
>	Objects 1524: Event_Money_Rain_obj
>	Objects 501: Ice_Spikes_obj
>	Objects 1013: Rampage_Controller_obj
>	Objects 1525: Event_Toxic_Fire_Rain_obj
>	Objects 502: Jormungar_Spike_obj
>	Objects 1014: Turret_Multi_obj
>	Objects 1526: Event_Turrets_obj
>	Objects 503: Karp_Light_obj
>	Objects 1015: Turret_obj
>	Objects 1527: Fire_Trap_Left_obj
>	Objects 504: Karp_Light_Shadow_obj
>	Objects 1016: Turret_Arrow_obj
>	Objects 1528: Fire_Trap_Right_obj
>	Objects 505: Kayo_Skull_obj
>	Objects 1017: Channel_obj
>	Objects 1529: Flame_Tower_obj
>	Objects 506: Khorga_Hook_obj
>	Objects 1018: Channel_Small_obj
>	Objects 1530: Flame_Tower_Static_obj
>	Objects 507: Maggot_Spit_Ground_obj
>	Objects 1019: Poison_Nova_obj
>	Objects 1531: Giljotiini_obj
>	Objects 508: Maggot_Spit_obj
>	Objects 1020: Wisp_obj
>	Objects 1532: Giljotiini_Shadow_obj
>	Objects 509: Meteor_Impact_Spot_obj
>	Objects 1021: Meat_Bomb_obj
>	Objects 1533: Goblin_Train_Cannon_obj
>	Objects 510: Molten_Bubbling_obj
>	Objects 1022: Small_Meat_obj
>	Objects 1534: Hand_Statue_obj
>	Objects 511: Volcanic_Bubbling_obj
>	Objects 1023: Necromancer_Dust_obj
>	Objects 1535: Karp_King_Spike_Ball_obj
>Room_Prepare() 
>Sound_Prepare() 
>Cannot connect to server socket err = No such file or directory
>Cannot connect to server request channel
>jack server is not running or cannot be started
>JackShmReadWritePtr::~JackShmReadWritePtr - Init not done for -1, skipping unlock
>JackShmReadWritePtr::~JackShmReadWritePtr - Init not done for -1, skipping unlock
>InitGraphics() 
>Finished PrepareGame() 
>Run_Start
>LOAD: checking file shop.ini
>LOAD: numFiles 1, numBundleFiles 0
>Total memory used = 254117192(0x0f258548) bytes
>**********************************.
>Entering main loop.
>**********************************.
>Texture #1 16,16
>Texture #2 16,16
>Texture #3 966,544
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL OUT[0], POSITION
>DCL OUT[1], GENERIC[0]
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1], IN[1]
>  2: END
>radeonsi: Compiling shader 30
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #0
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
>
>define amdgpu_vs void @wrapper([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #2 {
>main_body:
>  %12 = add i32 %8, %4
>  %13 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %14 = load <4 x i32>, <4 x i32> addrspace(2)* %13, align 16, !invariant.load !0, !alias.scope !1
>  %15 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %14, i32 %12, i32 0, i1 false, i1 false) #3
>  %16 = extractelement <4 x float> %15, i32 0
>  %17 = extractelement <4 x float> %15, i32 1
>  %18 = extractelement <4 x float> %15, i32 2
>  %19 = extractelement <4 x float> %15, i32 3
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %16, float %17, float %18, float %19, i1 true, i1 false) #1, !noalias !1
>  ret void
>}
>
>attributes #0 = { nounwind readonly }
>attributes #1 = { nounwind }
>attributes #2 = { "no-signed-zeros-fp-math"="true" }
>attributes #3 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!2}
>!2 = distinct !{!2, !3, !"main: argument 0"}
>!3 = distinct !{!3, !"main"}
>
>SHADER KEY
>  part.vs.prolog.instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  mono.u.vs_export_prim_id = 0
>  opt.hw_vs.kill_outputs = 0x2
>  opt.hw_vs.clip_disable = 0
>
>Vertex Shader as VS:
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[6:7], 0x0                  ; C00A0003 00000000
>	v_add_i32_e32 v0, vcc, s8, v0                       ; 32000008
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen ; E00C2000 80000000
>	s_waitcnt vmcnt(0)                                  ; BF8C0F70
>	exp pos0 v0, v1, v2, v3 done                        ; C40008CF 03020100
>	s_endpgm                                            ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 16
>VGPRS: 4
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 40 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>FRAG
>DCL IN[0], GENERIC[0], LINEAR
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL SVIEW[0], 2D, FLOAT
>DCL TEMP[0..1]
>  0: F2I TEMP[1], IN[0]
>  1: TXF_LZ TEMP[0], TEMP[1], SAMP[0], 2D
>  2: MOV OUT[0], TEMP[0]
>  3: END
>radeonsi: Compiling shader 31
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = bitcast <2 x i32> %10 to <2 x float>
>  %22 = extractelement <2 x float> %21, i32 0
>  %23 = extractelement <2 x float> %21, i32 1
>  %24 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 0, i32 0, i32 %4) #3
>  %25 = call nsz float @llvm.amdgcn.interp.p2(float %24, float %23, i32 0, i32 0, i32 %4) #3
>  %26 = fptosi float %25 to i32
>  %27 = call nsz float @llvm.amdgcn.interp.p1(float %22, i32 1, i32 0, i32 %4) #3
>  %28 = call nsz float @llvm.amdgcn.interp.p2(float %27, float %23, i32 1, i32 0, i32 %4) #3
>  %29 = fptosi float %28 to i32
>  %30 = getelementptr [80 x <8 x i32>], [80 x <8 x i32>] addrspace(2)* %2, i64 0, i64 16, !amdgpu.uniform !0
>  %31 = load <8 x i32>, <8 x i32> addrspace(2)* %30, align 32, !invariant.load !0
>  %32 = insertelement <2 x i32> undef, i32 %26, i32 0
>  %33 = insertelement <2 x i32> %32, i32 %29, i32 1
>  %34 = call nsz <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %33, <8 x i32> %31, i32 15, i1 false, i1 false, i1 false, i1 false) #3
>  %35 = extractelement <4 x float> %34, i32 0
>  %36 = extractelement <4 x float> %34, i32 1
>  %37 = extractelement <4 x float> %34, i32 2
>  %38 = extractelement <4 x float> %34, i32 3
>  %39 = bitcast float %3 to i32
>  %40 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %39, 6
>  %41 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %40, float %35, 7
>  %42 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %41, float %36, 8
>  %43 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %42, float %37, 9
>  %44 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %43, float %38, 10
>  %45 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %44, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %45
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p1(float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.p2(float, float, i32, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readonly }
>attributes #3 = { nounwind readnone }
>
>!0 = !{}
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>	s_mov_b32 m0, s7                                   ; BEFC0007
>	v_interp_p1_f32 v0, v8, attr0.x                    ; D4000008
>	v_interp_p1_f32 v1, v8, attr0.y                    ; D4040108
>	v_interp_p2_f32 v0, v9, attr0.x                    ; D4010009
>	v_interp_p2_f32 v1, v9, attr0.y                    ; D4050109
>	s_load_dwordx8 s[8:15], s[4:5], 0x200              ; C00E0202 00000200
>	v_cvt_i32_f32_e32 v0, v0                           ; 7E001100
>	v_cvt_i32_f32_e32 v1, v1                           ; 7E021101
>	s_waitcnt lgkmcnt(0)                               ; BF8C007F
>	image_load v[0:3], v[0:1], s[8:15] dmask:0xf unorm ; F0001F00 00020000
>	s_waitcnt vmcnt(0)                                 ; BF8C0F70
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32 v0, v0, v1        ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32 v1, v2, v3        ; D2960001 00020702
>	exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100
>	s_endpgm                              ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0020
>*** SHADER STATS ***
>SGPRS: 16
>VGPRS: 16
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 80 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>radeonsi: Compiling shader 32
>Vertex Shader Prolog LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_vs <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> @vs_prolog(i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 {
>main_body:
>  %16 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> undef, i32 %0, 0
>  %17 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %16, i32 %1, 1
>  %18 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %17, i32 %2, 2
>  %19 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %18, i32 %3, 3
>  %20 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %19, i32 %4, 4
>  %21 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %20, i32 %5, 5
>  %22 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %21, i32 %6, 6
>  %23 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %22, i32 %7, 7
>  %24 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %23, i32 %8, 8
>  %25 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %24, i32 %9, 9
>  %26 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %25, i32 %10, 10
>  %27 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %26, i32 %11, 11
>  %28 = bitcast i32 %12 to float
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %27, float %28, 12
>  %30 = bitcast i32 %13 to float
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %29, float %30, 13
>  %32 = bitcast i32 %14 to float
>  %33 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %31, float %32, 14
>  %34 = bitcast i32 %15 to float
>  %35 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %33, float %34, 15
>  %36 = add i32 %12, %8
>  %37 = bitcast i32 %36 to float
>  %38 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %35, float %37, 16
>  %39 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %38, float %37, 17
>  %40 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %39, float %37, 18
>  ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float }> %40
>}
>
>attributes #0 = { "no-signed-zeros-fp-math"="true" }
>
>SHADER KEY
>  part.vs.prolog.instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  mono.u.vs_export_prim_id = 0
>  opt.hw_vs.kill_outputs = 0x0
>  opt.hw_vs.clip_disable = 0
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>	v_add_i32_e32 v4, vcc, s8, v0 ; 32080008
>	v_mov_b32_e32 v5, v4          ; 7E0A0304
>	v_mov_b32_e32 v6, v4          ; 7E0C0304
>Shader main disassembly:
>	s_load_dwordx4 s[8:11], s[6:7], 0x0                    ; C00A0203 00000000
>	s_load_dwordx4 s[12:15], s[6:7], 0x10                  ; C00A0303 00000010
>	s_load_dwordx4 s[4:7], s[6:7], 0x20                    ; C00A0103 00000020
>	s_load_dwordx4 s[0:3], s[2:3], 0x100                   ; C00A0001 00000100
>	s_waitcnt lgkmcnt(0)                                   ; BF8C007F
>	buffer_load_format_xyzw v[0:3], v4, s[8:11], 0 idxen   ; E00C2000 80020004
>	buffer_load_format_xyzw v[7:10], v5, s[12:15], 0 idxen ; E00C2000 80030705
>	s_waitcnt vmcnt(1)                                     ; BF8C0F71
>	buffer_load_format_xyzw v[3:6], v6, s[4:7], 0 idxen    ; E00C2000 80010306
>	s_buffer_load_dword s4, s[0:3], 0x100                  ; C0220100 00000100
>	s_buffer_load_dword s5, s[0:3], 0x104                  ; C0220140 00000104
>	s_buffer_load_dword s6, s[0:3], 0x108                  ; C0220180 00000108
>	s_buffer_load_dword s7, s[0:3], 0x10c                  ; C02201C0 0000010C
>	s_buffer_load_dword s8, s[0:3], 0x110                  ; C0220200 00000110
>	s_buffer_load_dword s9, s[0:3], 0x114                  ; C0220240 00000114
>	s_buffer_load_dword s10, s[0:3], 0x118                 ; C0220280 00000118
>	s_buffer_load_dword s11, s[0:3], 0x11c                 ; C02202C0 0000011C
>	s_buffer_load_dword s12, s[0:3], 0x120                 ; C0220300 00000120
>	s_buffer_load_dword s13, s[0:3], 0x124                 ; C0220340 00000124
>	s_buffer_load_dword s14, s[0:3], 0x128                 ; C0220380 00000128
>	s_buffer_load_dword s15, s[0:3], 0x12c                 ; C02203C0 0000012C
>	s_buffer_load_dword s16, s[0:3], 0x130                 ; C0220400 00000130
>	s_buffer_load_dword s17, s[0:3], 0x134                 ; C0220440 00000134
>	s_buffer_load_dword s18, s[0:3], 0x138                 ; C0220480 00000138
>	s_buffer_load_dword s0, s[0:3], 0x13c                  ; C0220000 0000013C
>	s_waitcnt vmcnt(0)                                     ; BF8C0F70
>	exp param0 v3, v4, v5, v6                              ; C400020F 06050403
>	s_waitcnt expcnt(0) lgkmcnt(0)                         ; BF8C000F
>	v_mul_f32_e32 v3, s4, v0                               ; 0A060004
>	v_mul_f32_e32 v4, s5, v0                               ; 0A080005
>	v_mul_f32_e32 v5, s6, v0                               ; 0A0A0006
>	v_mul_f32_e32 v0, s7, v0                               ; 0A000007
>	v_mac_f32_e32 v3, s8, v1                               ; 2C060208
>	v_mac_f32_e32 v4, s9, v1                               ; 2C080209
>	v_mac_f32_e32 v5, s10, v1                              ; 2C0A020A
>	exp param1 v7, v8, v0, v0                              ; C400021F 00000807
>	s_waitcnt expcnt(0)                                    ; BF8C0F0F
>	v_mac_f32_e32 v0, s11, v1                              ; 2C00020B
>	v_mac_f32_e32 v0, s15, v2                              ; 2C00040F
>	v_mac_f32_e32 v3, s12, v2                              ; 2C06040C
>	v_mac_f32_e32 v4, s13, v2                              ; 2C08040D
>	v_mac_f32_e32 v5, s14, v2                              ; 2C0A040E
>	v_add_f32_e32 v1, s16, v3                              ; 02020610
>	v_add_f32_e32 v2, s17, v4                              ; 02040811
>	v_add_f32_e32 v3, s18, v5                              ; 02060A12
>	v_add_f32_e32 v0, s0, v0                               ; 02000000
>	exp pos0 v1, v2, v3, v0                                ; C40000CF 00030201
>	s_waitcnt expcnt(0)                                    ; BF8C0F0F
>	v_mov_b32_e32 v0, 1.0                                  ; 7E0002F2
>	exp pos1 v0, off, off, off done                        ; C40008D1 00000000
>	s_endpgm                                               ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 24
>VGPRS: 12
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 324 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>	s_mov_b64 s[16:17], exec                               ; BE90017E
>	s_wqm_b64 exec, exec                                   ; BEFE077E
>	s_load_dwordx8 s[8:15], s[4:5], 0x200                  ; C00E0202 00000200
>	s_load_dwordx4 s[0:3], s[4:5], 0x230                   ; C00A0002 00000230
>	s_mov_b32 m0, s7                                       ; BEFC0007
>	v_interp_p1_f32 v0, v2, attr1.x                        ; D4000402
>	v_interp_p1_f32 v1, v2, attr1.y                        ; D4040502
>	v_interp_p2_f32 v0, v3, attr1.x                        ; D4010403
>	v_interp_p2_f32 v1, v3, attr1.y                        ; D4050503
>	s_and_b64 exec, exec, s[16:17]                         ; 86FE107E
>	s_waitcnt lgkmcnt(0)                                   ; BF8C007F
>	image_sample v[4:7], v[0:1], s[8:15], s[0:3] dmask:0xf ; F0800F00 00020400
>	v_interp_p1_f32 v0, v2, attr0.x                        ; D4000002
>	v_interp_p2_f32 v0, v3, attr0.x                        ; D4010003
>	s_waitcnt vmcnt(0)                                     ; BF8C0F70
>	v_mul_f32_e32 v0, v4, v0                               ; 0A000104
>	v_interp_p1_f32 v4, v2, attr0.z                        ; D4100202
>	v_interp_p1_f32 v1, v2, attr0.y                        ; D4040102
>	v_interp_p2_f32 v4, v3, attr0.z                        ; D4110203
>	v_interp_p1_f32 v2, v2, attr0.w                        ; D4080302
>	v_interp_p2_f32 v1, v3, attr0.y                        ; D4050103
>	v_interp_p2_f32 v2, v3, attr0.w                        ; D4090303
>	v_mul_f32_e32 v4, v6, v4                               ; 0A080906
>	v_mul_f32_e32 v3, v7, v2                               ; 0A060507
>	v_mul_f32_e32 v1, v5, v1                               ; 0A020305
>	v_mov_b32_e32 v2, v4                                   ; 7E040304
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32 v0, v0, v1        ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32 v1, v2, v3        ; D2960001 00020702
>	exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100
>	s_endpgm                              ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0002
>*** SHADER STATS ***
>SGPRS: 24
>VGPRS: 16
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 144 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>FRAG
>DCL IN[0], GENERIC[0], CONSTANT
>DCL OUT[0], COLOR
>  0: MOV OUT[0], IN[0]
>  1: END
>radeonsi: Compiling shader 33
>TGSI shader LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 {
>main_body:
>  %21 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %4) #2
>  %22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 1, i32 0, i32 %4) #2
>  %23 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 2, i32 0, i32 %4) #2
>  %24 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 3, i32 0, i32 %4) #2
>  %25 = bitcast float %3 to i32
>  %26 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %25, 6
>  %27 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %26, float %21, 7
>  %28 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %27, float %22, 8
>  %29 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %28, float %23, 9
>  %30 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %29, float %24, 10
>  %31 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %30, float %19, 20
>  ret <{ i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %31
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
>
>attributes #0 = { "InitialPSInputAddr"="36983" "no-signed-zeros-fp-math"="true" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readnone }
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>	s_mov_b32 m0, s7                 ; BEFC0007
>	v_interp_mov_f32 v0, p0, attr0.x ; D4020002
>	v_interp_mov_f32 v1, p0, attr0.y ; D4060102
>	v_interp_mov_f32 v2, p0, attr0.z ; D40A0202
>	v_interp_mov_f32 v3, p0, attr0.w ; D40E0302
>Shader epilog disassembly:
>	v_cvt_pkrtz_f16_f32 v0, v0, v1        ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32 v1, v2, v3        ; D2960001 00020702
>	exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100
>	s_endpgm                              ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xd077
>SPI_PS_INPUT_ENA  = 0x0020
>*** SHADER STATS ***
>SGPRS: 10
>VGPRS: 16
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 48 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>System event triggered: gamepad discovered
>Texture #3 1024,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>WindowCentre: 0,0
>Texture #3 2048,2048
>Texture #1 16,16
>Texture #2 16,16
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #1 1,1
>Texture #2 1,1
>Texture #3 1024,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Season event: 0
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>Texture #3 2048,2048
>

Actions: View

Attachments on bug 101384: 131895 | 131897 | 131899 | 131900 | 131901 | 131902 | 132057

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.