Attachment 132319 Details for Bug 101634 – kern.log

kern.log

kern.log (text/plain), 655.85 KB, created by Humberto Israel Perez Rodriguez on 2017-06-28 20:48:04 UTC

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Creator: Humberto Israel Perez Rodriguez

Created: 2017-06-28 20:48:04 UTC

Size: 655.85 KB

patch

obsolete

>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Linux version 4.12.0-rc7-drm-tip-ww26-commit-85a692e+ (gfx@bifrost) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4) ) #1 SMP PREEMPT Wed Jun 28 09:33:37 CDT 2017
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc7-drm-tip-ww26-commit-85a692e+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0x1e i915.alpha_support=1 resume=/dev/sda3 fastboot i915.enable_guc_loading=2 i915.enable_guc_submission=2 log_buf_len=1M
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/fpu: xstate_offset[3]:  576, xstate_sizes[3]:   64
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/fpu: xstate_offset[4]:  640, xstate_sizes[4]:   64
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/fpu: Enabled xstate features 0x1b, context size is 704 bytes, using 'compacted' format.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] e820: BIOS-provided physical RAM map:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000000058000-0x0000000000059fff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x000000000005a000-0x000000000009dfff] usable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000000fffffff] usable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000010000000-0x0000000012151fff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000012152000-0x0000000076cbcfff] usable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000076cbd000-0x0000000076efcfff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000076efd000-0x0000000076fecfff] type 20
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000076fed000-0x00000000799ecfff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x00000000799ed000-0x0000000079a4cfff] ACPI NVS
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000079a4d000-0x0000000079a8cfff] ACPI data
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000079a8d000-0x000000007abfffff] usable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x000000007ac00000-0x000000007fffffff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x00000000a121a000-0x00000000a121afff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000e3ffffff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x00000000fed01000-0x00000000fed01fff] reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000017fffffff] usable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] NX (Execute Disable) protection: active
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] efi: EFI v2.60 by EDK II
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] efi:  SMBIOS=0x76ef9000  SMBIOS 3.0=0x76ef7000  ACPI=0x79a8c000  ACPI 2.0=0x79a8c014  ESRT=0x799ac000 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] SMBIOS 3.1.1 present.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] DMI: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0050.B51.1706021357 06/02/2017
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] tsc: Using PIT calibration value
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] e820: last_pfn = 0x180000 max_arch_pfn = 0x400000000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] MTRR default type: uncachable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] MTRR fixed ranges enabled:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   00000-9FFFF write-back
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   A0000-BFFFF uncachable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   C0000-FFFFF write-protect
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] MTRR variable ranges enabled:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   0 base 00FF800000 mask 7FFF800000 write-combining
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   1 base 0000000000 mask 7F80000000 write-back
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   2 base 007B000000 mask 7FFF000000 uncachable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   3 base 007C000000 mask 7FFC000000 uncachable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   4 base 0100000000 mask 7F80000000 write-back
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   5 disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   6 disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   7 disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   8 disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   9 disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WC  UC- WT  
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] e820: last_pfn = 0x7ac00 max_arch_pfn = 0x400000000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] esrt: ESRT header is not in the memory map.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Using GB pages for direct mapping
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BRK [0x056c2000, 0x056c2fff] PGTABLE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BRK [0x056c3000, 0x056c3fff] PGTABLE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BRK [0x056c4000, 0x056c4fff] PGTABLE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BRK [0x056c5000, 0x056c5fff] PGTABLE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BRK [0x056c6000, 0x056c6fff] PGTABLE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] BRK [0x056c7000, 0x056c7fff] PGTABLE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] log_buf_len: 1048576 bytes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] early log buf free: 257608(98%)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Secure boot could not be determined
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] RAMDISK: [mem 0x36960000-0x374a7fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: Early table checksum verification disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: RSDP 0x0000000079A8C014 000024 (v02 INTEL )
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: XSDT 0x0000000079A5A188 0000FC (v01 INTEL  EDK2     00000003 BRXT 01000013)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: FACP 0x0000000079A84000 00010C (v05 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: DSDT 0x0000000079A6B000 011491 (v02 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: FACS 0x0000000079A3A000 000040
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: UEFI 0x0000000079A43000 000042 (v01 INTEL  EDK2     00000002 BRXT 01000013)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A8A000 0003E9 (v02 INTEL  Tpm2Tabl 00001000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: TPM2 0x0000000079A89000 000034 (v04                 00000000      00000000)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: BDAT 0x0000000079A88000 000030 (v02                 00000000      00000000)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: HPET 0x0000000079A83000 000038 (v01 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: LPIT 0x0000000079A82000 00005C (v01 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: APIC 0x0000000079A81000 000084 (v03 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: MCFG 0x0000000079A80000 00003C (v01 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: NPKT 0x0000000079A7F000 000065 (v01 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: PRAM 0x0000000079A7E000 000030 (v01 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: WSMT 0x0000000079A7D000 000028 (v01 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A67000 003EA7 (v02 INTEL  DptfTab  00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A61000 0059F0 (v02 INTEL  RVPRtd3  00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A5F000 0010B3 (v02 INTEL  UsbCTabl 00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A5D000 001524 (v01 Intel_ Platform 00001000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A5C000 0000B1 (v01 Intel_ ADebTabl 00001000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A5B000 0003F7 (v02 PmRef  Cpu0Ist  00003000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A8B000 000775 (v02 CpuRef CpuSsdt  00003000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A59000 000388 (v02 PmRef  Cpu0Tst  00003000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A58000 0001E6 (v02 PmRef  ApTst    00003000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: SSDT 0x0000000079A55000 002939 (v02 SaSsdt SaSsdt   00003000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: FPDT 0x0000000079A54000 000044 (v01 INTEL  EDK2     00000002 BRXT 01000013)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: DBGP 0x0000000079A86000 000034 (v01 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: DBG2 0x0000000079A87000 000072 (v00 INTEL  EDK2     00000003 BRXT 0100000D)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: WDAT 0x0000000079A85000 000104 (v01                 00000000      00000000)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: NHLT 0x0000000079A52000 001A50 (v00 INTEL  EDK2     00000002 BRXT 01000013)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: Local APIC address 0xfee00000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Zone ranges:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   Normal   [mem 0x0000000100000000-0x000000017fffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Movable zone start for each node
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Early memory node ranges
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   node   0: [mem 0x0000000000001000-0x0000000000057fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   node   0: [mem 0x000000000005a000-0x000000000009dfff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   node   0: [mem 0x0000000000100000-0x000000000fffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   node   0: [mem 0x0000000012152000-0x0000000076cbcfff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   node   0: [mem 0x0000000079a8d000-0x000000007abfffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   node   0: [mem 0x0000000100000000-0x000000017fffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000017fffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] On node 0 totalpages: 1006713
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   DMA zone: 64 pages used for memmap
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   DMA zone: 23 pages reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   DMA zone: 3995 pages, LIFO batch:0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   DMA32 zone: 7476 pages used for memmap
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   DMA32 zone: 478430 pages, LIFO batch:31
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   Normal zone: 8192 pages used for memmap
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]   Normal zone: 524288 pages, LIFO batch:31
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Reserving Intel graphics memory at 0x000000007c000000-0x000000007fffffff
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: PM-Timer IO Port: 0x408
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: Local APIC address 0xfee00000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high level lint[0x1])
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high level lint[0x1])
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high level lint[0x1])
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high level lint[0x1])
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-119
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: IRQ0 used by override.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: IRQ9 used by override.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Using ACPI (MADT) for SMP configuration information
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] smpboot: Allowing 4 CPUs, 0 hotplug CPUs
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x00058000-0x00059fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x000fffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x10000000-0x12151fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x76cbd000-0x76efcfff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x76efd000-0x76fecfff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x76fed000-0x799ecfff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x799ed000-0x79a4cfff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x79a4d000-0x79a8cfff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x7ac00000-0x7fffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0x80000000-0xa1219fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0xa121a000-0xa121afff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0xa121b000-0xdfffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0xe0000000-0xe3ffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0xe4000000-0xfed00fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0xfed01000-0xfed01fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PM: Registered nosave memory: [mem 0xfed02000-0xffffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] e820: [mem 0xa121b000-0xdfffffff] available for PCI devices
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] setup_percpu: NR_CPUS:16 nr_cpumask_bits:16 nr_cpu_ids:4 nr_node_ids:1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] percpu: Embedded 37 pages/cpu @ffff88017fc00000 s114376 r8192 d28984 u524288
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] pcpu-alloc: s114376 r8192 d28984 u524288 alloc=1*2097152
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] pcpu-alloc: [0] 0 1 2 3 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 990958
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.12.0-rc7-drm-tip-ww26-commit-85a692e+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0x1e i915.alpha_support=1 resume=/dev/sda3 fastboot i915.enable_guc_loading=2 i915.enable_guc_submission=2 log_buf_len=1M
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Memory: 3793728K/4026852K available (8673K kernel code, 1378K rwdata, 3444K rodata, 1200K init, 22640K bss, 233124K reserved, 0K cma-reserved)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Running RCU self tests
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Preemptible hierarchical RCU implementation.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] 	RCU lockdep checking is enabled.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] 	RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=4.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] kmemleak: Kernel memory leak detector disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] NR_IRQS:4352 nr_irqs:1024 16
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Console: colour dummy device 80x25
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] console [tty0] enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ... MAX_LOCKDEP_SUBCLASSES:  8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ... MAX_LOCK_DEPTH:          48
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ... MAX_LOCKDEP_KEYS:        8191
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ... CLASSHASH_SIZE:          4096
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ... MAX_LOCKDEP_ENTRIES:     32768
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ... MAX_LOCKDEP_CHAINS:      65536
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] ... CHAINHASH_SIZE:          32768
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]  memory used by lock dependency info: 8159 kB
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000]  per task-struct memory footprint: 1920 bytes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] kmemleak: Early log buffer exceeded (2878), please increase DEBUG_KMEMLEAK_EARLY_LOG_SIZE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.000000] hpet clockevent registered
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.002000] tsc: PIT calibration matches HPET. 1 loops
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.002000] tsc: Detected 1094.589 MHz processor
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.002000] Calibrating delay loop (skipped), value calculated using timer frequency.. 2188.80 BogoMIPS (lpj=1094400)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.002000] pid_max: default: 32768 minimum: 301
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.002000] ACPI: Core revision 20170303
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.256037] random: fast init done
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.416585] ACPI Error: Invalid type (RegionField) for target of Scope operator [SSP2] (Cannot override) (20170303/dswload-273)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.416671] ACPI Exception: AE_AML_OPERAND_TYPE, During name lookup/catalog (20170303/psobject-241)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.418187] ACPI Exception: AE_AML_OPERAND_TYPE, (SSDT: RVPRtd3) while loading table (20170303/tbxfload-228)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.493332] ACPI Error: 1 table load failures, 11 successful (20170303/tbxfload-246)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.494353] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.494361] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.496650] CPU: Physical Processor ID: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.496655] CPU: Processor Core ID: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.496678] mce: CPU supports 7 MCE banks
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.496788] CPU0: Thermal monitoring enabled (TM1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.496862] process: using mwait in idle threads
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.496869] Last level iTLB entries: 4KB 0, 2MB 0, 4MB 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.496873] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.497547] Freeing SMP alternatives memory: 32K
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.511742] smpboot: Max logical packages: 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.513279] x2apic: IRQ remapping doesn't support X2APIC mode
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.519000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.528111] TSC deadline timer enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.528132] smpboot: CPU0: Genuine Intel(R) CPU @ 1.10GHz (family: 0x6, model: 0x7a, stepping: 0x0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.530255] mce: [Hardware Error]: Machine check events logged
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.530270] mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: a600000000020408
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.530322] mce: [Hardware Error]: TSC 0 ADDR fef4c9a0 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.530366] mce: [Hardware Error]: PROCESSOR 0:706a0 TIME 1498682475 SOCKET 0 APIC 0 microcode 1c
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532099] Performance Events: PEBS fmt3+, generic architected perfmon, full-width counters, Intel PMU driver.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532136] ... version:                4
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532140] ... bit width:              48
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532144] ... generic registers:      4
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532148] ... value mask:             0000ffffffffffff
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532153] ... max period:             00007fffffffffff
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532157] ... fixed-purpose events:   3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.532161] ... event mask:             000000070000000f
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.540811] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.542025] smp: Bringing up secondary CPUs ...
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.550224] x86: Booting SMP configuration:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.550238] .... node  #0, CPUs:      #1 #2 #3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.749282] smp: Brought up 1 node, 4 CPUs
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.749282] smpboot: Total of 4 processors activated (8848.12 BogoMIPS)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.750806] sched_clock: Marking stable (750000000, 0)->(760952667, -10952667)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.752525] devtmpfs: initialized
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.755443] PM: Registering ACPI NVS region [mem 0x799ed000-0x79a4cfff] (393216 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.757189] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.757205] futex hash table entries: 1024 (order: 5, 131072 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.757721] xor: measuring software checksum speed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.767180]    prefetch64-sse:  5676.000 MB/sec
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.777300]    generic_sse:  4856.000 MB/sec
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.777306] xor: using function: prefetch64-sse (5676.000 MB/sec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.777336] pinctrl core: initialized pinctrl subsystem
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.783807] NET: Registered protocol family 16
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.787147] cpuidle: using governor menu
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.787162] PCCT header not found.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.787645] ACPI: bus type PCI registered
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.788372] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.788494] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.788537] PCI: Using configuration type 1 for base access
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.818923] HugeTLB registered 2 MB page size, pre-allocated 0 pages
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.838261] raid6: sse2x1   gen()  2531 MB/s
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.855423] raid6: sse2x1   xor()  1697 MB/s
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.872615] raid6: sse2x2   gen()  3003 MB/s
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.889816] raid6: sse2x2   xor()  1998 MB/s
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.906989] raid6: sse2x4   gen()  3476 MB/s
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924174] raid6: sse2x4   xor()  1833 MB/s
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924180] raid6: using algorithm sse2x4 gen() 3476 MB/s
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924184] raid6: .... xor() 1833 MB/s, rmw enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924190] raid6: using ssse3x2 recovery algorithm
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924639] ACPI: Added _OSI(Module Device)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924646] ACPI: Added _OSI(Processor Device)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924651] ACPI: Added _OSI(3.0 _SCP Extensions)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.924657] ACPI: Added _OSI(Processor Aggregator Device)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    0.935091] ACPI: Executed 15 blocks of module-level executable AML code
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.213144] ACPI: Dynamic OEM Table Load:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.213217] ACPI: SSDT 0xFFFF88017A530358 0001A5 (v02 PmRef  Cpu0Cst  00003001 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.215100] ACPI: Executed 1 blocks of module-level executable AML code
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.224202] ACPI: Dynamic OEM Table Load:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.224268] ACPI: SSDT 0xFFFF88017A533858 0001E6 (v02 PmRef  ApIst    00003000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.227704] ACPI: Executed 1 blocks of module-level executable AML code
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.229690] ACPI: Dynamic OEM Table Load:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.229753] ACPI: SSDT 0xFFFF88017A43C6F8 0000C9 (v02 PmRef  ApCst    00003000 INTL 20160527)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.231277] ACPI: Executed 1 blocks of module-level executable AML code
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.280130] ACPI : EC: EC started
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.280142] ACPI : EC: interrupt blocked
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.459299] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as first EC
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.459320] ACPI: \_SB_.PCI0.LPCB.H_EC: GPE=0x25, EC_CMD/EC_SC=0x66, EC_DATA=0x62
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.459343] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as boot DSDT EC to handle transactions
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.459352] ACPI: Interpreter enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.459661] ACPI: (supports S0 S3 S4 S5)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.459667] ACPI: Using IOAPIC for interrupt routing
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.460201] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    1.559382] ACPI: Power Resource [PXP] (on)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.314752] ACPI: Power Resource [FN00] (on)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.360849] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.360892] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.383455] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.383508] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385882] PCI host bridge to bus 0000:00
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385898] pci_bus 0000:00: root bus resource [io  0x0070-0x0077]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385911] pci_bus 0000:00: root bus resource [io  0x0000-0x006f window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385923] pci_bus 0000:00: root bus resource [io  0x0078-0x0cf7 window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385935] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385946] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385958] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385969] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000fffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385980] pci_bus 0000:00: root bus resource [mem 0x7c000001-0x7fffffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.385991] pci_bus 0000:00: root bus resource [mem 0x80000000-0xbfffffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386002] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xefffffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386013] pci_bus 0000:00: root bus resource [mem 0xfea00000-0xfeafffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386024] pci_bus 0000:00: root bus resource [mem 0xfed00000-0xfed003ff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386035] pci_bus 0000:00: root bus resource [mem 0xfed01000-0xfed01fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386046] pci_bus 0000:00: root bus resource [mem 0xfed03000-0xfed03fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386056] pci_bus 0000:00: root bus resource [mem 0xfed06000-0xfed06fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386079] pci_bus 0000:00: root bus resource [mem 0xfed08000-0xfed09fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386092] pci_bus 0000:00: root bus resource [mem 0xfed80000-0xfedbffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386104] pci_bus 0000:00: root bus resource [mem 0xfed1c000-0xfed1cfff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386115] pci_bus 0000:00: root bus resource [mem 0xfee00000-0xfeefffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386129] pci_bus 0000:00: root bus resource [bus 00-ff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.386238] pci 0000:00:00.0: [8086:31f0] type 00 class 0x060000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.391940] pci 0000:00:00.1: [8086:318c] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.392002] pci 0000:00:00.1: reg 0x10: [mem 0x80000000-0x80007fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.397460] pci 0000:00:00.3: [8086:3190] type 00 class 0x088000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.397516] pci 0000:00:00.3: reg 0x10: [mem 0xa1218000-0xa1218fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.402812] pci 0000:00:02.0: [8086:3184] type 00 class 0x030000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.402855] pci 0000:00:02.0: reg 0x10: [mem 0xa0000000-0xa0ffffff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.402917] pci 0000:00:02.0: reg 0x18: [mem 0x90000000-0x9fffffff 64bit pref]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.402936] pci 0000:00:02.0: reg 0x20: [io  0x2000-0x203f]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.409037] pci 0000:00:0e.0: [8086:3198] type 00 class 0x040100
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.409117] pci 0000:00:0e.0: reg 0x10: [mem 0xa1210000-0xa1213fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.409204] pci 0000:00:0e.0: reg 0x20: [mem 0xa1000000-0xa10fffff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.409456] pci 0000:00:0e.0: PME# supported from D0 D3hot D3cold
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.419299] pci 0000:00:0e.0: System wakeup disabled by ACPI
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.419817] pci 0000:00:0f.0: [8086:319a] type 00 class 0x078000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.419894] pci 0000:00:0f.0: reg 0x10: [mem 0xa1219000-0xa1219fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.420269] pci 0000:00:0f.0: PME# supported from D3hot
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.425392] pci 0000:00:11.0: [8086:31a2] type 00 class 0x005007
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.425471] pci 0000:00:11.0: reg 0x10: [mem 0xa1214000-0xa1215fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.425523] pci 0000:00:11.0: reg 0x18: [mem 0xa121c000-0xa121cfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431472] pci 0000:00:12.0: [8086:31e3] type 00 class 0x010601
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431523] pci 0000:00:12.0: reg 0x10: [mem 0xa1216000-0xa1217fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431565] pci 0000:00:12.0: reg 0x14: [mem 0xa1241000-0xa12410ff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431592] pci 0000:00:12.0: reg 0x18: [io  0x2080-0x2087]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431618] pci 0000:00:12.0: reg 0x1c: [io  0x2088-0x208b]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431645] pci 0000:00:12.0: reg 0x20: [io  0x2060-0x207f]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431673] pci 0000:00:12.0: reg 0x24: [mem 0xa123f000-0xa123f7ff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.431882] pci 0000:00:12.0: PME# supported from D3hot
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.437132] pci 0000:00:13.0: [8086:31da] type 01 class 0x060400
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.437455] pci 0000:00:13.0: PME# supported from D0 D3hot D3cold
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.442367] pci 0000:00:13.0: System wakeup disabled by ACPI
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.442980] pci 0000:00:15.0: [8086:31a8] type 00 class 0x0c0330
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.443046] pci 0000:00:15.0: reg 0x10: [mem 0xa1200000-0xa120ffff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.443347] pci 0000:00:15.0: PME# supported from D3hot D3cold
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.448413] pci 0000:00:15.0: System wakeup disabled by ACPI
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.448992] pci 0000:00:16.0: [8086:31ac] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.449060] pci 0000:00:16.0: reg 0x10: [mem 0xa121d000-0xa121dfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.449103] pci 0000:00:16.0: reg 0x18: [mem 0xa121e000-0xa121efff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.454508] pci 0000:00:16.1: [8086:31ae] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.454575] pci 0000:00:16.1: reg 0x10: [mem 0xa121f000-0xa121ffff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.454618] pci 0000:00:16.1: reg 0x18: [mem 0xa1220000-0xa1220fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.460061] pci 0000:00:16.2: [8086:31b0] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.460128] pci 0000:00:16.2: reg 0x10: [mem 0xa1221000-0xa1221fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.460171] pci 0000:00:16.2: reg 0x18: [mem 0xa1222000-0xa1222fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.465668] pci 0000:00:16.3: [8086:31b2] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.465735] pci 0000:00:16.3: reg 0x10: [mem 0xa1223000-0xa1223fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.465778] pci 0000:00:16.3: reg 0x18: [mem 0xa1224000-0xa1224fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.471302] pci 0000:00:17.0: [8086:31b4] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.471370] pci 0000:00:17.0: reg 0x10: [mem 0xa1225000-0xa1225fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.471413] pci 0000:00:17.0: reg 0x18: [mem 0xa1226000-0xa1226fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.476895] pci 0000:00:17.1: [8086:31b6] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.476961] pci 0000:00:17.1: reg 0x10: [mem 0xa1227000-0xa1227fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.477004] pci 0000:00:17.1: reg 0x18: [mem 0xa1228000-0xa1228fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.482482] pci 0000:00:17.2: [8086:31b8] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.482549] pci 0000:00:17.2: reg 0x10: [mem 0xa1229000-0xa1229fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.482608] pci 0000:00:17.2: reg 0x18: [mem 0xa122a000-0xa122afff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.488071] pci 0000:00:17.3: [8086:31ba] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.488138] pci 0000:00:17.3: reg 0x10: [mem 0xa122b000-0xa122bfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.488181] pci 0000:00:17.3: reg 0x18: [mem 0xa122c000-0xa122cfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.493691] pci 0000:00:18.0: [8086:31bc] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.493758] pci 0000:00:18.0: reg 0x10: [mem 0xa122d000-0xa122dfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.493801] pci 0000:00:18.0: reg 0x18: [mem 0xa122e000-0xa122efff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.499204] pci 0000:00:18.1: [8086:31be] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.499285] pci 0000:00:18.1: reg 0x10: [mem 0xa122f000-0xa122ffff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.499328] pci 0000:00:18.1: reg 0x18: [mem 0xa1230000-0xa1230fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.504746] pci 0000:00:18.3: [8086:31ee] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.504834] pci 0000:00:18.3: reg 0x10: [mem 0xa1231000-0xa1231fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.504877] pci 0000:00:18.3: reg 0x18: [mem 0xa1232000-0xa1232fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.510351] pci 0000:00:19.0: [8086:31c2] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.510418] pci 0000:00:19.0: reg 0x10: [mem 0xa1233000-0xa1233fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.510461] pci 0000:00:19.0: reg 0x18: [mem 0xa1234000-0xa1234fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.515878] pci 0000:00:19.1: [8086:31c4] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.515957] pci 0000:00:19.1: reg 0x10: [mem 0xa1235000-0xa1235fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.516021] pci 0000:00:19.1: reg 0x18: [mem 0xa1236000-0xa1236fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.521439] pci 0000:00:19.2: [8086:31c6] type 00 class 0x118000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.521506] pci 0000:00:19.2: reg 0x10: [mem 0xa1237000-0xa1237fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.521549] pci 0000:00:19.2: reg 0x18: [mem 0xa1238000-0xa1238fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.527054] pci 0000:00:1b.0: [8086:31ca] type 00 class 0x080501
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.527121] pci 0000:00:1b.0: reg 0x10: [mem 0xa1239000-0xa1239fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.527164] pci 0000:00:1b.0: reg 0x18: [mem 0xa123a000-0xa123afff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.533353] pci 0000:00:1c.0: [8086:31cc] type 00 class 0x080501
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.533420] pci 0000:00:1c.0: reg 0x10: [mem 0xa123b000-0xa123bfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.533464] pci 0000:00:1c.0: reg 0x18: [mem 0xa123c000-0xa123cfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.539572] pci 0000:00:1e.0: [8086:31d0] type 00 class 0x080501
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.539639] pci 0000:00:1e.0: reg 0x10: [mem 0xa123d000-0xa123dfff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.539683] pci 0000:00:1e.0: reg 0x18: [mem 0xa123e000-0xa123efff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.545173] pci 0000:00:1f.0: [8086:3197] type 00 class 0x060100
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.550805] pci 0000:00:1f.1: [8086:31d4] type 00 class 0x0c0500
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.550893] pci 0000:00:1f.1: reg 0x10: [mem 0xa1240000-0xa12400ff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.551016] pci 0000:00:1f.1: reg 0x20: [io  0x2040-0x205f]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.556638] pci 0000:01:00.0: [10ec:8168] type 00 class 0x020000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.556697] pci 0000:01:00.0: reg 0x10: [io  0x1000-0x10ff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.556781] pci 0000:01:00.0: reg 0x18: [mem 0xa1104000-0xa1104fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.556821] pci 0000:01:00.0: reg 0x20: [mem 0xa1100000-0xa1103fff 64bit]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.556862] pci 0000:01:00.0: can't set Max Payload Size to 256; if necessary, use "pci=pcie_bus_safe" and report a bug
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.557174] pci 0000:01:00.0: supports D1 D2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.557180] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.557671] pci 0000:01:00.0: System wakeup disabled by ACPI
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.560924] pci 0000:00:13.0: PCI bridge to [bus 01]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.560937] pci 0000:00:13.0:   bridge window [io  0x1000-0x1fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.560947] pci 0000:00:13.0:   bridge window [mem 0xa1100000-0xa11fffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.560981] pci_bus 0000:00: on NUMA node 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.684304] ACPI: PCI Interrupt Link [LNKA] (IRQs *3 4 5 6 10 11 12 14 15)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.686377] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 *4 5 6 10 11 12 14 15)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.688431] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 *5 6 10 11 12 14 15)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.690480] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 *6 10 11 12 14 15)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.692529] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 15) *7
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.694603] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 15) *9
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.696644] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 *10 11 12 14 15)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.698701] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 *11 12 14 15)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.719622] ACPI: Enabled 3 GPEs in block 00 to 7F
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.721279] ACPI : EC: interrupt unblocked
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.721309] ACPI : EC: event unblocked
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.721351] ACPI: \_SB_.PCI0.LPCB.H_EC: GPE=0x25, EC_CMD/EC_SC=0x66, EC_DATA=0x62
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.721374] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as boot DSDT EC to handle transactions and events
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.723341] pci 0000:00:02.0: vgaarb: setting as boot VGA device
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.723354] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.723395] pci 0000:00:02.0: vgaarb: bridge control possible
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.723401] vgaarb: loaded
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.725157] SCSI subsystem initialized
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.725711] libata version 3.00 loaded.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.726118] ACPI: bus type USB registered
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.726453] usbcore: registered new interface driver usbfs
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.726601] usbcore: registered new interface driver hub
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.726822] usbcore: registered new device driver usb
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.727903] Registered efivars operations
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.740110] Advanced Linux Sound Architecture Driver Initialized.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.740244] PCI: Using ACPI for IRQ routing
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.749788] PCI: pci_cache_line_size set to 64 bytes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.750122] e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.750151] e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.750168] e820: reserve RAM buffer [mem 0x76cbd000-0x77ffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.750183] e820: reserve RAM buffer [mem 0x7ac00000-0x7bffffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.752597] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.752638] hpet0: 8 comparators, 64-bit 19.200000 MHz counter
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.754971] clocksource: Switched to clocksource hpet
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.982273] pnp: PnP ACPI init
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.984790] system 00:00: [io  0x06a4] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.984812] system 00:00: [io  0x06a0] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.984853] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.990713] pnp 00:01: disabling [io  0x164e-0x164f] because it overlaps 0000:00:13.0 BAR 7 [io  0x1000-0x1fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.991248] system 00:01: [io  0x0680-0x069f] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.991268] system 00:01: [io  0x0400-0x047f] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.991287] system 00:01: [io  0x0500-0x05fe] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.991305] system 00:01: [io  0x0600-0x061f] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.991324] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    2.992700] pnp 00:02: Plug and Play ACPI device, IDs PNP0303 (active)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084361] system 00:03: [mem 0xe0000000-0xefffffff] could not be reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084382] system 00:03: [mem 0xfea00000-0xfeafffff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084401] system 00:03: [mem 0xfed01000-0xfed01fff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084431] system 00:03: [mem 0xfed03000-0xfed03fff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084450] system 00:03: [mem 0xfed06000-0xfed06fff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084469] system 00:03: [mem 0xfed08000-0xfed09fff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084487] system 00:03: [mem 0xfed80000-0xfedbffff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084506] system 00:03: [mem 0xfed1c000-0xfed1cfff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084524] system 00:03: [mem 0xfee00000-0xfeefffff] has been reserved
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.084542] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.091788] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.101908] pnp: PnP ACPI: found 5 devices
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140652] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140702] pci 0000:00:13.0: PCI bridge to [bus 01]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140713] pci 0000:00:13.0:   bridge window [io  0x1000-0x1fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140727] pci 0000:00:13.0:   bridge window [mem 0xa1100000-0xa11fffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140753] pci_bus 0000:00: resource 4 [io  0x0070-0x0077]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140759] pci_bus 0000:00: resource 5 [io  0x0000-0x006f window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140766] pci_bus 0000:00: resource 6 [io  0x0078-0x0cf7 window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140771] pci_bus 0000:00: resource 7 [io  0x0d00-0xffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140777] pci_bus 0000:00: resource 8 [mem 0x000a0000-0x000bffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140783] pci_bus 0000:00: resource 9 [mem 0x000c0000-0x000dffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140789] pci_bus 0000:00: resource 10 [mem 0x000e0000-0x000fffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140794] pci_bus 0000:00: resource 11 [mem 0x7c000001-0x7fffffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140800] pci_bus 0000:00: resource 12 [mem 0x80000000-0xbfffffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140806] pci_bus 0000:00: resource 13 [mem 0xe0000000-0xefffffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140812] pci_bus 0000:00: resource 14 [mem 0xfea00000-0xfeafffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140818] pci_bus 0000:00: resource 15 [mem 0xfed00000-0xfed003ff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140824] pci_bus 0000:00: resource 16 [mem 0xfed01000-0xfed01fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140829] pci_bus 0000:00: resource 17 [mem 0xfed03000-0xfed03fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140835] pci_bus 0000:00: resource 18 [mem 0xfed06000-0xfed06fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140841] pci_bus 0000:00: resource 19 [mem 0xfed08000-0xfed09fff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140846] pci_bus 0000:00: resource 20 [mem 0xfed80000-0xfedbffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140852] pci_bus 0000:00: resource 21 [mem 0xfed1c000-0xfed1cfff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140858] pci_bus 0000:00: resource 22 [mem 0xfee00000-0xfeefffff window]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140865] pci_bus 0000:01: resource 0 [io  0x1000-0x1fff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.140870] pci_bus 0000:01: resource 1 [mem 0xa1100000-0xa11fffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.145414] NET: Registered protocol family 2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.147241] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.147392] TCP bind hash table entries: 32768 (order: 9, 2097152 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.152514] TCP: Hash tables configured (established 32768 bind 32768)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.152928] UDP hash table entries: 2048 (order: 6, 327680 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.153700] UDP-Lite hash table entries: 2048 (order: 6, 327680 bytes)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.155369] NET: Registered protocol family 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.155476] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.161644] PCI: CLS 64 bytes, default 64
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.162606] Unpacking initramfs...
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.771920] Freeing initrd memory: 11552K
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.771934] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.771943] software IO TLB [mem 0x6ec00000-0x72c00000] (64MB) mapped at [ffff88006ec00000-ffff880072bfffff]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.772277] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0xfc66f4fc7c, max_idle_ns: 440795224246 ns
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.786136] workingset: timestamp_bits=46 max_order=20 bucket_order=0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.835067] ntfs: driver 2.1.32 [Flags: R/O].
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.872203] NET: Registered protocol family 38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.872726] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 250)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.872751] io scheduler noop registered
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.873532] io scheduler cfq registered (default)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.873539] io scheduler mq-deadline registered
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.873544] io scheduler kyber registered
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.873549] start plist test
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.879135] end plist test
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    3.886745] pcieport 0000:00:13.0: Signaling PME with IRQ 120
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    4.802572] clocksource: Switched to clocksource tsc
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.218055] uvesafb: Getting VBE info block failed (eax=0x4f00, err=1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.218115] uvesafb: vbe_init() failed with -22
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.218214] uvesafb: probe of uvesafb.0 failed with error -22
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.218434] intel_idle: MWAIT substates: 0x11242020
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.218440] intel_idle: v0.4.1 model 0x7A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.222263] intel_idle: lapic_timer_reliable_states 0xffffffff
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.223795] ACPI: AC Adapter [ADP1] (off-line)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.232572] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:01/PNP0C09:00/PNP0C0D:00/input/input0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.241367] ACPI: Lid Switch [LID0]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.242116] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.242179] ACPI: Power Button [PWRB]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.290982] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info().
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.340874] thermal LNXTHERM:00: registered as thermal_zone0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.340884] ACPI: Thermal Zone [TZ01] (29 C)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.341833] GHES: HEST is not enabled!
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.342655] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.345368] ACPI: Battery Slot [BAT0] (battery present)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.346122] ACPI: Battery Slot [BAT1] (battery absent)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.365060] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.371256] Non-volatile memory driver v1.3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.372232] Linux agpgart interface v0.103
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.377468] loop: module loaded
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.379322] ahci 0000:00:12.0: version 3.0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.392822] ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.392836] ahci 0000:00:12.0: flags: 64bit ncq sntf pm clo only pmp pio slum part deso sadm sds apst 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.396334] scsi host0: ahci
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.397744] ata1: SATA max UDMA/133 abar m2048@0xa123f000 port 0xa123f100 irq 121
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.398334] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.398387] ehci-pci: EHCI PCI platform driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.398556] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.398585] ohci-pci: OHCI PCI platform driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.398718] uhci_hcd: USB Universal Host Controller Interface driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.402465] xhci_hcd 0000:00:15.0: xHCI Host Controller
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.402677] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.404322] xhci_hcd 0000:00:15.0: hcc params 0x200077c1 hci version 0x100 quirks 0x00009810
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.404342] xhci_hcd 0000:00:15.0: cache line size of 64 is not supported
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.405681] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.405696] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.405702] usb usb1: Product: xHCI Host Controller
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.405709] usb usb1: Manufacturer: Linux 4.12.0-rc7-drm-tip-ww26-commit-85a692e+ xhci-hcd
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.405714] usb usb1: SerialNumber: 0000:00:15.0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.408154] hub 1-0:1.0: USB hub found
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.408436] hub 1-0:1.0: 9 ports detected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.459878] xhci_hcd 0000:00:15.0: xHCI Host Controller
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.459944] xhci_hcd 0000:00:15.0: new USB bus registered, assigned bus number 2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.460838] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.460850] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.460856] usb usb2: Product: xHCI Host Controller
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.460861] usb usb2: Manufacturer: Linux 4.12.0-rc7-drm-tip-ww26-commit-85a692e+ xhci-hcd
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.460867] usb usb2: SerialNumber: 0000:00:15.0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.463011] hub 2-0:1.0: USB hub found
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.463265] hub 2-0:1.0: 7 ports detected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.503604] usbcore: registered new interface driver usb-storage
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.504213] i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.504219] i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.504869] i8042: Warning: Keylock active
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.505120] serio: i8042 KBD port at 0x60,0x64 irq 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.506591] mousedev: PS/2 mouse device common for all mice
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.509075] rtc_cmos 00:04: RTC can wake from S4
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.510307] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.510444] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.511818] softdog: initialized. soft_noboot=0 soft_margin=60 sec soft_panic=0 (nowayout=0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.513341] device-mapper: uevent: version 1.0.3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.514767] device-mapper: ioctl: 4.35.0-ioctl (2016-06-23) initialised: dm-devel@redhat.com
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.514780] intel_pstate: Intel P-state driver initializing
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.520140] EFI Variables Facility v0.08 2004-May-17
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.537810] hidraw: raw HID events driver (C) Jiri Kosina
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.538466] usbcore: registered new interface driver usbhid
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.538469] usbhid: USB HID core driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.538914] intel_rapl: Found RAPL domain package
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.538918] intel_rapl: Found RAPL domain core
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.538922] intel_rapl: Found RAPL domain uncore
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.538926] intel_rapl: Found RAPL domain dram
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.541047] Initializing XFRM netlink socket
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682489.7231] NetworkManager (version 1.2.4) is starting...
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.542450] NET: Registered protocol family 10
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.544406] Segment Routing with IPv6
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.544456] mip6: Mobile IPv6
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.544472] NET: Registered protocol family 17
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.544493] NET: Registered protocol family 15
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.546017] SSE version of gcm_enc/dec engaged.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.603634] alg: No test for pcbc(aes) (pcbc-aes-aesni)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.605032] registered taskstats version 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.609733] Btrfs loaded, crc32c=crc32c-generic
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.617560] rtc_cmos 00:04: setting system clock to 2017-06-28 20:41:24 UTC (1498682484)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.618090] PM: Checking hibernation image partition /dev/sda3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682489.7239] Read config: /etc/NetworkManager/NetworkManager.conf (etc: default-wifi-powersave-on.conf)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.730148] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.866180] ata1: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.881493] ata1.00: ATA-9: INTEL SSDSC2BW080A4, DC32, max UDMA/133
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.881502] ata1.00: 156301488 sectors, multi 16: LBA48 NCQ (depth 31/32), AA
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.907367] ata1.00: configured for UDMA/133
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.909893] scsi 0:0:0:0: Direct-Access     ATA      INTEL SSDSC2BW08 DC32 PQ: 0 ANSI: 5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.914567] sd 0:0:0:0: Attached scsi generic sg0 type 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.914861] sd 0:0:0:0: [sda] 156301488 512-byte logical blocks: (80.0 GB/74.5 GiB)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.915114] sd 0:0:0:0: [sda] Write Protect is off
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.915123] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.915532] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.921914]  sda: sda1 sda2 sda3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [    9.924635] sd 0:0:0:0: [sda] Attached SCSI disk
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.106256] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.106648] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.107994] PM: Hibernation image partition 8:3 present
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.107997] PM: Looking for hibernation image.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.110359] PM: Image not found (code -22)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.110367] PM: Hibernation image not present or could not be loaded.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.110434] ALSA device list:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.110438]   No soundcards found.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.115048] Freeing unused kernel memory: 1200K
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.115053] Write protecting the kernel read-only data: 14336k
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.117524] Freeing unused kernel memory: 1544K
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.120725] Freeing unused kernel memory: 652K
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.541900] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.547767] r8169 0000:01:00.0 eth0: RTL8168h/8111h at 0xffffc90000059000, 90:49:fa:02:ae:70, XID 14100880 IRQ 123
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.547775] r8169 0000:01:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.557912] Setting dangerous option alpha_support - tainting kernel
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.557922] Setting dangerous option enable_guc_loading - tainting kernel
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682489.7474] manager[0x556bafc4f1a0]: monitoring kernel firmware directory '/lib/firmware'.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.557926] Setting dangerous option enable_guc_submission - tainting kernel
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.560506] sdhci: Secure Digital Host Controller Interface driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.560509] sdhci: Copyright(c) Pierre Ossman
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.561568] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.578485] sdhci-pci 0000:00:1c.0: SDHCI controller found [8086:31cc] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.594522] mmc0: SDHCI controller on PCI [0000:00:1c.0] using ADMA 64-bit
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.594922] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.600333] [drm:i915_driver_load [i915]] No PCH found.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.600397] [drm:intel_power_domains_init [i915]] Allowed DC state mask 09
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602071] [drm:intel_device_info_dump [i915]] i915 device info: platform=GEMINILAKE gen=9 pciid=0x3184 rev=0x01
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602125] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682489.7476] monitoring ifupdown state file '/run/network/ifstate'.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602178] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602230] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602282] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602332] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602383] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602434] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602485] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602535] [drm:intel_device_info_dump [i915]] i915 device info: has_reset_engine: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602586] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602636] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602687] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682489.7543] dns-mgr[0x556bafc47940]: init: dns=dnsmasq, rc-manager=resolvconf, plugin=dnsmasq
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602737] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602788] [drm:intel_device_info_dump [i915]] i915 device info: has_gmbus_irq: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602838] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602888] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602938] [drm:intel_device_info_dump [i915]] i915 device info: has_guc_ct: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.602988] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603083] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603135] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603185] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603235] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603286] [drm:intel_device_info_dump [i915]] i915 device info: has_pipe_cxsr: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603336] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603386] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603436] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603486] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603536] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603586] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603637] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603687] [drm:intel_device_info_dump [i915]] i915 device info: unfenced_needs_alignment: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603737] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603787] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603837] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.603887] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606573] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606630] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606682] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606734] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606785] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606836] [drm:intel_device_info_runtime_init [i915]] EU total: 18
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606886] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 6
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606937] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.606988] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: y
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607447] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607502] [drm:i915_driver_load [i915]] ppgtt mode: 3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607554] [drm:i915_driver_load [i915]] use GPU semaphores? no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607610] [drm] Memory usable by graphics device = 4078M
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607668] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607724] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 64M
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607793] [drm] Replacing VGA console driver
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607928] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 57344K
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.607994] [drm:sanitize_rc6_option [i915]] BIOS enabled RC states: HW_CTRL off HW_RC6 off SW_TARGET_STATE 4
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608211] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x79a35018
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608309] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608367] [drm:intel_opregion_setup [i915]] ASLE supported
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608452] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (RVDA)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608767] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608779] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608782] [drm] Driver supports precise vblank timestamp query.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608842] [drm:intel_bios_init [i915]] Set default to SSC at 100000 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608901] [drm:intel_bios_init [i915]] VBT signature "$VBT GEMINILAKE     ", BDB version 210
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.608961] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 0 fdi_rx_polarity_inverted 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609037] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609122] [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-19)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609181] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609239] [drm:intel_bios_init [i915]] DRRS supported mode is seamless
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609303] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609312] [drm:drm_mode_debug_printmodeline] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609370] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609428] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 180, controller 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609485] [drm:intel_bios_init [i915]] Unsupported child device size for SDVO mapping.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609542] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 210 not known; assuming 38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609604] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609663] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609720] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609777] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609833] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609889] [drm:intel_bios_init [i915]] Port C VBT info: DP:0 HDMI:1 DVI:1 EDP:0 CRT:0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.609944] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.610615] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.610690] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.610814] [drm:intel_power_well_enable [i915]] enabling power well 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.610893] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.610966] [drm:intel_power_well_enable [i915]] enabling always-on
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.611038] [drm:intel_power_well_enable [i915]] enabling DC off
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.611093] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.611156] [drm:intel_power_well_enable [i915]] enabling power well 2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.611212] [drm:intel_power_well_enable [i915]] enabling dpio-common-a
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.611663] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.611763] [drm:_bxt_ddi_phy_init [i915]] DDI PHY 0 already enabled, won't reprogram it
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.611819] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.612538] [drm:intel_power_well_enable [i915]] enabling AUX A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.612595] [drm:skl_set_power_well [i915]] Enabling AUX A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.612650] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.612777] [drm:intel_power_well_enable [i915]] enabling AUX C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.612831] [drm:skl_set_power_well [i915]] Enabling AUX C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.612943] [drm:intel_csr_ucode_init [i915]] Loading i915/glk_dmc_ver1_04.bin
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.614611] [drm] Finished loading DMC firmware i915/glk_dmc_ver1_04.bin (v1.4)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.614864] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001a18 hp_port:38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.616766] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.616840] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 7 (7.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.616893] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 7 (7.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.616946] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 8 (8.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.616997] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 22 (22.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.617066] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 22 (22.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.617117] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 22 (22.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.617169] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 22 (22.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.617221] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 22 (22.0 usec)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.617283] [drm:intel_modeset_init [i915]] 3 display pipes available.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618040] [drm:intel_update_cdclk [i915]] Current CD clock rate: 316800 kHz, VCO: 633600 kHz, ref: 19200 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618113] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 316800 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618171] [drm:intel_update_max_cdclk [i915]] Max dotclock rate: 627264 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618188] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618615] [drm:intel_ddi_init [i915]] BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618688] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618776] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618880] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.618945] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 6000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.619003] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 600
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.619103] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.619167] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.619225] [drm:intel_edp_panel_vdd_sanitize [i915]] VDD left on by BIOS, adjusting state tracking
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.620144] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.620563] r8169 0000:01:00.0 enp1s0: renamed from eth0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.620574] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.620967] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.621389] [drm:intel_dp_init_connector [i915]] EDP DPCD : 02 fb e7
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.625242] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.625431] [drm:intel_dp_init_connector [i915]] Downclock mode is not found. DRRS not supported
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.625496] [drm:intel_dp_aux_init_backlight_funcs [i915]] AUX Backlight Control Supported!
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626331] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, enabled, brightness 65472/65535
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626512] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626578] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626693] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626756] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x1 for port B (VBT)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626851] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626911] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (VBT)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.626985] [drm:intel_dsi_init [i915]] 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627248] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627315] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:36:pipe A] hw state readout: enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627382] [drm:intel_set_plane_visible [i915]] pipe B active planes 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627456] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:47:pipe B] hw state readout: disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627522] [drm:intel_set_plane_visible [i915]] pipe C active planes 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627582] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:58:pipe C] hw state readout: disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627643] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL A hw state readout: crtc_mask 0x00000000, on 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627723] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL B hw state readout: crtc_mask 0x00000001, on 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627783] [drm:intel_modeset_setup_hw_state [i915]] PORT PLL C hw state readout: crtc_mask 0x00000000, on 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627845] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DDI A] hw state readout: disabled, pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627922] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:67:DDI B] hw state readout: enabled, pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.627981] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:69:DP-MST A] hw state readout: disabled, pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628053] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:70:DP-MST B] hw state readout: disabled, pipe B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628109] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:71:DP-MST C] hw state readout: disabled, pipe C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628179] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:74:DDI C] hw state readout: disabled, pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628264] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:60:eDP-1] hw state readout: disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628330] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:68:DP-1] hw state readout: enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628390] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:72:HDMI-A-1] hw state readout: disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628447] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:75:HDMI-A-2] hw state readout: disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628476] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801758aae98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628542] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628705] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][setup_hw_state]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628816] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628869] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 109 270000 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628932] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.628938] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 109 270000 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629032] [drm:intel_dump_pipe_config [i915]] crtc timings: 270000 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x40 flags: 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629117] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629172] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629227] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629279] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629338] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629390] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629444] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629496] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629551] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629605] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 4A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629659] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629713] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][setup_hw_state]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629764] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629815] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629866] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629871] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629921] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629926] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.629998] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630362] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630417] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630471] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630524] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630581] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630635] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630689] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630743] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630797] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630850] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630903] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.630958] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][setup_hw_state]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631026] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631079] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631131] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631136] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631189] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631194] [drm:drm_mode_debug_printmodeline] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631247] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631299] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631352] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631405] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631514] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631567] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631620] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631672] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631725] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631778] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.631830] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632046] [drm:intel_power_well_disable [i915]] disabling AUX C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632123] [drm:skl_set_power_well [i915]] Disabling AUX C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632181] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632237] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632293] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632404] [drm:skylake_get_initial_plane_config [i915]] pipe A with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632468] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=7e9000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632573] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] failed to allocate stolen space
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632640] [drm:intel_set_plane_visible [i915]] pipe A active planes 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.632700] [drm:fetch_uc_fw [i915]] before requesting firmware: uC fw fetch status PENDING
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.633258] [drm:fetch_uc_fw [i915]] fetch uC fw from i915/glk_huc_ver02_00_1748.bin succeeded, fw ffff880174cb7598
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.633315] [drm:fetch_uc_fw [i915]] firmware version 2.0 OK (minimum 2.0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.633650] [drm:fetch_uc_fw [i915]] uC fw fetch status SUCCESS, obj ffff880175348040
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.633824] [drm:fetch_uc_fw [i915]] before requesting firmware: uC fw fetch status PENDING
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.634164] [drm:fetch_uc_fw [i915]] fetch uC fw from i915/glk_guc_ver10_56.bin succeeded, fw ffff880174cb7598
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.634221] [drm:fetch_uc_fw [i915]] firmware version 10.56 OK (minimum 10.56)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.634440] [drm:fetch_uc_fw [i915]] uC fw fetch status SUCCESS, obj ffff88017534f840
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.635114] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, fee00000]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.635275] [drm:i915_gem_contexts_init [i915]] logical context support initialized
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.635435] [drm:intel_engine_create_scratch [i915]] rcs0 pipe control offset: 0xfedff000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.637462] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.637547] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 12
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.637672] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.637813] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.637937] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.640385] [drm:intel_huc_init_hw [i915]] i915/glk_huc_ver02_00_1748.bin fw status: fetch SUCCESS, load NONE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.642125] [drm:intel_huc_init_hw [i915]] HuC DMA transfer wait over with ret 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.642194] [drm:intel_huc_init_hw [i915]] i915/glk_huc_ver02_00_1748.bin fw status: fetch SUCCESS, load SUCCESS
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.642253] [drm:intel_guc_init_hw [i915]] GuC fw status: path i915/glk_guc_ver10_56.bin, fetch SUCCESS, load NONE
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.642305] [drm:intel_guc_init_hw [i915]] GuC fw status: fetch SUCCESS, load PENDING
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.648378] [drm:guc_ucode_xfer_dma [i915]] DMA status 0x10, GuC status 0x8002f0ec
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.648454] [drm:guc_ucode_xfer_dma [i915]] returning 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.648459] [drm] GuC submission enabled (firmware i915/glk_guc_ver10_56.bin [version 10.56])
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.655671] [drm:i915_guc_submission_enable [i915]] reserved cacheline 0x0, next 0x40, linesize 64
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.655749] [drm:i915_guc_submission_enable [i915]] Host engines 0x17 => GuC engines used 0xf
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.655823] [drm:__reserve_doorbell [i915]] client 0 (high prio=no) reserved doorbell: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.658197] [drm:i915_guc_submission_enable [i915]] new priority 2 client ffff880175b60a58 for engine(s) 0x17: stage_id 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.658273] [drm:i915_guc_submission_enable [i915]] doorbell id 0, cacheline offset 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.661980] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.662086] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.662157] [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.662228] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.662409] [drm:__bxt_hpd_detection_setup [i915]] Invert bit setting: hp_ctl:18001818 hp_port:38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.665364] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.665525] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.666798] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.668319] [drm] Initialized i915 1.6.0 20170619 for 0000:00:02.0 on minor 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.670363] [drm:intel_opregion_register [i915]] 4 outputs detected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.684678] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.688742] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.689736] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690721] [drm] DRM_I915_DEBUG enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690724] [drm] DRM_I915_DEBUG_GEM enabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690748] [drm:drm_setup_crtcs] 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690765] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690862] [drm:intel_dp_detect [i915]] [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690864] sdhci-pci 0000:00:1e.0: SDHCI controller found [8086:31d0] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690933] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.690993] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.691068] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.691121] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.691607] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692347] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1] status updated from unknown to connected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692491] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692506] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1] probed modes :
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692512] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692517] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692585] [drm:intel_dp_detect [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692646] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.692713] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.693786] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.694611] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.694733] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.694795] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.694854] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.694911] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.695097] mmc1: SDHCI controller on PCI [0000:00:1e.0] using ADMA 64-bit
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.695896] [drm:drm_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.695963] [drm:intel_dp_detect [i915]] Sink is not MST capable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.698547] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705360] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705421] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705431] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1] status updated from unknown to connected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705505] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705521] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1] probed modes :
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705526] [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705531] [drm:drm_mode_debug_printmodeline] Modeline 81:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705535] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705540] [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705544] [drm:drm_mode_debug_printmodeline] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705549] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705553] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705557] [drm:drm_mode_debug_printmodeline] Modeline 89:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705562] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705566] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705571] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705575] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705581] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.705645] [drm:intel_hdmi_detect [i915]] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.707329] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.707397] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.709320] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.709340] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.711636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.711698] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.713439] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.713460] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.713470] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1] status updated from unknown to disconnected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.713475] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1] disconnected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.713484] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.713545] [drm:intel_hdmi_detect [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.791405] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.791493] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.793862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.793887] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.793899] [drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.793911] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2] status updated from unknown to connected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794284] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794291] [drm:drm_edid_to_eld] ELD monitor HP E232
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794298] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794303] [drm:drm_edid_to_eld] ELD size 28, SAD count 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794408] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2] probed modes :
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794418] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794425] [drm:drm_mode_debug_printmodeline] Modeline 113:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794431] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794438] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794444] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794450] [drm:drm_mode_debug_printmodeline] Modeline 101:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794457] [drm:drm_mode_debug_printmodeline] Modeline 99:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794463] [drm:drm_mode_debug_printmodeline] Modeline 100:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794470] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794476] [drm:drm_mode_debug_printmodeline] Modeline 115:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794482] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794489] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794495] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794501] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794508] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794514] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794521] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794527] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794564] [drm:drm_setup_crtcs] connector 60 enabled? yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794569] [drm:drm_setup_crtcs] connector 68 enabled? yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794574] [drm:drm_setup_crtcs] connector 72 enabled? no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794579] [drm:drm_setup_crtcs] connector 75 enabled? yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794678] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794692] [drm:drm_setup_crtcs] looking for cmdline mode on connector 60
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794698] [drm:drm_setup_crtcs] looking for preferred mode on connector 60 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794703] [drm:drm_setup_crtcs] found mode 1920x1080
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794708] [drm:drm_setup_crtcs] looking for cmdline mode on connector 68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794713] [drm:drm_setup_crtcs] looking for preferred mode on connector 68 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794718] [drm:drm_setup_crtcs] found mode 1920x1080
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794723] [drm:drm_setup_crtcs] looking for cmdline mode on connector 75
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794727] [drm:drm_setup_crtcs] looking for preferred mode on connector 75 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794732] [drm:drm_setup_crtcs] found mode 1920x1080
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794736] [drm:drm_setup_crtcs] picking CRTCs for 8192x8192 config
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794910] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794922] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 47 (0,0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.794934] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 58 (0,0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.795062] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.799228] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00180000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.800404] fbcon: inteldrmfb (fb0) is primary device
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801567] [drm:drm_atomic_state_init] Allocated atomic state ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801582] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017598d288 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801592] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017598ee48 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801596] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598ee48 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801600] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598ee48
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801611] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017598d038 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801614] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598d038 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801617] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598d038
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801626] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88017598cde8 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801629] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598cde8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801632] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598cde8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801642] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff880176465728 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801644] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880176465728 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801647] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880176465728
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801657] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880179efb098 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801666] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff880179efb2e8 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801669] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880179efb2e8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801672] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880179efb2e8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801680] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff880179ef8b98 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801683] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880179ef8b98 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801686] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880179ef8b98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801711] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff8801764d8008 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801714] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d8008 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801717] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764d8008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801727] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff8801764dbc28 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801730] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764dbc28 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801733] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764dbc28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801743] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff8801764d8258 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801754] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff8801764db9d8 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801757] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db9d8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801760] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764db9d8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801770] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff8801764d84a8 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801773] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d84a8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801776] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764d84a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801786] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff8801764db788 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801789] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db788 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801792] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764db788
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801802] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff8801764d86f8 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801805] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d86f8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801808] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764d86f8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801821] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880175acc138 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801839] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880175acc138
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801842] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598d288 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801846] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88017598d288
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801851] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801879] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880179f16918 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801888] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f16918 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801899] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880179f16748 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801903] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f16748 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801914] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff880175acae98 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801925] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880175acae98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801929] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880179efb098 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801932] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880179efb098
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801936] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801944] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f16918 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801980] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff880175acb7e8 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801991] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880175acb7e8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801994] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d8258 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.801997] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff8801764d8258
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802002] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802016] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880179f175c8 state to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802019] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f175c8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802022] [drm:drm_atomic_check_only] checking ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802028] [drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] mode changed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802032] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802034] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802037] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802040] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] mode changed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802043] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] enable changed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802046] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] active changed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802055] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802061] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] using [ENCODER:59:DDI A] on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802064] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802068] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802071] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802076] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] using [ENCODER:74:DDI C] on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802079] [drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable: y, active: y
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802083] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802091] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802095] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802102] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: y, active: y
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802106] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802115] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802209] [drm:intel_atomic_check [i915]] [CONNECTOR:60:eDP-1] checking for sink bpp constrains
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802286] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802452] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802526] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802607] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802685] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802763] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802838] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802911] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.802982] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803012] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803083] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803089] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803162] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803233] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803305] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803376] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803447] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803527] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803598] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803671] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803741] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803811] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803880] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 4A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803949] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.803978] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804054] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804127] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804201] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804276] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804348] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804490] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804560] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804629] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804697] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804765] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804771] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804839] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804844] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804914] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.804982] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805070] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805138] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805206] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805279] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805348] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805416] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805485] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805552] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805620] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805687] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805693] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805769] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805920] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.805992] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806081] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806151] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806286] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806353] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806359] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806425] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806430] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806498] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806564] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806633] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806700] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806766] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806838] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x0, ebb4: 0x0,pll0: 0x0, pll1: 0x0, pll2: 0x0, pll3: 0x0, pll6: 0x0, pll8: 0x0, pll9: 0x0, pll10: 0x0, pcsdw12: 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.806971] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807055] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807122] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807187] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807253] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807330] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807409] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807478] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807548] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807616] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807752] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807827] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe A] using pre-allocated PORT PLL A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807897] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.807969] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808057] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808128] [drm:skl_update_scaler [i915]] scaler_user index 1.31: Staged freeing scaler id 0 scaler_users = 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808203] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808271] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808338] [drm:skl_update_scaler [i915]] scaler_user index 2.31: Staged freeing scaler id 0 scaler_users = 0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808457] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 510) -> (0 - 332)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808526] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (332 - 340)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808594] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1020) -> (340 - 672)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808661] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (672 - 680)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808728] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (0 - 0) -> (680 - 1012)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808794] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.808797] [drm:drm_atomic_commit] committing ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.809483] [drm:intel_disable_pipe [i915]] disabling pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.811906] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.811974] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.812562] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.812618] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.812687] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.812750] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.812933] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 1, on? 1) for crtc 36
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813170] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813247] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813647] [drm:intel_set_cdclk [i915]] Changing CDCLK to 79200 kHz, VCO 633600 kHz, ref 19200 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813747] [drm:intel_update_cdclk [i915]] Current CD clock rate: 79200 kHz, VCO: 633600 kHz, ref: 19200 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.813985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814176] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814234] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814292] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814405] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 36
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814461] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814869] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   10.814935] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.226422] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 0000006a
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.226537] [drm:wait_panel_status [i915]] Wait complete
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.226642] [drm:edp_panel_on [i915]] Wait for panel power on
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.226747] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 0000006b
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.428862] [drm:wait_panel_status [i915]] Wait complete
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.428983] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.6997] init!
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.429137] [drm:skl_set_power_well [i915]] Enabling DDI A IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.430569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.430674] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.430784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.431658] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.431759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.432931] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7008] guessed connection type (enp1s0) = 802-3-ethernet
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.433034] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.434924] [drm:intel_enable_pipe [i915]] enabling pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.435110] [drm:intel_edp_backlight_on [i915]] 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.435213] [drm:intel_panel_enable_backlight [i915]] pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.436026] [drm:intel_dp_aux_enable_backlight [i915]] VBT defined backlight frequency 200 Hz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.437567] [drm:intel_dp_aux_enable_backlight [i915]] Enable dynamic brightness.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.438121] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.438220] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.438382] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.438495] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7010] update_connection_setting_from_if_block: name:enp1s0, type:802-3-ethernet, id:Ifupdown (enp1s0), uuid: d4f520cc-fe82-d7ba-f35b-8e9bb7ffe98b
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.452138] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.452242] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.452515] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.452618] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.452719] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.452821] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.453422] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.453522] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.454276] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.454378] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.454956] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.455099] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7012] addresses count: 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.455203] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.455300] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.455877] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.455976] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.456134] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.456234] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.456336] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.456441] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.456540] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.457148] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.457247] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7013] adding enp1s0 to connections
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.458001] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.458130] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.458733] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.458832] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.459816] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.459928] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.460632] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.460730] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.460958] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.461081] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.461652] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.461746] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.462735] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.462845] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.463444] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.463542] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.463643] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.463735] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.464350] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.464444] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.464577] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7014] adding iface enp1s0 to eni_ifaces
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.464689] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.464790] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.464910] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.465510] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.465628] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.466133] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.466226] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.466746] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7015] autoconnect
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.466796] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.467771] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.467833] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.468466] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.468517] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.468571] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.468620] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.469158] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.469222] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.469289] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.471651] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.471742] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.471801] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.472327] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.472381] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.473400] [drm:intel_enable_pipe [i915]] enabling pipe B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.473635] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.473695] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.473896] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.473952] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.475004] [drm:intel_enable_pipe [i915]] enabling pipe C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.492935] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.493064] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.493191] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.493258] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.493486] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.493549] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.493738] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.493928] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.494127] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.494306] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.494437] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.494609] [drm:__drm_atomic_state_free] Freeing atomic state ffff8801766edfa8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.494691] Console: switching to colour frame buffer device 240x67
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495272] [drm:drm_atomic_state_init] Allocated atomic state ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495289] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801758aae98 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7015] management mode: unmanaged
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7034] devices added (path: /sys/devices/pci0000:00/0000:00:13.0/0000:01:00.0/net/enp1s0, iface: enp1s0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7036] locking wired connection setting
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7037] devices added (path: /sys/devices/virtual/net/lo, iface: lo)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495306] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff8801764db538 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495323] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801758aae98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495328] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db538 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495333] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff8801764db538
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495339] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495361] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880179f161d8 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495369] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f161d8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495374] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f161d8 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495387] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff880174cbe678 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495400] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff8801764d8948 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495413] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880174cbe678
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495417] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d8948 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495421] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff8801764d8948
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495427] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7038] device added (path: /sys/devices/virtual/net/lo, iface: lo): no ifupdown configuration found.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495440] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880179f17798 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495447] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f17798 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495452] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f17798 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495464] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff880174cbefc8 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495477] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff8801764db2e8 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495489] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880174cbefc8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495493] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db2e8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495497] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff8801764db2e8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495502] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495517] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880179f16ae8 state to ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495522] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f16ae8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495527] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880179f16ae8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495531] [drm:drm_atomic_check_only] checking ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495547] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495553] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495557] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495562] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495566] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495571] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495669] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495756] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495843] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.495927] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.496011] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.496118] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.496142] [drm:drm_atomic_commit] committing ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.509395] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.509534] [drm:__drm_atomic_state_free] Freeing atomic state ffff880175823528
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.524600] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.615109] EXT4-fs (sda2): mounted filesystem with ordered data mode. Opts: (null)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   11.779086] [drm] RC6 on
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   12.331076] EXT4-fs (sda2): re-mounted. Opts: (null)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.381837] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.408497] snd_hda_intel 0000:00:0e.0: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.409900] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.440495] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=65472/65535
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.440569] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 65472
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.462657] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC298: line_outs=1 (0x14/0x0/0x0/0x0/0x0) type:speaker
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.462663] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.462666] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.462669] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.462672] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.462675] snd_hda_codec_realtek hdaudioC0D0:      Mic=0x18
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.462678] snd_hda_codec_realtek hdaudioC0D0:      Internal Mic=0x12
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.510815] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.521706] input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:0e.0/sound/card0/input4
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.522814] input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:0e.0/sound/card0/input5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7038] end _init.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.524024] sdhci-pci 0000:00:1b.0: SDHCI controller found [8086:31ca] (rev 1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567231] [drm:drm_atomic_state_init] Allocated atomic state ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567251] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801787c12a8 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567260] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880177b92068 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567280] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801787c12a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567283] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177b92068 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567287] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177b92068
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567290] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7039] settings: loaded plugin ifupdown: (C) 2008 Canonical Ltd.  To report bugs please use the NetworkManager mailing list. (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-settings-plugin-ifupdown.so)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7040] settings: loaded plugin keyfile: (c) 2007 - 2015 Red Hat, Inc.  To report bugs please use the NetworkManager mailing list.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7045] SettingsPlugin-Ofono: init!
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <warn>  [1498682490.7046] SettingsPlugin-Ofono: file doesn't exist: /var/lib/ofono
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7047] SettingsPlugin-Ofono: end _init.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7047] settings: loaded plugin ofono: (C) 2013-2016 Canonical Ltd.  To report bugs please use the NetworkManager mailing list. (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-settings-plugin-ofono.so)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7048] (-1345926096) ... get_connections.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7048] (-1345926096) ... get_connections (managed=false): return empty list.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7054] SettingsPlugin-Ofono: (-1345925776) ... get_connections.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7055] SettingsPlugin-Ofono: (-1345925776) connections count: 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682490.7056] get unmanaged devices count: 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0241] settings: hostname: using hostnamed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0242] settings: hostname changed from (none) to "GLK-2-GLKRVP1DDR405"
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0245] Using DHCP client 'dhclient'
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0246] manager: WiFi enabled by radio killswitch; enabled by state file
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0247] manager: WWAN enabled by radio killswitch; enabled by state file
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0247] manager: Networking is enabled by state file
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0248] Loaded device plugin: NMVxlanFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0249] Loaded device plugin: NMVlanFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0250] Loaded device plugin: NMVethFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0251] Loaded device plugin: NMTunFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0251] Loaded device plugin: NMMacvlanFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0252] Loaded device plugin: NMIPTunnelFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0253] Loaded device plugin: NMInfinibandFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0254] Loaded device plugin: NMEthernetFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0255] Loaded device plugin: NMBridgeFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0255] Loaded device plugin: NMBondFactory (internal)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0278] Loaded device plugin: NMWwanFactory (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-wwan.so)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0291] Loaded device plugin: NMAtmManager (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-adsl.so)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0298] Loaded device plugin: NMWifiFactory (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-wifi.so)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0336] Loaded device plugin: NMBluezManager (/usr/lib/x86_64-linux-gnu/NetworkManager/libnm-device-plugin-bluetooth.so)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0379] manager: (enp1s0): new Ethernet device (/org/freedesktop/NetworkManager/Devices/0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: nm_device_get_device_type: assertion 'NM_IS_DEVICE (self)' failed
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0393] device (lo): link connected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0402] manager: (lo): new Generic device (/org/freedesktop/NetworkManager/Devices/1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0415] manager: startup complete
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0417] manager: NetworkManager state is now CONNECTED_GLOBAL
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0483] urfkill disappeared from the bus
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0518] ofono is now available
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <warn>  [1498682491.0542] failed to enumerate oFono devices: GDBus.Error:org.freedesktop.DBus.Error.ServiceUnknown: The name org.ofono was not provided by any .service files
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682491.0544] ModemManager available in the bus
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 NetworkManager[690]: <info>  [1498682492.8309] device (enp1s0): link connected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 content-hub-pee[1149]: Error parsing manifest for package 'com.ubuntu.gallery': com.ubuntu.gallery does not exist in any database for user gfx
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 content-hub-pee[1149]: Unable to get snap information for 'com.ubuntu.gallery': Status code is: 404
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 content-hub-pee[1149]: Error parsing manifest for package 'com.ubuntu.gallery': com.ubuntu.gallery does not exist in any database for user gfx
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 content-hub-pee[1149]: Unable to get snap information for 'com.ubuntu.gallery': Status code is: 404
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 click[1125]: hooks.vala:1216: User-level hook push-helper failed: Hook command '/usr/lib/ubuntu-push-client/click-hook-wrapper' failed: Child process exited with code 1
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567317] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880178feecb8 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567327] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178feecb8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567330] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178feecb8 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567339] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801787c5d28 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567346] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880177b91bc8 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567355] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801787c5d28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567357] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177b91bc8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567359] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177b91bc8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567362] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567372] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880178fef798 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567375] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178fef798 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567378] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178fef798 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567387] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff8801787c1bf8 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567394] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880177b914d8 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567402] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801787c1bf8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567404] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177b914d8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567407] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177b914d8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567410] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567421] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880176610e88 state to ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567424] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880176610e88 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567427] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880176610e88 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567429] [drm:drm_atomic_check_only] checking ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567442] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567446] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567449] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567452] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567455] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567458] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567532] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567579] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567626] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567671] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567761] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.567781] [drm:drm_atomic_commit] committing ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.583495] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.583586] [drm:__drm_atomic_state_free] Freeing atomic state ffff8801787b7a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665666] [drm:drm_atomic_state_init] Allocated atomic state ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665681] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017801e678 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665690] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880177f2f538 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665703] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801e678
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665706] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f538 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665709] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f538
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665713] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665728] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88017804a1d8 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665733] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a1d8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665737] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a1d8 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665746] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801780192a8 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665754] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880177f2f788 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665763] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801780192a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665765] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f788 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665768] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f788
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665771] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665780] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88017804b3f8 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665783] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804b3f8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665787] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804b3f8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665796] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88017801dd28 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665803] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880177f2f2e8 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665811] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801dd28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665814] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f2e8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665816] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f2e8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665819] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665829] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88017804a3a8 state to ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665832] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a3a8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665834] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a3a8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665837] [drm:drm_atomic_check_only] checking ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665850] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665854] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665856] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665860] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665862] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665865] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665939] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.665987] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.666050] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.666096] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.666141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.666186] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.666202] [drm:drm_atomic_commit] committing ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.675824] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.675914] [drm:__drm_atomic_state_free] Freeing atomic state ffff8801787b2fd8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.724919] Adding 16642044k swap on /dev/sda3.  Priority:-1 extents:1 across:16642044k SSFS
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744341] [drm:drm_atomic_state_init] Allocated atomic state ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744356] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801787c1bf8 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744365] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880177f2c4a8 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744378] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801787c1bf8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744381] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2c4a8 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744384] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2c4a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744388] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744404] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880177e84008 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744410] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177e84008 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744413] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177e84008 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744423] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017801ca88 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744431] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880177f2cde8 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744439] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801ca88
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744442] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2cde8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744444] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2cde8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744447] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744456] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880177e84cb8 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744460] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177e84cb8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744463] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177e84cb8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744472] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff880174cbe678 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744479] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880177f2de18 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744487] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880174cbe678
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744489] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2de18 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744492] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2de18
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744495] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744505] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880177e853f8 state to ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744508] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177e853f8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744510] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177e853f8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744513] [drm:drm_atomic_check_only] checking ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744526] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744529] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744532] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744535] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744537] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744540] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744614] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744662] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744710] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744757] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744803] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744849] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.744865] [drm:drm_atomic_commit] committing ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.759182] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.759261] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177027a38
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.771996] [drm:drm_atomic_state_init] Allocated atomic state ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772009] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017801dd28 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772018] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880177f2f2e8 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772029] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801dd28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772032] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f2e8 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772035] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f2e8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772039] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772054] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88017804b3f8 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772060] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804b3f8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772063] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804b3f8 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772072] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017801e678 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772082] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880177f2e2b8 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772090] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801e678
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772092] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2e2b8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772095] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2e2b8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772098] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772107] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88017804aae8 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772110] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804aae8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772113] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804aae8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772123] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff8801780192a8 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772130] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880177f2f788 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772138] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801780192a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772141] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f788 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772143] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f788
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772147] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772157] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88017804a1d8 state to ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772160] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a1d8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772163] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a1d8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772166] [drm:drm_atomic_check_only] checking ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772177] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772181] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772184] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772187] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772189] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772192] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772265] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772313] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772361] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772407] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772453] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772498] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.772514] [drm:drm_atomic_commit] committing ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.783165] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.783248] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177020558
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796428] [drm:drm_atomic_state_init] Allocated atomic state ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796440] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880166868008 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796448] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880177f2de18 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796459] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880166868008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796462] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2de18 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796465] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2de18
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796468] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796482] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88017804b968 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796488] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804b968 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796491] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804b968 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796500] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801668692a8 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796508] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880177f2cde8 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796515] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801668692a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796518] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2cde8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796520] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2cde8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796523] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796532] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88017804a008 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796535] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a008 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796538] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a008 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796546] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff880166869bf8 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796554] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880177f2fc28 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796562] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880166869bf8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796564] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2fc28 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796566] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2fc28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796569] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796579] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88017804a918 state to ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796582] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a918 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796584] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017804a918 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796587] [drm:drm_atomic_check_only] checking ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796598] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796602] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796604] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796607] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796609] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796613] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796685] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796732] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796777] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796821] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796865] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796907] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.796922] [drm:drm_atomic_commit] committing ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.809306] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.809433] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177021a98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846608] [drm:drm_atomic_state_init] Allocated atomic state ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846621] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88016686dd28 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846629] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880177f2f098 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846643] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686dd28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846646] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f098 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846649] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f098
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846653] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846668] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880177f05b38 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846674] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177f05b38 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846677] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177f05b38 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846687] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686e678 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846694] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880177f2f788 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846703] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686e678
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846705] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f788 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846707] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f788
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846711] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846720] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880177f041d8 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846724] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177f041d8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846727] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177f041d8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846735] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88016686d3d8 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846744] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880177f2ebf8 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846752] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686d3d8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846754] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2ebf8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846757] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2ebf8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846760] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846769] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880177f04e88 state to ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846772] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177f04e88 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846775] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880177f04e88 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846777] [drm:drm_atomic_check_only] checking ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846790] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846794] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846796] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846800] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846802] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846805] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846880] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846928] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.846976] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.847037] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.847084] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.847129] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.847146] [drm:drm_atomic_commit] committing ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.851807] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.859202] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.859289] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177026f98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.976277] r8169 0000:01:00.0 enp1s0: link down
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.976281] r8169 0000:01:00.0 enp1s0: link down
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   13.976574] IPv6: ADDRCONF(NETDEV_UP): enp1s0: link is not ready
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   14.185968] random: crng init done
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   14.579780] new mount options do not match the existing superblock, will be ignored
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   16.450735] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   16.450835] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   16.450891] [drm:intel_power_well_disable [i915]] disabling AUX A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   16.450952] [drm:skl_set_power_well [i915]] Disabling AUX A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   17.945932] r8169 0000:01:00.0 enp1s0: link up
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   17.946017] IPv6: ADDRCONF(NETDEV_CHANGE): enp1s0: link becomes ready
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591749] [drm:drm_atomic_state_init] Allocated atomic state ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591786] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880175acae98 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591810] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cdfa758 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591853] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880175acae98
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591859] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cdfa758 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591866] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88015cdfa758
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591875] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.591934] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88015cdca1d8 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592018] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cdca1d8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592027] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cdca1d8 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592048] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8b7e8 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592066] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cdfabf8 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592086] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015da8b7e8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592092] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cdfabf8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592097] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88015cdfabf8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592105] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592125] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015cdcb058 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592135] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cdcb058 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592141] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cdcb058 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592160] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d9312a8 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592178] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88015cdfb9d8 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592195] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d9312a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592201] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cdfb9d8 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592206] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88015cdfb9d8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592214] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592236] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88015cdcb968 state to ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592243] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cdcb968 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592249] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cdcb968 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592255] [drm:drm_atomic_check_only] checking ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592280] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592288] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592294] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592301] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592306] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592313] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592450] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592555] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592758] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592858] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.592956] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.593074] [drm:drm_atomic_commit] committing ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.609256] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   19.609344] [drm:__drm_atomic_state_free] Freeing atomic state ffff880163958008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995274] [drm:drm_fb_helper_hotplug_event] 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995300] [drm:drm_setup_crtcs] 
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995336] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995474] [drm:intel_dp_detect [i915]] [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995590] [drm:intel_power_well_enable [i915]] enabling AUX A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995694] [drm:skl_set_power_well [i915]] Enabling AUX A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995773] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995849] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995922] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.995993] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.996205] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.996308] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.997089] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.998074] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.998097] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1] probed modes :
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.998107] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.998115] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.998194] [drm:intel_dp_detect [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.998262] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.998333] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   20.999454] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.000562] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.000638] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.000708] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.000778] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.001889] [drm:drm_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.001969] [drm:intel_dp_detect [i915]] Sink is not MST capable
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012598] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012669] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012762] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012826] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1] probed modes :
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012833] [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012838] [drm:drm_mode_debug_printmodeline] Modeline 81:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012842] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012846] [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012850] [drm:drm_mode_debug_printmodeline] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012854] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012859] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012863] [drm:drm_mode_debug_printmodeline] Modeline 89:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012867] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012871] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012876] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012880] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012887] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.012934] [drm:intel_hdmi_detect [i915]] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.015123] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.015180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.017250] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.017256] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.019327] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.019391] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.021471] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.021480] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.021486] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1] disconnected
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.021492] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.021541] [drm:intel_hdmi_detect [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.101667] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.101746] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.104162] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.104185] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.104197] [drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.104579] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.104586] [drm:drm_edid_to_eld] ELD monitor HP E232
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.104593] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.104598] [drm:drm_edid_to_eld] ELD size 28, SAD count 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105335] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2] probed modes :
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105346] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105353] [drm:drm_mode_debug_printmodeline] Modeline 113:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105361] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105367] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105374] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105381] [drm:drm_mode_debug_printmodeline] Modeline 101:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105388] [drm:drm_mode_debug_printmodeline] Modeline 99:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105395] [drm:drm_mode_debug_printmodeline] Modeline 100:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105402] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105409] [drm:drm_mode_debug_printmodeline] Modeline 115:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105416] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105424] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105432] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105439] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105446] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105453] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105460] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105467] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105510] [drm:drm_setup_crtcs] connector 60 enabled? yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105516] [drm:drm_setup_crtcs] connector 68 enabled? yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105521] [drm:drm_setup_crtcs] connector 72 enabled? no
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105526] [drm:drm_setup_crtcs] connector 75 enabled? yes
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105610] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105631] [drm:drm_setup_crtcs] looking for cmdline mode on connector 60
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105637] [drm:drm_setup_crtcs] looking for preferred mode on connector 60 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105643] [drm:drm_setup_crtcs] found mode 1920x1080
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105650] [drm:drm_setup_crtcs] looking for cmdline mode on connector 68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105655] [drm:drm_setup_crtcs] looking for preferred mode on connector 68 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105661] [drm:drm_setup_crtcs] found mode 1920x1080
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105665] [drm:drm_setup_crtcs] looking for cmdline mode on connector 75
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105670] [drm:drm_setup_crtcs] looking for preferred mode on connector 75 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105676] [drm:drm_setup_crtcs] found mode 1920x1080
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105681] [drm:drm_setup_crtcs] picking CRTCs for 1920x1080 config
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105886] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 36 (0,0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105901] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 47 (0,0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.105913] [drm:drm_setup_crtcs] desired mode 1920x1080 set on crtc 58 (0,0)
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106109] [drm:drm_atomic_state_init] Allocated atomic state ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106132] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880177f2f098 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106155] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88016686d3d8 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106172] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff880177f2e2b8 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106181] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2e2b8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106188] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880177f2e2b8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106204] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff880177f2c4a8 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106210] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2c4a8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106217] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880177f2c4a8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106235] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff880177f2fc28 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106242] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2fc28 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106248] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880177f2fc28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106264] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff880177f2f538 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106271] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f538 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106278] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880177f2f538
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106293] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880177f2dbc8 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106311] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686e678 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106327] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff880177f2d728 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106333] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2d728 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106340] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880177f2d728
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106356] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff880175810948 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106364] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880175810948 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106370] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880175810948
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106386] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff880175811288 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106392] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880175811288 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106399] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880175811288
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106416] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff880175813788 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106423] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880175813788 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106429] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880175813788
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106445] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880175812508 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106464] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88016686dd28 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106480] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff880175811bc8 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106487] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880175811bc8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106495] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880175811bc8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106510] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff8801758132e8 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106516] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801758132e8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106523] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801758132e8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106539] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff880177b92068 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106546] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177b92068 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106555] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880177b92068
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106570] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff88017674c008 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106577] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017674c008 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106583] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017674c008
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106604] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686d3d8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106612] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2f098 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106620] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2f098
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106629] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106688] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88015c203058 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106725] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203058 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106733] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203058 to [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106753] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686e678
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106760] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880177f2dbc8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106767] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880177f2dbc8
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106776] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106796] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c2021d8 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106806] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c2021d8 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106814] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c2021d8 to [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106863] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686dd28
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106871] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880175812508 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106880] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880175812508
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106889] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106910] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88015c203b38 state to ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106919] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203b38 to [NOCRTC]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106927] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203b38 to [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106934] [drm:drm_atomic_check_only] checking ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.106994] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107007] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107014] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107023] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107029] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107038] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107145] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107241] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107336] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107431] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107523] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107616] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.107663] [drm:drm_atomic_commit] committing ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.123803] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   21.124128] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015cf3ca68
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   24.002484] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   24.002779] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   24.002890] [drm:intel_power_well_disable [i915]] disabling AUX A
>Jun 28 15:41:53 GLK-2-GLKRVP1DDR405 kernel: [   24.003026] [drm:skl_set_power_well [i915]] Disabling AUX A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.473518] Console: switching to colour dummy device 80x25
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504329] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504446] [drm:intel_dp_detect [i915]] [CONNECTOR:60:eDP-1]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504554] [drm:intel_power_well_enable [i915]] enabling AUX A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504651] [drm:skl_set_power_well [i915]] Enabling AUX A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504722] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504788] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504851] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.504913] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.505118] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.505187] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.505862] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.506871] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.506890] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1] probed modes :
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.506910] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507282] [drm:drm_atomic_state_init] Allocated atomic state ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507297] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880177f2a008 state to ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507307] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8efc8 state to ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507312] [drm:drm_atomic_check_only] checking ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507329] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507334] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507338] [drm:drm_atomic_helper_check_modeset] [CRTC:36:pipe A] needs all connectors, enable: y, active: y
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507342] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507354] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cdf9288 state to ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507360] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507416] [drm:intel_atomic_check [i915]] [CONNECTOR:60:eDP-1] checking for sink bpp constrains
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507464] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 141000KHz
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507564] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507609] [drm:intel_dp_compute_config [i915]] DP link bw required 423000 available 540000
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507706] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6571076, gmch_n: 8388608, link_m: 273794, link_n: 524288, tu: 64
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507844] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507888] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507893] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507936] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507941] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.507986] [drm:intel_dump_pipe_config [i915]] crtc timings: 141000 1920 1936 1952 2104 1080 1083 1097 1116, type: 0x48 flags: 0xa
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508057] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 141000
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508105] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508151] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508251] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8100, ebb4: 0x2000,pll0: 0x1b, pll1: 0x100, pll2: 0x0, pll3: 0x0, pll6: 0x10803, pll8: 0x9, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508297] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508346] [drm:intel_dump_pipe_config [i915]] [PLANE:26:plane 1A] FB:107, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508393] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508442] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 2A] disabled, scaler_id = -1
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508490] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 3A] disabled, scaler_id = -1
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508538] [drm:intel_dump_pipe_config [i915]] [PLANE:32:plane 4A] disabled, scaler_id = -1
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508586] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508640] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508693] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508738] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 1, on 1, ms 1
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508788] [drm:bxt_get_dpll [i915]] [CRTC:36:pipe A] using pre-allocated PORT PLL A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508833] [drm:intel_reference_shared_dpll [i915]] using PORT PLL A for pipe A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.508855] [drm:drm_atomic_commit] committing ffff880176b45a58
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.509412] [drm:intel_edp_backlight_off [i915]] 
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.714490] [drm:intel_disable_pipe [i915]] disabling pipe A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.717434] [drm:intel_edp_panel_off.part.26 [i915]] Turn eDP port A panel power off
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.717549] [drm:intel_edp_panel_off.part.26 [i915]] Wait for panel power off time
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.717602] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status 80000008 control 00000060
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.768423] [drm:wait_panel_status [i915]] Wait complete
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.768497] [drm:intel_power_well_disable [i915]] disabling AUX A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.768543] [drm:skl_set_power_well [i915]] Disabling AUX A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.768591] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.768633] [drm:skl_set_power_well [i915]] Disabling DDI A IO power well
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.768701] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.768808] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL A (active 1, on? 1) for crtc 36
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769163] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769511] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769559] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769627] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769788] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL A (active 1, on? 0) for crtc 36
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.769834] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.770524] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.770616] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.770895] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.770973] [drm:intel_power_well_enable [i915]] enabling AUX A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.771040] [drm:skl_set_power_well [i915]] Enabling AUX A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.771091] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.771137] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>Jun 28 15:42:50 GLK-2-GLKRVP1DDR405 kernel: [   95.771261] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.322430] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 08000001 control 00000060
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.347635] [drm:wait_panel_status [i915]] Wait complete
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.347716] [drm:edp_panel_on [i915]] Wait for panel power on
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.347794] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.450025] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x00000008, dig 0x1a001818, pins 0x00000010
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.450104] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.450172] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.450366] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.548690] [drm:wait_panel_status [i915]] Wait complete
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.548781] [drm:intel_power_well_disable [i915]] disabling AUX A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.548867] [drm:skl_set_power_well [i915]] Disabling AUX A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.548958] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.549190] [drm:skl_set_power_well [i915]] Enabling DDI A IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.549308] [drm:intel_power_well_enable [i915]] enabling AUX A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.549436] [drm:skl_set_power_well [i915]] Enabling AUX A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.549603] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.549704] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.551252] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.551357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.551460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.552441] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.552548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.553903] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.554008] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 270000, Lane count = 2
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.556203] [drm:intel_enable_pipe [i915]] enabling pipe A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.556424] [drm:intel_edp_backlight_on [i915]] 
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.556524] [drm:intel_panel_enable_backlight [i915]] pipe A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.557854] [drm:intel_dp_aux_enable_backlight [i915]] VBT defined backlight frequency 200 Hz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.559635] [drm:intel_dp_aux_enable_backlight [i915]] Enable dynamic brightness.
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.560282] [drm:intel_psr_enable [i915]] PSR not supported on this platform
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.560395] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.560528] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.560605] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.560902] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:60:eDP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.560994] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.561265] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.573228] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880176b45a58
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.573281] [drm:__drm_atomic_state_free] Freeing atomic state ffff880176b45a58
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.573385] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.573487] [drm:intel_dp_detect [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.573562] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.573634] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.574833] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.575913] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.575988] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.576113] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.576188] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.577252] [drm:drm_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.577323] [drm:intel_dp_detect [i915]] Sink is not MST capable
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587451] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587512] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587605] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587659] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1] probed modes :
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587665] [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587670] [drm:drm_mode_debug_printmodeline] Modeline 81:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587674] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587678] [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587683] [drm:drm_mode_debug_printmodeline] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587687] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587691] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587695] [drm:drm_mode_debug_printmodeline] Modeline 89:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587699] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587703] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587707] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.587712] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588140] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588334] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880177f2bb38 state to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588347] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8ca88 state to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588351] [drm:drm_atomic_check_only] checking ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588360] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588366] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588370] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588374] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588388] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017583e9a8 state to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588393] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588447] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588494] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588589] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588633] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588682] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588728] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588774] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588821] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588866] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588909] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588915] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588958] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.588989] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589034] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589083] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589129] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589177] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589222] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589273] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589322] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589372] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:107, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589419] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589468] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589514] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589562] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589657] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589708] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589760] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589805] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 1, on 1, ms 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589853] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589898] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.589911] [drm:drm_atomic_commit] committing ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.590060] [drm:intel_disable_pipe [i915]] disabling pipe B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.592430] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.592497] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593074] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593120] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593175] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593221] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593281] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593499] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593823] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593888] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.593933] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.594120] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.594165] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.594352] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.594398] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.594443] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.594489] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.594971] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.595116] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.595779] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.595821] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.596361] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.596404] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.596449] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.596491] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.596979] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597101] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597169] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597215] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597310] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597380] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597928] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.597971] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.598197] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.598252] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.598751] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.598816] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.599608] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.599651] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.600141] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.600221] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.600268] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.600312] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.600853] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.600934] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.600985] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.601059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.601108] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.601188] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.601699] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.601743] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.602197] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.602267] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.602737] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.602782] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.603445] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.603490] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.603968] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.604062] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.604141] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.604186] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.604714] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.604777] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.604860] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.607196] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.607259] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.607307] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.607869] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.607914] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.608807] [drm:intel_enable_pipe [i915]] enabling pipe B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.611442] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.611506] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.611659] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.625925] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.626054] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.626144] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.626227] [drm:intel_hdmi_detect [i915]] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.628733] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.628830] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.631166] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.631188] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.633616] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.633688] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636160] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636182] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636194] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1] disconnected
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636741] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636761] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:72:HDMI-A-1] ffff880160dabb38 state to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636767] [drm:drm_atomic_check_only] checking ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636775] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636780] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636789] [drm:drm_atomic_commit] committing ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636885] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.636899] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.637042] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.637122] [drm:intel_hdmi_detect [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.722537] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.722636] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.725154] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.725181] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.725195] [drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.725678] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.725687] [drm:drm_edid_to_eld] ELD monitor HP E232
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.725696] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.725703] [drm:drm_edid_to_eld] ELD size 28, SAD count 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726624] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2] probed modes :
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726643] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726652] [drm:drm_mode_debug_printmodeline] Modeline 113:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726661] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726670] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726678] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726687] [drm:drm_mode_debug_printmodeline] Modeline 101:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726696] [drm:drm_mode_debug_printmodeline] Modeline 99:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726704] [drm:drm_mode_debug_printmodeline] Modeline 100:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726713] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726722] [drm:drm_mode_debug_printmodeline] Modeline 115:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726730] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726744] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726758] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726770] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726785] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726799] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726813] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.726827] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727601] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727631] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88017714fb38 state to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727653] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da88958 state to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727661] [drm:drm_atomic_check_only] checking ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727679] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727689] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727698] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: y, active: y
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727706] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727731] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88015cd69e18 state to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727742] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727847] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.727943] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728041] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728306] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728401] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728496] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728591] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728681] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728770] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728781] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728869] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728880] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.728971] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729106] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729199] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729296] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729386] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729489] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729583] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729680] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] FB:107, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729771] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729865] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.729954] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730080] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730176] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730380] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730471] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 1, on 1, ms 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730575] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730665] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730686] [drm:drm_atomic_commit] committing ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.730928] [drm:intel_disable_pipe [i915]] disabling pipe C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.744446] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.744570] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.744704] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745020] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.745876] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.746007] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.746186] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.746352] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.746449] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.746703] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.746811] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.748711] [drm:intel_enable_pipe [i915]] enabling pipe C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.749116] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.749272] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.749473] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.765863] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.765933] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadea48
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.768036] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadd508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.768068] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88015d9043a8 state to ffff88015dadd508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.768090] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da88008 state to ffff88015dadd508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.768099] [drm:drm_atomic_check_only] checking ffff88015dadd508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.768121] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.768131] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.768157] [drm:drm_atomic_commit] committing ffff88015dadd508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.773114] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadd508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.773167] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadd508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.773567] [drm:drm_mode_addfb2] [FB:62]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.930608] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.930625] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0c578 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.930636] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8dd28 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.930640] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.930653] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.930658] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.930671] [drm:drm_atomic_commit] committing ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.942528] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.942560] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.942797] [drm:drm_mode_addfb2] [FB:109]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.971171] [drm:drm_mode_addfb2] [FB:110]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.971834] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972021] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6b788 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972046] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972096] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6b788 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972111] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8ca88 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972116] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b788 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972121] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88015cd6b788
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972142] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88015cd694d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972146] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd694d8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972151] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd694d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972162] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88015cd69038 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972166] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69038 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972172] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69038
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972178] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972207] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd69038 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972217] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8ca88 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972221] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69038 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972227] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88015cd69038
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972244] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88015cd69288 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972248] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69288 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972253] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69288
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972263] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88015cd694d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972267] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd694d8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972272] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd694d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972282] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88015cd6b098 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972286] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b098 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972292] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b098
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972303] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd6b788 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972306] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b788 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972311] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88015cd6b788
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972326] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015da8ca88
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972340] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd68b98 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972350] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8efc8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972355] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68b98 to [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972360] [drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff88015cd68b98
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972378] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88015cd684a8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972382] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd684a8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972386] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd684a8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972397] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88015cd6b2e8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972401] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b2e8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972405] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b2e8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972416] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88015cd69bc8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972420] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69bc8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972425] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69bc8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972432] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972483] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd69bc8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972492] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8efc8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972496] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69bc8 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972501] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88015cd69bc8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972518] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88015cd68258 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972522] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68258 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972526] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68258
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972536] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88015cd6b2e8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972540] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b2e8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972546] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b2e8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972555] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88015cd6a9a8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972559] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6a9a8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972564] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6a9a8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972575] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd684a8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972579] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd684a8 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972584] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88015cd684a8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972597] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015da8efc8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972609] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6b9d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972618] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da89bf8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972622] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b9d8 to [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972627] [drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff88015cd6b9d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972644] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88015cd68b98 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972647] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68b98 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972652] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68b98
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972662] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88015cd69978 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972665] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69978 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972670] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69978
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972679] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88015cd6b788 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972684] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b788 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972688] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b788
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972699] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd6bc28 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972703] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6bc28 to [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972709] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88015cd6bc28
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972722] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015da89bf8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972734] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88015cd6b098 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972745] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da8ca88 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972749] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b098 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972754] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b098
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972765] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff88015cd6a508 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972768] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6a508 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972773] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6a508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972783] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff88015cd694d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972786] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd694d8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972791] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd694d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972802] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff88015cd68008 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972807] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68008 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972811] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68008
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972822] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff88015cd69288 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972826] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69288 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972832] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69288
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972837] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015da8ca88
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972856] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880162c0d5c8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972869] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0db38 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972880] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:72:HDMI-A-1] ffff880162c0d3f8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972892] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880162c0c008 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972896] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880162c0c008 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972901] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972908] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] mode changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972911] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] enable changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972914] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] active changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972930] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972935] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972939] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972943] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972947] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972950] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972990] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972993] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.972997] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: n, active: n
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973001] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973085] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973145] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973195] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973246] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973293] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973343] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973391] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973439] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973487] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973536] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973582] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973649] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 332) -> (0 - 502)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973693] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (332 - 340) -> (502 - 510)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973738] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (340 - 672) -> (510 - 1012)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973782] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (672 - 680) -> (1012 - 1020)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973827] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (680 - 1012) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973870] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973878] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.973978] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974348] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974360] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd69288 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974371] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017ab1ae98 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974375] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69288 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974381] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88015cd69288
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974394] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974418] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd69288 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974428] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017801dd28 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974432] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69288 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974438] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88015cd69288
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974455] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88015cd68008 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974460] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68008 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974464] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68008
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974475] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88015cd69038 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974479] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69038 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974483] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69038
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974490] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974521] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd69038 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974530] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017801dd28 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974534] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69038 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974539] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88015cd69038
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974556] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88015cd68948 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974560] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68948 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974564] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68948
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974574] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88015cd68008 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974578] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68008 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974583] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68008
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974593] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88015cd6b538 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974597] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b538 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974601] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b538
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974612] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd69288 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974616] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69288 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974621] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88015cd69288
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974634] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801dd28
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974646] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd69bc8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974655] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017801ca88 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974659] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69bc8 to [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974664] [drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff88015cd69bc8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974681] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88015cd694d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974684] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd694d8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974689] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd694d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974699] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88015cd68258 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974703] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68258 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974707] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68258
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974717] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88015cd6a508 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974721] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6a508 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974725] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6a508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974732] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974786] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6a508 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974796] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017ab8efc8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974800] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6a508 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974805] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88015cd6a508
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974822] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88015cd6b098 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974826] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b098 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974830] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b098
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974840] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88015cd68258 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974844] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68258 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974848] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68258
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974859] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88015cd6bc28 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974863] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6bc28 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974867] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6bc28
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974878] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd694d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974882] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd694d8 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974887] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88015cd694d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974901] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab8efc8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974912] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6b788 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974921] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab8d3d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974925] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b788 to [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974932] [drm:drm_atomic_set_fb_for_plane] Set [FB:109] for plane state ffff88015cd6b788
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974948] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88015cd69bc8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974952] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69bc8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974981] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69bc8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974993] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88015cd69978 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.974997] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69978 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975001] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69978
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975011] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88015cd69288 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975015] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69288 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975020] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69288
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975031] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd68b98 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975038] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68b98 to [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975045] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88015cd68b98
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975064] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab8d3d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975078] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88015cd6b538 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975089] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff8801766a2548 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975096] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b538 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975104] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b538
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975117] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff88015cd6b9d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975124] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b9d8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975131] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b9d8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975143] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff88015cd68008 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975148] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68008 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975156] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68008
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975168] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff88015cd684a8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975173] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd684a8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975180] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd684a8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975190] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff88015cd68948 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975194] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68948 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975199] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68948
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975206] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff8801766a2548
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975223] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88015db581d8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975235] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015db59d08 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975245] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:72:HDMI-A-1] ffff88015db59228 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975256] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88015db58cb8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975260] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015db58cb8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975263] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975270] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] mode changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975276] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] enable changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975282] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] active changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975290] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975296] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975302] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975309] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975313] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975319] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975325] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975330] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975336] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: n, active: n
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975343] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975451] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975497] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975544] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975590] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975635] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975680] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975726] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975770] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975815] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb -1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975860] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975912] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 332) -> (0 - 502)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.975954] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (332 - 340) -> (502 - 510)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.976020] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (340 - 672) -> (510 - 1012)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.976064] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (672 - 680) -> (1012 - 1020)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.976109] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (680 - 1012) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.976156] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.976166] [drm:drm_atomic_nonblocking_commit] committing ffff88015dad9fe8 nonblocking
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978433] [drm:intel_disable_pipe [i915]] disabling pipe C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978535] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978550] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801766a12a8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978556] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801766a12a8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978571] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801758aae98 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978576] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801758aae98
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978589] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d930008 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978594] [drm:drm_atomic_check_only] checking ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978605] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978638] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d930008 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978642] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d930008
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978655] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d936fc8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978660] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d936fc8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978673] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d934a88 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978678] [drm:drm_atomic_check_only] checking ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978692] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6a9a8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978696] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978729] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880175acae98 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978734] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880175acae98
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978748] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686dd28 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978753] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686dd28
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978765] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88016686d3d8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978770] [drm:drm_atomic_check_only] checking ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978782] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6a9a8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978790] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd6b2e8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978799] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd69038 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978808] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff8801764db2e8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978856] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 332) -> (0 - 502)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978904] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (332 - 340) -> (502 - 510)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978946] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (340 - 672) -> (510 - 1012)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.978988] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (672 - 680) -> (1012 - 1020)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.979062] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (680 - 1012) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.979106] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.979113] [drm:drm_atomic_commit] committing ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.982838] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.982917] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983156] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983449] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983840] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983893] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.983941] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.984037] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   96.984107] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.022941] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.023119] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.023585] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.023718] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.039535] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.039636] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.056213] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801764d8de8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.056288] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.056334] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.056376] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801764d8de8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.056423] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.056465] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.072857] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801764d8de8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.072958] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073095] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073687] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073707] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff8801765421d8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073726] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da88958 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073732] [drm:drm_atomic_check_only] checking ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073746] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073754] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.073772] [drm:drm_atomic_commit] committing ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.075847] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.075889] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076432] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076459] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff8801764d8de8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076477] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8efc8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076485] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d8de8 to [CRTC:36:pipe A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076495] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff8801764d8de8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076524] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da89bf8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076531] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015da89bf8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076556] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c2021d8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076562] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c2021d8 to [NOCRTC]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076568] [drm:drm_atomic_check_only] checking ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076576] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076581] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076586] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076592] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076597] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076603] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076609] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076629] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff8801764d8948 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076642] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff8801764d86f8 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076745] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076829] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.076921] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077118] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077193] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077271] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077344] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077373] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff8801764d8008 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077391] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da8dd28 state to ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077465] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 502) -> (0 - 988)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077533] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (502 - 510) -> (988 - 1020)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077602] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077667] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077674] [drm:drm_atomic_nonblocking_commit] committing ffff88015dade4f8 nonblocking
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.077935] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801764db788
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078008] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078087] [drm:intel_disable_pipe [i915]] disabling pipe B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078164] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078222] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078237] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff8801764db788 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078252] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8ca88 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078257] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db788 to [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078263] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801764db788
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078269] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078287] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff8801764d84a8 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078355] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078420] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.078480] [drm:drm_atomic_commit] committing ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.094179] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.094303] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.095236] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.095314] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.095401] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.095479] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.095633] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.095854] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096531] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096614] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096729] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.096809] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.106248] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.106357] [drm:intel_power_well_disable [i915]] disabling power well 2
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.106618] [drm:skl_set_power_well [i915]] Disabling power well 2
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.106759] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.106824] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.106939] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dade4f8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107045] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107097] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107730] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107765] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017ab1a548 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107778] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab1a548
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107806] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab1ae98 state to ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107818] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.107850] [drm:drm_atomic_commit] committing ffff88015dad9fe8
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.110102] [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO underrun
>Jun 28 15:42:51 GLK-2-GLKRVP1DDR405 kernel: [   97.110599] [drm:intel_fbc_underrun_work_fn [i915]] Disabling FBC due to FIFO underrun.
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.122804] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.122885] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.139481] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801764d86f8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.139635] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.139751] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.140869] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.140908] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203058 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.140919] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.140933] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.140942] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.141031] [drm:drm_atomic_commit] committing ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.141136] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.141162] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142300] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142337] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff8801764d86f8 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142366] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017801ca88 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142379] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d86f8 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142394] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff8801764d86f8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142450] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801766a2548 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142465] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801766a2548
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142507] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203228 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142519] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203228 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142529] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142542] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142551] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142560] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142578] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142590] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] using [ENCODER:67:DDI B] on [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142599] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142611] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142642] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff8801764d8948 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142664] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff8801764db9d8 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142678] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142818] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.142944] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.143156] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.143294] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.143430] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.143562] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.143699] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.143830] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.143962] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144127] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144253] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144275] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144399] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144416] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144543] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144665] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144791] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.144913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145036] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145197] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145264] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145333] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145398] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145465] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145529] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145596] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145661] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] FB:110, fb = 64x64 format = AR24 little-endian (0x34325241)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145725] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145801] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145872] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.145941] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146007] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146105] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146173] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146241] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146320] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146388] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146405] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146459] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff8801764db9d8 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146478] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801758aae98 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146484] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db9d8 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146496] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff8801764db9d8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146525] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d934a88 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146532] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d934a88
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146545] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146586] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff8801764db9d8 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146599] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d934a88 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146606] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db9d8 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146614] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff8801764db9d8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146640] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d936fc8 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146647] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d936fc8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146665] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203228 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146671] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203228 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146676] [drm:drm_atomic_check_only] checking ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146682] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146687] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146692] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146701] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146707] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] using [ENCODER:67:DDI B] on [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146713] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146720] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146736] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff8801764d8948 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146749] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff8801764dbc28 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146756] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146826] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146890] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.146958] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147061] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147130] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147201] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147270] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147338] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147404] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147470] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147536] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147549] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147614] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147623] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147690] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147757] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147825] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147890] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.147956] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148049] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148116] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148184] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148251] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148318] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148384] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148450] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148516] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] FB:110, fb = 64x64 format = AR24 little-endian (0x34325241)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148582] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148657] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148725] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148791] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148856] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148921] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.148986] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149082] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149154] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149222] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149242] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff8801764d86f8 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149259] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d930008 state to ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149330] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 988) -> (0 - 502)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149395] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (988 - 1020) -> (502 - 510)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149459] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (510 - 1012)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149520] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149527] [drm:drm_atomic_nonblocking_commit] committing ffff88015dad9fe8 nonblocking
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149722] [drm:intel_power_well_enable [i915]] enabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149727] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff8801764db2e8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149794] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149856] [drm:skl_set_power_well [i915]] Enabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149921] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.149982] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150071] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150087] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834cde8 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150102] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686d3d8 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150111] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834cde8 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150116] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834cde8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150121] [drm:drm_atomic_check_only] checking ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150189] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150257] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150279] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017834ebf8 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150348] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (510 - 1012)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150412] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150419] [drm:drm_atomic_commit] committing ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.150989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.151104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.151162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.151220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.151276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.151333] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.151412] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.151467] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.156180] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.156241] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.157218] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.157273] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.157327] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.157434] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.157985] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.158075] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.158750] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.158800] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.159306] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.159358] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.160304] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.160362] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.160884] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.160936] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.161837] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.161911] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.162466] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.162530] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.162642] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.162703] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.163254] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.163318] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.163409] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.163473] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.163540] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.163603] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.163663] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.164213] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.164276] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.164446] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.164505] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.165055] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.165126] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.165811] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.165912] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.166466] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.166528] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.166592] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.166653] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.167202] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.167263] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.167334] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.167401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.167464] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.167553] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.168129] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.168191] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.168662] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.168721] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.169222] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.169284] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.170258] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.170329] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.170856] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.170920] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.170985] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.171079] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.171647] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.171693] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.171764] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.174129] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.174194] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.174244] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.174752] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.174799] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.175659] [drm:intel_enable_pipe [i915]] enabling pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.175917] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.175975] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.176164] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.192741] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.192817] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.192823] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad9fe8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.192862] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.193404] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.193429] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88016686e678 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.193439] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686e678
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.193458] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab8efc8 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.193465] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab8efc8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.193472] [drm:drm_atomic_check_only] checking ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.193497] [drm:drm_atomic_commit] committing ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.209385] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.209462] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.222739] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834f788
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.222852] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.222932] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.223684] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.223709] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203b38 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.223727] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8ca88 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.223734] [drm:drm_atomic_check_only] checking ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.223751] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.223759] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.223781] [drm:drm_atomic_commit] committing ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226044] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226089] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226762] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226793] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017834f788 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226812] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8efc8 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226820] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f788 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226830] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88017834f788
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226862] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da88958 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226870] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015da88958
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226896] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c202918 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226903] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c202918 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226909] [drm:drm_atomic_check_only] checking ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226918] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226924] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226929] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226935] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226940] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226947] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.226953] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227041] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017834f098 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227057] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834c4a8 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227268] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227349] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227508] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227589] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227665] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227692] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017834de18 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227710] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da8dd28 state to ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227790] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 502) -> (0 - 988)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227863] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (502 - 510) -> (988 - 1020)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.227939] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228011] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228046] [drm:drm_atomic_nonblocking_commit] committing ffff88015dadafd8 nonblocking
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228335] [drm:intel_disable_pipe [i915]] disabling pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228342] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834f538
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228435] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228525] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228593] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228611] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834f538 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228629] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da88008 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228636] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f538 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228643] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834f538
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228650] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228664] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228690] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228746] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228763] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834f538 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228780] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff880175acae98 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228787] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f538 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228794] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834f538
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228801] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228824] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017834c6f8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228910] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.228993] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.229039] [drm:drm_atomic_commit] committing ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.243549] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.243607] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244128] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244183] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244244] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244294] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244360] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244596] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244858] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.244955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.245044] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.245102] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.245176] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.245227] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256140] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256216] [drm:intel_power_well_disable [i915]] disabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256300] [drm:skl_set_power_well [i915]] Disabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256400] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256449] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256530] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadafd8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256551] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.256590] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.257239] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.257264] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801780192a8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.257273] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801780192a8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.257293] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801766a2548 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.257302] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.257326] [drm:drm_atomic_commit] committing ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.272548] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.272600] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.289362] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834c4a8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.289492] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.289588] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290515] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290545] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203798 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290553] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290564] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290572] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290583] [drm:drm_atomic_commit] committing ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290695] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.290717] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291453] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291487] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017834c4a8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291512] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017ab1ae98 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291523] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834c4a8 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291537] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88017834c4a8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291586] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab1a548 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291598] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab1a548
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291636] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203058 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291646] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203058 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291655] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291666] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291674] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291682] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291698] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291710] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] using [ENCODER:67:DDI B] on [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291721] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291731] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291760] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017834f098 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291781] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834c258 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291794] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.291917] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292032] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292205] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292328] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292445] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292563] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292682] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.292917] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293029] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293177] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293199] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293310] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293330] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293442] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293555] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293668] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293776] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.293890] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294010] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294174] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294294] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294404] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294514] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294622] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294731] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294840] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] FB:110, fb = 64x64 format = AR24 little-endian (0x34325241)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.294951] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295123] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295245] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295359] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295477] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295587] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295700] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295807] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.295924] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296034] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296118] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017834cde8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296149] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d936fc8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296268] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 988) -> (0 - 502)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296373] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (988 - 1020) -> (502 - 510)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296479] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (510 - 1012)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296580] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296591] [drm:drm_atomic_nonblocking_commit] committing ffff88015dadba78 nonblocking
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296901] [drm:intel_power_well_enable [i915]] enabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.296908] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834d038
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297023] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297122] [drm:skl_set_power_well [i915]] Enabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297233] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297313] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297334] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834d038 state to ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297355] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d930008 state to ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297364] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834d038 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297373] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834d038
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297381] [drm:drm_atomic_check_only] checking ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297495] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297604] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297635] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017834e758 state to ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297744] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (510 - 1012)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297846] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.297857] [drm:drm_atomic_commit] committing ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298346] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298850] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298927] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.298981] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.306121] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.306179] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.306364] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.306415] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.306467] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.306517] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.307057] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.307109] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.307771] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.307854] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.308407] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.308456] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.308507] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.308555] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309062] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309114] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309242] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309347] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309396] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.309957] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.310053] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.310210] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.310258] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.310737] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.310786] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.311528] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.311600] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.312158] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.312246] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.312320] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.312387] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.312947] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.313055] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.313141] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.313221] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.313340] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.313410] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.313956] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.314051] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.314528] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.314591] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.315099] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.315165] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.316186] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.316261] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.316797] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.316862] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.316930] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.316993] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.317627] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.317700] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.317780] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.320172] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.320258] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.320327] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.320902] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.320996] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.322168] [drm:intel_enable_pipe [i915]] enabling pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.322522] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.322603] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.322757] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.339229] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.339271] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.339332] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadd508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.339338] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.340141] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.340168] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88016686e678 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.340178] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686e678
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.340500] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab8efc8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.340509] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab8efc8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.340516] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.340543] [drm:drm_atomic_commit] committing ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.355741] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.355792] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.372559] [drm:drm_atomic_set_fb_for_plane] Set [FB:110] for plane state ffff88017834f538
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.372666] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.372740] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.373676] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.373699] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c202918 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.373716] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8dd28 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.373723] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.373739] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.373747] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.373767] [drm:drm_atomic_commit] committing ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.389202] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.389246] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.389907] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.389938] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017834f538 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390052] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da88008 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390062] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f538 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390073] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88017834f538
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390112] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8efc8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390122] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015da8efc8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390155] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203798 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390163] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203798 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390169] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390179] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390186] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390191] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390198] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390204] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390211] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390219] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390236] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390291] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017834f538 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390309] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8efc8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390318] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f538 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390329] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88017834f538
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390364] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da89bf8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390371] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015da89bf8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390384] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390429] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017834f538 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390445] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da89bf8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390453] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f538 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390463] [drm:drm_atomic_set_fb_for_plane] Set [FB:62] for plane state ffff88017834f538
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390494] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da88958 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390503] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015da88958
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390523] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015c203798 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390530] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015c203798 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390536] [drm:drm_atomic_check_only] checking ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390544] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390550] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390555] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390561] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390567] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390573] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390581] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390602] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017834c6f8 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390619] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834e508 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390840] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 62
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.390925] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391012] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 109
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391146] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391236] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 110
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391321] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391352] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017834c258 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391373] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da88008 state to ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391467] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 502) -> (0 - 988)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391550] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (502 - 510) -> (988 - 1020)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391627] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391704] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.391716] [drm:drm_atomic_nonblocking_commit] committing ffff88015dadba78 nonblocking
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.392008] [drm:intel_disable_pipe [i915]] disabling pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.406071] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.406120] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.406611] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.406675] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.406728] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.406775] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.406835] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407043] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407422] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407474] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407542] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.407592] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415615] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415635] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017598f098 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415649] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017801dd28 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415657] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017598d4d8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415660] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598d4d8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415663] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598d4d8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415671] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017598cde8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415673] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598cde8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415675] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598cde8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415683] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88017598d288 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415685] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598d288 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415687] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598d288
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415695] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017598d038 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415697] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598d038 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415699] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598d038
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415708] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017598e068 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415717] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801780192a8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415724] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88017598ee48 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415726] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598ee48 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415728] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598ee48
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415735] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88017598de18 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415738] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598de18 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415740] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598de18
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415747] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88017598dbc8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415749] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598dbc8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415752] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017598dbc8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415762] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff880163bd7788 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415764] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd7788 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415766] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd7788
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415774] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880163bd72e8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415783] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff880163bd6508 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415785] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd6508 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415787] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd6508
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415794] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff880163bd6758 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415796] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd6758 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415798] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd6758
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415806] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff880163bd69a8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415809] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd69a8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415811] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd69a8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415818] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff880163bd5e18 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415820] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd5e18 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415822] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd5e18
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415846] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801dd28
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415848] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598f098 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415852] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88017598f098
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415856] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415888] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff8801786375c8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415900] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786375c8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415903] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786375c8 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415912] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff8801780192a8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415914] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017598e068 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415917] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88017598e068
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415920] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415932] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880178637968 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415935] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178637968 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415945] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88017801ca88 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415952] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801ca88
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415971] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd72e8 to [CRTC:58:pipe C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415974] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880163bd72e8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415977] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415988] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880178637b38 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415991] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178637b38 to [CRTC:58:pipe C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.415993] [drm:drm_atomic_check_only] checking ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416000] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416003] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416005] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416007] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] mode changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416009] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] enable changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416011] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] active changed
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416021] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416024] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416027] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416030] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] using [ENCODER:67:DDI B] on [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416033] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416036] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] using [ENCODER:74:DDI C] on [CRTC:58:pipe C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416038] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416041] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416047] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: y, active: y
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416050] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416058] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416125] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416226] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416273] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416317] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416368] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416416] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416463] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416552] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416594] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416601] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416643] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416647] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416690] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416733] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416777] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416819] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416862] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416913] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.416956] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417028] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:109, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417071] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417116] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417159] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417201] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417244] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] FB:110, fb = 64x64 format = AR24 little-endian (0x34325241)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417287] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-128+-128 dst 128x128+-128+-128
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417293] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417340] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417383] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417433] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417476] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417566] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417608] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417651] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417692] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417696] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417738] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417742] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417785] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417827] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417871] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417913] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.417954] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418016] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418058] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418100] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418142] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418184] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418225] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418267] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418409] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418454] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb -1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418496] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418540] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418583] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418626] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418668] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418721] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418765] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418814] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418857] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418918] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 988) -> (0 - 332)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.418958] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (988 - 1020) -> (332 - 340)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.419014] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (340 - 672)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.419054] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (672 - 680)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.419094] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (0 - 0) -> (680 - 1012)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.419134] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.419136] [drm:drm_atomic_commit] committing ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.422492] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.422542] [drm:intel_power_well_disable [i915]] disabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.422602] [drm:skl_set_power_well [i915]] Disabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.422672] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.422709] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.422765] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadba78
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.423319] [drm:intel_power_well_enable [i915]] enabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.423379] [drm:skl_set_power_well [i915]] Enabling power well 2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.423480] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424070] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424534] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424612] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.424658] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.439347] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.439401] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.440261] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.440306] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.440381] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.440438] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.441061] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.441104] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.441766] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.441808] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.442336] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.442397] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.442442] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.442484] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.442977] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443057] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443125] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443168] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443218] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443262] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443304] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443867] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.443928] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.444821] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.444872] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.445419] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.445479] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.446432] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.446479] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.447030] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.447120] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.447270] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.447311] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.447823] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.447883] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.448819] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.448869] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.449421] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.449490] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.449563] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.449629] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.450216] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.450284] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.450366] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.450441] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.450536] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.450603] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.451131] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.451175] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.451636] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.451679] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.452159] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.452203] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.453166] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.453218] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.453732] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.453777] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.453851] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.453894] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.454423] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.454468] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.454521] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.456873] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.456934] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.456981] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.457550] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.457595] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.458567] [drm:intel_enable_pipe [i915]] enabling pipe B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.458865] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.458937] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.459114] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.459158] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.460114] [drm:intel_enable_pipe [i915]] enabling pipe C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.478275] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.478364] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.478652] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.478847] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.479055] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.479200] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.479379] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.479543] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.479914] Console: switching to colour frame buffer device 240x67
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.497823] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.497909] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff880163bd5bc8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.497923] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d936fc8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.497934] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff880163bd4008 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.497938] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd4008 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.497942] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd4008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.497950] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff880163bd7c28 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498261] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd7c28 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498264] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd7c28
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498274] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff880163bd62b8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498278] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd62b8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498283] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd62b8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498291] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff880163bd4258 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498295] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd4258 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498298] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd4258
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498307] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff880163bd7098 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498317] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d934a88 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498326] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff880163bd6068 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498329] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd6068 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498333] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd6068
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498341] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff880163bd6bf8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498344] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd6bf8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498349] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd6bf8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498357] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff880163bd5978 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498360] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd5978 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498364] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd5978
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498372] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff880163bd4b98 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498375] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd4b98 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498378] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd4b98
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498386] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff880163bd6e48 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498396] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d930008 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498404] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff880163bd46f8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498407] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd46f8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498410] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd46f8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498419] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff880163bd5288 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498422] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd5288 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498425] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880163bd5288
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498435] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff880179ef8b98 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498438] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880179ef8b98 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498442] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880179ef8b98
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498450] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff880179efb2e8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498453] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880179efb2e8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498457] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880179efb2e8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498482] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d936fc8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498487] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd5bc8 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498491] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880163bd5bc8
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498496] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498530] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880178636748 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498552] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178636748 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498557] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178636748 to [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498568] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d934a88
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498571] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd7098 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498575] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880163bd7098
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498580] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498591] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880178637d08 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498596] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178637d08 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498601] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178637d08 to [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498611] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d930008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498614] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880163bd6e48 to [CRTC:58:pipe C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498618] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff880163bd6e48
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498623] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498635] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff8801786361d8 state to ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498639] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786361d8 to [NOCRTC]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498644] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786361d8 to [CRTC:58:pipe C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498647] [drm:drm_atomic_check_only] checking ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498662] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498667] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498671] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498675] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498678] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498682] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498758] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498806] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498854] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498901] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498948] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.498993] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.499042] [drm:drm_atomic_commit] committing ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.511007] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dad8008
>Jun 28 15:42:52 GLK-2-GLKRVP1DDR405 kernel: [   97.511195] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dad8008
>Jun 28 15:42:54 GLK-2-GLKRVP1DDR405 kernel: [   99.586575] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>Jun 28 15:42:54 GLK-2-GLKRVP1DDR405 kernel: [   99.586765] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>Jun 28 15:42:54 GLK-2-GLKRVP1DDR405 kernel: [   99.586876] [drm:intel_power_well_disable [i915]] disabling AUX A
>Jun 28 15:42:54 GLK-2-GLKRVP1DDR405 kernel: [   99.586986] [drm:skl_set_power_well [i915]] Disabling AUX A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.297823] Console: switching to colour dummy device 80x25
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.336878] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.336969] [drm:intel_dp_detect [i915]] [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337073] [drm:intel_power_well_enable [i915]] enabling AUX A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337155] [drm:skl_set_power_well [i915]] Enabling AUX A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337234] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337305] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337369] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337434] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337531] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.337603] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.338123] [drm:drm_dp_read_desc] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.338892] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.338906] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:60:eDP-1] probed modes :
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.338913] [drm:drm_mode_debug_printmodeline] Modeline 61:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.339318] [drm:drm_atomic_state_init] Allocated atomic state ffff88017ab16a48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.339331] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880176610ae8 state to ffff88017ab16a48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.339341] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da88008 state to ffff88017ab16a48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.339345] [drm:drm_atomic_check_only] checking ffff88017ab16a48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.339355] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.339360] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.339373] [drm:drm_atomic_commit] committing ffff88017ab16a48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.340345] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88017ab16a48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.340379] [drm:__drm_atomic_state_free] Freeing atomic state ffff88017ab16a48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.340459] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.340535] [drm:intel_dp_detect [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.340585] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.340634] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.341773] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.342768] [drm:intel_dp_detect [i915]] Display Port TPS3 support: source yes, sink no
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.342816] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 243000, 270000, 324000, 432000, 540000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.342860] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.342903] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.343994] [drm:drm_dp_read_desc] DP sink: OUI 00-e0-4c dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.344039] [drm:intel_dp_detect [i915]] Sink is not MST capable
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.353926] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.353987] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354130] [drm:drm_edid_to_eld] ELD: no CEA Extension found
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354190] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:68:DP-1] probed modes :
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354196] [drm:drm_mode_debug_printmodeline] Modeline 78:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354201] [drm:drm_mode_debug_printmodeline] Modeline 81:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354205] [drm:drm_mode_debug_printmodeline] Modeline 86:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354210] [drm:drm_mode_debug_printmodeline] Modeline 80:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354214] [drm:drm_mode_debug_printmodeline] Modeline 79:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354219] [drm:drm_mode_debug_printmodeline] Modeline 87:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354223] [drm:drm_mode_debug_printmodeline] Modeline 88:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354227] [drm:drm_mode_debug_printmodeline] Modeline 89:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354232] [drm:drm_mode_debug_printmodeline] Modeline 82:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354236] [drm:drm_mode_debug_printmodeline] Modeline 83:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354240] [drm:drm_mode_debug_printmodeline] Modeline 84:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354244] [drm:drm_mode_debug_printmodeline] Modeline 85:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354624] [drm:drm_atomic_state_init] Allocated atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354639] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880179f161d8 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354653] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da8dd28 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354657] [drm:drm_atomic_check_only] checking ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354666] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354671] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.354685] [drm:drm_atomic_commit] committing ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.359136] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.359172] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.359261] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.359332] [drm:intel_hdmi_detect [i915]] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.361776] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.361825] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.364206] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.364223] [drm:drm_do_probe_ddc_edid] drm: skipping non-existent adapter i915 gmbus dpb
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.366642] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.366690] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369159] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369177] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369186] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:72:HDMI-A-1] disconnected
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369591] [drm:drm_atomic_state_init] Allocated atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369605] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:72:HDMI-A-1] ffff880177f2bd08 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369609] [drm:drm_atomic_check_only] checking ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369614] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369618] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369624] [drm:drm_atomic_commit] committing ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369672] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369682] [drm:__drm_atomic_state_free] Freeing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369728] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.369782] [drm:intel_hdmi_detect [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.455966] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.456103] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.458644] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.458664] [drm:drm_dp_dual_mode_detect] DP dual mode HDMI ID:  (err -6)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.458675] [drm:drm_rgb_quant_range_selectable] CEA VCDB 0x2b
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459057] [drm:drm_add_edid_modes] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459063] [drm:drm_edid_to_eld] ELD monitor HP E232
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459069] [drm:drm_edid_to_eld] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459074] [drm:drm_edid_to_eld] ELD size 28, SAD count 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459259] [drm:drm_helper_probe_single_connector_modes] [CONNECTOR:75:HDMI-A-2] probed modes :
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459268] [drm:drm_mode_debug_printmodeline] Modeline 91:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459275] [drm:drm_mode_debug_printmodeline] Modeline 113:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459281] [drm:drm_mode_debug_printmodeline] Modeline 93:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459287] [drm:drm_mode_debug_printmodeline] Modeline 98:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459293] [drm:drm_mode_debug_printmodeline] Modeline 97:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459300] [drm:drm_mode_debug_printmodeline] Modeline 101:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459306] [drm:drm_mode_debug_printmodeline] Modeline 99:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459312] [drm:drm_mode_debug_printmodeline] Modeline 100:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459318] [drm:drm_mode_debug_printmodeline] Modeline 94:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459324] [drm:drm_mode_debug_printmodeline] Modeline 115:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459332] [drm:drm_mode_debug_printmodeline] Modeline 95:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459337] [drm:drm_mode_debug_printmodeline] Modeline 104:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459343] [drm:drm_mode_debug_printmodeline] Modeline 102:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459349] [drm:drm_mode_debug_printmodeline] Modeline 111:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459355] [drm:drm_mode_debug_printmodeline] Modeline 116:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459362] [drm:drm_mode_debug_printmodeline] Modeline 96:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459368] [drm:drm_mode_debug_printmodeline] Modeline 117:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459374] [drm:drm_mode_debug_printmodeline] Modeline 103:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459872] [drm:drm_atomic_state_init] Allocated atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459892] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880177f2a748 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459908] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da8efc8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459913] [drm:drm_atomic_check_only] checking ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459926] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459933] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.459953] [drm:drm_atomic_commit] committing ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.461112] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.461158] [drm:__drm_atomic_state_free] Freeing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.462324] [drm:drm_atomic_state_init] Allocated atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.462348] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880177f2b968 state to ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.462366] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8ca88 state to ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.462373] [drm:drm_atomic_check_only] checking ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.462390] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.462398] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.462418] [drm:drm_atomic_commit] committing ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.473541] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.473588] [drm:__drm_atomic_state_free] Freeing atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.473914] [drm:drm_mode_addfb2] [FB:77]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.557219] [drm:drm_atomic_state_init] Allocated atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.557237] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880177f2a578 state to ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.557250] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff880175acae98 state to ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.557254] [drm:drm_atomic_check_only] checking ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.557266] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.557271] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.557286] [drm:drm_atomic_commit] committing ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.558815] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.558846] [drm:__drm_atomic_state_free] Freeing atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.559127] [drm:drm_mode_addfb2] [FB:112]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.587873] [drm:drm_mode_addfb2] [FB:114]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588589] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588610] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583cb98 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588623] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff8801780192a8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588628] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cb98 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588635] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583cb98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588654] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583e9a8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588658] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583e9a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588663] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583e9a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588674] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017583c258 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588678] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c258 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588682] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c258
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588691] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588721] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583c258 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588731] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017ab1a548 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588735] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c258 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588740] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583c258
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588757] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583f788 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588761] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f788 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588765] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583f788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588771] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588795] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583f788 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588804] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d9312a8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588808] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f788 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588813] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583f788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588830] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583d038 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588833] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d038 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588838] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588848] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017583c258 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588851] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c258 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588856] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c258
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588867] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88017583c948 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588870] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c948 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588875] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c948
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588886] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017583e9a8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588890] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583e9a8 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588895] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88017583e9a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588909] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d9312a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588922] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017583fc28 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588933] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d934a88 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588937] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583fc28 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588942] [drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88017583fc28
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588992] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88017583cb98 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.588998] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cb98 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589002] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583cb98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589013] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88017583dbc8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589019] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583dbc8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589027] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583dbc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589042] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88017583d728 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589048] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d728 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589055] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d728
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589065] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589120] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583d728 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589130] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d934a88 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589133] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d728 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589139] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583d728
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589156] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583c6f8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589160] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c6f8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589164] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c6f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589175] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017583dbc8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589179] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583dbc8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589187] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583dbc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589200] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88017583c4a8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589204] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c4a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589209] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c4a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589220] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017583cb98 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589225] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cb98 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589232] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88017583cb98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589245] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d934a88
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589258] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017583f2e8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589267] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d936fc8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589273] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f2e8 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589278] [drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88017583f2e8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589295] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88017583fc28 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589299] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583fc28 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589304] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583fc28
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589314] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88017583d4d8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589318] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d4d8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589322] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d4d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589333] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88017583e9a8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589337] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583e9a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589341] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583e9a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589352] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017583e758 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589356] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583e758 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589361] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88017583e758
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589374] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d936fc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589385] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88017583c948 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589395] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d9312a8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589400] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c948 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589404] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c948
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589416] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff88017583ebf8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589419] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583ebf8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589424] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583ebf8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589434] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff88017583c258 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589438] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c258 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589442] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c258
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589453] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff88017583cde8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589457] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cde8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589461] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583cde8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589472] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff88017583d038 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589475] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d038 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589480] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589486] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015d9312a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589504] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880177f2bb38 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589516] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880177f2a008 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589528] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:72:HDMI-A-1] ffff880177f2a1d8 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589540] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff880160dabb38 state to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589545] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880160dabb38 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589548] [drm:drm_atomic_check_only] checking ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589556] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589560] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589563] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589573] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589578] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589582] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589586] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589591] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589594] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589597] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589600] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589604] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: n, active: n
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589608] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589686] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589742] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 77
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589789] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589837] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589884] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589931] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 112
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.589976] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590051] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590099] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590149] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590196] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590255] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 332) -> (0 - 502)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590299] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (332 - 340) -> (502 - 510)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590344] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (340 - 672) -> (510 - 1012)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590388] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (672 - 680) -> (1012 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590432] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (680 - 1012) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590476] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590484] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590566] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dadea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590904] [drm:drm_atomic_state_init] Allocated atomic state ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590917] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583d038 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590927] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d9312a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590931] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d038 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590937] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583d038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590977] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583f788 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590982] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f788 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590988] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583f788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.590999] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017583cde8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591003] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cde8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591008] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583cde8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591020] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88017583d728 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591023] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d728 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591028] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d728
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591035] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591066] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583d728 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591075] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d9312a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591081] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d728 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591086] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583d728
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591104] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583c6f8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591110] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c6f8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591118] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c6f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591124] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591148] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583c6f8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591158] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d9312a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591164] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c6f8 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591172] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583c6f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591189] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583dbc8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591193] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583dbc8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591198] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583dbc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591211] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017583d728 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591215] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d728 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591220] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d728
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591232] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88017583c4a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591236] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c4a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591241] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c4a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591253] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017583cde8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591257] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cde8 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591264] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88017583cde8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591278] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d9312a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591291] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017583cb98 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591301] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d930008 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591305] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cb98 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591312] [drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88017583cb98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591330] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88017583f788 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591334] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f788 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591338] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583f788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591348] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88017583f2e8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591352] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f2e8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591356] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583f2e8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591366] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88017583d038 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591371] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d038 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591376] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591382] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591432] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583d038 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591441] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d930008 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591445] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d038 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591450] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88017583d038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591467] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88017583c258 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591471] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c258 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591475] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c258
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591486] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88017583f2e8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591490] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f2e8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591494] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583f2e8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591505] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88017583ebf8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591508] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583ebf8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591512] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583ebf8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591523] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88017583f788 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591527] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583f788 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591532] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88017583f788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591545] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d930008
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591556] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88017583c948 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591565] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d934a88 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591568] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c948 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591574] [drm:drm_atomic_set_fb_for_plane] Set [FB:112] for plane state ffff88017583c948
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591590] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88017583cb98 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591594] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cb98 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591599] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583cb98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591608] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88017583e758 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591612] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583e758 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591616] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583e758
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591626] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88017583cde8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591630] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583cde8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591634] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583cde8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591644] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017583e9a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591648] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583e9a8 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591654] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88017583e9a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591666] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d934a88
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591677] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88017583c4a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591686] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d9312a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591690] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583c4a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591695] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583c4a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591704] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff88017583d4d8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591709] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d4d8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591714] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d4d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591723] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff88017583d728 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591727] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583d728 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591732] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583d728
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591741] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff88017583fc28 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591745] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583fc28 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591749] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583fc28
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591758] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff88017583dbc8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591762] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017583dbc8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591766] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017583dbc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591772] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015d9312a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591787] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880160daa3a8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591798] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880160daacb8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591810] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:72:HDMI-A-1] ffff88017714fb38 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591820] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88017714f5c8 state to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591826] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88017714f5c8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591829] [drm:drm_atomic_check_only] checking ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591833] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591837] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591840] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591847] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591851] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591854] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591858] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591862] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591865] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591869] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591872] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591876] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: n, active: n
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591880] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591932] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.591980] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 77
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592050] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592098] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592146] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592193] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 112
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592241] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592287] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592333] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592381] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592427] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592479] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 332) -> (0 - 502)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592523] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (332 - 340) -> (502 - 510)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592569] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (340 - 672) -> (510 - 1012)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592613] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (672 - 680) -> (1012 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592657] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (680 - 1012) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592700] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.592708] [drm:drm_atomic_nonblocking_commit] committing ffff88015dade4f8 nonblocking
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.593994] [drm:drm_atomic_state_init] Allocated atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594008] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d936fc8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594013] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015d936fc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594028] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686e678 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594033] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686e678
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594045] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88016686dd28 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594051] [drm:drm_atomic_check_only] checking ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594063] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88017583c6f8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594077] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd68de8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594087] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd69e18 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594091] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594133] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88016686dd28 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594137] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686dd28
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594150] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686d3d8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594154] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686d3d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594166] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88016686e678 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594171] [drm:drm_atomic_check_only] checking ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594178] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594203] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017ab8efc8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594209] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab8efc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594222] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab8d3d8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594226] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab8d3d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594242] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da8dd28 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594247] [drm:drm_atomic_check_only] checking ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594258] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd69e18 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594268] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd6a508 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594277] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd68de8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594286] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd694d8 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594334] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 332) -> (0 - 502)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594376] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (332 - 340) -> (502 - 510)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594421] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (340 - 672) -> (510 - 1012)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594463] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (672 - 680) -> (1012 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594505] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (680 - 1012) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594546] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594550] [drm:drm_atomic_commit] committing ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.594760] [drm:intel_disable_pipe [i915]] disabling pipe C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.611791] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.611895] [drm:skl_set_power_well [i915]] Disabling DDI C IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.611981] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL C (active 4, on? 1) for crtc 58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612277] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612852] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:72:HDMI-A-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.612966] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.613086] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.613194] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.613322] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.656796] [drm:intel_power_well_disable [i915]] disabling dpio-common-c
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.656910] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.657090] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.657257] [drm:__drm_atomic_state_free] Freeing atomic state ffff88015dade4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.673399] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.673527] [drm:__drm_atomic_state_free] Freeing atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.690097] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd6a068
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.690227] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.690322] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.690402] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd6a068
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.690497] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.690585] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.706732] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd6a068
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.706862] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.706957] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.707835] [drm:drm_atomic_state_init] Allocated atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.707863] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0ccb8 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.707885] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801758aae98 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.707892] [drm:drm_atomic_check_only] checking ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.707912] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.707922] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.707948] [drm:drm_atomic_commit] committing ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.708841] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.708890] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710084] [drm:drm_atomic_state_init] Allocated atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710121] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6a068 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710146] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017801dd28 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710157] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6a068 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710171] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88015cd6a068
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710218] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab1a548 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710229] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88017ab1a548
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710266] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0d3f8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710276] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880162c0d3f8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710285] [drm:drm_atomic_check_only] checking ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710297] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710305] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710313] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710321] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710329] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710339] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710349] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710381] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6a2b8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710402] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd6b788 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710551] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710677] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 77
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710791] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.710903] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 112
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711012] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711191] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711306] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711351] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd686f8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711380] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d9312a8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711498] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 502) -> (0 - 988)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711608] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (502 - 510) -> (988 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711712] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711814] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.711828] [drm:drm_atomic_nonblocking_commit] committing ffff88016395da58 nonblocking
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712224] [drm:intel_disable_pipe [i915]] disabling pipe B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712230] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd68b98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712309] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712389] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712453] [drm:drm_atomic_state_init] Allocated atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712469] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd68b98 state to ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712484] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d934a88 state to ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712491] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68b98 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712496] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd68b98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712502] [drm:drm_atomic_check_only] checking ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712522] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6a9a8 state to ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712595] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712665] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.712673] [drm:drm_atomic_commit] committing ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.725698] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.725781] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.726334] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.726411] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.726497] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.726623] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.726721] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.726940] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727678] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727763] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727866] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.727943] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740203] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740313] [drm:intel_power_well_disable [i915]] disabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740435] [drm:skl_set_power_well [i915]] Disabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740576] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740639] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740759] [drm:__drm_atomic_state_free] Freeing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740784] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.740838] [drm:__drm_atomic_state_free] Freeing atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.741552] [drm:drm_atomic_state_init] Allocated atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.741589] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88016686e678 state to ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.741601] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686e678
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.741630] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686dd28 state to ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.741642] [drm:drm_atomic_check_only] checking ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.741676] [drm:drm_atomic_commit] committing ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.756675] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.756761] [drm:__drm_atomic_state_free] Freeing atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.773341] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd6b788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.773482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.773587] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.774850] [drm:drm_atomic_state_init] Allocated atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.774882] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0db38 state to ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.774891] [drm:drm_atomic_check_only] checking ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.774903] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.774911] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.774922] [drm:drm_atomic_commit] committing ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775092] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775114] [drm:__drm_atomic_state_free] Freeing atomic state ffff88017ab15a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775779] [drm:drm_atomic_state_init] Allocated atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775809] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6b788 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775852] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015da8ca88 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775866] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b788 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775881] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88015cd6b788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775937] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da89bf8 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.775952] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015da89bf8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776074] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0c008 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776087] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880162c0c008 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776104] [drm:drm_atomic_check_only] checking ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776121] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776133] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776148] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776171] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776183] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] using [ENCODER:67:DDI B] on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776193] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776204] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776238] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6a2b8 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776263] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd6b2e8 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776282] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776431] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776560] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776699] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776829] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.776955] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777142] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777279] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777410] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777542] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777664] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777785] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777802] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777922] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.777939] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778065] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778224] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778301] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778381] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778457] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778544] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778621] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778697] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:112, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778772] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778847] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778921] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.778995] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779101] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] FB:114, fb = 64x64 format = AR24 little-endian (0x34325241)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779181] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-192+-192 dst 192x192+-192+-192
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779271] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779354] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 77
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779430] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779506] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 112
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779582] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779658] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779732] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779817] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779893] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779917] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd694d8 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.779937] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da88008 state to ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780023] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 988) -> (0 - 502)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780128] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (988 - 1020) -> (502 - 510)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780202] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (510 - 1012)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780277] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780287] [drm:drm_atomic_nonblocking_commit] committing ffff880177024a68 nonblocking
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780495] [drm:intel_power_well_enable [i915]] enabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780578] [drm:skl_set_power_well [i915]] Enabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780583] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd69038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780663] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780734] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780811] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.780941] [drm:drm_atomic_state_init] Allocated atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781027] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd69038 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781045] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff8801766a2548 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781050] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69038 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781055] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd69038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781140] [drm:drm_atomic_check_only] checking ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781214] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781292] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781442] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781594] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781598] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6b098 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781674] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (510 - 1012)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781747] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781818] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781888] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.781898] [drm:drm_atomic_commit] committing ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.790157] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.790242] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.790460] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.790537] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.790614] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.790690] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.791258] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.791335] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.792061] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.792130] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.792653] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.792717] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.792785] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.792848] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.793415] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.793506] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.793600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.793668] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.793738] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.793804] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.793867] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.794417] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.794482] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.794706] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.794769] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.795276] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.795341] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.796350] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.796424] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.796961] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.797076] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.797152] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.797216] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.797771] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.797835] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.797912] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.797986] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.798097] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.798165] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.798713] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.798777] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.799247] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.799310] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.799811] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.799875] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.800767] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.800844] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.801358] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.801403] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.801451] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.801494] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.802081] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.802136] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.802191] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.804529] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.804592] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.804641] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.805161] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.805209] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.805993] [drm:intel_enable_pipe [i915]] enabling pipe B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.806233] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.806289] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.806475] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823078] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823110] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823144] [drm:__drm_atomic_state_free] Freeing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823150] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177024a68
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823562] [drm:drm_atomic_state_init] Allocated atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823581] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88017ab8d3d8 state to ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823587] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017ab8d3d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823604] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017801dd28 state to ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823609] [drm:drm_atomic_set_mode_prop_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88017801dd28
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823614] [drm:drm_atomic_check_only] checking ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.823633] [drm:drm_atomic_commit] committing ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.839704] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.839755] [drm:__drm_atomic_state_free] Freeing atomic state ffff880176b45a58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.856508] [drm:drm_atomic_set_fb_for_plane] Set [FB:114] for plane state ffff88015cd68b98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.856582] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.856628] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.857147] [drm:drm_atomic_state_init] Allocated atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.857162] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0d3f8 state to ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.857175] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88017ab1a548 state to ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.857179] [drm:drm_atomic_check_only] checking ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.857190] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.857195] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.857210] [drm:drm_atomic_commit] committing ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873058] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873107] [drm:__drm_atomic_state_free] Freeing atomic state ffff8801786ee4f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873653] [drm:drm_atomic_state_init] Allocated atomic state ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873683] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd68b98 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873700] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d936fc8 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873707] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68b98 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873717] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88015cd68b98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873747] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d934a88 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873753] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015d934a88
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873765] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873807] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd68b98 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873820] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d934a88 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873826] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68b98 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873833] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88015cd68b98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873861] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d930008 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873867] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015d930008
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873888] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0db38 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873894] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880162c0db38 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873899] [drm:drm_atomic_check_only] checking ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873908] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873912] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873917] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873922] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873927] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873933] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873939] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.873950] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874086] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd68b98 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874099] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88015d930008 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874105] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68b98 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874113] [drm:drm_atomic_set_fb_for_plane] Set [FB:77] for plane state ffff88015cd68b98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874138] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015d936fc8 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874144] [drm:drm_atomic_set_mode_prop_for_crtc] Set [NOMODE] for CRTC state ffff88015d936fc8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874160] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff880162c0db38 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874166] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880162c0db38 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874170] [drm:drm_atomic_check_only] checking ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874176] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874181] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874185] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874190] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874197] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874207] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874218] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874238] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6a9a8 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874252] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd68258 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874351] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874526] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 77
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874600] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874674] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 112
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874745] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874817] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:45:cursor B] with fb 114
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874886] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:45:cursor B] visible 1 -> 0, off 1, on 0, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874912] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd6b2e8 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.874929] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015d934a88 state to ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.875003] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 502) -> (0 - 988)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.875103] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (502 - 510) -> (988 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.875173] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (510 - 1012) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.875243] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (1012 - 1020) -> (0 - 0)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.875253] [drm:drm_atomic_nonblocking_commit] committing ffff880160fcea48 nonblocking
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.875521] [drm:intel_disable_pipe [i915]] disabling pipe B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.891293] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.891344] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.891867] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.891912] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.891980] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892062] [drm:skl_set_power_well [i915]] Disabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892124] [drm:intel_disable_shared_dpll [i915]] disable PORT PLL B (active 2, on? 1) for crtc 47
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892304] [drm:intel_disable_shared_dpll [i915]] disabling PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892710] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892759] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892827] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.892873] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903349] [drm:drm_atomic_state_init] Allocated atomic state ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903365] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff88015cd6a068 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903382] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff88016686dd28 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903393] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff88015cd69978 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903397] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69978 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903401] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69978
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903411] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff88015cd68de8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903414] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68de8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903417] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68de8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903428] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff88015cd69288 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903431] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69288 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903434] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69288
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903444] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff88015cd6a508 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903447] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6a508 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903450] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6a508
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903461] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff88015cd6b538 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903474] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88016686e678 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903483] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88015cd69e18 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903486] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd69e18 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903489] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd69e18
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903499] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88015cd6b9d8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903502] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b9d8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903505] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6b9d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903515] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88015cd6ae48 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903518] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6ae48 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903521] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd6ae48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903530] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88015cd68008 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903533] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68008 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903536] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd68008
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903545] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88015cd68948 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903554] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff88015cd684a8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903557] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd684a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903560] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88015cd684a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903570] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff8801764d86f8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903574] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d86f8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903576] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764d86f8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903587] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff8801764db2e8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903590] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db2e8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903593] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764db2e8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903602] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff8801764db9d8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903605] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db9d8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903608] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764db9d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903625] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686dd28
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903629] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6a068 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903633] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88015cd6a068
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903639] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903660] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff88015cff0008 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903668] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cff0008 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903673] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cff0008 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903687] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686e678
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903690] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd6b538 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903693] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88015cd6b538
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903698] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903713] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff88015cff15c8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903716] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cff15c8 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903729] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88016686d3d8 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903740] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88016686d3d8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903743] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88015cd68948 to [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903746] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88015cd68948
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903751] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903765] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff88015cff1968 state to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903769] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff88015cff1968 to [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903772] [drm:drm_atomic_check_only] checking ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903780] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903783] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903786] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903789] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] mode changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903792] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] enable changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903795] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] active changed
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903808] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903813] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903817] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903822] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] using [ENCODER:67:DDI B] on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903825] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903829] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] using [ENCODER:74:DDI C] on [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903833] [drm:drm_atomic_helper_check_modeset] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903837] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903845] [drm:drm_atomic_helper_check_modeset] [CRTC:58:pipe C] needs all connectors, enable: y, active: y
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903849] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903859] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.903948] [drm:intel_atomic_check [i915]] [CONNECTOR:68:DP-1] checking for sink bpp constrains
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904011] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904104] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904168] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904228] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904295] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904357] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904423] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904485] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904544] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904602] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904609] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904672] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904732] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904791] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904850] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904908] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.904966] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905052] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x8200, ebb4: 0x2000,pll0: 0x20, pll1: 0x100, pll2: 0x19999a, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905112] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905172] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:112, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905231] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+0+0 dst 0x0+0+0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905289] [drm:intel_dump_pipe_config [i915]] [PLANE:39:plane 2B] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905346] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 3B] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905404] [drm:intel_dump_pipe_config [i915]] [PLANE:43:plane 4B] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905463] [drm:intel_dump_pipe_config [i915]] [PLANE:45:cursor B] FB:114, fb = 64x64 format = AR24 little-endian (0x34325241)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905522] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+-128+-128 dst 128x128+-128+-128
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905527] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905593] [drm:intel_atomic_check [i915]] [CONNECTOR:75:HDMI-A-2] checking for sink bpp constrains
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905715] [drm:intel_hdmi_compute_config [i915]] picking bpc to 8 for HDMI output
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905775] [drm:intel_hdmi_compute_config [i915]] forcing pipe bpp to 24 for HDMI
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905895] [drm:intel_dump_pipe_config [i915]] [CRTC:58:pipe C][modeset]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.905954] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906036] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906093] [drm:intel_dump_pipe_config [i915]] requested mode:
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906099] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906156] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906162] [drm:drm_mode_debug_printmodeline] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906220] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906418] [drm:intel_dump_pipe_config [i915]] port clock: 148500, pipe src size: 1920x1080, pixel rate 148500
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906479] [drm:intel_power_well_disable [i915]] disabling dpio-common-b
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906536] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906596] [drm:intel_power_well_disable [i915]] disabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906712] [drm:skl_set_power_well [i915]] Disabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906771] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906840] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906902] [drm:bxt_dump_hw_state [i915]] dpll_hw_state: ebb0: 0x6300, ebb4: 0x2000,pll0: 0x21, pll1: 0x100, pll2: 0x1a6666, pll3: 0x10000, pll6: 0x30904, pll8: 0x8, pll9: 0xa, pll10: 0x8003c00, pcsdw12: 0x4d
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906910] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.906967] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907075] [drm:intel_dump_pipe_config [i915]] [PLANE:48:plane 1C] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907084] [drm:__drm_atomic_state_free] Freeing atomic state ffff880160fcea48
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907148] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907214] [drm:intel_dump_pipe_config [i915]] [PLANE:52:plane 3C] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907279] [drm:intel_dump_pipe_config [i915]] [PLANE:54:plane 4C] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907345] [drm:intel_dump_pipe_config [i915]] [PLANE:56:cursor C] disabled, scaler_id = -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907422] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 79200 kHz, actual 79200 kHz
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907502] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907570] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907639] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:34:cursor A] with fb -1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907707] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:34:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907775] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907842] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907910] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.907977] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 0 -> 1, off 0, on 1, ms 1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908075] [drm:bxt_get_dpll [i915]] [CRTC:47:pipe B] using pre-allocated PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908145] [drm:intel_reference_shared_dpll [i915]] using PORT PLL B for pipe B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908220] [drm:bxt_get_dpll [i915]] [CRTC:58:pipe C] using pre-allocated PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908287] [drm:intel_reference_shared_dpll [i915]] using PORT PLL C for pipe C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908366] [drm:skl_compute_wm [i915]] [PLANE:26:plane 1A] ddb (0 - 988) -> (0 - 332)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908430] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (988 - 1020) -> (332 - 340)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908493] [drm:skl_compute_wm [i915]] [PLANE:37:plane 1B] ddb (0 - 0) -> (340 - 672)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908556] [drm:skl_compute_wm [i915]] [PLANE:45:cursor B] ddb (0 - 0) -> (672 - 680)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908619] [drm:skl_compute_wm [i915]] [PLANE:48:plane 1C] ddb (0 - 0) -> (680 - 1012)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908682] [drm:skl_compute_wm [i915]] [PLANE:56:cursor C] ddb (0 - 0) -> (1012 - 1020)
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908686] [drm:drm_atomic_commit] committing ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908880] [drm:intel_power_well_enable [i915]] enabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.908970] [drm:skl_set_power_well [i915]] Enabling power well 2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909135] [drm:intel_power_well_enable [i915]] enabling dpio-common-b
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909354] [drm:intel_power_well_enable [i915]] enabling dpio-common-c
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DDI A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:67:DDI B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:71:DP-MST C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DDI C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.909975] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL A
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.910154] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.910224] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.923360] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL B (active 2, on? 0) for crtc 47
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.923447] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.923695] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.923777] [drm:skl_set_power_well [i915]] Enabling DDI B IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.923859] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.923938] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.924590] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.924670] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.925374] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.925452] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.926022] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.926138] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.926221] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.926332] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.926885] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.926964] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.927115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.927197] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.927285] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.927367] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.927445] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.928062] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.928141] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.928329] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.928406] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.928949] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.929064] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.930017] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.930195] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.930774] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.930855] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.930939] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.931017] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.931676] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.931756] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.931850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.931939] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.932023] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.932140] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.932740] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.932820] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.933310] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.933388] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.933870] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.933929] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.934875] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.934925] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.935466] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.935509] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.935555] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.935596] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.936177] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.936219] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.936273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.938655] [drm:intel_dp_start_link_train [i915]] Link Training Passed at Link Rate = 162000, Lane count = 4
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.938736] [drm:intel_power_well_enable [i915]] enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.938781] [drm:skl_set_power_well [i915]] Enabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.939314] [drm:intel_power_well_disable [i915]] disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.939356] [drm:skl_set_power_well [i915]] Disabling AUX B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.940290] [drm:intel_enable_pipe [i915]] enabling pipe B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.940526] [drm:intel_enable_shared_dpll [i915]] enable PORT PLL C (active 4, on? 0) for crtc 58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.940571] [drm:intel_enable_shared_dpll [i915]] enabling PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.940761] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.940803] [drm:skl_set_power_well [i915]] Enabling DDI C IO power well
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.941738] [drm:intel_enable_pipe [i915]] enabling pipe C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.959629] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.959722] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.959931] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL B
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.960292] [drm:verify_connector_state.isra.51 [i915]] [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.960381] [drm:intel_atomic_commit_tail [i915]] [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.960534] [drm:verify_single_dpll_state.isra.77 [i915]] PORT PLL C
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.960645] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.960833] [drm:__drm_atomic_state_free] Freeing atomic state ffff880177025fa8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.961228] Console: switching to colour frame buffer device 240x67
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978897] [drm:drm_atomic_state_init] Allocated atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978910] [drm:drm_atomic_get_plane_state] Added [PLANE:26:plane 1A] ffff8801764d8de8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978923] [drm:drm_atomic_get_crtc_state] Added [CRTC:36:pipe A] ffff880175acae98 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978932] [drm:drm_atomic_get_plane_state] Added [PLANE:28:plane 2A] ffff8801764d8008 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978936] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d8008 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978940] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764d8008
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978949] [drm:drm_atomic_get_plane_state] Added [PLANE:30:plane 3A] ffff8801764dbc28 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978953] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764dbc28 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978980] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764dbc28
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978990] [drm:drm_atomic_get_plane_state] Added [PLANE:32:plane 4A] ffff8801764d84a8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978993] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d84a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.978997] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764d84a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979005] [drm:drm_atomic_get_plane_state] Added [PLANE:34:cursor A] ffff8801764d8948 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979009] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d8948 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979012] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff8801764d8948
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979024] [drm:drm_atomic_get_plane_state] Added [PLANE:37:plane 1B] ffff8801764db788 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979037] [drm:drm_atomic_get_crtc_state] Added [CRTC:47:pipe B] ffff88015da88008 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979050] [drm:drm_atomic_get_plane_state] Added [PLANE:39:plane 2B] ffff88017834ebf8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979054] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834ebf8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979057] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834ebf8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979065] [drm:drm_atomic_get_plane_state] Added [PLANE:41:plane 3B] ffff88017834c4a8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979069] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834c4a8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979073] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834c4a8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979081] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 4B] ffff88017834f788 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979085] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f788 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979088] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834f788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979096] [drm:drm_atomic_get_plane_state] Added [PLANE:45:cursor B] ffff88017834cde8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979100] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834cde8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979103] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834cde8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979112] [drm:drm_atomic_get_plane_state] Added [PLANE:48:plane 1C] ffff88017834de18 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979122] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe C] ffff88015da89bf8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979130] [drm:drm_atomic_get_plane_state] Added [PLANE:50:plane 2C] ffff88017834e758 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979137] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834e758 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979143] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834e758
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979155] [drm:drm_atomic_get_plane_state] Added [PLANE:52:plane 3C] ffff88017834f098 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979161] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834f098 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979168] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834f098
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979178] [drm:drm_atomic_get_plane_state] Added [PLANE:54:plane 4C] ffff88017834d038 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979181] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834d038 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979184] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834d038
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979193] [drm:drm_atomic_get_plane_state] Added [PLANE:56:cursor C] ffff88017834e508 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979196] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834e508 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979200] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff88017834e508
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979215] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff880175acae98
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979219] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764d8de8 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979225] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff8801764d8de8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979230] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:36:pipe A] to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979247] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:60:eDP-1] ffff880178371798 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979254] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178371798 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979258] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880178371798 to [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979270] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015da88008
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979276] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff8801764db788 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979281] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff8801764db788
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979286] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:47:pipe B] to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979300] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:68:DP-1] ffff8801786361d8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979305] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786361d8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979311] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786361d8 to [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979321] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:1920x1080] for CRTC state ffff88015da89bf8
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979327] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88017834de18 to [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979332] [drm:drm_atomic_set_fb_for_plane] Set [FB:107] for plane state ffff88017834de18
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979336] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:58:pipe C] to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979348] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:75:HDMI-A-2] ffff8801786375c8 state to ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979353] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786375c8 to [NOCRTC]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979357] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff8801786375c8 to [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979361] [drm:drm_atomic_check_only] checking ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979376] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:60:eDP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979382] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:60:eDP-1] keeps [ENCODER:59:DDI A], now on [CRTC:36:pipe A]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979390] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:68:DP-1]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979394] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:68:DP-1] keeps [ENCODER:67:DDI B], now on [CRTC:47:pipe B]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979397] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:75:HDMI-A-2]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979404] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:75:HDMI-A-2] keeps [ENCODER:74:DDI C], now on [CRTC:58:pipe C]
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979477] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:36:pipe A] has [PLANE:26:plane 1A] with fb 107
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979525] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:26:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979572] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:37:plane 1B] with fb 107
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979618] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:37:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979665] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:58:pipe C] has [PLANE:48:plane 1C] with fb 107
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979710] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:48:plane 1C] visible 1 -> 1, off 0, on 0, ms 0
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.979729] [drm:drm_atomic_commit] committing ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.992691] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff88016395da58
>Jun 28 15:43:11 GLK-2-GLKRVP1DDR405 kernel: [  116.992895] [drm:__drm_atomic_state_free] Freeing atomic state ffff88016395da58
>Jun 28 15:43:14 GLK-2-GLKRVP1DDR405 kernel: [  119.362603] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>Jun 28 15:43:14 GLK-2-GLKRVP1DDR405 kernel: [  119.362774] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>Jun 28 15:43:14 GLK-2-GLKRVP1DDR405 kernel: [  119.362897] [drm:intel_power_well_disable [i915]] disabling AUX A
>Jun 28 15:43:14 GLK-2-GLKRVP1DDR405 kernel: [  119.363022] [drm:skl_set_power_well [i915]] Disabling AUX A

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Attachments on bug 101634: 132318 | 132319 | 134206 | 136572

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