Attachment 132579 Details for Bug 101325 – ddebug_mono_500ms_hang.log

ddebug_mono_500ms_hang.log

glretrace_17455_00000000 (text/plain), 29.62 KB, created by Julien Isorce on 2017-07-10 11:46:07 UTC

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Creator: Julien Isorce

Created: 2017-07-10 11:46:07 UTC

Size: 29.62 KB

patch

obsolete

>Command: /usr/bin/glretrace /chattel/jisorce/UE4Editor.5.trace 
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD CAPE VERDE (DRM 2.50.0 / 4.12.0-rc7+, LLVM 5.0.0)
>
>Draw call sequence # = 450
>HW reached sequence # = 449
>Elapsed time = 509 ms
>
>[1;33mdraw_info: [0m{index_size = 0, has_user_indices = 0, mode = triangle_strip, start = 0, count = 4, start_instance = 0, instance_count = 1, drawid = 0, vertices_per_patch = 0, index_bias = 0, min_index = 0, max_index = 3, primitive_restart = 0, restart_index = 0, index.resource = NULL, count_from_stream_output = NULL, indirect = NULL, }
>
>[1;33mvertex_buffer 0: [0m{stride = 8, is_user_buffer = 0, buffer_offset = 14816, buffer.resource = 0x7fb874003560, }
>  buffer.resource: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 1048576, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 3, bind = 0, flags = 3, }
>[1;33mnum vertex elements[0m = 1
>  [1;33mvertex_element 0: [0m{src_offset = 0, instance_divisor = 0, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, }
>[1;33mnum stream output targets[0m = 0
>
>[1;32mbegin shader: VERTEX[0m
>[1;33mshader_state: [0m{tokens = "
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL SV[0], INSTANCEID
>DCL OUT[0], POSITION
>DCL OUT[1], LAYER
>  0: MOV OUT[0], IN[0]
>  1: MOV OUT[1].x, SV[0].xxxx
>  2: END
>", }
>[1;32mend shader: VERTEX[0m
>
>[1;33mviewport_state 0: [0m{scale = {2048, 0.5, 0.5, }, translate = {2048, 0.5, 0.5, }, }
>[1;33mrasterizer_state: [0m{flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 0, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 0, point_quad_rasterization = 0, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 0, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 1, bottom_edge_rule = 0, rasterizer_discard = 0, depth_clip = 0, clip_halfz = 0, clip_plane_enable = 0, line_width = 0, point_size = 0, offset_units = 0, offset_scale = 0, offset_clamp = 0, }
>
>[1;32mbegin shader: FRAGMENT[0m
>[1;33mshader_state: [0m{tokens = "
>FRAG
>DCL IN[0], LAYER, CONSTANT
>DCL SV[0], POSITION
>DCL OUT[0], COLOR
>DCL SAMP[0]
>DCL CONST[0..1]
>DCL TEMP[0]
>IMM[0] UINT32 {0, 0, 0, 0}
>  0: F2I TEMP[0].xy, SV[0].xyyy
>  1: UADD TEMP[0].xy, TEMP[0].xyyy, CONST[0].xyyy
>  2: UMAD TEMP[0].x, CONST[0].zzzz, TEMP[0].yyyy, TEMP[0].xxxx
>  3: UMAD TEMP[0].x, CONST[0].wwww, IN[0].xxxx, TEMP[0].xxxx
>  4: MOV TEMP[0].w, IMM[0].xxxx
>  5: TXF TEMP[0], TEMP[0], SAMP[0], BUFFER
>  6: MOV OUT[0], TEMP[0]
>  7: END
>", }
>[1;33mconstant_buffer 0: [0m{buffer = NULL, buffer_offset = 0, buffer_size = 20, user_buffer = 0x7fb87b5ef990, }
>[1;33msampler_state 0: [0m{wrap_s = repeat, wrap_t = repeat, wrap_r = repeat, min_img_filter = nearest, min_mip_filter = nearest, mag_img_filter = nearest, compare_mode = 0, compare_func = never, normalized_coords = 0, max_anisotropy = 0, seamless_cube_map = 0, lod_bias = 0, min_lod = 0, max_lod = 0, border_color.f = {0, 0, 0, 0, }, }
>[1;33msampler_view 0: [0m{target = buffer, format = PIPE_FORMAT_B8G8R8A8_UNORM, texture = 0x7fb860006bf0, u.buf.offset = 0, u.buf.size = 16384, swizzle_r = 0, swizzle_g = 1, swizzle_b = 2, swizzle_a = 3, }
>  texture: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 16384, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, usage = 2, bind = 10, flags = 0, }
>[1;32mend shader: FRAGMENT[0m
>
>[1;33mdepth_stencil_alpha_state: [0m{depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, }
>[1;33mstencil_ref: [0m{ref_value = {0, 0, }, }
>[1;33mblend_state: [0m{dither = 0, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 0, colormask = 15, }, }, }
>[1;33mblend_color: [0m{color = {0, 0, 0, 0, }, }
>[1;33mmin_samples[0m = 1
>[1;33msample_mask[0m = 0xffffffff
>
>[1;33mframebuffer_state: [0m{width = 4096, height = 1, samples = 0, layers = 0, nr_cbufs = 1, cbufs = {0x7fb860002cd0, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, }
>  [1;33mcbufs[0]:[0m
>    [1;33msurface: [0m{format = PIPE_FORMAT_R8G8B8A8_UNORM, width = 4096, height = 1, texture = 0x7fb8600022d0, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
>    [1;33mresource: [0m{target = 2d, format = PIPE_FORMAT_R8G8B8A8_UNORM, width0 = 4096, height0 = 1, depth0 = 1, array_size = 1, last_level = 12, nr_samples = 0, usage = 0, bind = 10, flags = 4, }
>
>
>
>*****************************************************************************
>Driver-specific state:
>
>SHADER KEY
>  part.vs.prolog.instance_divisors = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  mono.u.vs_export_prim_id = 0
>  opt.kill_outputs[0] = 0x0
>  opt.kill_outputs[1] = 0x0
>  opt.clip_disable = 0
>
>Vertex Shader as VS - main shader part - LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #0
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #1
>
>define amdgpu_vs void @wrapper([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32 inreg, i32 inreg, i32, i32, i32, i32) #2 {
>main_body:
>  %12 = bitcast i32 %9 to float
>  %13 = add i32 %8, %4
>  %14 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %3, i64 0, i64 0, !amdgpu.uniform !0
>  %15 = load <4 x i32>, <4 x i32> addrspace(2)* %14, align 16, !invariant.load !0, !alias.scope !1
>  %16 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %15, i32 %13, i32 0, i1 false, i1 false) #3
>  %17 = extractelement <4 x float> %16, i32 0
>  %18 = extractelement <4 x float> %16, i32 1
>  %19 = extractelement <4 x float> %16, i32 2
>  %20 = extractelement <4 x float> %16, i32 3
>  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %12, float undef, float undef, float undef, i1 false, i1 false) #1, !noalias !1
>  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %17, float %18, float %19, float %20, i1 false, i1 false) #1, !noalias !1
>  call void @llvm.amdgcn.exp.f32(i32 13, i32 4, float undef, float undef, float %12, float undef, i1 true, i1 false) #1, !noalias !1
>  ret void
>}
>
>attributes #0 = { nounwind readonly }
>attributes #1 = { nounwind }
>attributes #2 = { "no-signed-zeros-fp-math"="true" }
>attributes #3 = { nounwind readnone }
>
>!0 = !{}
>!1 = !{!2}
>!2 = distinct !{!2, !3, !"main: argument 0"}
>!3 = distinct !{!3, !"main"}
>
>
>Vertex Shader as VS:
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[6:7], 0x0                  ; C0800700
>	v_add_i32_e32 v0, vcc, s8, v0                       ; 4A000008
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	buffer_load_format_xyzw v[2:5], v0, s[0:3], 0 idxen ; E00C2000 80000200
>	exp param0 v1, v0, v0, v0                           ; F800020F 00000001
>	s_waitcnt vmcnt(0)                                  ; BF8C0F70
>	exp pos0 v2, v3, v4, v5                             ; F80000CF 05040302
>	exp pos1 off, off, v1, off done                     ; F80008D4 00010000
>	s_endpgm                                            ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 16
>VGPRS: 8
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 52 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader - main shader part - LLVM IR:
>
>; ModuleID = 'tgsi'
>source_filename = "tgsi"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn--"
>
>; Function Attrs: nounwind readnone
>declare float @llvm.SI.load.const.v4i32(<4 x i32>, i32) #0
>
>; Function Attrs: nounwind readnone speculatable
>declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
>
>; Function Attrs: nounwind readonly
>declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
>
>; Function Attrs: nounwind readnone speculatable
>declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
>
>; Function Attrs: nounwind
>declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #3
>
>define amdgpu_ps void @wrapper([11 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [32 x <4 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), [80 x <8 x i32>] addrspace(2)* byval noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #4 {
>main_body:
>  %21 = fptosi float %13 to i32
>  %22 = fptosi float %14 to i32
>  %23 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %1, i64 0, i64 16, !amdgpu.uniform !0
>  %24 = load <4 x i32>, <4 x i32> addrspace(2)* %23, align 16, !invariant.load !0, !alias.scope !1, !noalias !4
>  %25 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %24, i32 0)
>  %26 = bitcast float %25 to i32
>  %27 = add i32 %21, %26
>  %28 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %24, i32 4)
>  %29 = bitcast float %28 to i32
>  %30 = add i32 %22, %29
>  %31 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %24, i32 8)
>  %32 = bitcast float %31 to i32
>  %33 = mul i32 %30, %32
>  %34 = add i32 %33, %27
>  %35 = call nsz float @llvm.SI.load.const.v4i32(<4 x i32> %24, i32 12)
>  %36 = bitcast float %35 to i32
>  %37 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %4) #0
>  %38 = bitcast float %37 to i32
>  %39 = mul i32 %36, %38
>  %40 = add i32 %39, %34
>  %41 = bitcast [80 x <8 x i32>] addrspace(2)* %2 to [0 x <4 x i32>] addrspace(2)*
>  %42 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %41, i64 0, i64 33, !amdgpu.uniform !0
>  %43 = load <4 x i32>, <4 x i32> addrspace(2)* %42, align 16, !invariant.load !0, !alias.scope !4, !noalias !1
>  %44 = call nsz <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %43, i32 %40, i32 0, i1 false, i1 false) #0
>  %45 = extractelement <4 x float> %44, i32 0
>  %46 = extractelement <4 x float> %44, i32 1
>  %47 = extractelement <4 x float> %44, i32 2
>  %48 = extractelement <4 x float> %44, i32 3
>  %49 = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %45, float %46) #0
>  %50 = call nsz <2 x half> @llvm.amdgcn.cvt.pkrtz(float %47, float %48) #0
>  %51 = bitcast <2 x half> %49 to <2 x i16>
>  %52 = bitcast <2 x half> %50 to <2 x i16>
>  call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> %51, <2 x i16> %52, i1 true, i1 true) #3
>  ret void
>}
>
>attributes #0 = { nounwind readnone }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind readonly }
>attributes #3 = { nounwind }
>attributes #4 = { "no-signed-zeros-fp-math"="true" }
>
>!0 = !{}
>!1 = !{!2}
>!2 = distinct !{!2, !3, !"main: argument 0"}
>!3 = distinct !{!3, !"main"}
>!4 = !{!5}
>!5 = distinct !{!5, !3, !"main: argument 1"}
>
>
>Pixel Shader:
>Shader main disassembly:
>	s_load_dwordx4 s[0:3], s[2:3], 0x40                 ; C0800340
>	v_cvt_i32_f32_e32 v0, v3                            ; 7E001103
>	v_cvt_i32_f32_e32 v1, v2                            ; 7E021102
>	s_mov_b32 m0, s7                                    ; BEFC0307
>	v_interp_mov_f32 v2, p0, attr0.x                    ; C80A0002
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	s_buffer_load_dword s8, s[0:3], 0x1                 ; C2040101
>	s_buffer_load_dword s9, s[0:3], 0x2                 ; C2048102
>	s_buffer_load_dword s6, s[0:3], 0x0                 ; C2030100
>	s_buffer_load_dword s0, s[0:3], 0x3                 ; C2000103
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	v_add_i32_e32 v0, vcc, s8, v0                       ; 4A000008
>	v_mul_lo_i32 v0, v0, s9                             ; D2D60000 00001300
>	v_add_i32_e32 v1, vcc, s6, v1                       ; 4A020206
>	v_mul_lo_i32 v2, s0, v2                             ; D2D60002 00020400
>	s_load_dwordx4 s[0:3], s[4:5], 0x84                 ; C0800584
>	v_add_i32_e32 v0, vcc, v0, v1                       ; 4A000300
>	v_add_i32_e32 v0, vcc, v2, v0                       ; 4A000102
>	s_waitcnt lgkmcnt(0)                                ; BF8C007F
>	buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen ; E00C2000 80000000
>	s_waitcnt vmcnt(0)                                  ; BF8C0F70
>	v_cvt_pkrtz_f16_f32_e32 v0, v0, v1                  ; 5E000300
>	v_cvt_pkrtz_f16_f32_e32 v1, v2, v3                  ; 5E020702
>	exp mrt0 v0, v0, v1, v1 done compr vm               ; F8001C0F 00000100
>	s_endpgm                                            ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0x0301
>SPI_PS_INPUT_ENA  = 0x0301
>*** SHADER STATS ***
>SGPRS: 16
>VGPRS: 4
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 116 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 10
>********************
>
>
>[1;32mRW buffers slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 2 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 3 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 4 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 5 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 6 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 7 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 8 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 9 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mRW buffers slot 10 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x0102a000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 8
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mVS - Vertex buffer slot 0 (CPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>[1;32mPS - Constant buffer slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x0103f460
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 20 (0x00000014)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>                             USER_VM_ENABLE = 0
>                             USER_VM_MODE = 0
>                             NV = 0
>
>
>Memory-mapped registers:
>        [1;33mGRBM_STATUS[0m <- ME0PIPE0_CMDFIFO_AVAIL = 8
>                       SRBM_RQ_PENDING = 1
>                       ME0PIPE0_CF_RQ_PENDING = 0
>                       ME0PIPE0_PF_RQ_PENDING = 0
>                       GDS_DMA_RQ_PENDING = 0
>                       DB_CLEAN = 1
>                       CB_CLEAN = 1
>                       TA_BUSY = 0
>                       GDS_BUSY = 0
>                       WD_BUSY_NO_DMA = 0
>                       VGT_BUSY = 0
>                       IA_BUSY_NO_DMA = 0
>                       IA_BUSY = 0
>                       SX_BUSY = 0
>                       WD_BUSY = 0
>                       SPI_BUSY = 0
>                       BCI_BUSY = 0
>                       SC_BUSY = 0
>                       PA_BUSY = 0
>                       DB_BUSY = 0
>                       CP_COHERENCY_BUSY = 0
>                       CP_BUSY = 0
>                       CB_BUSY = 0
>                       GUI_ACTIVE = 0
>                       RSMU_RQ_PENDING = 1
>
>

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Attachments on bug 101325: 131758 | 131759 | 131760 | 131837 | 132579 | 132581 | 133369 | 133809

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